FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 1.0 * Figure 1: Block Diagram Features Generates all clocks required for single and two-way multi-processor (MP) platforms, including: M Four differential current-mode Host clock pairs M Four 66.67MHz 3.3V CK66 clock outputs M Ten 33.3MHz 3.3V PCI clock outputs M Two 3.3V Memory Reference clock outputs M Two 48MHz 3.3V CK48 clock outputs M Two buffered copies of the crystal reference * Control of current-mode Host clocks via IREF current programming pin and ISEL_0:1 current multiplier pins * Host clock frequency selection via the SEL_A, SEL_B, and SEL133/100# pins * Active-low PWR_DWN# signal allows one complete clock cycle on each clock outputs and then shuts down the crystal oscillator, PLLs, and outputs * XIN XOUT ISEL_0:1 VDD_R Crystal Oscillator REF_0:1 VSS_R adjust IREF VDD_H PWR_DWN# SS_EN# SEL133/100# SEL_A:B /1 HOST_P1:4 /2 HOST_N1:4 SSCG PLL /3 Control /4 VSS_H CK66_0:3 VDD_M Available in a 56-pin SSOP and TSSOP VSS_M VDD_48 Table 1: Clock Parameters Figure 2: Pin Configuration 56 VDD_M 4 4 1 CK66 4 3.3V PCI 10 CK48 REF 0 51 HOST_P1 150ps VSS_P 7 50 HOST_N1 Pair to Pair PCI_0 8 49 VDD_H PCI_1 9 48 HOST_P2 VDD_P 10 47 HOST_N2 66.67 50.00 180 VDD_66 66.67 0 250ps VSS_P 13 3.3V VDD_P 33.33 0 300ps PCI_4 14 2 3.3V VDD_48 48.008 0 - VDD_P 16 2 3.3V VDD_R 14.318 0 - PCI_6 17 3.3V VDD_M - Table 2: Clock Offsets RELATION CK66 leads PCI PHASE 0 MIN 1.5ns TYP 52 SS_EN# XOUT 6 MAX 3.5ns PCI_2 11 46 VSS_H PCI_3 12 45 HOST_P3 PCI_5 15 44 HOST_N3 43 VDD_H 42 HOST_P4 41 HOST_N4 Pair 4 MREF_N 180 53 VSS_M XIN 5 Pair 3 1 133.33 100.00 54 MREF_N VDD_R 4 FS6232-01 MREF_P VDD_H 55 MREF_P REF_1 / ISEL_1 3 Pair 2 HOST_N 3.3V 0 SKEW (MAX) REF_0 / ISEL_0 2 Pair 1 HOST_P PHASE CK48_0:1 FS6232 VSS_R 1 FREQ. (MHz) MREF_P MREF_N /4 VSS_48 * SUPPLY GROUP PCI_0:9 PLL Supports test mode and tristate output control to facilitate board testing SUPPLY VOLTAGE /2 VSS_P * # PINS VSS_66 VDD_P delay Spread-spectrum modulation (-0.5% at 31.5kHz) of SSCG PLL clocks, enabled via SS_EN# input CLOCK GROUP VDD_66 40 VSS_H PCI_7 18 39 IREF VSS_P 19 38 VDD PCI_8 20 37 VSS PCI_9 21 36 VDD_66 VDD_P 22 35 CK66_0 SEL133/100# 23 34 CK66_1 VSS_48 24 33 VSS_66 CK48_0 / SEL_A 25 32 VSS_66 CK48_1 / SEL_B 26 31 CK66_2 VDD_48 27 30 CK66_3 PWR_DWN# 28 29 VDD_66 Intel and Pentium are registered trademarks of Intel Corporation. Lexmark is a trademark of Lexmark International, Inc. Non-linear spread spectrum modulation profile is licensed under US Patent No. 5488627, Lexmark International, Inc. This document contains information on a preproduction product. Specifications and information herein are subject to change without notice. ISO9001 9.18.00 IntSKS FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 Table 3: Pin Descriptions Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down; DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active-low pin PIN TYPE NAME 25 DIO 26 DIO 35, 34, 31, 30 DO 50, 51 AO 47, 48 AO 44, 45 AO 41, 42 AO 39 AI IREF 54 DO MREF_N 55 8, 9, 11, 12, 14, 15, 17, 18, 20, 21 DO CK48_0 SEL_A CK48_1 SEL_B CK66_0:3 HOST_P1 HOST_N1 HOST_P2 HOST_N2 HOST_P3 HOST_N3 HOST_P4 HOST_N4 DESCRIPTION One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL One of two latched inputs that select the HOST and MREF output frequency One of two 3.3V 48MHz clock outputs, generated from the non-spread PLL One of two latched inputs that select the HOST and MREF output frequency Four 3.3V 66.67MHz clock outputs, generated from the spread spectrum PLL Host clock pair #1; one of six pairs of current-steering differential current-mode outputs. The current is established via a reference current at IREF and a multiplying factor set by ISEL_0:1 SUPPLY VDD_48 VDD_48 VDD_66 VDD_H Host clock pair #2; one of six pairs of current-steering differential current-mode outputs VDD_H Host clock pair #3; one of six pairs of current-steering differential current-mode outputs VDD_H Host clock pair #4; one of six pairs of current-steering differential current-mode outputs VDD_H MREF_P A fixed precision resistor from this pin to ground provides a reference current used for the differential current-mode HOST clock outputs One clock (180 out of phase with MREF_P) in a pair of outputs provided as a reference clock to a memory clock driver One clock in a pair of outputs provided as a reference clock to a memory clock driver VDD_M DO PCI_0:9 Ten 3.3V 33.3MHz PCI clocks, lagging the CK66 clock by 1.5 to 3.5ns VDD_P 28 DI PWR_DWN# 2 DIO 3 DIO 23 DI SEL133/100# 52 DI 38 27 29, 36 43, 49 56 10, 16, 22 4 37 24 32, 33 40, 46 53 7, 13, 19 1 5 6 P P P P P P P P P P P P P P AI AO VDD_M Asynchronous active-low LVTTL power-down signal shuts down oscillator and PLL, puts all clocks in low state. Complete clock cycles on all outputs will occur before shut down begins. One of two 3.3V buffered copies of the crystal reference frequency clock One of two latched inputs that select the multiplying factor of the IREF reference current for the HOST pair outputs One of two 3.3V buffered copies of the crystal reference frequency clock One of two latched inputs that select the multiplying factor of the IREF reference current for the HOST pair outputs Selects 133MHz (logic high) or 100MHz (logic low) Host clock frequency VDD_48 SS_EN# Active low spread-spectrum enable turns on spread spectrum modulation VDD_M VDD VDD_48 VDD_66 VDD_H VDD_M VDD_P VDD_R VSS VSS_48 VSS_66 VSS_H VSS_M VSS_P VSS_R XIN XOUT 3.3V core power supply 3.3V power supply for CK48 clock outputs 3.3V power supply for CK66 clock outputs 3.3V power supply for the differential HOST clock outputs 3.3V power supply for MREF clock outputs 3.3V power supply for PCI clock outputs 3.3V power supply for the REF clock output and the crystal oscillator Core ground Ground for the CK48 clock outputs Ground for the CK66 clock outputs Ground for the differential HOST clock outputs Ground for the MREF clock outputs Ground for the PCI clock outputs Ground for the REF clock outputs and the crystal oscillator 14.318MHz crystal oscillator input 14.318MHz crystal oscillator output REF_0 ISEL_0 REF_1 ISO9001 VDD ISEL_1 VDD_48 VDD_R VDD_R VDD_R VDD_R 9.18.00 2 FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 2.0 Programming Information Table 4: Function/Clock Enable Configuration CONTROL INPUTS CLOCK OUTPUTS (MHz) PWR_ DWN# SEL 133/100# SEL_A SEL_B HOST_P 1:4 HOST_N 1:4 MREF_P, MREF_N CK66_ 0:3 PCI_ 0:9 CK48_ 0:1 REF 1 0 0 0 100.00 100.00 50.00 66.67 33.33 48.008 14.318 1 0 0 1 reserved reserved reserved reserved reserved reserved reserved 1 0 1 0 reserved reserved reserved reserved reserved reserved reserved 1 0 1 1 tristate tristate tristate tristate tristate tristate tristate 1 1 0 0 133.33 133.33 66.67 66.67 33.33 48.008 14.318 1 1 0 1 reserved reserved reserved reserved reserved reserved reserved 1 1 1 0 reserved reserved reserved reserved reserved reserved reserved 1 1 1 1 XIN / 2 XIN / 2 XIN / 4 XIN / 4 XIN / 8 XIN / 2 XIN X 2 x IREF tristate low low low low low 0 X X Table 5: Synthesis Error CLOCK TARGET (MHz) 3.1 ACTUAL (MHz) 100.0000 99.9963 -36.657 133.3333 133.3072 -195.924 MREF_P, MREF_N 50.0000 49.9982 -36.657 66.6667 66.6536 -195.924 CK66 66.6667 66.6642 -36.657 PCI 33.3333 33.3321 -36.657 CK48 (1) 48.000 48.008 +167 1. 48MHz USB clock is required to be +167ppm off from 48.000MHz to conform to USB standards. 2. Spread spectrum is disabled 3.0 The HOST output current is a mirrored and scaled copy of the reference current flowing through the programming resistor on the IREF pin. Conceptually, the circuit given in Figure 2 shows how the mirror current is generated. The voltage that appears at the IREF pin is one-third of the voltage at the VDD_I pin. The reference current is DEVIATION (ppm) HOST_P1:4, HOST_N1:4 I REF 3.2 1 x VDD_I 3 . = RIREF Current Scaling The mirrored reference current can be increased by adding one or more copies of the mirror current together. The additional current is controlled by the logic settings on the ISEL_0 and ISEL_1 pins. HOST Buffer Current Control The current supplied at the HOST outputs is controlled by two parameters: 1) the value of the programming resistor from the IREF pin to ground (VSS), and 2) the multiplier factor determined by the logic setting of the ISEL_0 and ISEL_1 pins. ISO9001 Current Reference Table 6: Current Multiplier ISEL_0 ISEL_1 MULTPLIER 0 0 IO = 5 x IREF 0 1 IO = 6 x IREF 1 0 IO = 4 x IREF 1 1 IO = 7 x IREF 9.18.00 3 FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 Figure 2: Current Reference Circuit Table 8: HOST Buffer Clock Output VDD_I (3.3V) 2R 1.1V Mirror Current R IREF Reference Current IREF RIREF MIN. ISEL_0:1 HOST_N HOST_P RS RP 475 (1%) 2.32mA 2.32mA IO = 4 x IREF 475 (1%) 2.32mA IO = 7 x IREF 221 (1%) 5mA IO = 5 x IREF 221 (1%) 5mA IO = 6 x IREF 221 (1%) 5mA IO = 4 x IREF 221 (1%) 5mA IO = 7 x IREF 0.00 0.00 -3.03 -4.22 -5.76 2.97 -5.66 -7.68 -9.86 2.81 -7.87 -10.30 -11.85 2.64 -9.67 -11.91 -12.45 2.48 -11.05 -12.56 -12.84 RP 2.31 -11.98 -12.85 -13.16 2.14 -12.52 -13.07 -13.45 1.98 -12.77 -13.26 -13.72 1.81 -12.91 -13.42 -13.96 1.65 -12.99 -13.54 -14.17 1.48 -13.04 -13.64 -14.36 1.32 -13.07 -13.70 -14.52 OUTPUT VOLTAGE 1.15 -13.08 -13.73 -14.64 0.99 -13.09 -13.75 -14.71 60 0.71V 0.82 -13.11 -13.76 -14.74 50 0.59V 0.66 -13.12 -13.78 -14.76 60 0.85V 0.49 -13.13 -13.79 -14.78 50 0.71V 0.33 -13.13 -13.80 -14.80 60 0.56V 0.16 -13.14 -13.81 -14.82 50 0.47V 0.00 -13.15 -13.82 -14.83 60 0.99V IO = 6 x IREF 2.32mA 0.00 3.14 TRACE IMPEDANCE IO = 5 x IREF 475 (1%) MAX. 3.30 50 Output Voltage (V) 0 0.82V 1 2 3 0 30 0.75V 25 0.62V -2 30 0.90V -4 25 0.75V 30 0.60V 25 0.50V 30 1.05V 25 0.84V Output Current (mA) 475 (1%) REFERENCE CURRENT CURRENT MULTIPLIER IREF TYP. RS Table 7: HOST Current Selection PROGRAM RESISTOR RIREF HIGH DRIVE CURRENT (mA) AT PRIMARY SYSTEM CONFIGURATION Output Voltage (V) Additional Mirror Current NOTE: Shaded row indicates the Primary System Configuration -6 -8 -10 -12 -14 -16 -18 -20 30 50 90 Max VOH Data in this table represents nominal characterization data only ISO9001 9.18.00 4 FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 4.0 Table 9: Latency Table Power Management The PWR_DWN# signal is an asynchronous, active-low LVTTL input that places the device in a low power inactive state without removing power from the device. All internal clocks are turned off, and all clock outputs are held low. Since PWR_DWN# is asynchronous, the signal is synchronized internally to each individual clock. As shown in Figure 3, a falling-rising-falling edge sequence on any individual clock output is required before that clock output is disabled low. This edge sequence ensures that one complete clock cycle will occur before the clock stops. PWR_ DWN# LATENCY SIGNAL STATE SIGNAL 0 Power OFF 1 Power ON MIN. MAX. Output: 2 clocks 3 clocks Device: 2x REF clocks 3x REF clocks 3ms Upon the release of PWR_DWN# (power-up), external circuitry should allow a minimum of 3ms for the PLL to lock before enabling any clocks. Figure 3: PWR_DWN# Timing Any Clock (internal) PWR_DWN# Any Clock (output) After REF output shuts off... 3ms until clock is valid VCO Crystal Oscillator Shaded regions in the Crystal Oscillator and VCO waveforms indicate that the clock is valid and the Crystal Oscillator and VCO are active. 5.0 Figure 4: I/O Pin Programming Dual Function I/O Pins Several pins on this device serve as dual function input/output pins. During the initial application of VDD to the device, this type of pin functions as an input pin. Upon completion of power-up, the logic state present on the pin is latched internally, and the pin is converted to an output driver. An external 10k pull-down resistor to ground is required for a logic low and a 10k pull-up resistor to the clock output VDD is required for a logic high. The 10k resistor presents an insignificant load to the output driver that should not affect the output clock. Note that the latching of the logic state occurs only on the application of the chip supply voltage (VDD). The logic state on the pin is not latched if the PWR_DWN# signal is used to power-down the device with VDD still applied. ISO9001 Termination Resistor Clock Trace Device Solder Pads 10k Programming Resistor Ground or Power Via 9.18.00 5 FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 6.0 Electrical Specifications Table 10: Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for extended conditions may affect device performance, functionality, and reliability. PARAMETER Supply Voltage (VSS = ground) SYMBOL MIN. MAX. UNITS VDD VSS-0.5 7 V Input Voltage, dc VI VSS-0.5 VDD+0.5 V Output Voltage, dc VO VSS-0.5 VDD+0.5 V Input Clamp Current, dc (VI < 0 or VI > VDD) IIK -50 50 mA Output Clamp Current, dc (VI < 0 or VI > VDD) IOK -50 50 mA Storage Temperature Range (non-condensing) TS -65 150 C Ambient Temperature Range, Under Bias TA -55 125 C Junction Temperature TJ 125 C Lead Temperature (soldering, 10s) 260 C 2 kV Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) CAUTION: ELECTROSTATIC SENSITIVE DEVICE Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy electrostatic discharge. Table 11: Operating Conditions PARAMETER Supply Voltage Operating Temperature Range SYMBOL VDD CONDITIONS/DESCRIPTION MIN. TYP. MAX. Core (VDD) 3.135 3.3 3.465 Clock Buffers (VDD_48, VDD_66, VDD_H, VDD_M, VDD_P, VDD_R) 3.135 3.3 3.465 UNITS V TA 0 70 C Crystal Resonator Frequency fXTAL 14.316 14.318 14.32 MHz Crystal Resonator Load Capacitance CXL 13.5 18 22.5 pF Load Capacitance CL XIN, XOUT pins MREF_P, MREF_N 10 30 PCI_0:9 10 30 CK66_0:3 10 30 CK48_0:1 10 20 REF_0:1 10 20 20 105 1.20 V Load Resistance RL HOST_P1 to HOST_P4, HOST_N1 to HOST_N4 Maximum High-Level Output Voltage VOH HOST_P1 to HOST_P4, HOST_N1 to HOST_N4 ISO9001 pF 9.18.00 6 FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 Table 12: DC Electrical Specifications Unless otherwise stated, all power supplies = 3.3V 5%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 f rom typical. Negative currents indicate current flows out of the device. PARAMETER SYMBOL Supply Current, Dynamic, with Loaded Outputs IDD Supply Current, Static IDDs CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Overall fHOST=133MHz; VDD=3.465V, RIREF=475, IOH=6IREF 260 fHOST=100MHz; VDD=3.465V, RIREF=475, IOH=6IREF 250 mA PWR_DWN# low, all supplies = 3.465V, RIREF= 475, IOH = 6 x IREF A Digital Inputs (PWR_DWN#, SEL133/100#, SS_EN#) High-Level Input Voltage VIH 2.0 VDD+0.3 V Low-Level Input Voltage VIL VSS-0.3 0.8 V Input Leakage Current IIL -5 +5 A Crystal Oscillator Feedback (XIN) Threshold Bias Voltage VTH 1.5 High-Level Input Current IIH VIH = 3.3V 32 A Low-Level Input Current IIL VIL = 0V -32 A Crystal Loading Capacitance * CL(xtal) As seen by an external crystal connected to XIN and XOUT Input Loading Capacitance * CL(XIN) As seen by an external clock driver on XOUT; XIN unconnected 36 13.5 18 V 22.5 pF pF Crystal Oscillator Drive (XOUT) High Level Output Source Current IOH VI (XIN) = 3.3V, VO = 0V -8.0 mA Low Level Output Sink Current IOL VI (XIN) = 0V, VO = 3.3V 8.7 mA Bias Voltage VOH no load 1.1 Short Circuit Output Source Current IOH VO = 0V Current Reference (IREF) V mA MREF_P, MREF_N, CK66_0:3, PCI_0:9 Clock Outputs (Type 5 Clock Driver) IOH min VDD_M, VDD_66, VDD_P = 3.135V, VO = 1.0V IOH max VDD_M, VDD_66, VDD_P = 3.465V, VO = 3.135V IOL min VDD_M, VDD_66, VDD_P = 3.135V, VO = 1.95V IOL max VDD_M, VDD_66, VDD_P = 3.465V, VO = 0.4V zOL Measured at 1.65V, output driving low 12 55 zOH Measured at 1.65V, output driving high 12 55 High Level Output Source Current Low Level Output Sink Current Output Impedance -33 mA -33 30 mA 38 10 A Tristate Output Current IOZ Short Circuit Output Source Current IOSH VO = 0V; shorted for 30s, max. -51 mA Short Circuit Output Sink Current IOSL VO = 3.3V; shorted for 30s, max. 62 mA ISO9001 -10 9.18.00 7 FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 Table 13: DC Electrical Specifications, continued Unless otherwise stated, all power supplies = 3.3V 5%, no load on any output, and ambient temperature range TA = 0C to 70C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 f rom typical. Negative currents indicate current flows out of the device. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS 55 %VOH HOST_P1:4, HOST_N1:4 Clock Outputs (Type X1 Clock Driver) Crossover Voltage VX High-Level Output Source Current IOH Output Source Current Tolerance IOH Output Impedance zOH Tristate Output Current IOZ RS = 33.2, RP = 49.9, RIREF = 475, IOH = 6 x IREF 45 VO = 0.65V, RIREF = 475, IOH = 6 x IREF 12.9 VO = 0.74V, RIREF = 475, IOH = 6 x IREF 14.9 VDD = 3.3V, over settings in Table 7 -7 +7 VDD_I = 3.3V5%, over settings in Table 7 -12 +12 VO/IO, where VO1 = 1.0V, VO2 = VSS, RIREF = 475, IOH = 6 x IREF mA %IOH 3000 -10 10 A V REF_0 / ISEL_0, REF_1 / ISEL_1 Clock Driver I/O, (Type 3) CK48_0 / SEL_A, CK48_1 / SEL_B Clock Driver I/O (Type 3) VIH 2.0 VDD+0.3 Low-Level Input Voltage VIL VSS-0.3 0.8 V 5 A Input High-Level Input Voltage High-Level Input Current IIH Low-Level Input Current (pull-up) IIL VIL = 0.4V -9 A High Level Output Source Current IOH VDD_R, VDD_48 = 3.465V, VO = 2.4V -32 mA Low Level Output Sink Current IOL VDD_R, VDD_48 = 3.465V, VO = 0.4V 13 mA zOL Measured at 1.65V, output driving low 20 60 zOH Measured at 1.65V, output driving high 20 60 -10 10 Output Output Impedance Tristate Output Current IOZ A Short Circuit Output Source Current IOSH VO = 0V; shorted for 30s, max. -41 mA Short Circuit Output Sink Current IOSL VO = 3.3V; shorted for 30s, max. 40 mA Figure 5: DC Measurement Diagram Figure 6: AC Measurement Diagram VDD = 3.3V VOH = 2.4V VOL = 0.4V tr tf 3.3V VIH = 2.0V 2.4V 1.5V VIL = 0.8V 0.4V dt Figure 7: HOST Clock VX Crossover Point Figure 8: HOST Clock Test Circuit HOST_P From output under test VX Test node RS RP HOST_N ISO9001 9.18.00 8 FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 Table 14: AC Timing Specifications Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 f rom typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS Overall Spread Spectrum Modulation Frequency * fm SS_EN# low 31.5 kHz Spread Spectrum Modulation Index * m SS_EN# low -0.5 % Clock Offset tpd CK66 leads @ 1.5V, CL=30pF to PCI @ 1.5V, CL = 30pF (measured on rising edges) 1.5 3.5 ns Output Tristate Enable Delay * tDZL, tDZH SEL_A:B = 00, SEL133/100# = 0 1.0 10 ns Output Tristate Disable Delay * tDLZ, tDHZ SEL_A:B = 11, SEL133/100# = 0 1.0 10 ns via PWR_DWN# 3.0 ms HOST pair to HOST pair @ VX, RIREF = 475, IOH = 6 x IREF, RS = 33.2, RP = 49.9 150 ps 55 % 200 ps 450 ps 20 % 55 % 250 ps Power-up PLL Lock Time tL HOST_P1:4, HOST_N1:4 Clock Outputs Clock Skew * tsk(o) Duty Cycle * dt Jitter, Period (peak-peak) * Rise Time * Ratio of high pulse width to one clock period at VX, RIREF = 475, IOH = 6 x IREF, RS=33.2, RP=49.9 tj(P) Rising edge to rising edge at VX, RIREF = 475, IOH = 6 x IREF RS = 33.2, RP = 49.9 tr Measured at 20% - 80% of VOH; RIREF = 475, IOH = 6 x IREF RS = 33.2, RP = 49.9 45 175 Measured at 20% - 80% of VOH; RIREF = 475, IOH = 6 x IREF RS = 33.2, RP = 49.9 Rise/Fall Time Matching* MREF_P, MREF_N Clock Outputs Duty Cycle * Jitter, Period (peak-peak) * Rise Time * Fall Time * ISO9001 dt Ratio of high pulse width to one clock period, measured at 1.5V tj(P) From rising edge to rising edge at 1.5V, CL=30pF tr min Measured @ 0.4V - 2.4V; CL=10pF tr max Measured @ 0.4V - 2.4V; CL=30pF tf min Measured @ 2.4V - 0.4V; CL=10pF tf max Measured @ 2.4V - 0.4V; CL=30pF 45 0.4 1.6 0.4 1.6 ns ns 9.18.00 9 FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 Table 15: AC Timing Specifications, continued Unless otherwise stated, all power supplies = 3.3V, no load on any output, and ambient temperature TA = 25C. Parameters denoted with an asterisk ( * ) represent nominal characterization data and are not currently production tested to any specific limits. MIN and MAX characterization data are 3 f rom typical. Spread spectrum modulation is disabled except for Rise/Fall time measurements. PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN. TYP. MAX. UNITS 55 % PCI_0:9 Clock Outputs Ratio of high pulse width to one clock period, measured at 1.5V 45 Duty Cycle * dt Clock Skew * tsk(o) One clock output relative to another at 1.5V 500 ps Jitter, Period (peak-peak) * tj(P) From rising edge to rising edge at 1.5V, CL = 30pF 500 ps Rise Time * Fall Time * tr min Measured at 0.4V - 2.4V; CL = 10pF tr max Measured at 0.4V - 2.4V; CL = 30pF tf min Measured at 2.4V - 0.4V; CL = 10pF tf max Measured at 2.4V - 0.4V; CL = 30pF 0.5 2.0 0.5 2.0 ns ns CK66_0:3 Clock Outputs Ratio of high pulse width to one clock period, measured at 1.5V Duty Cycle * dt Clock Skew * tsk(o) One clock output relative to another at 1.5V Jitter, Period (peak-peak) * tj(P) From rising edge to rising edge at 1.5V, CL = 30pF tr min Measured at 0.4V - 2.4V; CL = 10pF tr max Measured at 0.4V - 2.4V; CL = 30pF tf min Measured at 2.4V - 0.4V; CL = 10pF tf max Measured at 2.4V - 0.4V; CL = 30pF Rise Time * Fall Time * 45 55 % 250 ps 300 ps 0.5 2.0 0.5 2.0 ns ns REF_0:1 Clock Outputs Duty Cycle * Jitter, Period (peak-peak) * Rise Time * Fall Time * dt Ratio of high pulse width to one clock period, measured at 1.5V tj(P) From rising edge to rising edge at 1.5V, CL = 20pF tr min Measured at 0.4V - 2.4V; CL = 10pF tr max Measured at 0.4V - 2.4V; CL = 20pF tf min Measured at 2.4V - 0.4V; CL = 10pF tf max Measured at 2.4V - 0.4V; CL = 20pF 45 55 % 1000 ps 1.0 4.0 1.0 4.0 ns ns CK48_0:1 Clock Outputs Duty Cycle * Jitter, Period (peak-peak) * Rise Time * Fall Time * ISO9001 dt Ratio of high pulse width to one clock period, measured at 1.5V tj(P) From rising edge to rising edge at 1.5V, CL = 20pF tr min Measured at 0.4V - 2.4V; CL = 10pF tr max Measured at 0.4V - 2.4V; CL = 20pF tf min Measured at 2.4V - 0.4V; CL = 10pF tf max Measured at 2.4V - 0.4V; CL = 20pF 45 55 % 350 ps 1.0 4.0 1.0 4.0 ns ns 9.18.00 10 FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 Table 16: MCLK_P, MCLK_N, PCI_0:9, CK66_0:3 Clock Outputs High Drive Current (mA) MIN. TYP. MAX. Voltage (V) 0 0 0 0 0.2 11 17 0.4 21 32 0.6 30 0.8 Voltage (V) Low Drive Current (mA) MIN. TYP. MAX. 150 0 -49 -83 -132 125 24 0.2 -48 -83 -131 100 45 0.4 -48 -82 -130 45 64 0.6 -47 -81 -129 37 56 79 0.8 -47 -80 -127 1.0 43 65 92 1.0 -46 -79 -126 1.2 47 73 103 1.2 -46 -78 -124 1.4 50 78 112 1.4 -45 -76 -121 1.6 53 82 117 1.6 -43 -74 -117 1.8 54 84 120 1.8 -41 -70 -112 2.0 55 85 121 2.0 -37 -65 -105 2.2 55 85 122 2.2 -33 -59 -97 2.4 55 86 123 2.4 -28 -52 -87 -125 2.6 56 86 123 2.6 -22 -43 -74 -150 2.8 56 86 124 2.8 -14 -32 -60 3.0 56 87 124 3.0 -6 -20 -45 87 124 3.2 -7 -27 125 3.4 3.2 3.4 -7 Output Current (mA) 75 50 25 0 -25 0 0.5 1 1.5 2 2.5 3 3.5 -50 -75 -100 30 50 Output Voltage (V) 90 Data in this table represents nominal characterization data only Table 17: REF_0:1, CK48_0:1 Clock Outputs Voltage (V) High Drive Current (mA) MIN. TYP. MAX. Voltage (V) 0 0 0 0.2 8 13 0.4 15 24 0.6 22 0.8 Low Drive Current (mA) MIN. TYP. MAX. 120 0 -38 -64 -102 100 18 0.2 -37 -64 -101 80 33 0.4 -37 -63 -100 33 47 0.6 -37 -63 -99 27 41 58 0.8 -36 -62 -98 1.0 31 48 68 1.0 -36 -61 -97 1.2 35 53 76 1.2 -35 -60 -95 1.4 37 57 82 1.4 -34 -59 -93 1.6 39 60 86 1.6 -33 -57 -90 1.8 39 61 88 1.8 -31 -54 -87 2.0 40 62 89 2.0 -29 -50 -81 2.2 40 63 90 2.2 -25 -46 -75 2.4 41 63 90 2.4 -21 -40 -67 -100 2.6 41 63 90 2.6 -17 -33 -57 -120 2.8 41 63 91 2.8 -11 -25 -47 3.0 41 64 91 3.0 -5 -16 -34 64 91 3.2 -6 -21 91 3.4 3.2 3.4 ISO9001 -5 60 Output Current (mA) 0 40 20 0 -20 0 0.5 1 1.5 2 2.5 3 3.5 -40 -60 -80 30 Output Voltage (V) 50 90 Data in this table represents nominal characterization data only 9.18.00 11 FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 7.0 Package Information Table 18: 56-pin SSOP (0.300") Package Dimensions DIMENSIONS INCHES A 56 MILLIMETERS MIN. MAX. MIN. MAX. 0.095 0.110 2.41 2.79 A1 0.008 0.016 0.20 0.41 b 0.008 0.0135 0.20 0.34 c 0.005 0.010 0.13 0.25 D 0.720 0.730 18.29 18.54 E 0.395 0.420 10.03 10.67 E1 0.291 0.299 7.39 7.59 e 0.025 BSC E1 E AMERICAN MICROSYSTEMS, INC. 1 b SEATING PLANE e h x 45 0.64 BSC h 0.015 0.025 0.38 0.64 L 0.020 0.040 0.51 1.01 0 8 0 8 A D A1 c L Table 19: 56-pin SSOP (0.300") Package Characteristics PARAMETER Thermal Impedance, Junction to Free-Air Lead Inductance, Self SYMBOL JA L11 L12 Lead Inductance, Mutual L13 Lead Capacitance, Bulk C11 C12 Lead Capacitance, Mutual C13 ISO9001 CONDITIONS/DESCRIPTION Air flow = 0 m/s TYP. UNITS 73 C/W Longest trace + wire 6.41 Shortest trace + wire 2.49 Longest trace + wire to first adjacent trace 3.65 Shortest trace + wire to first adjacent trace 1.35 Longest trace + wire to next adjacent trace 2.50 Shortest trace + wire to next adjacent trace 0.90 Longest trace + wire to VSS 0.94 Shortest trace + wire to VSS 0.50 Longest trace + wire to first adjacent trace 0.48 Shortest trace + wire to first adjacent trace 0.20 Longest trace + wire to next adjacent trace 0.07 Shortest trace + wire to next adjacent trace 0.02 nH nH pF pF 9.18.00 12 FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 Table 20: 56-pin TSSOP (6.1mm) Package Dimensions DIMENSIONS INCHES MIN. MILLIMETERS MAX. MIN. MAX. A - 0.047 - 1.20 A1 0.002 0.006 0.05 0.15 b 0.0067 0.011 0.17 0.27 c 0.0035 0.008 0.09 0.20 D 0.547 0.555 13.9 14.1 E E1 e 0.318 BSC 0.236 0.244 56 E1 E AMERICAN MICROSYSTEMS, INC. 8.10 BSC 6.00 0.019 BSC 6.20 1 0.50 BSC L 0.018 0.030 0.45 0.75 S 0.008 - 0.20 - 1 0 8 0 8 2 12 REF 12 REF 3 12 REF 12 REF b SEATING PLANE e A D A1 2 S c 3 L 1 Table 21: 56-pin TSSOP (6.1mm) Package Characteristics PARAMETER SYMBOL Thermal Impedance, Junction to Free-Air JA Lead Inductance, Self L11 L12 Lead Inductance, Mutual L13 Lead Capacitance, Bulk C11 C12 Lead Capacitance, Mutual C13 ISO9001 CONDITIONS/DESCRIPTION Air flow = 0 m/s TYP. UNITS 81 C/W Longest trace + wire 4.04 Shortest trace + wire 1.38 Longest trace + wire to first adjacent trace 2.20 Shortest trace + wire to first adjacent trace 0.72 Longest trace + wire to next adjacent trace 1.43 Shortest trace + wire to next adjacent trace 0.48 Longest trace + wire to VSS 0.63 Shortest trace + wire to VSS 0.21 Longest trace + wire to first adjacent trace 0.31 Shortest trace + wire to first adjacent trace 0.07 Longest trace + wire to next adjacent trace 0.04 Shortest trace + wire to next adjacent trace 0.01 nH nH pF pF 9.18.00 13 FS6232-01 Two-Way MP Motherboard Clock Generator IC AMERICAN MICROSYSTEMS, INC. September 2000 8.0 Ordering Information Table 22: Device Ordering Codes DEVICE NUMBER ORDERING CODE PACKAGE TYPE 11995-801 FS6232-01 0 C to 70 C (Commercial) 56-pin (6.1mm) TSSOP 11995-211 SHIPPING CONFIGURATION Tape and Reel 56-pin (0.300") SSOP 11995-811 11995-201 OPERATING TEMPERATURE RANGE Tubes Tape and Reel Tubes Copyright (c) 2000 American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796, WWW Address: http://www.amis.com E-mail: tgp@amis.com ISO9001 9.18.00 14