January 2005
Copyright © Alliance Semiconductor. All rights reserved.
AS7C4096
AS7C34096
5V/3.3V 512K × 8 CMOS SRAM
®
1/13/05; v.1.9 Alliance Semiconductor P. 1 of 9
Features
• AS7C4096 (5V version)
• AS7C34096 (3.3V version)
• Industrial and commercial temperature
• Organization: 524,288 words × 8 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 5/6/7/8 ns output enable access time
• Low power consumption: ACTIVE
- 1375 mW (AS7C4096) / max @ 12 ns
- 576 mW (AS7C34096) / max @ 10 ns
• Low power consumption: STANDBY
- 110 mW (AS7C4096) / max CMOS
- 72 mW (AS7C34096) / max CMOS
• Equal access and cycle times
• Easy memory expansion with
CE
,
OE
inputs
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 100 mA
Logic block diagram
524,288 × 8
Array
(4,194,304)
Sense amp
Input buffer
I/O8
I/O1
OE
CE
WE
Column decoder
Row decoder
Control
Circuit
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A8
A10
A11
A12
A13
A14
A15
A16
A17
A18
A9
Pin arrangements
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
A15
OE
I/O8
I/O7
GND
V
CC
I/O6
I/O5
A14
A13
A12
A11
A10
NC
A0
A1
A2
A3
A4
CE
I/O1
I/O2
V
CC
GND
I/O3
I/O4
WE
A5
A6
A7 17
18
A8
A9
36
35
34
33
NC
A18
A17
A16
GND
V
CC
I/O6
I/O5
NC
A14
A13
A12
A11
A10
A4
CE
I/O1
I/O2
V
CC
GND
I/O3
I/O4
WE
A5
A6
A7
A8
A9
I/O8
I/O7
A1
A2
A3
A0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
43
42
41
44
A16
A15
A17
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
2
3
4
1
NC
NC
NC
NC
NC
NC NC
NC
NC
OE
A18
36-pin SOJ (400 mil) 44-pin TSOP 2
Selection guide
–10 –12 –15 –20 Unit
Maximum address access time 10 12 15 20 ns
Maximum outputenable access time 5 6 7 8 ns
Maximum operating current AS7C4096 – 250 220 180 mA
AS7C34096 160 130 110 100 mA
Maximum CMOS standby current AS7C4096 – 20 20 20 mA
AS7C34096 20 20 20 20 mA
®
AS7C4096
AS7C34096
1/13/05; v.1.9 Alliance Semiconductor P. 2 of 9
Functional description
The AS7C4096 and AS7C34096 are high-performance CMOS 4,194,304-bit Static Random Access Memory (SRAM) devices
organized as 524,288 words × 8 bits. They are designed for memory applications where fast data access, low power, and simple
interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/7/8 ns are
ideal for high-performance applications. The chip enable input CE permits easy memory expansion with multiple-bank
memory systems.
When CE is high the device enters standby mode. The AS7C4096/AS7C34096 is guaranteed not to exceed 110/72 mW power
consumption in CMOS standby mode.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O1–I/O8 is
written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/
O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. The chip
drives I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or
write enable is active, output drivers stay in high-impedance mode.
All chip inputs and outputs are TTL-compatible, and operation is from either a single 5V(AS7C4096) or 3.3V(AS7C34096)
supply. Both devices are available in the JEDEC standard 400-mil 36-pin SOJ and 44-pin TSOP 2 packages.
NOTE: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and func-
tional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Key: X = Don’t care, L = Low, H = High
Absolute maximum ratings
Parameter Device Symbol Min Max Unit
Voltage on VCC relative to GND AS7C4096 Vt1 –1 +7.0 V
AS7C34096 Vt1 –0.5 +5.0 V
Voltage on any pin relative to GND Vt2 –0.5 VCC +0.5 V
Power dissipation PD–1.0W
Storage temperature Tstg –65 +150 °C
Temperature with VCC applied Tbias –55 +125 °C
DC current unto output (low) IOUT –20mA
Truth table
CE WE OE Data Mode
H X X High Z Standby (ISB, ISB1)
L H H High Z Output disable (ICC)
LHL D
OUT Read (ICC)
LLX D
IN Write (ICC)
®
AS7C4096
AS7C34096
1/13/05; v.1.9 Alliance Semiconductor P. 3 of 9
Recommended operating condition
Parameter Device Symbol Min Nominal Max Unit
Supply voltage
AS7C4096 VCC(12/15/20) 4.5 5.0 5.5 V
AS7C34096 VCC (10) 3.15 3.30 3.6 V
AS7C34096 VCC(12/15/20) 3.0 3.3 3.6 V
Input voltage
AS7C4096 VIH 2.2 – VCC + 0.5 V
AS7C34096 VIH 2.0 – VCC + 0.5 V
VIL1
1 VIL min = –1.0V for pulse width less than 5ns.
–0.5 – 0.8 V
Ambient operating
temperature
commercial TA0– 70°C
industrial TA–40 – 85 °C
DC operating characteristics (over the operating range)1
Parameter Symbol Test condit ions Device
–10 –12 –15 –20
UnitMin Max Min Max Min Max Min Max
Input leakage
current |ILI|V
CC = Max, VIN = GND to VCC
AS7C4096/
AS7C34096 –1–1–1–1µA
Output
leakage
current
|ILO|VCC = Max, CE = VIH
VOUT= GND to VCC
AS7C4096/
AS7C34096 –1–1–1–1µA
Operating
power supply
current
ICC
VCC = Max, CE < VIL
f = fMax, IOUT = 0mA
AS7C4096 – – – 250 – 220 – 180 mA
AS7C34096 – 160 – 130 – 110 – 100
Standby
power supply
current
ISB
VCC = Max, CE = VIH
f = fMax, IOUT = 0mA
AS7C4096– – –60–60–60
mA
AS7C34096 – 60 – 60 – 60 – 60
ISB1
VCC = Max,
CE ≥ VCC – 0.2V, VIN ≤ 0.2V or VIN
≥ VCC – 0.2V, f = 0
AS7C4096– – –20–20–20
mA
AS7C34096 – 20 – 20 – 20 – 20
Output
voltage
VOL IOL = 8 mA, VCC = Min AS7C4096/
AS7C34096
–0.4–0.4–0.4–0.4V
VOH IOH = –4 mA, VCC = Min 2.4–2.4–2.4–2.4– V
Capacitance (f = 1MHz, TA= 25° C, VCC = NOMINAL)2
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A, CE, WE, OE VIN = 0V 5 pF
I/O capacitance CI/O I/O VIN = VOUT = 0V 7 pF
®
AS7C4096
AS7C34096
1/13/05; v.1.9 Alliance Semiconductor P. 4 of 9
Key to switching waveforms
Read waveform 1 (address controlled)3,6,7,9
Read waveform 2 (CE, OE controlled)3,6,8,9
Read cycle (over the operating range)3,9
Parameter
Symbo
l
–10 –12 –15 –20
Unit NotesMin Max Min Max Min Max Min Max
Read cycle time tRC 10–12–15–20–ns
Address access time tAA –10–12–15–20ns3
Chip enable (CE) access time tACE –10–12–15–20ns3
Output enable (OE) access time tOE –5–6–7–8ns
Output hold from address change tOH 3–3–3–3–ns5
CE Low to output in low Z tCLZ 3–3–0–0–ns4, 5
CE High to output in high Z tCHZ –5–6–7–9ns4, 5
OE Low to output in low Z tOLZ 0–0–0–0–ns4, 5
OE High to output in high Z tOHZ –5–6–7–9ns4, 5
Power up time tPU 0–0–0–0–ns4, 5
Power down time tPD –10–12–15–20ns4, 5
Undefined/don’t careFalling inputRising input
Address
D
OUT
Data valid
t
OH
t
AA
t
RC
current
Supply
OE
D
OUT
t
OE
t
OLZ
t
ACE
t
CHZ
t
CLZ
t
PU
t
PD
I
CC
I
SB
50% 50%
t
OHZ
Data valid
t
RC1
CE
®
AS7C4096
AS7C34096
1/13/05; v.1.9 Alliance Semiconductor P. 5 of 9
Write waveform 1 (WE controlled)10,11
Write waveform 2 (CE controlled)10,11
Write cycle (over the operating range)11
Parameter Symbol
–10 –12 –15 –20
Unit NotesMin Max Min Max Min Max Min Max
Write cycle time tWC 10–12–15–20–ns
Chip enable (CE) to write end tCW 7 – 8 –10–12–ns
Address setup to write end tAW 7 – 8 –10–12–ns
Address setup time tAS 0–0–0–0–ns
Write pulse width (OE = high) tWP1 7 – 8 –10–12–ns
Write pulse width (OE = low tWP2 10–12–15–20–ns
Address hold from end of write tAH 0–0–0–0–ns
Write recovery time tWR 0–0–0–0–ns
Data valid to write end tDW 5–6–7–9–ns
Data hold time tDH 0–0–0–0–ns4, 5
Write enable to output in high Z tWZ 05060709ns4, 5
Output active from write end tOW 3–3–3–3–ns4, 5
t
AW
t
AH
t
WC
Address
WE
D
OUT
t
DH
t
OW
t
DW
t
WZ
t
WP
t
AS
Data valid
D
IN
t
WR
t
AW
Address
CE
WE
D
OUT
t
CW
t
WP
t
DW
t
DH
t
AH
t
WZ
t
WC
t
AS
Data valid
D
IN
t
WR
®
AS7C4096
AS7C34096
1/13/05; v.1.9 Alliance Semiconductor P. 6 of 9
AC test conditions
Notes
1During V
CC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
2 This parameter is sampled, but not 100% tested.
3 For test conditions, see AC Test Conditions.
4t
CLZ and tCHZ are specified with CL = 5pF as in Figure C. Transition is measured ±500 mV from steady-state voltage.
5 This parameter is guaranteed, but not tested.
6WE
is HIGH for read cycle.
7CE
and OE are LOW for read cycle.
8 Address valid prior to or coincident with CE transition Low.
9 All read cycle timings are referenced from the last valid address to the first transitioning address.
10 CE or WE must be HIGH during address transitions. Either CE or WE asserting high terminates a write cycle.
11 All write cycle timings are referenced from the last valid address to the first transitioning address.
12 Not applicable.
13 C = 30pF, except at high Z and low Z parameters, where C = 5pF.
350
Ω
C
13
320
Ω
D
OUT
GND
+3.3V
Figure C: 3.3V Output load
- Output load: see Figure B or Figure C.
- Input pulse level: GND to 3.0V. See Figures A, B, and C.
- Input rise and fall times: 2 ns. See Figure A.
- Input and output timing reference levels: 1.5V.
168
Ω
Thevenin equivalent:
D
OUT
+1.728V
255
Ω
C
13
480
Ω
D
OUT
GND
+5V
Figure B: 5V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
2 ns
®
AS7C4096
AS7C34096
1/13/05; v.1.9 Alliance Semiconductor P. 7 of 9
Typical DC and AC characteristics 12
Supply voltage (V)
MIN MAX
NOMINAL
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized I
CC
, I
SB
Normalized supply current I
CC
, I
SB
Ambient temperature (
°
C)
–55 80 12535–10
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized I
CC
, I
SB
Normalized supply current I
CC
, I
SB
vs. ambient temperature T
a
vs. supply voltage V
CC
I
CC
I
SB
I
CC
I
SB
Ambient temperature (
°
C)
–55 80 125
35–10
0.2
1
0.04
5
25
625
Normalized I
SB1
(log scale)
Normalized supply current I
SB1
vs. ambient temperature T
a
V
CC
= V
CC
(NOMINAL)
Supply voltage (V)
MIN MAX
NOMINAL
0.8
0.9
1.1
1.2
1.0
1.3
1.4
1.5
Normalized access time
Normalized access time t
AA
Ambient temperature (
°
C)
–55 80 125
35–10
0.8
0.9
1.1
1.2
1.0
1.3
1.4
1.5
Normalized access time
Normalized access time t
AA
Cycle frequency (MHz)
075
100
5025
0.0
0.2
0.6
0.8
0.4
1.0
1.2
1.4
Normalized I
CC
Normalized supply current I
CC
vs. ambient temperature T
a
vs. cycle frequency 1/t
RC
, 1/t
WC
vs. supply voltage V
CC
V
CC
= V
CC
(NOMINAL) V
CC
= V
CC
(NOMINAL)
T
a
= 25
°
C
T
a
= 25
°
C
Output voltage (V) V
CC
0
20
60
80
40
100
120
140
Output source current (mA)
Output source current I
OH
Output voltage (V) V
CC
Output sink current (mA)
Output sink current I
OL
vs. output voltage V
OL
vs. output voltage V
OH
0
20
60
80
40
100
120
140
Capacitance (pF)
0750 1000500250
0
5
15
20
10
25
30
35
Change in t
AA
(ns)
Typical access time change
∆
t
AA
vs. output capacitive loading
00
V
CC
= V
CC
(NOMINAL) V
CC
= V
CC
(NOMINAL) V
CC
= V
CC
(NOMINAL)
T
a
= 25
°
C T
a
= 25
°
C
®
AS7C4096
AS7C34096
1/13/05; v.1.9 Alliance Semiconductor P. 8 of 9
Package dimensions
44-pin TSOP 2
Min (mm) Max (mm)
A1.2
A10.05 0.15
A20.95 1.05
b0.30 0.45
c0.12 0.21
d18.31 18.52
e10.06 10.26
He11.68 11.94
E0.80 (typical)
l0.40 0.60
36-pin SOJ 400
Min(mm) Max(mm)
A.128 0.148
A10.025 –
A20.105 0.115
b0.015 0.020
b10.026 0.032
c0.007 0.013
D.920 .930
e0.045 0.055
E1 0.395 0.405
E2 0.435 0.445
E0.370 BSC
Seating
Plane
D
Pin 1
e
E
1
E
2
A2
c
A1
b
1
b
A
E
36-pin SOJ
d
H
e
1234567891011121314
44 43424140393837363534333231
1516
3029
1718 1920
272625
c
l
A
1
A
2
E
44-pin TSOP 2
0–5
°
21
24
22
23
e
A
b
28
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marks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document.
The data contained herein represents Alliance’s best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under
development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate
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®
AS7C4096
AS7C34096
1/13/05; v.1.9 Alliance Semiconductor P. 9 of 9
Note:
Add suffix “N” to the above part number for lead free devices, Ex. AS7C4096-12JCN
Ordering codes
Package Version 10 ns 12 ns 15 ns 20 ns
SOJ
5V commercial NA AS7C4096-12JC AS7C4096-15JC AS7C4096-20JC
5V industrial NA AS7C4096-12JI AS7C4096-15JI AS7C4096-20JI
3.3V commercial AS7C34096-10JC AS7C34096-12JC AS7C34096-15JC AS7C34096-20JC
3.3V industrial NA AS7C34096-12JI AS7C34096-15JI AS7C34096-20JI
TSOP 2
5V commercial NA AS7C4096-12TC AS7C4096-15TC AS7C4096-20TC
5V industrial NA AS7C4096-12TI AS7C4096-15TI AS7C4096-20TI
3.3V commercial AS7C34096-10TC AS7C34096-12TC AS7C34096-15TC AS7C34096-20TC
3.3V industrial NA AS7C34096-12TI AS7C34096-15TI AS7C34096-20TI
Part numbering system
AS7C X 4096 –XX J or T X N
SRAM prefix
Voltage:
Blank: 5V CMOS
3: 3.3V CMOS
Device
number
Access
time
Packages:
J: SOJ 400 mil
T: TSOP 2
Temperature ranges:
C: Commercial, 0°C to 70°C
I: Industrial, –40°C to 85°C
Lead free device