K3P7V(U)1000B-GC, K3P7V(U)1000B-TC, K3P7 - Samsung Electronics

K3P7V(U)1000B-FC CMOS MASK ROM

Preliminary Information

64M-Bit (8Mx8 /4Mx16) CMOS MASK ROM

The K3P7V(U)1000B-FC is a fully static mask programmable

ROM fabricated using silicon gate CMOS process technology,

and is organized either as 8,388,608 x 8 bit(byte mode) or as

4,194,304 x 16 bit(word mode) depending on BHE voltage level.

This device includes page read mode function, page read mode

allows 8 words (or 16 bytes) of data to be read fast in the same

page, CE and A3 ~ A21 should not be changed.

This device operates with 3.0V or 3.3V power supply, and all

inputs and outputs are TTL compatible.

Because of its asynchronous operation, it requires no external

clock assuring extremely easy operation.

It is suitable for use in program memory of microprocessor, and

operating system and/or application software storage for hand-

held application.

The K3P7V(U)1000B-FC is packaged in a 48-CSP with 0.75mm

ball pitch and 6x8 ball array.

GENERAL DESCRIPTIONFEATURES

• Switchable organization

8,388,608 x 8(byte mode)

4,194,304 x 16(word mode)

• Fast access Time

Random Access Time/Page Access Time

3.3V Operation : 100/30ns(max.)

3.0V Operation : 120/40ns(max.)

• 8 words / 16bytes page access

• Supply voltage

VCC : single +3.3V/ single +3.0V

VCCQ : equal to VCC

• Temperature : 0°C ~ +70°C

• Current consumption

Operating(ICC) : 60mA (max)

Standby(ISB2) : 50uA (max)

• Fully static operation

• All inputs and outputs TTL compatible

• Package

K3P7V(U)1000B-FC : 48-CSP with 0.75mm ball pitch

A21 X

A0~A2

AND

DECODER

BUFFERS

AND

DECODER

BUFFERS

MEMORY CELL

SENSE AMP.

CONTROL

LOGIC

MATRIX

(4,194,304x16/

8,388,608x8)

DATA OUT

BUFFERS

A-1

BHE

Q0/Q8Q7/Q15

. . .

FUNCTIONAL BLOCK DIAGRAM

Pin Name Pin Function

A0 - A2Page Address Inputs

A3 - A21 Address Inputs

Q0 - Q14 Data Outputs

Q15 /A-1 Output 15(Word mode)/

LSB Address(Byte mode)

BHE Word/Byte selection

CE Chip Enable

OE Output Enable

VCC Power

VCCQ Data Output Power ( =VCC)

VSS Ground

NC No Connection

K3P7V(U)1000B-FC CMOS MASK ROM

Preliminary Information

48FP-BGA PIN CONFIGURATION (TOP VIEW)

Note : See last page for package dimension.

ABSOLUTE MAXIMUM RATINGS

NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be

restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating

conditions for extended periods may affect device reliability.

Item Symbol Rating Unit

Voltage on Any Pin Relative to VSS VIN -0.3 to +4.5 V

Temperature Under Bias TBIAS -10 to +85 °C

Storage Temperature TStg -55 to +150 °C

Operating Temperature TA0 to +70 °C

RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA = 0 to 70°C)

Item Symbol Min Typ Max Unit

Supply Voltage VCC/VCCQ 2.7/3.0 3.0/3.3 3.3/3.6 V

Supply Voltage VSS 000V

N.C* : will be MSB Address for the 128Mbit.

1 23456

A14 A10 N.C A20 A6 A2

A13 A11 A19 N.C A7 A3

A15 A12 A8 A21 A5 A4

D15/ A9 A18 VCCQ A17 OE

Vss D6 VCC D2 D9

BHE D7 D5 D10 D0 CE

A16 D14 D12 D11 D8 A0

N.C* D13 D4 D3 D1 A1

Vss

A-1

K3P7V(U)1000B-FC CMOS MASK ROM

Preliminary Information

DC CHARACTERISTICS

NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns.

Maximum DC voltage on input pins(VIH) is VDD+0.3V which, during transitions, may overshoot to VDD+2.0V for periods <20ns.

Parameter Symbol Test Conditions Min Max Unit

Operating Current ICC CE=OE=VIL,

all outputs open VCC=3.3V±0.3V -60 mA

VCC=3.0V±0.3V 50 mA

Standby Current(TTL) ISB1 CE=VIH, all outputs open 500 µA

Standby Current(CMOS) ISB2 CE=VCC, all outputs open 50 µA

Input Leakage Current ILI VIN=0 to VCC -10 µA

Output Leakage Current ILO VOUT=0 to VCC -10 µA

Input High Voltage, All Inputs VIH 2.0 VCC+0.3 V

Input Low Voltage, All Inputs VIL -0.3 0.6 V

Output High Voltage Level VOH IOH=-400µA2.4 -V

Output Low Voltage Level VOL IOL=2.1mA -0.4 V

TEST CONDITIONS

Item Value

Input Pulse Levels 0.45V to 2.4V

Input Rise and Fall Times 10ns

Input and Output Timing Levels 1.5V

Output Loads 1 TTL Gate and CL=100pF

AC CHARACTERISTICS(TA=0°C to +70°C, VCC=3.3V/3.0V±0.3V, VCCQ=VCC, unless otherwise noted.)

MODE SELECTION

CE OE BHE Q15/A-1 Mode Data Power

HX X X Standby High-Z Standby

LHX X Operating High-Z Active

L L HOutput Operating Q0~Q15 : Dout Active

LInput Operating Q0~Q7 : Dout

Q8~Q14 : Hi-Z Active

CAPACITANCE( TA =25°C, f=1.0MHz)

NOTE : Capacitance is periodically sampled and not 100% tested.

Item Symbol Test Conditions Min Max Unit

Output Capacitance COUT VOUT=0V -12 pF

Input Capacitance CIN VIN=0V -12 pF

K3P7V(U)1000B-FC CMOS MASK ROM

Preliminary Information

READ CYCLE

NOTE : Page Address is determined as below.

Word mode (BHE=VIH) : A0, A1, A2

Byte mode (BHE=VIL) : A-1, A0, A1, A2

Item Symbol VCC=3.3V±0.3V VCC=3.0V±0.3V Unit

Min Max Min Max

Read Cycle Time tRC 100 120 ns

Chip Enable Access Time tACE 100 120 ns

Address Access Time tAA 100 120 ns

Page Address Access Time tPA 30 40 ns

Output Enable Access Time tOE 30 40 ns

Output or Chip Disable to Output High-Z tDF 20 20 ns

Output Hold from Address Change tOH 0 0 ns

K3P7V(U)1000B-FC CMOS MASK ROM

Preliminary Information

TIMING DIAGRAM

READ

ADD

DOUT

A0~A21

A-1(*1)

D0~D7

D8~D15(*2)

PAGE READ

ADD

DOUT

ADD

A0,A1,A2

A3~A21

VALID DATA VALID DATA VALID DATA VALID DATA

1 st 2 nd 3 rd

tDF(*3)

ADD1 ADD2

VALID DATA VALID DATA

tOH

tDF(*3)

tRC

tACE

tOE tAA

NOTES :

*1.Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL)

*2. Word Mode only.(BHE = VIH)

*3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.

tAA tPA

A -1(*1)

D0~D7

D8~D15(*2)

≈

≈ ≈

≈

K3P7V(U)1000B-FC CMOS MASK ROM

Preliminary Information

0.65

654321

C/2

B/2

Detail A

B/2

A1 Index Mark

C/2

Side View

Top View

0.77

Detail A

(Typ.)

0.30

(Typ.)

Min Typ. Max

A-0.75 -

B8.90 9.00 9.10

B1 -3.75 -

C8.90 9.00 9.10

C1 -5.25 -

D0.35 0.40 0.45

E1.00 1.10 1.20

E1 0.72 0.77 0.82

E2 0.25 0.30 0.35

Y- - 0.08

Bottom View

Notes.

1. Bump counts : 48 (6 x 8 Array)

2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)

3. All tolerance are +/-0.050 unless

otherwise specified.

4. Typ : Typical

5. Y is coplanarity : 0.08(max)

A1 Index Mark

(Unit : mm)

0.27

PACKAGE DIMENSIONS (48 FP-BGA)