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12/03/04
IRFR3704ZPbF
IRFU3704ZPbF
HEXFET® Power MOSFET
Notes through are on page 11
Applications
Benefits
lVery Low RDS(on) at 4.5V VGS
lUltra-Low Gate Impedance
lFully Characterized Avalanche Voltage
and Current
lHigh Frequency Synchronous Buck
Converters for Computer Processor Power
lHigh Frequency Isolated DC-DC
Converters with Synchronous Rectification
for Telecom and Industrial Use
lLead-Free
PD - 95442A
I-Pak
IRFU3704Z
D-Pak
IRFR3704Z
VDSS RDS(on) max Qg
20V 8.4m
:
9.3nC
Absolute Maximum Ratings
Parameter Units
VDS Dr ain-t o- Source Volt age V
VGS Gat e- to-S ource Voltage
ID @ TC = 25 °C Co nti n uous D r ai n C ur rent, VGS @ 10V A
ID @ TC = 10 0°C Co nti n uous D r ai n C ur rent, VGS @ 10V
IDM Pulsed Dr ain Current
c
PD @TC = 25°C Maximum Power D issi pation W
PD @TC = 100°C Maximum Power D issi pation
Linear Derating Factor W/°C
TJ Operating Junction and °C
TSTG Stor ag e Tem per atur e Ra ng e
Soldering Temperature, for 10 seconds
Thermal Resist ance
Parameter Typ. Max. Units
RθJC Junction-to-Case ––– 3.1 °C/W
RθJA Junc tio n- t o- Am bient ( PC B Moun t )
g
––– 50
RθJA Junction-to-Ambient ––– 110
300 ( 1.6mm fr om ca se)
-55 to + 175
48
0.32
24
Max.
60
f
42
f
240
± 20
20
IRFR/U3704ZPbF
2www.irf.com
S
D
G
Stat ic @ TJ = 25°C (unless otherwise specified)
Parameter Min. Typ. Max. Units
BV
DSS Dr ai n- to- Sour c e B reakd ow n Volta ge 20 ––– ––– V
∆Β
V
DSS
/
∆
T
J Breakdown Vo lt age Temp. Coefficient ––– 0.015 ––– V/°C
R
DS(on) Static Dr ain- to- Sou r c e O n- R e s i s tanc e ––– 6. 7 8.4
Ω
––– 9.2 11.4
V
GS(th) G at e Thr es hold Vol t age 1. 65 2.1 2.55 V
∆
V
GS(th)
/
∆
T
J G ate Thr es hold V o ltage C oe f fic ient ––– -5 .5 ––– m V / °C
I
DSS Dr ai n- to- Sour c e Leak age Cu r rent ––– ––– 1.0 µA
––– ––– 150
I
GSS Gate-to- Sou r c e For war d Leak age ––– ––– 100 nA
Gate- to- Sour c e R ev e r s e Leaka ge ––– ––– -100
gfs For ward Tra nsconductance 41 ––– ––– S
Q
gTotal Gate Charge ––– 9.3 14
Q
gs1 Pre-Vth Gate-to-Source Charge ––– 3.0 –––
Q
gs2 Post - Vt h G ate-t o- Source Cha rge ––– 1.1 –– – n C
Q
gd Gate-to-D r ain Char ge ––– 2.7 –––
Q
godr G ate Cha rge Ov e r dr i ve ––– 2.5 ––– Se e Fi g. 16
Q
sw
Switch Charge (Q
gs2
+ Q
gd
)
––– 3.8 –––
Q
oss Output Charge ––– 5.6 ––– nC
t
d(on) Turn-On Delay Time ––– 41 –––
t
rRise Time ––– 8.9 –––
t
d(off) Turn-Off Delay Time ––– 4.9 ––– ns
t
fFall Time ––– 12 –––
C
iss Input Capacitance ––– 1190 –––
C
oss Out pu t Capac ita nc e ––– 380 ––– pF
C
rss Reve r s e Tr a ns fer Capac it a nc e ––– 170 –––
Aval anc he Cha racteri stics
Parameter Units
E
AS
Si ngle P ul se Avalanch e E n er g y
d
mJ
I
AR
Avalanche Current
c
A
E
AR
Repeti ti ve Avalanche Ener gy
c
mJ
Diode Charac teri stics
Pa ra me t e r Min. Ty p. Max . Units
I
SContin uous Sour ce Cur rent ––– –––
60
f
(Body Diode) A
I
SM Puls e d Sourc e Curren t ––– ––– 240
(Body Diode)
c
V
SD Diode Forward Voltage ––– ––– 1.0 V
t
rr Reverse Recovery Time –––1319ns
Q
rr Reverse Recovery Charge ––– 4.2 6.3 nC
t
on Forward Turn-On Time Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
VGS = 20V
VGS = -20V
Conditions
4.8
Max.
41
12
ƒ = 1. 0M H z
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 1mA
VGS = 10V, ID = 15A
e
VDS = VGS, ID = 250µ A
VDS =16V, VGS = 0V
VDS = 16V , V GS = 0V , TJ = 12 5°C
Cla m ped I n duc t iv e Load
VDS = 10V , I D = 12A
VDS = 10V , V GS = 0V
VDD = 10V, VGS = 4. 5V
e
ID = 12A
VDS = 10V
TJ = 25°C, IF = 12 A , V DD = 10V
di /dt = 100A/µ s
e
TJ = 25°C, IS = 12A, VGS = 0V
e
showing the
integra l revers e
p-n junct ion diode.
MOSFET symbol
VGS = 4.5V, ID = 12 A
e
–––
VGS = 4.5V
Typ.
–––
–––
ID = 12A
VGS = 0V
VDS = 10V
IRFR/U3704ZPbF
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Fig 4. Normalized On-Resistance
vs. Temperature
Fig 2. Typical Output CharacteristicsFig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics
0.01 0.1 110
VDS, Dr ain-to-Source Volt age (V)
0.001
0.01
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
2.4V
20µs PULSE WIDTH
Tj = 25°C
VGS
TOP 10V
6.0V
4.5V
4.0V
3.3V
2.8V
2.6V
BOTTOM 2.4V
0.01 0.1 110
VDS, Dr ain-to-Source V oltage (V)
0.01
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
2.4V
20µs PU LSE WIDTH
Tj = 175°C
VGS
TOP 10V
6.0V
4.5V
4.0V
3.3V
2.8V
2.6V
BOTTOM 2.4V
2 3 4 5 6 7 8 9
VGS, Gate-to-Source Voltage (V)
0.01
0.1
1
10
100
1000
ID, Drain-to-Source Current (Α)
TJ = 25°C
TJ = 175°C
VDS = 10V
20µs PULSE WIDTH
-60 -40 -20 020 40 60 80 100 120 140 160 180
TJ , Junction Temperat ure (° C)
0.5
1.0
1.5
2.0
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 30A
VGS = 10V
IRFR/U3704ZPbF
4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 6. Typical Gate Charge vs.
Gate-to-Source Voltage
Fig 5. Typical Capacitance vs.
Drain-to-Source Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
110 100
VDS, Drai n-to-Source Vol tage (V)
100
1000
10000
C, Capacitance(pF)
VGS = 0V, f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
02468101214
QG Total Gate Charge (nC)
0.0
1.0
2.0
3.0
4.0
5.0
6.0
VGS, Gate-to-Source Voltage (V)
VDS= 18V
VDS= 10V
ID= 12A
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
VSD, Source-to- Drai n Voltage (V)
0.10
1.00
10.00
100.00
1000.00
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
0 1 10 100
VDS, Dr ain-to-Source V oltage ( V)
1
10
100
1000
ID, Drain-to-Source Current (A)
1msec
10msec
OPERATION IN THIS AREA
LIMITED BY RDS(on)
100µsec
Tc = 25°C
Tj = 175°C
Single Pulse
IRFR/U3704ZPbF
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Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Case
Fig 9. Maximum Drain Current vs.
Case Temperature Fig 10. Threshold Voltage vs. Temperature
25 50 75 100 125 150 175
TC , Case Temperat ure (° C)
0
10
20
30
40
50
60
ID, Drain Current (A)
Lim ited By Package
-75 -50 -25 025 50 75 100 125 150 175 200
TJ , Temperature ( °C )
0.5
1.0
1.5
2.0
2.5
VGS(th) Gate threshold Voltage (V)
ID = 250µA
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration ( sec)
0.001
0.01
0.1
1
10
Thermal Response ( Z thJC )
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE ) Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
τJ
τJ
τ1
τ1τ2
τ2τ3
τ3
R1
R1R2
R2R3
R3
Ci= i/Ri
Ci= τi/Ri
τ
τ
C
τ4
τ4
R4
R4Ri (°C/W) τi (sec)
0.8190 0.000092
1.6018 0.000698
0.6592 0.009033
0.0418 0.046618
IRFR/U3704ZPbF
6www.irf.com
D.U.T. V
D
S
I
D
I
G
3mA
V
GS
.3µF
50KΩ
.2µF
12V
Current Regulator
Same Type as D.U.T.
Current Sampling Resistors
+
-
Fig 13. Gate Charge Test Circuit
Fig 12b. Unclamped Inductive Waveforms
Fig 12a. Unclamped Inductive Test Circuit
tp
V
(BR)DSS
I
AS
Fig 12c. Maximum Avalanche Energy
vs. Drain Current
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
25 50 75 100 125 150 175
Start ing TJ , Junction Temperat ure (° C)
0
20
40
60
80
100
120
140
160
180
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 4.9A
6.5A
BOTTOM12A
Fig 14a. Switching Time Test Circuit
Fig 14b. Switching Time Waveforms
VGS
VDS
9
0%
10%
td(on) td(off)
trtf
VGS
Pu l se Wi dt h < 1µs
Duty Factor < 0.1%
VDD
VDS
LD
D.U.T
+
-
IRFR/U3704ZPbF
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Fig 15. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
R
e-Applied
V
oltage
Reverse
Recovery
Current Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P.W.
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Fig 16. Gate Charge Waveform
Vds
Vgs
Id
Vgs(th)
Qgs1 Qgs2 Qgd Qgodr
IRFR/U3704ZPbF
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Control FET
Special attention has been given to the power losses
in the switching elements of the circuit - Q1 and Q2.
Power losses in the high side switch Q1, also called
the Control FET, are impacted by the Rds(on) of the
MOSFET, but these conduction losses are only about
one half of the total losses.
Power losses in the control switch Q1 are given
by;
Ploss = Pconduction+ Pswitching+ Pdrive+ Poutput
This can be expanded and approximated by;
P
loss =Irms 2×Rds(on)
()
+I×Qgd
ig
×Vin ×f
⎛
⎝
⎜ ⎞
⎠
⎟ +I×Qgs2
ig
×Vin ×
f
⎛
⎝
⎜ ⎞
⎠
⎟
+Qg×Vg×f
()
+Qoss
2×Vin ×f
⎛
⎝ ⎞
⎠
This simplified loss equation includes the terms Qgs2
and Qoss which are new to Power MOSFET data sheets.
Qgs2 is a sub element of traditional gate-source
charge that is included in all MOSFET data sheets.
The importance of splitting this gate-source charge
into two sub elements, Qgs1 and Qgs2, can be seen from
Fig 16.
Qgs2 indicates the charge that must be supplied by
the gate driver between the time that the threshold
voltage has been reached and the time the drain cur-
rent rises to Idmax at which time the drain voltage be-
gins to change. Minimizing Qgs2 is a critical factor in
reducing switching losses in Q1.
Qoss is the charge that must be supplied to the out-
put capacitance of the MOSFET during every switch-
ing cycle. Figure A shows how Qoss is formed by the
parallel combination of the voltage dependant (non-
linear) capacitances Cds and Cdg when multiplied by
the power supply input buss voltage.
Synchronous FET
The power loss equation for Q2 is approximated
by;
P
loss =P
conduction +P
drive +P
output
*
P
loss =Irms
2×Rds(on)()
+Qg×Vg×f
()
+Qoss
2×Vin ×f
⎛
⎝
⎜ ⎞
⎠ +Qrr ×Vin ×
f
(
)
*dissipated primarily in Q1.
For the synchronous MOSFET Q2, Rds(on) is an im-
portant characteristic; however, once again the im-
portance of gate charge must not be overlooked since
it impacts three critical areas. Under light load the
MOSFET must still be turned on and off by the con-
trol IC so the gate drive losses become much more
significant. Secondly, the output charge Qoss and re-
verse recovery charge Qrr both generate losses that
are transfered to Q1 and increase the dissipation in
that device. Thirdly, gate charge will impact the
MOSFETs’ susceptibility to Cdv/dt turn on.
The drain of Q2 is connected to the switching node
of the converter and therefore sees transitions be-
tween ground and Vin. As Q1 turns on and of f there is
a rate of change of drain voltage dV/dt which is ca-
pacitively coupled to the gate of Q2 and can induce
a voltage spike on the gate that is sufficient to turn
the MOSFET on, resulting in shoot-through current .
The ratio of Qgd/Qgs1 must be minimized to reduce the
potential for Cdv/dt turn on.
Power MOSFET Selection for Non-Isolated DC/DC Converters
Figure A: Qoss Characteristic
IRFR/U3704ZPbF
www.irf.com 9
D-Pak (TO-252AA) Part Marking Information
D-Pak (TO-252AA) Package Outline
12
I N THE ASSEMBLY LINE "A"
ASSEMBLED ON WW 16, 1999
EXAMPLE: WITH ASS EMBLY
THIS IS AN IRFR120
LOT C ODE 1234 YEAR 9 = 199
9
DATE CODE
WEEK 16
PART NUM BER
LOGO
INTERNATIONAL
RECTIFIER
AS S EMBLY
LOT CODE
916A
IRFU120
34
YEAR 9 = 1999
DA TE CODE
OR
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
Note: "P" in assembly line position
indicates "Lead-Free"
12 34
WEEK 16
A = AS SEMBL Y SIT E CODE
PART NUMBER
IRFU120
LINE A
LOGO
LOT CODE
AS S EMBLY
INTERNATIONAL
RECTIFIER
IRFR/U3704ZPbF
10 www.irf.com
I-Pak (TO-251AA) Package Outline
Dimensions are shown in millimeters (inches)
I-Pak (TO-251AA) Part Marking Information
ASSEMBLY
EXAMPLE: WITH ASSEMBLY
THIS IS AN IRFU120
YEAR 9 = 199
9
DAT E CODE
LINE A
WEEK 1 9
IN THE ASSEMB LY LINE "A"
ASSEM BLED ON W W 19, 1999
LOT CODE 5678
PART NUMBER
56
IRFU120
INTERNATIONAL
LOGO
RECTIFIER
LOT CODE
919A
78
Note: "P " in assem bly lin e
positi on i ndicates "Lead- F ree"
OR
56 78
AS S E MB L Y
LOT CODE
RECTIFIER
LOGO
INTERNATIONAL
IRFU120
PART NUMBER
WE E K 19
DATE C O DE
YEAR 9 = 1999
A = AS S E MB LY S IT E CODE
P = DESIGNATES LEAD-FREE
PRODUCT (OPTIONAL)
IRFR/U3704ZPbF
www.irf.com 11
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 12/04
Notes:
Repetitive rating; pulse width limited by
max. junction temperature.
Starting TJ = 25°C, L = 0.57mH, RG = 25Ω,
IAS = 12A.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Calculated continuous current based on maximum allowable
junction temperature. Package limitation current is 30A.
When mounted on 1" square PCB (FR-4 or G-10 Material).
For recommended footprint and soldering techniques refer to
application note #AN-994.
D-Pak (TO-252AA) Tape & Reel Information
Dimensions are shown in millimeters (inches)
TR
16.3 ( .641 )
15.7 ( .619 )
8 .1 ( .3 18 )
7 .9 ( .3 12 )
12.1 ( .476 )
11.9 ( .469 ) FEED DIRECTION FEED DIRECTION
16.3 ( .641
)
15.7 ( .619
)
TRR TRL
N
OTES :
1
. CONTROLLING DIMEN SION : MILLIMETER.
2
. AL L D IMENS IONS ARE SHOWN IN M IL L IME TERS ( INCH ES ).
3
. OUTLINE CONFORMS TO EIA-481 & EIA-541.
NOTES :
1. OUTLINE CONFORMS TO EIA-481.
16 mm
13 INCH
Note: For the most current drawings please refer to the IR website at:
http://www.irf.com/package/