S7-400 Instruction List CPU 412, 414, 416, 417 This Instruction List has the order number: 6ES7498-8AA04-8BN0 Edition 12/2004 A5E00267845-02 Copyright Siemens AG 2004 All rights reserved Disclaimer of Liability The reproduction, transmission or use of this document or its contents is not permitted without express written authority. Offenders will be liable for damages. All rights, including rights created by patent grant or registration of a utility model or design, are reserved. We have checked the contents of this manual for agreement with the hardware and software described. Since deviations cannot be precluded entirely, we cannot guarantee full agreement. However, the data in this manual are reviewed regularly and any necessary corrections included in subsequent editions. Suggestions for improvement are welcomed. Siemens AG Bereich Automation and Drives Geschaeftsgebiet Industrial Automation Systems Postfach 4848, D- 90327 Nuernberg Siemens Aktiengesellschaft Siemens AG 2004 Subject to change without prior notice 6ES7498-8AA04-8BN0 Contents Contents Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applicability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Constants and Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Abbreviations and Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Examples of Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Examples of how to calculate the pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Execution Times with Indirect Addressing1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Examples of Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 List of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Bit Logic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Bit Logic Instructions with Parenthetical Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Bit Logic Instructions with Parenthetical Expressions, continued . . . . . . . . . . . . . . . . . . . . . 29 ORing of AND Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Logic Instructions with Timers and Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Word Logic Instructions with the Contents of Accumulator 1 . . . . . . . . . . . . . . . . . . . . . . . . 33 Evaluating Conditions Using AND, OR and EXCLUSIVE OR . . . . . . . . . . . . . . . . . . . . . . . 35 S7-400 Instruction List A5E00267845-02 1 Contents Edge-Triggered Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Setting/Resetting Bit Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Instructions Directly Affecting the RLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Timer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Counter Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Load Instructions for Timers and Counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Load and Transfer Instructions for Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Load and Transfer Instructions for the Status Word . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Load Instructions for DB Number and DB Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Integer Math (16 Bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Integer Math (32 Bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Floating-Point Math (32 Bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Square Root and Square Instructions (32 Bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Logarithmic Function (32 Bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Trigonometrical Functions (32 Bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Adding Constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Adding Using Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 S7-400 Instruction List A5E00267845-02 2 Contents Comparison Instructions (16-Bit Integers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Comparison Instructions (32-Bit Integers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Comparison Instructions (32-Bit Real Numbers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Rotate Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Accumulator Transfer Instructions, Incrementing and Decrementing . . . . . . . . . . . . . . . . . 79 Accumulator Transfer Instructions, Incrementing and Decrementing, continued . . . . . . . . 80 Program Display and Null Operation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Data Type Conversion Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Forming the Ones and Twos Complements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Block Call Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Block End Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Exchanging Shared Data Block and Instance Data Block . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Jump Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Instructions for the Master Control Relay (MCR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 S7-400 Instruction List A5E00267845-02 3 Contents Oganization Blocks (OB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Function Blocks (FB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Functions (FC) and Data Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 System Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 System Function Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Sublist of the System Status List (SSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Alphabetical Index of Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 S7-400 Instruction List A5E00267845-02 4 Applicability Applicability This list of instructions applies to the CPUs listed below. Name Order number CPU 412-1 CPU 412-2 6ES7412-1XF04-0AB0 6ES7412-2XG04-0AB0 CPU 414-2 6ES7414-2XG04-0AB0 CPU 414-3 6ES7414-3XJ04-0AB0 CPU 414-4H 6ES7414-4HJ04-0AB0 CPU 416-2 6ES7416-2XK04-0AB0 CPU 416F-2 6ES7416-2FK04-0AB0 CPU 416-3 6ES7416-3XL04-0AB0 CPU 417-4 6ES7417-4XL04-0AB0 CPU 417-4 H 6ES7417-4HL04-0AB0 1) subsequently described as1) CPU 412 CPU 414 CPU 416 CPU 417 except in the tables, where a detailled differentiation is necessary S7-400 Instruction List A5E00267845-02 5 Address Identifier and Parameter Ranges Address Identifier and Parameter Ranges Addr. ID Q2) Parameter Range Description CPU 412 CPU 414 CPU 416 CPU 417 0.0 to 127.7 0.0 to 255.7 0.0 to 511.7 0.0 to 1023.7 QB2) 0 to 127 0 to 255 0 to 511 0 to 1023 Output byte (in PIQ) QW2) 0 to 126 0 to 254 0 to 510 0 to 1022 Output word (in PIQ) QD2) 0 to 124 0 to 252 0 to 508 0 to 1020 Output double word (in PIQ) DBX 0.0 to 65533.71) 0.0 to 65533.7 0.0 to 65533.7 0.0 to 65533.7 1 to 511 1 to 4095 1 to 4095 1 to 8191 Data block DBB 0 to 655331) 0 to 65533 0 to 65533 0 to 65533 Data byte in DB DBW 0 to 65532*1) 0 to 65532 0 to 65532 0 to 65532 Data word in DB DBD 0 to 655301) 0 to 65530 0 to 65530 0 to 65530 Data double word in DB DIX 0.0 to 65533.71) 0.0 to 65533.7 0.0 to 65533.7 0.0 to 65533.7 Data bit in instance DB DB DI Output (in PIQ) Data bit in data block 1 to 511 1 to 4095 1 to 4095 1 to 8191 Instance data block DIB 0 to 655331) 0 to 65533 0 to 65533 0 to 65533 Data byte in instance DB DIW 0 to 655321) 0 to 65532 0 to 65532 0 to 65532 Data word in instance DB DID 0 to 655301) 0 to 65530 0 to 65530 0 to 65530 Data double word instance DB 1) 2) Also restricted by the size of the working memory. Default setting can be changed, see Technical Specifications S7-400 Instruction List A5E00267845-02 6 Address Identifier and Parameter Ranges Address Identifier and Parameter Ranges, continued Addr. ID I2) CPU 412 Parameter Range CPU 414 CPU 416 Description CPU 417 0.0 to 127.7 0.0 to 255.7 0.0 to 511.7 0.0 to 1023.7 IB2) 0 to 127 0 to 255 0 to 511 0 to 1023 Input bit (in PII) Input byte (in PII) IW2) 0 to 126 0 to 254 0 to 510 0 to 1022 Input word (in PII) ID2) 0 to 124 0 to 252 0 to 508 0 to 1020 Input double word (in PII) L2) 0.0 to 4095.7 0.0 to 8191.7 0.0 to 16383.7 0.0 to 32767.7 LB2) 0 to 4095 0 to 8191 0 to 16383 0 to 32767 Local data byte LW2) 0 to 4094 0 to 8190 0 to 16382 0 to 32766 Local data word LD2) 0 to 4092 0 to 8188 0 to 16380 0 to 32764 Local data double word M Local data 0.0 to 4095.7 0.0 to 8191.7 0.0 to 16383.7 0.0 to 16383.7 MB 0 to 4095 0 to 8191 0 to 16383 0 to 16383 memory byte MW 0 to 4094 0 to 8190 0 to 16382 0 to 16382 memory word MD 0 to 4092 0 to 8188 0 to 16380 0 to 16380 memory double word 2) Bit memory Default setting can be changed, see Technical Specifications S7-400 Instruction List A5E00267845-02 7 Address Identifier and Parameter Ranges Address Identifier and Parameter Ranges, continued Addr. ID CPU 412 Parameter Range CPU 414 CPU 416 CPU 417 PQB 0 to 4095 0 to 8191 0 to 16383 0 to 16383 Peripheral output byte (direct I/O access) PQW 0 to 4094 0 to 8190 0 to 16382 0 to 16382 Peripheral output word (direct I/O access) PQD 0 to 4092 0 to 8188 0 to 16380 0 to 16380 Peripheral output double word (direct I/O access) PIB 0 to 4095 0 to 8191 0 to 16383 0 to 16383 Peripheral input byte (direct I/O access) PIW 0 to 4094 0 to 8190 0 to 16382 0 to 16382 Peripheral input word (direct I/O access) PID 0 to 4092 0 to 8188 0 to 16380 0 to 16380 Peripheral output double word (direct I/O access) T 0 to 2047 0 to 2047 0 to 2047 0 to 2047 Timer C 0 to 2047 0 to 2047 0 to 2047 0 to 2047 Counter S7-400 Instruction List A5E00267845-02 Description 8 Constants and Ranges Constants and Ranges Constant Range Description B(b1,b2) B(b1,b2,b3,b4) - Constant, 2 or 4 bytes D# Date - IEC date constant L# Integer - 32-bit integer constant P# Bit pointer - Pointer constant S5T# Time value - S7 time constant 1) T# TIme value - Time constant TOD# Time value - IEC time constant C# Count value - Counter constant (BCD code) 2#n - Binary constant W#16# DW#16# - Hexadecimal constant 1) For loading of S7 timers. S7-400 Instruction List A5E00267845-02 9 Abbreviations and Mnemonics Abbreviations and Mnemonics The following abbreviations and mnemonics are used in the Instruction List: Abbrev. Description Example k8 8-bit constant 0 to 255 32 k16 16-bit constant 256 to 32 767 28 131 k32 32-bit constant 32 768 to 999 999 999 127 624 i8 8-bit integer -128 to +127 -113 i16 16-bit integer -32768 to +32767 +6523 i32 32-bit integer -2 147 483 648 to +2 147 483 647 -2 222 222 m Pointer constant P#240.3 n Binary constant 1001 1100 p Hexadecimal constant EA12 Label Symbolic jump address (max. 4 characters) DESTINATION a Byte address S7-400 Instruction List A5E00267845-02 10 Abbreviations and Mnemonics Abbreviations and Mnemonics, continued Abbrev. Description Example b Bit address c Address area d Address in: MD, DBD, DID or LD e Number in: MW, DBW, DIW or LW f Timer/counter No. g Address area IB, QB, PIB, PQB, MB, LB, DBB, DIB h Address area IW, QW, PIW, PQW, MW, LW, DBW, DIW i Address area ID, QD, PID, PQD, MD, LD, DBD, DID q Block No. S7-400 Instruction List A5E00267845-02 I, Q, M, L, DBX, DIX 11 Registers Registers ACCU1 to ACCU4 (32 Bits) The accumulators are registers for processing bytes, words or double words. The address identifiers are loaded into the accumulators, where they are logically gated. The result of the logic operation (RLO) is in ACCU1 and can be transferred from there to a memory cell. The accumulators are 32 bits long. Accumulator designations : Bits ACCU ACCUx (x = 1 to 4) Bit 0 to 31 ACCUx-L Bit 0 to 15 ACCUx-H Bit 16 to 31 ACCUx-LL Bit 0 to 7 ACCUx-LH Bit 8 to 15 ACCUx-HL Bit 16 to 23 ACCUx-HH Bit 24 to 31 S7-400 Instruction List A5E00267845-02 12 Registers Address Registers AR1 and AR2 (32 Bits) The address registers contain the area-internal or area-crossing pointers for instructions using indirect addressing. The address registers are 32 bits long. The area-internal and/or area-crossing pointers have the following syntax: Legend: * Area-internal pointer * Area-crossing pointer b x y S7-400 Instruction List A5E00267845-02 00000000 00000bbb bbbbbbbb bbbbbxxx yyyyyyyy 00000bbb bbbbbbbb bbbbbxxx Byte address Bit number Area identifier (see "Examples of Addressing") 13 Registers Status Word (16 Bits) The status word bits are evaluated or set by the instructions. The status word is 16 bits long. Bit Assignment 0 /FC First check bit 1 RLO Result of logic operation 2 STA Status 3 OR Or (AND before OR) 4 OS Stored overflow 5 OV Overflow 6 CC 0 Condition code 0 7 CC 1 Condition code 1 8 BR 9 to 15 Unassigned S7-400 Instruction List A5E00267845-02 Description Binary result - 14 Examples of Addressing Examples of Addressing Addressing Examples Description Immediate Addressing L +27 Load 16-bit integer constant "27" into ACCU1 L L#-1 Load 32-bit integer constant "-1" into ACCU1 L 2#1010101010101010 Load binary constant into ACCU1 L DW#16#A0F0BCFD Load hexadecimal constant into ACCU1 L 'ENDE' Load ASCII character into ACCU1 L T#500 ms Load time value into ACCU1 L C#100 Load count value into ACCU1 L B#(100,12) Load 2-byte constant L B#(100,12,50,8) Load 4-byte constant L P#10.0 Load area-internal pointer into ACCU1 L P#E20.6 Load area-crossing pointer into ACCU1 L -2.5 Load real number into ACCU1 L D# 1995-01-20 Load date L TOD 13:20:33.125 Load time of day S7-400 Instruction List A5E00267845-02 15 Examples of Addressing Addressing Examples Description Direct Addressing1 A I 0.0 ANDing of input bit 0.0 L IB 1 Load input byte 1 into ACCU1 L IW 0 Load input word 0 into ACCU1 L ID 0 Load input double word 0 into ACCU1 Indirect Addressing of Timers/Counters SP T [LW 8] Start timer; the timer number is in local data word 8 CU C [LW 10] Count upwards; the counter number is in local data word 10 Area-Internal Memory-Indirect Addressing A I [LD 12] Example: L P#22.2 T LD 12 A I [LD 12] AND operation: The address of the input is in local data double word 12 as pointer A I [DBD 1] AND operation: The address of the input is in data double word 1 of the open DB as pointer A I [DID 12] AND operation: The address of the output is in data double word 12 of the open instance DB as pointer A I [MD 12] AND operation: The address of the output is in memory double word 12 as pointer S7-400 Instruction List A5E00267845-02 16 Examples of Addressing Examples of Addressing, continued Addressing Examples Area-Internal Register-Indirect Addressing A I [AR1,P#12.2] Area-Crossing Register-Indirect Addressing For area-crossing register-indirect addressing, the address must also contain an area identifier. The address is in the address register. The area identifiers are as follows: Area identifier P I Q M DB DI L VL Coding (binary) 1000 0000 1000 0001 1000 0010 1000 0011 1000 0100 1000 0101 1000 0110 1000 0111 Area hex. 80 81 82 83 84 85 86 87 I/O area Input area Output area Bit memory area Data area Instance data area Local data area Predecessor local data area (access to local data of invoking block) L B [AR1,P#8.0] Load byte into ACCU1: The address is calculated from the "pointer value in AR 1 + P#8.0" A [AR1,P#32.3] AND operation: The address of the operand is calculated from the "pointer value in AR 1 + P#32.3" Addressing Via Parameters A Parameter S7-400 Instruction List A5E00267845-02 Addressing via parameters 17 Examples of how to calculate the pointer Examples of how to calculate the pointer * Example for sum of bit addresses x7: LAR1 P#8.2 A I [AR1,P#10.2] Result: Input 18.4 is addressed (by adding the byte and bit addresses) * Example for sum of bit addressesu7: L P#10.5 LAR1 A I [AR1,P#10.7] Result: Input 21.4 is addressed (by adding the byte and bit addresses with carry over) S7-400 Instruction List A5E00267845-02 18 Execution Times with Indirect Addressing23 Execution Times with Indirect Addressing23 When using indirect addresses statement consists of two parts: Part 1: Load the address of the instruction Part 2: Execute the instruction In other words, when working with indirect addresses, you must calculate the execution time of an instruction from these two parts. Calculating the Execution Time The total execution time is calculated as follows: Time required for loading the address + execution time of the instruction = Total execution time of the instruction The execution times listed in the chapter entitled "List of Instructions" apply to the execution times of the second part of an instruction, i.e. for the actual execution of an instruction. You must then add the time required for loading the address of the instruction to this execution time (see following Table). S7-400 Instruction List A5E00267845-02 19 Execution Times with Indirect Addressing23 The execution time for loading the address of the instruction from the various areas is shown in the following table. Execution Time in ms Address is in ... CPU 412 CPU 414 CPU 416 CPU 417 Bit memory area M Word Double word 0.2 0.2 0.12 0.12 0.08 0.08 0.06 0.06 Data block DB/DX Word Double word 0.3 0.3 0.18 0.18 0.12 0.12 0.12 0.12 Local data area L Word Double word 0.2 0.2 0.12 0.12 0.08 0.08 0.06 0.06 AR1/AR2 (area-internal) 0.0 1) 0.0 1) 0.0 1) 0.0 1) AR1/AR2 (area-crossing) 0.0 1) 0.0 1) 0.0 1) 0.0 1) 0.4 0.4 0.4 0.24 0.24 0.24 0.16 0.16 0.16 0.15 0.15 0.15 0.4 0.24 0.16 0.15 Parameter (word) ... for: S S S Timers Counters Block calls Parameter (double word) ... for Bits, bytes, words and double words 1) Address registers AR1/AR2 do not need to be loaded in separate cycles for addressing. The pages that follow contain examples for calculating the instruction run time for the various indirectly addressed instructions. S7-400 Instruction List A5E00267845-02 20 Examples of Calculations Examples of Calculations You will find a few examples here for calculating the execution times for the various methods of indirect addressing. Calculating the Execution Times for Area-Internal Memory-Indirect Addressing Example: A I [DBD 12] with CPU 414 Step 1: Load the contents of DBD 12 (time required is listed in the table on page 20) Execution Time in ms Address is in ... Bit memory area M Word Double word 0.2 0.3 Data block DB/DX Word Double word 0.2 0.3 Step 2: AND the input addressed in this way (you will find the execution time in the tables in the chapter entitled "List of Instructions" on page 25) Typical Execution Time in ms Direct Addressing 0.06/0.075 : Indirect Addressing Time for A I 0.06+ : Total execution time: + 0.18 ms 0.06 ms 0.24 ms S7-400 Instruction List A5E00267845-02 21 Examples of Calculations Execution Time for Area-Crossing Register-Indirect Addressing Example: A [AR1, P#23.1] ... with I 1.0 in AR1 with CPU 416 Step 1: Load the contents of AR1, and increment them by the offset 23.1 (the time required is in the table on page 20) Address is in ... Execution Time in ms : : AR1/AR2 (area-crossing) 0.00 : Step 2: : AND link of the input addressed this way (see page 25 for the execution time) Typical Execution Time in ms Direct Addressing 0.04/0.05 : Indirect Addressing Time for A I 0.05+ : Total execution time: + 0.00 ms 0.05 ms 0.05 ms S7-400 Instruction List A5E00267845-02 22 Examples of Calculations S7-400 Instruction List A5E00267845-02 23 List of Instructions List of Instructions This chapter contains the complete list of instructions for the S7-400 CPUs. The descriptions have been kept as concise as possible. You will find a detailed functional description in the various STEP 7 reference manuals. Please note that, in the case of indirect addressing (examples see page 16 ), you must add the time required for loading the address of the particular instruction to the execution times listed (see page 19 ). S7-400 Instruction List A5E00267845-02 24 Bit Logic Instructions Bit Logic Instructions All logic instructions generate a result (new RLO). The first instruction in a logic string generates the new RLO from the signal state scanned. The subsequent logic instructions generate the new RLO from the signal state scanned and the old RLO. The logic string ends with an instruction which limits the RLO (e.g. a memory instruction); that is, the /FC bit is set to zero. Instr. Address ID Description CPU 412 CPU 414 CPU 416 CPU 417 11)/2 12)/2 2 2 2 2 2 2 2 2 2 0.1/0.125 0.1/0.125 0.125 0.2 0.2 0,1+/0,2+ 0,125/0,2 0,125/0,2 0,125/0,2 0,125/0,2 0,525/0,6 0.06/0.075 0.06/0.075 0.075 0.12 0.12 0,06+/0,12+ 0,075/0,12 0,075/0,12 0,075/0,12 0,075/0,12 0,315/0,36 0.04/0.05 0.04/0.05 0.05 0.08 0.08 0,04+/0,08+ 0,05/0,08 0,05/0,08 0,05/0,08 0,05/0,08 0,21/0,24 0.03/0.042 0.03/0.042 0.042 0.09 0.09 0,04+/0,08+ 0,05/0,08 0,05/0,08 0,05/0,08 0,05/0,08 0,21/0,24 U/UN I/Q a.b M a.b L a.b DBX a.b DIX a.b c [d] c [AR1,m] c [AR2,m] [AR1,m] [AR2,m] Parameter Statusword for: Input/output Bit memory Local data bit Data bit Instance data bit Memory-indirect, area-internal3) Register-ind., area-internal (AR1)3) Register-ind., area-internal (AR2)3) Area-crossing (AR1)*** Area-crossing (AR2)*** Via parameter *** BIE A1 A0 OV OS OR STA RLO /FC Instruction depends on: - - - - - Yes - Yes Yes Instruction affects: - - - - - Yes Yes Yes 1 + 1) 2) 3) U/UN Execution Time in ms Length in Words Plus time required for loading the address of the instruction (see page 20) With direct instruction addressing;Address area 0 to 127 With direct instruction addressing;Address area 0 to 255 I,Q,M,L / DB, DI S7-400 Instruction List A5E00267845-02 25 Bit Logic Instructions Bit Logic Instructions, continued Instr. Address ID Description O/ON I/Q a.b M a.b L a.b DBX a.b DIX a.b c [d] c [AR1,m] c [AR2,m] [AR1,m] [AR2,m] Parameter Statusword for: Length in Words CPU 412 CPU 414 CPU 416 CPU 417 11)/2 12)/2 2 2 2 2 2 2 2 2 2 0.1/0.125 0.1/0.125 0.125 0.2 0.2 0,1+/0,2+ 0,125/0,2 0,125/0,2 0,125/0,2 0,125/0,2 0,525/0,6 0.06/0.075 0.06/0.075 0.075 0.12 0.12 0,06+/0,12+ 0,075/0,12 0,075/0,12 0,075/0,12 0,075/0,12 0,315/0,36 0.04/0.05 0.04/0.05 0.05 0.08 0.08 0,06+/0,12+ 0,075/0,12 0,075/0,12 0,075/0,12 0,075/0,12 0,315/0,36 0.03/0.042 0.03/0.042 0.042 0.09 0.09 0,03+/0,09+ 0,042/0,09 0,042/0,09 0,042/0,09 0,042/0,09 0,192/0,24 OR/OR-NOT Input/output Bit memory Local da Data bit Instance data bit Memory-indirect, area-internal 3) Register-ind., area-internal (AR1) 3) Register-ind., area-internal (AR2) 3) Area-crossing (AR1) *** Area-crossing (AR2) *** Via parameter *** BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - Yes Yes Instruction affects: - - - - - 0 Yes Yes 1 + 1) 2) 3) O, ON Plus time required for loading the address of the instruction (see page 20) With direct instruction addressing; Address area 0 to 127 With direct instruction addressing; Address area 0 to 255 I,Q,M,L / DB, DI S7-400 Instruction List A5E00267845-02 26 Bit Logic Instructions Bit Logic Instructions, continued Instr. AddressID X/XN E/A a.b M a.b L a.b DBX a.b DIX a.b c [d] c [AR1,m] c [AR2,m] [AR1,m] [AR2,m] Parameter Status word for: Length in Words Description EXKLUSIV-OR/ EXKLUSIV-OR-NOT Input/output Bit memory Local data bit Data bit Instance data bit Memory-indirect, area-internal. 1) Register-ind., area-internal (AR1) 1) Register-ind., area-internal (AR2) 1) Area-crossing (AR1) 1) Area-crossing (AR2) 1) Via parameter 1) X, XN Execution Time in ms 2 2 2 2 2 2 2 2 2 2 2 CPU 412 CPU 414 CPU 416 CPU 417 0.125 0.125 0.125 0.2 0.2 0,1+/0,2+ 0,125/0,2 0,125/0,2 0,125/0,2 0,125/0,2 0,525/0,6 0.075 0.075 0.075 0.12 0.12 0,06+/0,12+ 0,075/0,12 0,075/0,12 0,075/0,12 0,075/0,12 0,315/0,36 0.05 0.05 0.05 0.08 0.08 0,04+/0,08+ 0,05/0,08 0,05/0,08 0,05/0,08 0,05/0,08 0,21/0,24 0.042 0.042 0.042 0.09 0.09 0,03+/0,09+ 0,042/0,09 0,042/0,09 0,042/0,09 0,042/0,09 0,192/0,24 BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - Instruction affects: - - - - - - - Yes Yes 0 Yes Yes 1 +Plus time required for loading the address of the instruction (see page 20) 1) I,Q,M,L / DB, DI S7-400 Instruction List A5E00267845-02 27 Bit Logic Instructions with Parenthetical Expressions Bit Logic Instructions with Parenthetical Expressions Saving the RLO and OR bits and the relevant function identifier (A, AN, ...) to the nesting stack. Seven nesting levels are possible per block. After the right parenthesis, the logic operation indicated by the function identifier is performed on the saved RLO and the current RLO; the current OR is overwritten with the saved OR. Instruction Address ID Description Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 U( AND left parenthesis 1 0.1 0.06 0.04 0.03 UN( AND NOT left parenthesis 1 0.1 0.06 0.04 0.03 O( OR left parenthesis 1 0.1 0.06 0.04 0.03 ON( OR NOT left parenthesis 1 0.1 0.06 0.04 0.03 X( Exclusive OR left parenthesis 1 0.1 0.06 0.04 0.03 XN( EXKLUSIV-ODER-NICHT-Klamparenthesis 1 0.1 0.06 0.04 0.03 Statusword for: U(, UN(, O(, ON(, X(, XN( BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - Yes - Yes Yes Instruction affects: - - - - - 0 1 - 0 S7-400 Instruction List A5E00267845-02 28 Bit Logic Instructions with Parenthetical Expressions Bit Logic Instructions with Parenthetical Expressions, continued Instruction Address ID ) Statusword for: ) Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 Right parenthesis, removing an entry from the nesting stack. 1 0.1 0.06 0.04 0.03 Description BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - Yes - Instruction affects: - - - - - Yes 1 Yes 1 S7-400 Instruction List A5E00267845-02 29 ORing of AND Instructions ORing of AND Instructions The ORing of AND instructions is implemented according to the rule: AND before OR. Instruction Address ID Description O Status word for: CPU 412 CPU 414 CPU 416 CPU 417 1 0.1 0.06 0.04 0.03 ORing of AND operations according to the rule: AND before OR O Execution Time in ms Length in Words BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - Yes Yes Instruction affects: - - - - - Yes 1 - Yes S7-400 Instruction List A5E00267845-02 30 Logic Instructions with Timers and Counters Logic Instructions with Timers and Counters Examining the status of the addressed timer/counter and gating the result with the RLO according to the appropriate logic function. Instruction Address ID A/AN T T C C Description AND/AND NOT Timer Timer, memory-indirect addressing Counter Counter, memory-indirect addressing f [e] f [e] Timerpara. Counter para. Status word for: Length in Words Timer/counter (addressing via parameter) CPU 412 CPU 414 CPU 416 CPU 417 11)/2 2 11)/2 2 0.1/0.125 0.1+ 0.1/0.125 0.1+ 0.06/0.075 0.06+ 0.06/0.075 0.06+ 0.04/0.05 0.04+ 0.04/0.05 0.04+ 0.03/0.042 0.03+ 0.03/0.042 0.03+ 2 0.5 0.5 0.3 0.3 0.2 0.2 0.18 0.18 BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - Yes - Yes Yes Instruction affects: - - - - - Yes Yes Yes 1 + 1) A, AN Execution Time in ms Plus time required for loading the address of the instruction (see page 20) With direct instruction addressing ;Address area 0 to 255 S7-400 Instruction List A5E00267845-02 31 Logic Instructions with Timers and Counters Logic Instructions with Timers and Counters, continued Instruction Address ID Length in Words Description O/ON T T C C f [e] f [e] Timer Timer, memory-indirect addr. Counter Counter, memory-indirect addressing Timerpara. Counterpara. Timer/counter (addressing via parameter) T T C C EXCLUSIVE OR/EXCLUSIVE OR NOT Timer Timer, memory-indirect addr. Counter Counter, mem.-indirect addr. X/XN f [e] f [e] Timerpara. Counterpara. Status word for: CPU 412 CPU 414 CPU 416 CPU 417 11)/2 2 11)/2 2 0.1/0.125 0.1+ 0.1/0.125 0.1+ 0.06/0.075 0.06+ 0.06/0.075 0.06+ 0.04/0.05 0.04+ 0.04/0.05 0.04+ 0.03/0.042 0.03+ 0.03/0.042 0.03+ 2 0.5 0.5 0.3 0.3 0.2 0.2 0.18 0.18 2 2 2 2 0.125 0.1+ 0.125 0.1+ 0.075 0.06+ 0.075 0.06+ 0.05 0.04+ 0.05 0.04+ 0.042 0.03+ 0.042 0.03+ 2 0.5 0.5 0.3 0.3 0.2 0.2 0.18 0.18 EXCLUSIVE OR timer/counter (addressing via parameter) BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - Yes Yes Instruction affects: - - - - - 0 Yes Yes 1 + 1) O, ON, X, XN Execution Time in ms Plus time required for loading the address of the instruction (see page 20) With direct instruction addressing; address area 0 to 255 S7-400 Instruction List A5E00267845-02 32 Word Logic Instructions with the Contents of Accumulator 1 Word Logic Instructions with the Contents of Accumulator 1 Gating the contents of ACCU1 and/or ACCU1-L with a word or double word according to the appropriate function. The word or double word is either specified in the instruction as an address or is in ACCU2. The result is in ACCU1 and/or ACCU1-L. Instruction Address ID AW AW OW OW W#16#p XOW XOW CPU 412 CPU 414 CPU 416 CPU 417 0.1 0.06 0.04 0.03 AND 16-bit constant 2 0.125 0.075 0.05 0.042 OR ACCU2-L 1 0.1 0.06 0.04 0.03 OR 16-bit constant 2 0.125 0.075 0.05 0.042 EXCLUSIVE OR ACCU2-L 1 0.1 0.06 0.04 0.03 EXKLUSIV-ODER EXCLUSIVE OR 16-bit constant 2 0.125 0.075 0.05 0.042 AND ACCU2-L W#16#p W#16#p Status word for: Execution Time in ms Length in Words 1 Description BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: UW, OW, XOW - - - - - - - - - Instruction affects: - ja 0 0 - - - - - S7-400 Instruction List A5E00267845-02 33 Word Logic Instructions with the Contents of Accumulator 1 Word Logic Instructions with the Contents of Accumulator 1, continued Instruction AD AD OD OD DW#16#p XOD XOD CPU 412 CPU 414 CPU 416 CPU 417 0.1 0.6 0.04 0.3 AND 32-bit constant 3 0.185 0.112 0.075 0.062 OR ACCU2 1 0.1 0.06 0.04 0.3 OR 32-bit constant 3 0.185 0.112 0.075 0.062 EXCLUSIVE OR ACCU2 1 0.1 0.06 0.04 0.03 Description AND ACCU2 DW#16#p DW#16#p Status word for: Execution Time in ms Length in Words 1 Address ID EXCLUSIVE OR 32-bit constant UD, OD, XOD BR 3 0.185 0.112 0.075 0.062 CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - Yes 0 0 - - - - - S7-400 Instruction List A5E00267845-02 34 Evaluating Conditions Using AND, OR and EXCLUSIVE OR Evaluating Conditions Using AND, OR and EXCLUSIVE OR All logic instructions generate a result (new RLO). The first instruction in a logic string generates the new RLO from the signal state scanned. The subsequent logic instructions generate the new RL from the signal state scanned and the old RLO. The logic string ends with an instruction which limits the RLO (e.g. a memory instruction); that is, the FC bit is set to zero. Instruction Address ID A/AN O/ON X/XN Description AND/AND NOT OR/OR-NOT EXCLUSIVE OR/ EXCLUSIVE-OR-NOT Result=0 (A1=0 and A0=0) ==0 Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 1 0.1 0.06 0.04 0.03 >0 Result>0 (CC1=1 and CC0=0) 1 0.1 0.06 0.04 0.03 <0 Result<0 (CC1=0 and CC0=1) 1 0.1 0.06 0.04 0.03 <>0 Result00 ((CC1=0 and CC0=1) or (CC1=1 and CC0=0)) 1 0.1 0.06 0.04 0.03 Status word for: A/AN/O/ON/X/XN BR CC1 CC0 OV OS OR Instruction evaluates: - Yes Yes - - Instruction affects: - - - - - S7-400 Instruction List A5E00267845-02 STA RLO /FC Yes - Yes Yes Yes Yes Yes 1 35 Evaluating Conditions Using AND, OR and EXCLUSIVE OR Evaluating Conditions Using AND, OR and EXCLUSIVE OR, continued Instruction A/AN O/ON X/XN Address ID Description >=0 Result>=0 ((CC1=1 and CC0=0) or (CC1=0 and CC0=0)) <=0 Result<=0 ((CC1=0 and CC0=1) or (CC1=0 and CC0=0)) Status word for: A/AN/O/ON/X/XN Execution Time in ms Length in Words 1 CPU 412 CPU 414 CPU 416 CPU 417 0.1 0.06 0.04 0.03 1 0.1 0.06 0.04 0.03 BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - Yes Yes - - Yes - Yes Yes Instruction affects: - - - - - Yes Yes Yes 1 S7-400 Instruction List A5E00267845-02 36 Evaluating Conditions Using AND, OR and EXCLUSIVE OR Evaluating Conditions Using AND, OR and EXCLUSIVE OR, continued Instruction Address ID A/AN O/ON X/XN Length in Words Description AND/AND-NOT OR/OR-NOT EXCLUSIVE-OR/ EXCLUSIVE-OR-NOT Unordered math instruction (CC1=1 and CC0=1) UO Execution Time in ms CPU 412 CPU 414 CPU 416 CPU 417 1 0.1 0.06 0.04 0.03 OS AND OS=1 1 0.1 0.06 0.04 0.03 BR AND BR=1 1 0.1 0.06 0.04 0.03 OV Status word for: AND OV=1 A/AN/O/ON/X/XN Instruction evaluates: Instruction affects: S7-400 Instruction List A5E00267845-02 1 0.1 0.06 0.04 0.03 BR CC1 CC0 OV OS OR STA RLO /FC Yes Yes Yes Yes Yes Yes - Yes Yes - - - - - Yes Yes Yes 1 37 Edge-Triggered Instructions Edge-Triggered Instructions The current RLO is compared with the status of the instruction or "edge bit memory". FP detects a change from "0" to "1"; FN detects a change from "1" to "0". Instruction FP/FN Address ID I/Q a.b M a.b L a.b1) DBX a.b DIX a.b c [d] c [AR1,m] 2) c [AR2,m] 2) [AR1,m] 2) [AR2,m] 2) Parameter 2) Status word for: Description The positive/negative edge is indicated by RLO = 1. The bit addressed in the instruction is the auxiliary edge bit memory. Execution Time in ms 2 2 2 2 2 2 2 2 2 2 2 CPU 412 CPU 414 CPU 416 CPU 417 0.2 0.2 0.2 0.3 0.3 0,2+/0,3+ 0,2/0,3 0,2/0,3 0,2/0,3 0,2/0,3 0,6/0,7 0.12 0.12 0.12 0.18 0.18 0,12+/0,18+ 0,12/0,18 0,12/0,18 0,12/0,18 0,12/0,18 0,36/0,42 0.08 0.08 0.08 0.12 0.12 0,08+/0,12+ 0,08/0,12 0,08/0,12 0,08/0,12 0,08/0,12 0,24/0,28 0.06 0.06 0.06 0.12 0.12 0,06+/0,12+ 0,06/0,12 0,06/0,12 0,06/0,12 0,06/0,12 0,21/0,27 BR CC1 CC0 OV OS OR Instruction evaluates: - - - - - Instruction affects: - - - - - + 1) 2) FP, FN Length in Words STA RLO /FC - - Yes - 0 Yes Yes 1 Plus time required for loading the address of the instruction (see page 20) Unnecessary if the bit being monitored is in the process image (local data of a block are only valid while the block is running). I, Q, M, L /DB, DI S7-400 Instruction List A5E00267845-02 38 Setting/Resetting Bit Addresses Setting/Resetting Bit Addresses Assigning the value "1" or "0" to the addressed instruction when RLO = 1. The instructions can be dependent on the MCR (see page 97). Instruction Address ID S R I/Q a.b M a.b L a.b DBX a.b DIX a.b c [d] c [AR1,m] c [AR2,m] [AR1,m] [AR2,m] Parameter Status word for: Description Set addressed bit to "1" Set addressed bit to "0" Input/output Bit memory Local data bit Data bit Instance data bit Memory-indirect, area-internal 3) Register-indirect, area-internal (AR1) 3) Register-indirect, area-internal (AR2) 3) Area-crossing (AR1) 3) Area-crossing (AR2) 3) Via parameter CPU 412 CPU 414 CPU 416 CPU 417 11)/2 12)/2 2 2 2 2 2 2 2 2 2 0.2 0.2 0.2 0.3 0.3 0,2+/0,3+ 0,2/0,3 0,2/0,3 0,2/0,3 0,2/0,3 0,6/0,7 0.12 0.12 0.12 0.18 0.18 0,12+/0,18+ 0,12/0,18 0,12/0,18 0,12/0,18 0,12/0,18 0,36/0,42 0.08 0.08 0.08 0.12 0.12 0,08+/0,12+ 0,08/0,12 0,08/0,12 0,08/0,12 0,08/0,12 0,24/0,28 0.06 0.06 0.06 0.12 0.12 0,06+/0,12+ 0,06/0,12 0,06/0,12 0,06/0,12 0,06/0,12 0,21/0,27 BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - Yes - Instruction affects: - - - - - 0 Yes - 0 + 1) 2) 3) S, R Execution Time in ms Lengt h in Words Plus time required for loading the address of the instruction (see page 20) With direct instruction addressing; Address area 0 to 127 With direct instruction addressing; Address area 0 to 255 I, Q, M, L / DB, DI S7-400 Instruction List A5E00267845-02 39 Setting/Resetting Bit Addresses Setting/Resetting Bit Addresses, continued The RLO is written to the address of the instruction. The instructions can be dependent on the MCR (see page 97). Instru Ction Address ID Description = I/Q a.b M a.b L a.b DBX a.b DIX a.b c [d] c [AR1,m] c [AR2,m] [AR1,m] [AR2,m] Parameter Status word for: = Assign RLO To input/output To bit memory To local data bit To data bit To instance data bit Memory-indirect, area-internal 3) Register-indirect, area-internal (AR1) 3) Register-indirect, area-internal (AR2) 3) Area-crossing (AR1) 3) Area-crossing (AR2) 3) Via parameter 3) Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 11)/2 12)/2 2 2 2 2 2 2 2 2 2 0.2 0.2 0.2 0.3 0.3 0,2+/0,3+ 0,2/0,3 0,2/0,3 0,2/0,3 0,2/0,3 0,6/0,7 0.12 0.12 0.12 0.18 0.18 0,12+/0,18+ 0,12/0,18 0,12/0,18 0,12/0,18 0,12/0,18 0,36/0,42 0.08 0.08 0.08 0.12 0.12 0,08+/0,12+ 0,08/0,12 0,08/0,12 0,08/0,12 0,08/0,12 0,24/0,28 0.06 0.06 0.06 0.12 0.12 0,06+/0,12+ 0,06/0,12 0,06/0,12 0,06/0,12 0,06/0,12 0,21/0,27 BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - Yes - Instruction affects: - - - - - 0 Yes - 0 + Plus time required for loading the address of the instruction (see page 20) With direct instruction addressing; Address area 0 to 127 With direct instruction addressing; Address area 0 to 255 3)I, Q, M, L / DB, DI 1) 2) S7-400 Instruction List A5E00267845-02 40 Instructions Directly Affecting the RLO Instructions Directly Affecting the RLO The following instructions have a direct effect on the RLO. Instruction Address ID CLR Status word for: Length in Words 1 Description Set RLO to "0" CLR Execution Time in ms CPU 412 CPU 414 CPU 416 CPU 417 0.1 0.06 0.04 0.03 BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - - - - - 0 0 0 0 BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - - - - - 0 1 1 0 SET Status word for: Set RLO to "1" SET NOT Status word for: 1 Negate RLO NOT 0.1 1 0.06 0.1 0.04 0.06 0.03 0.04 0.03 BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - Yes - Yes - Instruction affects: - - - - - - 1 Yes - SAVE Status word for: Save RLO to the BR bit SAVE Instruction evaluates: Instruction affects: S7-400 Instruction List A5E00267845-02 1 0.1 0.06 0.04 0.03 BR CC1 CC0 OV OS OR STA RLO /FC - - - - - - - Yes - Yes - - - - - - - - 41 Timer Instructions Timer Instructions Starting or resetting a timer. The time value must be in ACCU1-L. The instructions are triggered by an edge transition in the RLO; that is, when the status of the RLO has changed between two calls. Instruction SP Address ID Length in Words Description T f T [e] CPU 412 CPU 414 CPU 416 CPU 417 Start timer as pulse on edge change from "0" to "1" 11)/2 0.2 0.2+ 0.12 0.12+ 0.08 0.08+ 0.06 0.06+ 2 0.6 0.36 0.24 0.21 Start timer as extended pulse on edge change from "0" to "1" 11)/2 0.2 0.2+ 0.12 0.2+ 0.08 0.08+ 0.06 0.06+ 2 0.6 0.36 0.24 0.21 11)/2 0.2 0.2+ 0.12 0.12+ 0.08 0.08+ 0.06 0.06+ 2 0.6 0.36 0.24 0.21 Timer para. SE T f T [e] Timer para. SD T f T [e] Start timer as ON delay on edge change from "0" to "1" Timer para. Status word for Execution Time in ms BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - Yes - Instruction affects: - - - - - 0 - - 0 + 1) SP, SE, SD Plus time required for loading the address of the instruction (see page 20) With direct instruction addressing Timer No.: 0 to 255 S7-400 Instruction List A5E00267845-02 42 Timer Instructions Timer Instructions, continued Instruction SS Address ID Length in Words Description T f T [e] CPU 412 CPU 414 CPU 416 CPU 417 Start timer as retentive ON delay on edge change from "0" to "1" 11)/2 0.2 0.2+ 0.12 0.12+ 0.08 0.08+ 0.06 0.06+ 2 0.6 0.36 0.24 0.21 Start timer as OFF delay on edge change from "0" to "1" 11)/2 0.2 0.2+ 0.12 0.12+ 0.08 0.08+ 0.06 0.06+ Timer para. SF T f T [e] Timer para. Status word for Execution Time in ms 2 SS, SF 0.6 0.36 0.24 0.21 BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - Yes - Instruction affects: - - - - - 0 - - 0 S7-400 Instruction List A5E00267845-02 43 Timer Instructions Timer Instructions, continued Instruction FR Address ID T f T [e] Timer para. R Length in Words Description T f T [e] CPU 414 CPU 416 CPU 417 Enable timer for restarting on edge change from "0" to "1" (reset edge bit memory for starting timer) 11)/2 0.2 0.2+ 0.12 0.12+ 0.08 0.08+ 0.06 0.06+ 2 0.6 0.36 0.24 0.21 Reset timer 11)/2 0.2 0.2+ 0.12 0.12+ 0.08 0.08+ 0.06 0.06+ Timer para. Status word for: Execution Time in ms CPU 412 2 0.6 0.36 0.24 0.21 BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - Yes - Instruction affects: - - - - - 0 - - 0 + 1) FR, R Plus time required for loading the address of the instruction (see page 20) With direct instruction addressing Timer No.: 0 to 255 S7-400 Instruction List A5E00267845-02 44 Counter Instructions Counter Instructions The count value must be in ACCU1-L in the form of a BCD number (0 - 999). Instruction S Address ID Cf C [e] Length in Words Description CPU 412 CPU 414 CPU 416 CPU 417 Presetting of counter on edge change from "0" to "1" 11)/2 0.2 0.4+ 0.12 0.12+ 0.08 0.08+ 0.06 0.06+ 2 0.6 0.36 0.24 0.21 Reset counter to "0" when RLO = "1" 11)/2 0.2 0.4+ 0.12 0.12+ 0.08 0.08+ 0.06 0.06+ 2 0.6 0.36 0.24 0.21 11)/2 0.2 0.2+ 0.12 0.12+ 0.08 0.08+ 0.06 0.06+ 2 0.6 0.36 0.24 0.21 Counter para. R Cf C [e] Counter para. CU Cf C [e] Increment counter by 1 on edge change from "0" to "1" Counter para. Status word for: Execution Time in ms BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - Yes - Instruction affects: - - - - - 0 - - 0 + 1) S, R, CU Plus time required for loading the address of the instruction (see page 20) With direct instruction addressing Counter No.: 0 to 255 S7-400 Instruction List A5E00267845-02 45 Counter Instructions Counter Instructions, continued Instruction CD Address ID Cf C [e] Length in Words Description CPU 412 CPU 414 CPU 416 CPU 417 Decrement counter by 1 on edge change from "0" to "1" 11)/2 0.2 0..2+ 0.12 0.2+ 0.08 0.08+ 0.06 0.06+ 2 0.6 0.36 0.24 0.21 Enable counter on edge change from "0" to "1" (reset edge bit memory for up and down counting and setting the counter) 11)/2 0.2 0.2+ 0.12 0.12+ 0.08 0.08+ 0.06 0.06+ 2 0.6 0.36 0.24 0.21 Counter para. FR Cf C [e] Counter para. Status word for: Execution Time in ms BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - Yes - Instruction affects: - - - - - 0 - - 0 + 1) CD, FR Plus time required for loading the address of the instruction (see page 20) With direct instruction addressing Counter No.: 0 to 255 S7-400 Instruction List A5E00267845-02 46 Load Instructions Load Instructions Loading address identifiers into ACCU1. The contents of ACCU1 are first saved to ACCU2. The status word is not affected. Instruction Address ID L 1) 2) 3) 4) Length in Words CPU 412 CPU 414 CPU 416 CPU 417 Execution Time in ms IB QB PIB a a a Load ... Input byte Output byte Peripheral input byte 2) 11)/2 11)/2 2 0.1/0.125 0.1/0.125 0.125 0.06/0.075 0.06/0.075 0.075 0.04/0.05 0.04/0.05 0.05 0.03/0.042 0.03/0.042 0.042 MB LB a a Bit memory byte Local data byte 13)/2 2 0.1/0.125 0.125 0.06/0.075 0.075 0.04/0.05 0.05 0.03/0.042 0.042 DBB DIB a a Data byte Instance data byte ... into ACCU1 2 2 0.2 0.2 0.12 0.12 0.08 0.08 0.09 0.09 Memory-indirect, area-internal 4) Register-indirect, area-internal (AR1) 4) Register-indirect, area-internal (AR2) 4) Area-crossing (AR1) 4) Area-crossing (AR2) 4) Via parameter 4) 2 2 2 2 2 2 0.1+/0.2+ 0,125/0,2 0,125/0,2 0,125/0,2 0,125/0,2 0,525/0,6 0.06+/0.12+ 0,075/0,12 0,075/0,12 0,075/0,12 0,075/0,12 0,315/0,36 0.04+/0.08+ 0,05/0,08 0,05/0,08 0,05/0,08 0,05/0,08 0,21/0,24 0.03+/0.09+ 0,42/0,09 0,42/0,09 0,42/0,09 0,42/0,09 0,57/0,24 g [d] g [AR1,m] g [AR2,m] B[AR1,m] B[AR2,m] Parameter + Description Plus time required for loading the address of the instruction (see page 20) With indirect instruction addressing; Address area 0 to 127 The following peripheral acknowledgement time must be observed with CPU 414-4H: solo 33 ms, redundant 77 ms with CPU 417-4H: solo 21 ms, redundant 45 ms With direct instruction addressing; Address area 0 to 255 I, Q, P, M, L / DB, DI S7-400 Instruction List A5E00267845-02 47 Load Instructions Load Instructions, continued If there is a remainder of 3 following an integral division of the used addresses by 4, the execution times for instructions specified on this page are doubled. Instruction Address ID L 1) 2) 3) 4) Length in Words CPU 412 CPU 414 CPU 416 CPU 417 11)/2 11)/2 11)/2 0.1/0.125 0.1/0.125 0.1/0.125 0.06/0.075 0.06/0.075 0.06/0.075 0.04/0.05 0.04/0.05 0.04/0.05 0.03/0.042 0.03/0.042 0.03/0.042 13)/2 2 0.1/0.125 0.125 0.06/0.075 0.075 0.04/0.05 0.05 0.03/0.042 0.042 Execution Time in ms IW QW PIW a a Load ... Input word Output word Peripheral input word 2) MW LW a a Bit memory word Local data word DBW DIW a a Data word Instance data word ... into ACCU1-L 2 2 0.2 0.2 0.12 0.12 0.08 0.08 0.09 0.09 Memory-indirect, area-internal4) Register-indirect, area-internal (AR1) 4) Register-indirect, area-internal (AR2) 4) Area-crossing (AR1) 4) Area-crossing (AR2) 4) Via parameter 4) 2 2 2 2 2 2 0.1+/0.2+ 0,125/0,2 0,125/0,2 0,125/0,2 0,125/0,2 0,525/0,6 0.06+/0.12+ 0,075/0,12 0,075/0,12 0,075/0,12 0,075/0,12 0,315/0,36 0.04+/0.08+ 0,05/0,08 0,05/0,08 0,05/0,08 0,05/0,08 0,21/0,24 0.03+/0.09+ 0,042/0,09 0,042/0,09 0,042/0,09 0,042/0,09 0,192/0,24 h [d] h [AR1,m] h [AR2,m] W[AR1,m] W[AR2,m] Parameter + Description Plus time required for loading the address of the instruction (see page 20) With indirect instruction addressing; Address area 0 to 127 The following peripheral acknowledgement time must be observed with CPU 414-4H: solo 36 ms, redundant 80 ms with CPU 417-4H: solo 23 ms, redundant 47 ms With direct instruction addressing; Address area 0 to 255 I, Q, P, M, L / DB, DI S7-400 Instruction List A5E00267845-02 48 Load Instructions Load Instructions, continued If the used address is divisible by 4without a remainder, the execution times for instructions specified on this page is doubled. Instruction Address ID L 1) 2) 3) 4) Length in Words CPU 412 CPU 414 CPU 416 CPU 417 11)/2 11)/2 11)/2 0.1/0.125 0.1/0.125 0.1/0.125 0.06/0.075 0.06/0.075 0.06/0.075 0.04/0.05 0.04/0.05 0.04/0.05 0.03/0.042 0.03/0.042 0.03/0.042 13)/2 2 0.1/0.125 0.125 0.06/0.075 0.075 0.04/0.05 0.05 0.03/0.042 0.042 Execution Time in ms IDa QD PID a a Load ... Input double word Output double word Peripheral input double word 2) MD LD a a Bit memory double word Local data double word DBD DID a a Data double word Instance data double word ... in ACCU1 2 2 0.2 0.2 0.12 0.12 0.08 0.08 0.09 0.09 Memory-indirect, area internal 4) Register-ind., area internal (AR1) 4) Register-ind., area internal (AR2) 4) Area-crossing (AR1) 4) Area-crossing (AR2) 4) Via parameter 4) 2 2 2 2 2 2 0.1+/0.2+ 0,125/0,2 0,125/0,2 0,125/0,2 0,125/0,2 0,525/0,6 0.06+/0.12+ 0,075/0,12 0,075/0,12 0,075/0,12 0,075/0,12 0,315/0,36 0.04+/0.08+ 0,05/0,08 0,05/0,08 0,05/0,08 0,05/0,08 0,21/0,24 0.03+/0.09+ 0,042/0,09 0,042/0,09 0,042/0,09 0,042/0,09 0,192/0,24 i [d] i [AR1,m] i [AR2,m] D[AR1,m] D[AR2,m] Parameter + Description Plus time required for loading the address of the instruction (see page 20) With indirect instruction addressing; Address area 0 to 127 The following peripheral acknowledgement time must be observed with CPU 414-4H: solo 40 ms, redundant 84 ms with CPU 417-4H: solo 26 ms, redundant 50 ms With direct instruction addressing; Address area 0 to 255 I, Q, P, M, L / DB, DI S7-400 Instruction List A5E00267845-02 49 Load Instructions Load Instructions, continued Instruction Address ID L k8 k16 k32 L L Description Load ... 8-bit constant into ACCU1-LL 16-bit constant into ACCU1-L 32-bit constant into ACCU1 Length in Words CPU 412 CPU 414 CPU 416 CPU 417 2 2 3 0.125 0.125 0.185 0.075 0.075 0.112 0.05 0.05 0.075 0.042 0.042 0.062 Execution Time in ms Parameter Load constant into ACCU1 (addressed via parameter) 2 0,3+ 0.18+ 0.12+ 0.12+ 2#n Load 16-bit binary constant into ACCU1-L 2 0.125 0.075 0.05 0.042 Load 32-bit binary constant into ACCU1 3 0.185 0.112 0.075 0.062 B#16#p Load 8-bit-hexadecimal constant into ACCU1-L 1 0.1 0.06 0.04 0.03 W#16#p Load 16-bit hexadecimal constant into ACCU1-L 2 0.125 0.075 0.05 0.042 DW#16#p Load 32-bit hexadecimal constant into ACCU1 3 0.185 0.112 0.075 0.065 S7-400 Instruction List A5E00267845-02 50 Load Instructions Load Instructions, continued Instruction L Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 Execution Time in ms 'x' Load 1 character 2 0.125 0.075 0.05 0.042 'xx' Load 2 characters 2 0.125 0.075 0.05 0.042 'xxx' Load 3 characters 3 0.185 0.112 0.075 0.062 'xxxx' Load 4 characters 3 0.185 0.112 0.075 0.062 L D# time value Load IEC date 3 0.185 0.112 0.075 0.062 L S5T# time value Load S7 time constant (16 bits) 2 0.125 0.075 0.05 0.042 L TOD# time value Load IEC time constant 3 0.185 0.112 0.075 0.062 L T# time value Load 16-bit time constant 2 0.125 0.075 0.05 0.042 Load 32-bit time constant 3 0.185 0.112 0.075 0.062 L C# count value Load counter constant (BCD code) 2 0.125 0.075 0.05 0.042 L B# (b1, b2) Load constant as byte (b1, b2) 2 0.125 0.075 0.05 0.042 B# (b1, b2, b3, b4) Load constant as 4 bytes (b1, b2, b3, b4) 3 0.185 0.112 0.075 0.062 S7-400 Instruction List A5E00267845-02 51 Load Instructions Load Instructions, continued Instruction Address ID Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 Execution Time in ms L P# bit pointer Load bit pointer 3 0.185 0.112 0.075 0.062 L L# integer Load 32-bit integer constant 3 0.185 0.112 0.075 0.062 L Real number Load floating-point number 3 0.185 0.112 0.075 0.062 S7-400 Instruction List A5E00267845-02 52 Load Instructions for Timers and Counters Load Instructions for Timers and Counters Loading a time value or count value into ACCU1. The contents of ACCU1 are first saved to ACCU2. The bits of the status word are not affected. Instruction L L LC LC + 1) Address ID Description Tf T (e) Load time value Timer para. Load time value (addressed via parameter) Cf C (e) Load count value Counter para. Load count value (addressed via parameter) Tf T (e) Load time value in BCD Timer para. Load time value in BCD (addressed via parameter) Cf C (e) Load count value in BCD Counter para. Load count value in BCD (addressed via parameter) Length in Words CPU 412 CPU 414 CPU 416 CPU 417 11)/2 2 0.1/0.125 0.1+ 0.06/0.075 0.06+ 0.04/0.05 0.04+ 0.03/0.042 0.03+ 2 0.5 0.3 0.2 0.18 11)/2 2 0.1/0.125 0.1+ 0.06/0.075 0.06+ 0.04/0.05 0.04+ 0.03/0.042 0.03+ 2 0.5 0.3 0.2 0.18 11)/2 2 0.3 0.3+ 0.18 0.18+ 0.12 0.12+ 0.09 0.09+ 2 0.7 0.42 0.28 0.24 11)/2 2 0.3 0.3+ 0.18 0.18+ 0.12 0.12+ 0.09 0.09+ 2 0.7 0.42 0.28 0.24 Execution Time in ms Plus time required for loading the address of the instruction (see page 20) With direct instruction addressing; Timer/counter No.: 0 to 255 S7-400 Instruction List A5E00267845-02 53 Transfer Instructions Transfer Instructions Transferring the contents of ACCU1 to the addressed operand. Note that some instructions are affected by the MCR (see page 97). The status word is not affected. Instruction Address ID T 1) 2) 3) Length in Words CPU 412 CPU 414 CPU 416 CPU 417 11)/2 11)/2 2 0.1/0.125 0.1/0.125 0.125 0.06/0.075 0.06/0.075 0.075 0.04/0.05 0.04/0.05 0.05 0.03/0.042 0.03/0.042 0.042 13)/2 2 0.1/0.125 0.125 0.06/0.075 0.075 0.04/0.05 0.05 0.03/0.042 0.042 Execution Time in ms IB QB PQB a a a Transfer contents of ACCU1-LL to ... input byte output byte peripheral output byte2) MB LB a a bit memory byte local data byte DBB DIB a a data byte instance data byte 2 2 0.335 0.335 0.075 0.075 0.05 0.05 0.042 0.042 Memory-indirect, area internal Register-ind., area internal (AR1) Register-ind., area internal (AR2) Area-crossing (AR1) Area-crossing (AR2) Via parameter 2 2 2 2 2 2 0.1+ 0.125 0.125 0.125 0.125 0.525 0.06+ 0.075 0.075 0.075 0.075 0.315 0.04+ 0.05 0.05 0.05 0.05 0.21 0.03+ 0.042 0.042 0.042 0.042 0.192 g [d] g [AR1,m] g [AR2,m] B[AR1,m] B[AR2,m] Parameter + Description Plus time required for loading the address of the instruction (see page 20) With direct instruction addressing; Address area 0 to 127 The following peripheral acknowledgement time must be observed with CPU 414-4H: solo 32 ms, redundant 77 ms with CPU 417-4H: solo 20 ms, redundant 46 ms With direct instruction addressing; Address area 0 to 255 S7-400 Instruction List A5E00267845-02 54 Transfer Instructions Transfer Instructions, continued If there is a remainder of 3 following an integral division of the used addresses by 4, the execution times for instructions specified on this page are doubled. Instruction Address ID T Description Transfer contents of ACCU1-L to ... input word output word peripheral output word2) Length in Words CPU 412 CPU 414 CPU 416 CPU 417 11)/2 11)/2 11)/2 0.1/0.125 0.1/0.125 0.1/0.125 0.06/0.075 0.06/0.075 0.06/0.075 0.04/0.05 0.04/0.05 0.04/0.05 0.03/0.042 0.03/0.042 0.03/0.042 13)/2 2 0.1/0.125 0.125 0.06/0.075 0.075 0.04/0.05 0.05 0.03/0.042 0.042 Execution Time in ms IW QW PQW a a a MW LW a a bit memory word local data word DBW DIW a a data word instance data word 2 2 0.335 0.335 0.075 0.075 0.05 0.05 0.042 0.042 Memory-indirect, area internal Register-ind., area internal (AR1) Register-ind., area internal (AR2) Area-crossing (AR1) Area-crossing (AR2) Via parameter 2 2 2 2 2 2 0.1+ 0.125 0.125 0.125 0.125 0.525 0.06+ 0.075 0.075 0.075 0.075 0.315 0.04+ 0.05 0.05 0.05 0.05 0.21 0.03+ 0.042 0.042 0.042 0.042 0.192 h [d] h [AR1,m] h [AR2,m] W[AR1,m] W[AR2,m] Parameter + Plus time required for loading the address of the instruction (see page 20) With direct instruction addressing; Address area 0 to 127 The following peripheral acknowledgement time must be observed with CPU 414-4H: solo 35 ms, redundant 80 ms with CPU 417-4H: solo 22 ms, redundant 48 ms 3) With direct instruction addressing; Address area 0 to 255 1) 2) S7-400 Instruction List A5E00267845-02 55 Transfer Instructions Transfer Instructions, continued If the used address is divisible by 4without a remainder, the execution times for instructions specified on this page is doubled. Instruction Address ID T T + 1) 2) 3) Description Length in Words CPU 412 CPU 414 CPU 416 CPU 417 11)/2 11)/2 2 0.1/0.125 0.1/0.125 0.125 0.06/0.075 0.06/0.075 0.075 0.04/0.05 0.04/0.05 0.05 0.03/0.042 0.03/0.042 0.042 13)/2 2 0.1/0.125 0.125 0.06/0.075 0.075 0.04/0.05 0.05 0.03/0.042 0.042 Execution Time in ms ED AD PAD a a a Transfer contents of ACCU1 to ... Input double word Output double word periph. output double word 2) MD LD a a Bit memory double word Local data double word DBD DID a a Data double word Instance data double word 2 2 0.11 0.11 0.075 0.075 0.05 0.05 0.042 0.042 Memory-indirect, area internal Register-ind., area internal (AR1) Register-ind., area internal (AR2) Area-crossing (AR1) Area-crossing (AR2) Via parameter 2 2 2 2 2 2 0.1+ 0.125 0.125 0.125 0.125 0.525 0.06+ 0.075 0.075 0.075 0.075 0.315 0.04+ 0.05 0.05 0.05 0.05 0.21 0.03+ 0.042 0.042 0.042 0.042 0.192 i [d] i [AR1,m] i [AR2,m] D[AR1,m] D[AR2,m] Parameter Plus time required for loading the address of the instruction (see page 20) With direct instruction addressing; Address area 0 to 127 The following peripheral acknowledgement time must be observed with CPU 414-4H: solo 39 ms, redundant 48 ms with CPU 417-4H: solo 25 ms, redundant 51 ms With direct instruction addressing; Address area 0 to 255 S7-400 Instruction List A5E00267845-02 56 Load and Transfer Instructions for Address Registers Load and Transfer Instructions for Address Registers Loading a double word from a memory area or register into address register 1 (AR1) or address register 2 (AR2). The status word is not affected. Instruction Address ID LAR1 - AR2 DBD DID m LD MD a a a a LAR2 - DBD DID m LD MD a a a a S7-400 Instruction List A5E00267845-02 Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 Load contents from ... ACCU1 Address register 2 Data double word Instance data double word 32-bit constant as pointer Local data double word Bit memory double word ... into AR1 1 1 2 2 3 2 2 0.2 0.2 0.3 0.3 0.2 0.2 0.2 0.12 0.12 0.18 0.18 0.12 0.12 0.12 0.08 0.08 0.12 0.12 0.08 0.08 0.08 0.06 0.06 0.12 0.12 0.062 006 006 Load contents from ... ACCU1 Data double word Instance data double word 32-bit constant as pointer Local data double word Bit memory double word ... into AR2 1 2 2 3 2 2 0.2 0.3 0.3 0.2 0.2 0.2 0.12 0.18 0.18 0.12 0.12 0.12 0.08 0.12 0.12 0.08 0.08 0.08 0.06 0.12 0.12 0.062 0.06 0.06 Description 57 Load and Transfer Instructions for Address Registers Load and Transfer Instructions forAddress Registers, continued Transferring a double word from address register 1 (AR1) or address register 2 (AR2) to a memory area or register. The contents of ACCU1 are first saved to ACCU2. The status word is not affected. Instruction CPU 412 CPU 414 CPU 416 CPU 417 a a a a Transfer contents from AR1 in ... ACCU1 Address register 2 Data double word Instance data double word Local data double word Bit memory double word 1 1 2 2 2 2 0.1 0.2 0.125 0.125 0.125 0.125 0.06 0.12 0.075 0.075 0.075 0.075 0.04 0.08 0.05 0.05 0.05 0.05 0.03 0.06 0.042 0.042 0.042 0.042 a a a a Transfer contents from AR2 in ... ACCU1 Data double word Instance data double word Local data double word Bit memory double word 1 2 2 2 2 0.1 0.125 0.125 0.125 0.125 0.06 0.075 0.075 0.075 0.075 0.04 0.05 0.05 0.05 0.05 0.03 0.042 0.042 0.042 0.042 1 0.2 0.12 0.08 0.06 TAR1 - AR2 DBD DID LD MD TAR2 - DBD DID LD MD Execution Time in ms Length in Words Address ID CAR S7-400 Instruction List A5E00267845-02 Description Exchange the contents of AR1 and AR2 58 Load and Transfer Instructions for the Status Word Load and Transfer Instructions for the Status Word Instruction L Address ID STW Status word for: L STW Instruction affects: T Address ID STW Status word for: Execution Time in ms CPU 412 CPU 414 CPU 416 CPU 417 0.1 0.06 0.04 0.3 Load status word into ACCU1 Instruction evaluates: Instruction Length in Words Description BR CC1 CC0 OV OS OR STA RLO /FC Yes Yes Yes Yes Yes Yes Yes Yes Yes - - - - - - - - - Length in Words Description Execution Time in ms CPU 412 CPU 414 CPU 416 CPU 417 0.1 0.06 0.04 0.03 Transfer ACCU1 (bits 0 to 8) to the status word T STW Instruction evaluates: Instruction affects: S7-400 Instruction List A5E00267845-02 BR CC1 CC0 OV OS OR STA RLO /FC - - - - - - - - - Yes Yes Yes Yes Yes Yes Yes Yes Yes 59 Load Instructions for DB Number and DB Length Load Instructions for DB Number and DB Length Loading the number/length of a data block into ACCU1. The old contents of ACCU1 are saved to ACCU2. The status word is not affected. Instruction Address ID Description Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 L DBNO Load number of data block 1 0.1 0.06 0.04 0.03 L DINO Load number of instance data block 1 0.1 0.06 0.04 0.03 L DBLG Load length of data block into byte 1 0.1 0.06 0.04 0.03 L DILG Load length of instance data block into byte 1 0.1 0.06 0.04 0.03 S7-400 Instruction List A5E00267845-02 60 Integer Math (16 Bits) Integer Math (16 Bits) Math instructions on two 16-bit words. The result is written to ACCU1 and/or ACCU1-L. ACCU3 and ACCU4 are then transferred to ACCU2 and ACCU3. Instruction Address ID Description Length in Words Execution Time in ms CPU 412 CPU 414 CPU 416 CPU 417 +I Add 2 integers (16 bits) (ACCU1-L)=(ACCU1-L)+(ACCU2-L) 1 0.1 0.06 0.04 0.03 -I Subtract 1 integer from another (16 bits) (ACCU1-L)=(ACCU2-L)-(ACCU1-L) 1 0.1 0.06 0.04 0.03 Status word for: +I, -I, BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - Yes Yes Yes Yes - - - - S7-400 Instruction List A5E00267845-02 61 Integer Math (16 Bits) Instruction Address ID Description Length in Words Execution Time in ms CPU 412 CPU 414 CPU 416 CPU 417 *I Multiply 1 integer by another (16 bits) (ACCU1)=(ACCU2-L)*(ACCU1-L) 1 0.1 0.06 0.04 0.03 /I Divide 1 integer by another (16 bits) (ACCU1-L)=(ACCU2-L):(ACCU1-L) The remainder is in ACCU1-H 1 0.1 0.24 0.16 0.12 Status word for: *I, /I BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - Yes Yes Yes Yes - - - - S7-400 Instruction List A5E00267845-02 62 Integer Math (32 Bits) Integer Math (32 Bits) Math instructions on two 32-bit words. The result is written to ACCU1. ACCU3 and ACCU4 are then transferred to ACCU2 and ACCU3. Instruction Address ID Description Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 +D Add 2 integers (32-bit) (ACCU1)=(ACCU2)+(ACCU1) 1 0.1 0.06 0.04 0.03 -D Subtract 2 integer from another (32 bits) (ACCU1)=(ACCU2)-(ACCU1) 1 0.1 0.06 0.04 0.03 *D Multiply 2 integer by another (32 bits) (ACCU1)=(ACCU2)*(ACCU1) 1 0.1 0.06 0.04 0.03 Status word for: +D, -D,*D, /D BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - Yes Yes Yes Yes - - - - S7-400 Instruction List A5E00267845-02 63 Integer Math (32 Bits) Instruction Address ID Description Length in Words Execution Time in ms CPU 412 CPU 414 CPU 416 CPU 417 /D Divide 2 integer by another (32 bits) (ACCU1)=(ACCU2):(ACCU1) 1 0.6 0.36 0.24 0.18 MOD Divide 2 integer by another (32 bits) and load the remainder into ACCU1: (ACCU1)=remainder of [(ACCU2):(ACCU1)] 1 0.6 0.36 0.24 0.18 Status word for: /D, MOD BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - Yes Yes Yes Yes - - - - S7-400 Instruction List A5E00267845-02 64 Floating-Point Math (32 Bits) Floating-Point Math (32 Bits) The result of the math instruction is in ACCU1. ACCU3 and ACCU4 are then transferred to ACCU2 and ACCU3. Instruction Address ID Description Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 +R Add 2 real numbers (32 bits) (ACCU1)=(ACCU2)+(ACCU1) 1 0.4 0.24 0.16 0.12 -R Subtract 1 real number from another (32 bits) (ACCU1)=(ACCU2)-(ACCU1) 1 0.4 0.24 0.16 0.12 *R Multiply 1 real number by another (32 bits) (ACCU1)=(ACCU2)*(ACCU1) 1 0.2 0.12 0.08 0.06 /R Divide 1 real number by another (32 bits) (ACCU1)=(ACCU2):(ACCU1) 1 0.7 0.42 0.28 0.21 Status word for: +R, -R, *R, /R BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - Yes Yes Yes Yes - - - - S7-400 Instruction List A5E00267845-02 65 Floating-Point Math (32 Bits) Floating-Point Math (32 Bits), continued Instruction Address ID Description Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 NEGR Negate the real number in ACCU1 1 0.1 0.06 0.04 0.03 ABS Form the absolute value of the real number in ACCU1 1 0.1 0.06 0.04 0.03 Status word for: NEGR, ABS BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - - - - - - - - - S7-400 Instruction List A5E00267845-02 66 Square Root and Square Instructions (32 Bits) Square Root and Square Instructions (32 Bits) The result of the instruction is in ACCU1. The SQRT instruction can be interrupted. Instruction Address ID Description Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 SQRT Calculate the square root of a real number in ACCU1 1 1.7 1.02 0.68 0.51 SQR Form the square of the real number in ACCU1 1 0.2 0.12 0.08 0.06 Status word for: SQRT, SQR BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - Yes Yes Yes Yes - - - - S7-400 Instruction List A5E00267845-02 67 Logarithmic Function (32 Bits) Logarithmic Function (32 Bits) The result of the logarithmic function is in ACCU1. The instructions can be interrupted. Instruction Address ID Description Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 LN Form the natural logarithm of a real number in ACCU1 1 20 13 9 7 EXP Calculate the exponential value of a real number in ACCU1 to the base e (= 2.71828) 1 21 15 10 8 Status word for: BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: LN, EXP - - - - - - - - - Instruction affects: - Yes Yes Yes Yes - - - - S7-400 Instruction List A5E00267845-02 68 Trigonometrical Functions (32 Bits) Trigonometrical Functions (32 Bits) The result of the instruction is in ACCU1. The instructions can be interrupted. Instruction Address ID Description Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 SIN Calculate the sine of a real number 1 6,6 3,96 2,64 1,98 ASIN Calculate the arcsine of a real number 1 33 - 38 22 - 24 15 - 17 13 COS Calculate the cosine of a real number 1 6,6 3,96 2,64 1,98 ACOS Calculate the arccosine of a real number 1 36 - 40 25 - 27 16 - 18 12 - 14 TAN Calculate the tangent of a real number 1 20 14 10 7 ATAN Calculate the arctangent of a real number 1 14 - 18 10 - 13 6-9 5-7 Status word for: SIN, ASIN, COS, ACOS, TAN, ATAN BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - Yes Yes Yes Yes - - - - S7-400 Instruction List A5E00267845-02 69 Adding Constants Adding Constants Adding integer constants and storing the result in ACCU1. The status word is not affected. Instruction Address ID Description Length in Words Execution Time in ms CPU 412 CPU 414 CPU 416 CPU 417 + i8 Add an 8-bit integer constant 1 0.1 0.06 0.04 0.03 + i16 Add a 16-bit integer constant 2 0.125 0.075 0.05 0.042 + i32 Add a 32-bit integer constant 3 0.185 0.11 0.075 0.062 S7-400 Instruction List A5E00267845-02 70 Adding Using Address Registers Adding Using Address Registers Adding a 16-bit integer to the contents of the address register. The value is either specified as an address in the instruction or is in ACCU1-L. The status word is not affected. Instruction Address ID +AR1 +AR1 m (0 to 4095) +AR2 +AR2 m (0 to 4095) S7-400 Instruction List A5E00267845-02 Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 Add the contents of ACCU1-L to those of AR1 1 0.2 0.12 0.08 0.06 Add a pointer constant to the contents of AR1 2 0.2 0.12 0.08 0.06 Add the contents of ACCU1-L to those of AR2 1 0.2 0.12 0.08 0.06 Add pointer constant to the contents of AR2 2 0.2 0.12 0.08 0.06 Description 71 Comparison Instructions (16-Bit Integers) Comparison Instructions (16-Bit Integers) Comparing the 16-bit integers in ACCU1-L and ACCU2-L. RLO = 1 if the condition is satisfied. Instruction Address ID Description Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 ==I ACCU2-L=ACCU1-L 1 0.1 0.06 0.04 0.03 <>I ACCU2-L0ACCU1-L 1 0.1 0.06 0.04 0.03 <I ACCU2-L<ACCU1-L 1 0.1 0.06 0.04 0.03 <=I ACCU2-L<=ACCU1-L 1 0.1 0.06 0.04 0.03 >I ACCU2-L>ACCU1-L 1 0.1 0.06 0.04 0.03 >=I Status word for: ACCU2-L>=ACCU1-L ==I, <>I, <I, <=I, >I, >=I 1 0.1 0.06 0.04 0.03 BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - Yes Yes 0 - 0 Yes Yes 1 S7-400 Instruction List A5E00267845-02 72 Comparison Instructions (32-Bit Integers) Comparison Instructions (32-Bit Integers) Comparing the 32-bit integers in ACCU1 and ACCU2. RLO = 1 if the condition is satisfied. Instruction Address ID Description Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 ==D ACCU2=ACCU1 1 0.1 0.06 0.04 0.03 <>D ACCU20ACCU1 1 0.1 0.06 0.04 0.03 <D ACCU2<ACCU1 1 0.1 0.06 0.04 0.03 <=D ACCU2<=ACCU1 1 0.1 0.06 0.04 0.03 >D ACCU2>ACCU1 1 0.1 0.06 0.04 0.03 >=D Status word for: ACCU2>=ACCU1 ==D,< >D, <D, <=D, >D, >=D 1 0.1 0.06 0.04 0.03 BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - Yes Yes 0 - 0 Yes Yes 1 S7-400 Instruction List A5E00267845-02 73 Comparison Instructions (32-Bit Real Numbers) Comparison Instructions (32-Bit Real Numbers) Comparing the 32-bit real numbers in ACCU1 and ACCU2. RLO = 1 if the condition is satisfied. Instruction Address ID Description Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 ==R ACCU2=ACCU1 1 0.1 0.06 0.04 0.03 <>R ACCU20ACCU1 1 0.1 0.06 0.04 0.03 <R ACCU2<ACCU1 1 0.1 0.06 0.04 0.03 <=R ACCU2<=ACCU1 1 0.1 0.06 0.04 0.03 >R ACCU2>ACCU1 1 0.1 0.06 0.04 0.03 >=R Status word for: ACCU2>=ACCU1 ==R, <>R, <R, <=R, >R, >=R 1 0.1 0.06 0.04 0.03 BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - Yes Yes Yes Yes 0 Yes Yes 1 S7-400 Instruction List A5E00267845-02 74 Shift Instructions Shift Instructions Shifting the contents of ACCU1 and ACCU1-L to the left or right by the specified number of places. If no address identifier is specified, the contents of ACCU2-LL are used as the number of places. The last bit shifted is loaded into condition code bit CC 1. Instruction SLW1) SLW SLD 0 ... 15 0 ... 32 SRW1) SRW CPU 412 CPU 414 CPU 416 CPU 417 0.1 0.06 0.04 0.03 Shift the contents of ACCU1 to the left. Positions that become free are provided with zeros. 1 0.1 0.06 0.04 0.03 Shift the contents of ACCU1-L to the right. Positions that become free are provided with zeros. 1 0.1 0.06 0.04 0.03 0 ... 15 Status word for: Description Shift the contents of ACCU1-L to the left. Positions that become free are provided with zeros. SLD Execution Time in ms Length in Words 1 Address ID BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - Yes 0 0 - - - - - 1) SLW, SLD, SRW No. of places shifted: 0 to 16 S7-400 Instruction List A5E00267845-02 75 Shift Instructions Shift Instructions, continued Instruction CPU 412 CPU 414 CPU 416 CPU 417 0.1 0.06 0.04 0.03 1 0.1 0.06 0.04 0.03 0 ... 15 Shift the contents of ACCU1-L with sign to the right. Positions that become free are provided with with the sign (bit 15). 1 0.1 0.06 0.04 0.03 0 ... 32 Shift the contents of ACCU1 with sign to the right. Positions that become free are provided with with the sign (bit 31). SRD SRD 0 ... 32 SSD SSD Status word for: Description Shift the contents of ACCU1 to the right. Positions that become free are provided with zeros. SSI1) SSI Execution Time in ms Length in Words 1 Address ID SRD,SSI, SSD BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - Yes 0 0 - - - - - 1) No. of places shifted: 0 to 16 S7-400 Instruction List A5E00267845-02 76 Rotate Instructions Rotate Instructions Rotate the contents of ACCU1 to the left or right by the specified number of places. If no address identifier is specified, the contents of ACCU2-LL are used as the number of places. The last bit shifted is loaded into condition code bit CC1. Instruction RLD RLD 0 ... 32 RRD RRD 0 ... 32 Status word for: Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 Rotate the contents of ACCU1 to the left 1 0.1 0.06 0.04 0.03 Rotate the contents of ACCU1 to the right 1 0.1 0.06 0.04 0.03 Address ID Description RLD, RRD BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - Yes 0 0 - - - - - S7-400 Instruction List A5E00267845-02 77 Rotate Instructions Rotate Instructions, continued Instruction Address ID Execution Time in ms Length in Words Description CPU 412 CPU 414 CPU 416 CPU 417 RLDA Rotate the contents of ACCU1 one bit position to the left through condition code bit CC 1 0.1 0.06 0.04 0.03 RRDA Rotate the contents of ACCU1 one bit position to the right through condition code bit CC 1 0.1 0.06 0.04 0.03 Status word for: RLDA, RRDA BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - Yes 0 0 - - - - - S7-400 Instruction List A5E00267845-02 78 Accumulator Transfer Instructions, Incrementing and Decrementing Accumulator Transfer Instructions, Incrementing and Decrementing The status word is not affected. Instruction Address ID Description Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 CAW Reverse the order of the bytes in ACCU1-L. 1 0.1 0.06 0.04 0.03 CAD Reverse the order of the bytes in ACCU1. 1 0.1 0.06 0.04 0.03 TAK Swap the contents of ACCU1 and ACCU2 1 0.1 0.06 0.04 0.03 ENT The contents of ACCU2 and ACCU3 are transferred to ACCU3 and ACCU4. 1 0.1 0.06 0.04 0.03 LEAVE The contents of ACCU3 and ACCU4 are transferred to ACCU2 and ACCU3. 1 0.1 0.06 0.04 0.03 PUSH The contents of ACCU1, ACCU2 and ACCU3 are transferred to ACCU2, ACCU3 and ACCU4 1 0.1 0.06 0.04 0.03 POP The contents of ACCU2, ACCU3 and ACCU4 are transferred to ACCU1, ACCU2 and ACCU3 1 0.1 0.06 0.04 0.03 S7-400 Instruction List A5E00267845-02 79 Accumulator Transfer Instructions, Incrementing and Decrementing, continued Accumulator Transfer Instructions, Incrementing and Decrementing, continued Instruction Address ID Description Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 INC k8 Increment ACCU1-LL 1 0.1 0.06 0.04 0.03 DEC k8 Decrement ACCU1-LL 1 0.1 0.06 0.04 0.03 S7-400 Instruction List A5E00267845-02 80 Program Display and Null Operation Instructions Program Display and Null Operation Instructions The status word is not affected. Instruction Address ID Description Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 BLD k8 Program display instruction: Is treated by the CPU as a null operation instruction. 1 0.1 0.06 0.04 0.03 NOP 0 1 Null operation instruction 1 0.1 0.06 0.04 0.03 S7-400 Instruction List A5E00267845-02 81 Data Type Conversion Instructions Data Type Conversion Instructions The results of the conversion are in ACCU1. Instruction Addr. ID Description Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 BTI Convert contents of ACCU1-L from BCD (0 to +/- 999) to integer (16 bits) (BCD To Int) 1 0.1 0.06 0.04 0.03 BTD Convert contents of ACCU1 from BCD (0 to +/-9 999 999) to double integer (32 bits) (BCD To Doubleint) 1 0.1 0.06 0.04 0.03 DTR Convert contents of ACCU1 from double integer (32 bits) to real number (32 bits) (Doubleint To Real) 1 0.3 0.18 0.12 0.09 ITD Convert contents of ACCU1 from integer (16 bits) to double integer (32 bits) (Int To Doubleint) 1 0.3 0.06 0.04 0.03 Status word for: BTI, BTD, DTR, ITD BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - - - - - - - - - S7-400 Instruction List A5E00267845-02 82 Data Type Conversion Instructions Data Type Conversion Instructions, continued Instruction Addr. ID Description Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 ITB Convert contents of ACCU1-L from integer (16 bits) to BCD from 0 to +/- 999 (Int To BCD) 1 0.1 0.06 0.04 0.03 DTB Convert contents of ACCU1 from double integer (32 bits) to BCD from 0 to +/- 9 999 999 (Doubleint To BCD) 1 0.2 0.12 0.08 0.06 Status word for: ITB, DTB BR CC1 CC0 Instruction evaluates: - - - Instruction affects: - - - S7-400 Instruction List A5E00267845-02 OV OS OR STA RLO /FC - - - - - - Yes Yes - - - - 83 Data Type Conversion Instructions Data Type Conversion Instructions, continued The real number to be converted is in ACCU1. Instruction Address ID Description Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 RND+ Convert a real number into a 32-bit integer. The number is rounded up to the next whole number. 1 0.4 0.24 0.16 0.12 RND Convert a real number into a 32-bit integer. 1 0.4 0.24 0.16 0.12 RND- Convert a real number into a 32-bit integer. The number is rounded down to the next whole number. 1 0.4 0.24 0.16 0.12 TRUNC Convert a real number into a 32-bit integer. The places after the decimal point are truncated. 1 0.4 0.24 0.16 0.12 Status word for: RND, RND-, RND+, TRUNC BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - - - Yes Yes - - - - S7-400 Instruction List A5E00267845-02 84 Forming the Ones and Twos Complements Forming the Ones and Twos Complements Instruction Address ID Description Length in Words Execution Time in ms CPU 412 CPU 414 CPU 416 CPU 417 INVI Form the ones complement of ACCU1-L 1 0.1 0.06 0.04 0.03 INVD Form the ones complement of ACCU1 1 0.1 0.06 0.04 0.03 Status word for: INVI, INVD BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - - - - - - - - - NEGI Form the twos complement of ACCU1-L (integer) 1 0.1 0.06 0.04 0.03 NEGD Form the twos complement of ACCU1 (double integer) 1 0.1 0.06 0.04 0.03 Status word for: BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: NEGI, NEGD - - - - - - - - - Instruction affects: - Yes Yes Yes Yes - - - - S7-400 Instruction List A5E00267845-02 85 Block Call Instructions Block Call Instructions The runtimes of the System Functions are specified in the chapter entitled "System Functions" as of page 106. The information on the status word only relates to the block call itself and not to the commands called in this block. Instruction Address ID Length in Words Description Execution Time in ms CPU 412 CPU 414 FB q, DB q Unconditional call of an FB, with parameter transfer CALL SFB q, DB q Unconditional call of an SFB, with parameter transfer 16/171) 4.0 2) 2.4 2) 1.6 2) 1.26 2) CALL FC q Unconditional call of a function, with parameter transfer 7/81) 3.2 2) 1.92 2) 1.28 2) 1.02 2) CALL SFC q Unconditional call of an SFC, with parameter transfer 8 3.2 2) 1.92 2) 1.28 2) 1.02 2) Status word for: 1.6 2) 1.26 2) BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - - - - 0 0 1 - 0 1) 2) CALL 2.4 2) CPU 417 CALL 4.0 2) CPU 416 15/171) The instruction length depends on the block number from (0...255 or more) Plus time required for supplying parameters S7-400 Instruction List A5E00267845-02 86 Block Call Instructions Block Call Instructions, continued Instruction UC CC Address ID Length in Words Description FB q FC q FB [e] FC [e] Parameter Unconditional call of blocks, without parameter transfer Memory-indirect FB call Memory-indirect FC call FB/FC call via parameter 11)/2 FB q FC q FB [e] FC [e] Parameter Conditional call of blocks, without parameter transfer Memory-indirect FB call Memory-indirect FC call FB/FC call via parameter 11)/2 Status word for: UC, CC 2) Execution Time in ms CPU 412 CPU 414 CPU 416 CPU 417 2.2 2.2 2.2+ 2.2+ 2.6 1.32 1.32 1.32+ 1.32+ 1.56 0.88 0.88 0.88+ 0.88+ 1.04 0.72 0.72 0.72+ 0.72+ 0.87 2.2/0.5 3) 2.2/0.5 3) 2.2+/0.5 3) 2.2+/0.5 3) 2.6/0.5 3) 1.32/0.3 3) 1.32/0.3 3) 1.32+/0.3 3) 1.32+/0.3 3) 1.56/0.3 3) 0.88/0.2 3) 0.88/0.2 3) 0.88+/0.2 3) 0.88+/0.2 3) 1.04/0.2 3) 0.72/0.18 3) 0.72/0.18 3) 0.72+/0.18 3) 0.72+/0.18 3) 0.87/0.18 3) 2 2 2 2 2 2 BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - - - - 0 0 1 - 0 + 1) 2) 3) Plus time required for loading the address of the instruction (see page 20) With direct instruction (DB) addressing; Block No. 0 to 255 Depending on RLO, sets RLO = 1 If call is not executed S7-400 Instruction List A5E00267845-02 87 Block Call Instructions Block Call Instructions, continued Execution Time in ms Instruction Address ID OPN Length in Words Description CPU 412 CPU 414 CPU 416 CPU 417 1. open 2. - n. open 1. open 2. - n. open 1. open 2. - n. open 1. open 2. - n. open 1) 1) 1) 1) Select a data block DB q Direct data block, DB no. 1 to 255 1 0.5 0.1 0.3 0.06 0.2 0.04 0.21 0.03 DB q DI q Direct data block, DB Direct instance DB 2 0.5 0.125 0.3 0.075 0.2 0.05 0.210 0.042 DB [e] Data block, indirect save Bit memory area M Local data area L Data block DB/DI 2 0.7 0.7 0.8 0.325 0.325 0.425 0.420 0.420 0.480 0.195 0.195 0.255 0.280 0.280 0.320 0.130 0.130 0.170 0.270 0.270 0.330 0.102 0.102 0.162 Instance DB, indirect save Bit memory area M Local data area L Data block DB/DI 2 0.7 0.7 0.8 0.325 0.325 0.425 0.420 0.420 0.480 0.195 0.195 0.255 0.280 0.280 0.320 0.130 0.130 0.170 0.270 0.270 0.330 0.102 0.102 0.162 0.9 0.525 0.54 0.315 0.36 0.192 DI [e] Param. Data block via parameters Status word for: 2 0.36 0.21 BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - - - - - - - - - 1) OPN if the same DB or DI is already selected S7-400 Instruction List A5E00267845-02 88 Block End Instructions Block End Instructions Instruction Address ID Description Length in Words Execution Time in ms CPU 412 CPU 414 CPU 416 CPU 417 BE End block 1 4.0 2.4 1.6 1.62 BEU End block unconditionally 1 4.0 2.4 1.6 1.62 Status word for: BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: BE, BEU - - - - - - - - - Instruction affects: - - - - 0 0 1 - 0 BEC Status word for: End block conditionally if RLO = "1" 2.52 0.31) 1.78 0.21) 1.68 0.181) BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - Yes - Instruction affects: - - - - Yes 0 1 1 0 1) BEC 4.2 0.51) If jump is not executed S7-400 Instruction List A5E00267845-02 89 Exchanging Shared Data Block and Instance Data Block Exchanging Shared Data Block and Instance Data Block Exchanging the two current data blocks. The current shared data block becomes the current instance data block, and vice versa. The status word is not affected. Instruction Address ID CDB S7-400 Instruction List A5E00267845-02 Description Exchange shared data block and instance data block Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 1 0.2 0.12 0.08 0.06 90 Jump Instructions Jump Instructions Jumping as a function of conditions. Instruction JU Address ID LABEL Status word for: Length in Words Description Jump unconditionally CPU 412 2 CPU 414 0.6 CPU 416 0.36 CPU 417 0.24 0.21 BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - - - - - - - - - JC JU Execution Time in ms LABEL JCN Jump if RLO = "1" LABEL Status word for: Jump if RLO = "0" 0.6; 0.1251) 0.36; 0.0751) 0.24; 0.051) 0.21; 0.0421) 2 0.6/0.125 1) 1) 1) 0.21/0.042 1) 0.36/0.075 0.24/0.05 BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - Yes - Instruction affects: - - - - - 0 1 1 0 1) JC, JCN 2 If jump is not executed S7-400 Instruction List A5E00267845-02 91 Jump Instructions Jump Instructions, continued Instruction Address ID Description Length in Words Execution Time in ms CPU 412 CPU 414 CPU 416 CPU 417 JCB LABEL Jump if RLO = "1". Save the RLO in the BR bit 2 0.6/0.125 1) 0.36/0.075 1) 0.24/0.05 1) 0.21/0.042 1) JNB LABEL Jump if RLO = "0". Save the RLO in the BR bit 2 0.6/0.125 1) 0.36/0.075 1) 0.24/0.05 1) 0.21/0.042 1) Status word for: JCB, JNB Instruction evaluates: Instruction affects: BR CC1 CC0 OV OS OR STA RLO /FC - - - - - - - Yes - Yes - - - - 0 1 1 0 JBI LABEL Jump if BR = "1" 2 0.6/0.125 1) 0.36/0.075 1) 0.24/0.05 1) 0.21/0.042 1) JNBI LABEL Jump if BR = "0" 2 0.6/0.125 1) 0.36/0.075 1) 0.24/0.05 1) 0.21/0.042 1) Status word for: JBI, JNBI Instruction evaluates: Instruction affects: 1) BR CC1 CC0 OV OS OR STA RLO /FC Yes - - - - - - - - - - - - - 0 1 - 0 If jump is not executed S7-400 Instruction List A5E00267845-02 92 Jump Instructions Jump Instructions, continued Instruction JO Address ID LABEL Status word for: Length in Words Description Jump on stored overflow (OV = "1") 2 0.6; CPU 414 0.1251) 0.36; CPU 416 0.0751) 0.24; 0.051) CPU 417 0.21; 0.0421) BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - Yes - - - - - Instruction affects: - - - - - - - - - JOS JO Execution Time in ms CPU 412 LABEL Status word for: Jump on stored overflow (OS = "1") 0.6/0.125 1) 0.36/0.075 1) 0.24/0.05 1) 0.21/0.042 1) BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - Yes - - - - Instruction affects: - - - - 0 - - - - 1) JOS 2 If jump is not executed S7-400 Instruction List A5E00267845-02 93 Jump Instructions Jump Instructions, continued Instruction Address ID Length in Words Description Execution Time in ms CPU 412 CPU 414 1) 0.21/0.042 1) LABEL Jump if "unordered math instruction" (CC1=1 and CC0=1) 2 0.6/0.125 JZ LABEL Jump if result = 0 (CC1=0 and CC0=0) 2 0.6; 0.125 1) 0.36; 0.075 1) 0.24; 0.05 1) 0.24; 0.05 1) JP LABEL Jump if result > 0 (CC1=1 and CC0=0) 2 0.6; 0.125 1) 0.36; 0.075 1) 0.24; 0.05 1) 0.24; 0.05 1) JM LABEL Jump if result < 0 (CC1=0 and CC0=1) 2 0.6; 0.125 1) 0.36; 0.075 1) 0.24; 0.05 1) 0.24; 0.05 1) JN LABEL Jump if result 0 0 (CC1=1 and CC0=0) or (CC1=0 and CC0=1) 2 0.6; 0.125 1) 0.36; 0.075 1) 0.24; 0.05 1) 0.24; 0.05 1) BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - Yes Yes - - - - - - Instruction affects: - - - - - - - - - 1) JUO, JZ, JP, JM, JN, 0.24/0.05 CPU 417 1) JUO Status word for: 0.36/0.075 CPU 416 1) If jump is not executed S7-400 Instruction List A5E00267845-02 94 Jump Instructions Instruction Address ID Length in Words Description Execution Time in ms CPU 412 CPU 414 CPU 416 CPU 417 JMZ LABEL Jump if result v 0 (CC1=0 and CC0=1) or (CC1=0 and CC0=0) 2 0.6/0.125 JPZ LABEL Jump if result w 0 (CC1=1 and CC0=0) or (CC1=0 and CC0=0) 2 0.6/0.125 1) BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - Yes Yes - - - - - - Instruction affects: - - - - - - - - - Status word for: 1) JUO, JZ, JP, JM, JN, JMZ, JPZ 1) 0.36/0.075 1) 1) 0.21/0.042 1) 0.24/0.05 1) 0.21/0.042 1) 0.24/0.05 0.36/0.075 1) If jump is not executed S7-400 Instruction List A5E00267845-02 95 Jump Instructions Jump Instructions, continued Instruction Address ID Description Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 JL LABEL Jump distributor This instruction is followed by a list of jump instructions. The address identifier is a jump label to subsequent instructions in this list. ACCU1-LL contains the number of the jump instruction to be executed (max. 254). The number of the first jump instruction is 0. 2 0.7 0.42 0.28 0.24 LOOP LABEL Decrement ACCU1-L and jump if ACCU1-L 0 0 (loop programming) 2 0.6/0.125 1) 0.36/0.075 1) 0.24/0.05 1) 0.21/0.042 1) Status word for: BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - - - - - - - - - 1) JL, LOOP If jump is not executed S7-400 Instruction List A5E00267845-02 96 Instructions for the Master Control Relay (MCR) Instructions for the Master Control Relay (MCR) MCR=1MCR is deactivated MCR=0MCR is activated; "T" and "=" instructions write zeros to the corresponding address identifiers if RLO = "0"; "S" and "R" instructions leave the memory contents unchanged. Instruction Address ID MCR( Status word for: Description Open an MCR zone. Save the RLO to the MCR stack. MCR( Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 1 0.1 0.06 0.04 0.03 CC1 BR CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - Yes - Instruction affects: - - - - - 0 1 - 0 )MCR Status word for: Close an MCR zone. Pop an entry off the MCR stack. )MCR 1 0.1 0.06 0.04 0.03 BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - - - - - 0 1 - 0 S7-400 Instruction List A5E00267845-02 97 Instructions for the Master Control Relay (MCR) Instructions for the Master Control Relay (MCR), continued Instruction Address ID MCRA Activate the MCR MCRD Status word for: Description Deactivate the MCR MCRA, MCRD Execution Time in ms Length in Words CPU 412 CPU 414 CPU 416 CPU 417 1 0.1 0.06 0.04 0.03 1 0.1 0.06 0.04 0.03 BR CC1 CC0 OV OS OR STA RLO /FC Instruction evaluates: - - - - - - - - - Instruction affects: - - - - - - - - - S7-400 Instruction List A5E00267845-02 98 Oganization Blocks (OB) Oganization Blocks (OB) A user program for the S7-400 is made up of blocks containing the statements, parameters and data for the relevant CPU. The number of blocks you can create or which are provided by the operating system is different for each of the S7-400 CPUs. You will find a detailed description of the OBs and their use in the STEP 7 Programming Manual. Organization Blocks CPU 412 CPU 414 CPU 414-4H CPU 416 CPU 417 CPU 417-4H Start Events (Hexadecimal Values) x x x x x x 1101, 1102, 1103, 1104, 1105 Free cycle OB 1 Time-of-day interrupts OB 10 x x x x x x 1111 OB 11 x x x x x x 1112 OB 12 x x x x x 1113 OB 13 x x x x x 1114 OB 14 x x x 1115 OB 15 x x x 1116 OB 16 x x x 1117 OB 17 x x x 1118 S7-400 Instruction List A5E00267845-02 99 Oganization Blocks (OB) Oganization Blocks (OB), continued Organization Blocks CPU 412 CPU 414 CPU 414-4H CPU 416 CPU 417 CPU 417-4H Start Events (Hexadecimal Values) Time-delay interrupts OB 20 x x x x x x 1121 OB 21 x x x x x x 1122 OB 22 x x x x x 1123 OB 23 x x x x x 1124 OB 30 x x x 1131 OB 31 x x x 1132 Timed interrupts 1) OB 32 x x x x x 1133 OB 33 x x x x x 1134 OB 34 x x x x x 1135 x x OB 35 x x x x 1136 OB 36 x x x 1137 OB 37 x x x 1138 OB 38 x x x 1139 1) x Further start events of H-CPUs for OB 30 to OB 38: 1130H S7-400 Instruction List A5E00267845-02 100 Oganization Blocks (OB) Organization Blocks (OB), continued Organization Blocks CPU 412 CPU 414 CPU 414-4H CPU 416 CPU 417 CPU 417-4H Start Events (Hexadecimal Values) OB 40 x x x x x x 1141, 1142, 1143, 1144, 1145 OB 41 x x x x x x 1141, 1142, 1143, 1144, 1145 OB 42 x x x x x 1141, 1142, 1143, 1144, 1145 OB 43 x x x x x 1141, 1142, 1143, 1144, 1145 OB 44 x x x 1141, 1142, 1143, 1144, 1145 OB 45 x x x 1141, 1142, 1143, 1144, 1145 OB 46 x x x 1141, 1142, 1143, 1144, 1145 OB 47 x x x 1141, 1142, 1143, 1144, 1145 Hardware interrupts Interrupt OBs for DPV1: OB 55 x x x x x x 1155 OB 56 x x x x x x 1156 OB 57 x x x x x x 1157 S7-400 Instruction List A5E00267845-02 101 Oganization Blocks (OB) Oganization Blocks (OB), continued Organization Blocks CPU 412 CPU 414 CPU 414-4H CPU 416 CPU 417 CPU 417-4H Start Events (Hexadecimal Values) x x x 1161, 1162 Multicomputing interrupts OB 60 x Synchronous cycle interrupt: OB 61 x x x x 1164 OB 62 x x x x 1165 OB 63 x x x x 1166 OB 64 x x x x 1167 Redundancy error interrupts: OB 70 x x 73A2, 73A3, 72A3 OB 72 x x 7301, 7302, 7303, 7320, 7321, 7322, 7323, 7331, 7333, 7334, 7335, 7340, 7341, 7342, 7343, 7344, 7950, 7951, 7952, 7852, 7953, 7954, 7955, 7855, 7956, 73C1, 73C2 Asynchronous error interrupts: OB 80 x x x x x x 3501, 3502, 3505, 3506, 3507, 350A OB 81 x x x x x x 3821, 3822, 3823, 3825, 3826, 3827, 3831, 3832, 3833, 3921, 3922, 3923, 3925, 3926, 3927, 3931, 3932, 3933 OB 82 x x x x x x 3842, 3942 S7-400 Instruction List A5E00267845-02 102 Oganization Blocks (OB) Organization Blocks CPU 412 CPU 414 CPU 414-4H CPU 416 CPU 417 CPU 417-4H Start Events (Hexadecimal Values) OB 83 x x x x x x OB 85 x x x x x OB 86 x x x x x x 38C1, 38C2, 39C1, 38C6, 38C7, 38C8 38C41), 38C51), 39C31), 39C41), 39C51) OB 87 x x x x x x 35D2, 35D3, 35D4, 35D5, 35E1, 35E2, 35E3, 35E4, 35E5, 35E6 OB 88 Background: x x x x x x 3571, 3572, 3573, 3574, 3575, 3576, 3578, 357A OB 90 x x x x x x x x x x x x x x x x x x 1385, 1386, 1387, 1388 3267, 3367, 3861, 3863, 3864, 3865, 3961, 3968 35A1, 35A2, 35A3, 38B3, 38B4, 39B1, 39B2, 39B3, 39B4 1191, 1192, 1193, 1195 Warm restart: 1) OB 100 x x 1381, 1382, 138A, 138B Hot restart: OB 101 1383, 1384 Cold restart: OB 102 Synchronous error interrupts: OB 121 x x x x x x 2521, 2522, 2523, 2524, 2525, 2526, 2527, 2528, 2529, 2530, 2531, 2532, 2533, 2534, 2535, 253A, 253C, 253D, 253E, 253F OB 122 x x x x x x 2942, 2943, 2944, 2945 1) Further start events of H-CPUs for OB 100: 138CH, 138DH S7-400 Instruction List A5E00267845-02 103 Function Blocks (FB) Function Blocks (FB) The following tables list the quantities, numbers and maximum sizes of the function blocks you can create for the various S7-400 CPUs. Function Blocks CPU 412-1 CPU 412-2 CPU 414 CPU 416 CPU 417 Quantity 256 256 1024 2048 6144 Permissible numbers 0 to 255 0 to 255 0 to 1023 0 to 2047 0 to 6143 Maximum size of a function block (code required for execution) 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes S7-400 Instruction List A5E00267845-02 104 Functions (FC) and Data Blocks Functions (FC) and Data Blocks The following tables list the quantities, numbers and maximum sizes of the functions and data blocks you can create for the various S7-400 CPUs. Functions CPU 412-1 CPU 412-2 CPU 414 CPU 416 CPU 417 Quantity 256 256 2048 2048 6144 Permissible numbers 0 to 255 0 to 255 0 to 2047 0 to 2047 0 to 6143 Maximum size of a function (code required for execution) 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes Data Blocks CPU 412-1 CPU 412-2 CPU 414 CPU 416 CPU 417 Quantity 511 511 4095 4095 8191 Permissible numbers 1 to 511 1 to 511 1 to 4095 1 to 4095 1 to 8191 Maximum size of a data block (number of data bytes) 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes 64 Kbytes S7-400 Instruction List A5E00267845-02 105 System Functions System Functions The following tables show the system functions which are provided by the operating system of the S7-400 CPUs and the execution times for the various CPUs. (X: function available, execution times not yet available before printing). SFC No. 0 1 2 3 4 5 CPU 412 CPU 414 CPU 416 Set clock Read clock Set run-time meter Start and stop run-time meter Read run-time meter Find logical address of a channel Rack 0 195 31 27 23 29 38 111 18 16 14 18 23 75 13 11 10 12 15 internal DP 51 31 21 SFC Name SET_CLK READ_CLK SET_RTM CTRL_RTM READ_RTM GADR_LGC Function Execution Time in ms CPU CPU CPU 417 414-4H 414-4H solo redundant 66 267 647 10 19 55 9 16 16 8 13 13 10 18 51 13 23 23 CPU CPU 417-4H 417-4H solo redundant 170 507 11 37 10 10 8 8 11 30 13 13 18 31 31 18 18 6 RD_SINFO Read start information of current OB 33 20 14 11 20 20 11 11 7 DP_PRAL Trigger a process interrupt at the DP master First call 275 170 113 106 -- -- -- -- Intermediate call 25 15 10 8 -- -- -- -- Last call 25 15 10 8 -- -- -- -- S7-400 Instruction List A5E00267845-02 106 System Functions SFC No. SFC Name 9 EN_MSG 10 DIS_MSG S7-400 Instruction List A5E00267845-02 Function Enable block-related, symbol-related, and group status messages. First call, REQ = 1 CPU 412 CPU 414 CPU 416 182 103 69 Execution Time in ms CPU CPU CPU CPU CPU 417 414-4H 414-4H 417-4H 417-4H solo redunsolo redundant dant 59 116 231 68 144 Last call 41 24 16 13 25 61 15 40 Disable block-related, symbol-related, and group status messages. First call, REQ = 1 183 104 70 60 117 240 68 145 Last call 41 24 16 13 25 60 15 40 107 System Functions SFC No. 11 11 1) SFC Name DPSYC_FR DPSYC_FR Execution Time in ms CPU CPU CPU CPU CPU 417 414-4H 414-4H 417-4H 417-4H solo redunsolo redundant dant 52 ----- CPU 412 CPU 414 CPU 416 Synchronize groups of DP Slaves First call, internal DP interface, REQ = 1 158 90 60 Intermediate call, internal DP interface, BUSY = 1 1) 40+ n* 4 23+ n* 3 16+ n* 2 13+ n* 2 -- -- -- -- Last call, internal DP interface, BUSY=0 1) 42+ n* 4 24+n *3 17+ n* 2 14+ n* 2 -- -- -- -- First call, external DP interface, REQ=1 76 51 40 36 -- -- -- -- Intermediate call, external DP interface, BUSY = 1 1) 56+ n* 4 35+ n* 3 26+ n* 2 52+ n* 2 -- -- -- -- Last call, external DP interface, BUSY= 0 1) 56+ n* 4 35+ n* 3 26+ n* 2 23+ n* 2 -- -- -- -- Function n = number of active jobs with the same logic address S7-400 Instruction List A5E00267845-02 108 System Functions Execution Time in ms SFC No. SFC Name Function CPU 412 CPU 414 CPU 416 CPU 417 CPU CPU CPU CPU 414-4H 414-4H 414-7H 417-4H solo redunsolo redundant dant 12 D_ACT_DP Deactivate and activate DP slaves via integrated DP interface, MODE = 0 86 50 34 29 -- -- -- -- 12 D_ACT_DP Deactivate and activate DP slaves via integrated DP interface, MODE = 1 First call 265 149 102 89 -- -- -- -- Intermediate call 81 48 33 28 -- -- -- -- Last call 103 61 41 36 -- -- -- -- Deactivate and activate DP slaves via integrated DP interface, MODE = 2 First call 485 290 193 170 -- -- -- -- Intermediate call 81 48 32 28 -- -- -- -- Last call 101 60 40 35 -- -- -- -- 12 D_ACT_DP 12 D_ACT_DP Deactivate and activate DP slaves via external DP interface, MODE = 0 86 51 34 29 -- -- -- -- 12 D_ACT_DP Deactivate and activate DP slaves via external DP interface, MODE = 1 First call 259 144 99 85 -- -- -- -- Intermediate call 81 48 33 28 -- -- -- -- Last call 103 61 41 36 -- -- -- -- S7-400 Instruction List A5E00267845-02 109 System Functions Execution Time in ms SFC No. 12 13 CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU 414-4H 414-7H redunsolo dant CPU 417-4H redundant Deactivate and activate DP slaves via external DP interface, MODE = 2 First call 472 280 186 169 -- -- -- -- Intermediate call 80 48 32 28 -- -- -- -- Last call 101 60 41 35 -- -- -- -- Read slave diagnostic data First call 240 141 95 83 155 200 90 122 Intermediate call 88 53 36 30 59 59 35 35 Last call (28 bytes) 122 72 48 42 79 79 45 45 SFC Name D_ACT_DP DP_NRMDG S7-400 Instruction List A5E00267845-02 Function 110 System Functions Execution Time in ms SFC No. 14 15 SFC Name DPRD_DAT DPWR_DAT 17 ALARM_SQ 18 ALARM_S 1) Function CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU 414-4H redundant CPU 417-4H solo CPU 417-4H redundant Read consistent user data (n bytes) via integrated DP interface 3 bytes 56 36 24 21 47 86 29 51 via integrated DP interface 32 bytes 60 37 25 22 50 98 30 57 via external DP interface 3 bytes 71 45 32 27 71 90 31 57 via external DP interface 32 bytes 187 146 115 107 145 192 112 135 Write consistent user data (n bytes) via integrated DP interface 3 bytes 601)/ 622) 361)/ 372) 251)/ 252) 211)/ 212) 421) 492) 781) 822) 271) 292) 451) 482) via integrated DP interface 32 bytes 641)/ 662) 371)/ 412) 251)/ 262) 211)/ 222) 481) 532) 801) 862) 271) 312) 491) 542) via external DP interface 3 bytes 661)/ 682) 421)/ 432) 301)/ 312) 271)/ 272) 721) 792) 891) 932) 341) 372) 501) 532) via external DP interface 32 bytes 1251)/ 1282) 961)/ 982) 831)/ 852) 791)/ 802) 1641) 1892) 1751) 2052) 811) 912) 981) 1042) Generate acknowledgeable block-related messages. First call, SIG = 0 -> 1 276 165 116 98 222 319 107 187 Empty call 123 72 48 41 74 154 43 93 Generate unacknowledgeable block-related messages. First call, SIG = 0 -> 1 263 155 108 88 214 329 102 184 38 87 Empty call without data transmission to the process image S7-400 Instruction List A5E00267845-02 CPU 412 111 64 43 36 66 151 with data transmission to the process image 2) 111 System Functions Execution Time in ms SFC No. SFC Name 19 ALARM_SC 20 BLKMOV Function CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU 414-4H redundant CPU 417-4H solo CPU 417-4H redundant Acknowledgment status of the last ALARM_SQ entering state message. Copy variable within the work memory (n = number of bytes to be copied) 81 45 30 25 48 144 27 75 58 + n* 0,08 36 + n* 0,046 23 + n* 0,03 19 + n* 0,03 36 + n* 0,046 36 + n* 0,046 18 + n * 0,03 18 + n * 0,03 Source = Load memory 610 + n* 0,79 400 + n* 0,48 339 + n* 0,47 386 + n* 0,47 610 + n* 1,6 1058 + n* 1,6 473 + n* 1,2 921 + n* 1,2 28 + n* 0,016 15 + n * 0,01 15 + n * 0,01 21 FILL Set array default variables within the work memory (n = length of target variables in bytes) 43 + n* 0,024 26 + n* 0,016 17 + n* 0,012 13 + n* 0,01 28 + n* 0,016 22 CREAT_DB Create data block n = DB length [bytes] 111 65 43 38 100 + 283 + 59 + 169 + n * 0,07 n * 0,07 n * 0,04 n * 0,04 Occupy last free DB No. from a field of 100 DBs 517 294 196 164 685 859 397 507 23 24 DEL_DB TEST_DB Delete data block Test data block 112 35 67 21 45 14 39 12 160 50 624 233 95 30 371 139 25 COMPRESS Compress user memory First call (trigger) 112 64 43 38 77 167 46 97 S7-400 Instruction List A5E00267845-02 112 System Functions Execution Time in ms SFC No. 26 27 SFC Name UPDAT_PI UPDAT_PO Function CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU 414-4H redundant CPU 417-4H solo CPU 417-4H redundant Intermediate call (active) 24 14 10 8 14 14 8 8 Update process image input table (run-time entry for 1 DI 32 in the central rack) 43 28 21 18 49 98 31 58 AI 8* 13Bit 67 50 42 39 124 173 81 109 Update process image output table (run-time entry for 1 DO 32 in the central rack) 39 27 21 18 42 74 27 45 AO 8* 13Bit 62 46 39 36 97 130 65 83 28 29 30 SET_TINT CAN_TINT ACT_TINT Set time-of-day interrupt Cancel time-of-day interrupt Activate time-of-day interrupt 92 30 63 54 17 35 36 12 24 32 10 21 54 119 36 92 374 72 32 74 22 56 234 48 31 QRY_TINT Query time-of-day interrupt 16 10 7 5 9 9 6 6 32 SRT_DINT Start time-delay interrupt 49 28 19 17 28 28 17 17 33 CAN_DINT Cancel time-delay interrupt 33 19 13 11 25 25 15 15 34 QRY_DINT Query time-delay interrupt 16 10 7 5 10 10 6 6 35 MP_ ALM Trigger multicomputing interrupt 368 209 142 130 -- -- -- -- 36 MSK_FLT Mask synchronous faults 19 12 8 7 12 12 7 7 S7-400 Instruction List A5E00267845-02 113 System Functions Execution Time in ms SFC No. SFC Name 37 DMSK_FLT 38 39 40 Function CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU 414-4H redundant CPU 417-4H solo CPU 417-4H redundant 23 14 10 8 14 14 8 8 READ_ERR Read error register 23 14 9 8 14 14 8 8 DIS_IRT Discard new events Block all events (MODE = 0) 254 126 85 78 128 128 75 75 Block all events of a priority class (MODE = 1) 55 31 21 18 31 31 18 18 Block one event (MODE = 2) 31 18 13 11 18 18 11 11 Stop discarding events Enable all events (MODE = 0) 205 121 82 71 129 129 75 75 Enable all events in a priority class (MODE = 1) 54 30 20 17 30 30 17 17 Enable an event (MODE = 2) 29 17 12 10 17 17 10 10 EN_IRT S7-400 Instruction List A5E00267845-02 Demask synchronous faults CPU 412 114 System Functions Execution Time in ms SFC No. SFC Name 41 DIS_AIRT 1) Function CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU 414-4H redundant CPU 417-4H solo CPU 417-4H redundant Delay interrupt events the first time delay is activated1) 215 129 86 77 140 140 83 83 if the delay is already activated 18 10 8 6 10 10 6 6 When activating the delay for the first time, the SFC 41 runtime depends on the priority class in which the SFC 41 is called. The specified runtime refers to the call in OB 1. It decreases while the priority class number increases. S7-400 Instruction List A5E00267845-02 115 System Functions Execution Time in ms SFC No. 42 SFC Name EN_AIRT CPU 412 CPU 414 CPU 416 CPU 417 CPU CPU CPU CPU 414-4H 414-4H 417-4H 417-4H solo redunsolo redundant dant if other delays are present 18 11 7 6 11 11 6 6 Stop delaying interrupt eventswhen canceling the last delay 1) 437 272 193 171 272 272 172 172 Function 43 RE_TRIGR Retrigger watchdog monitoring 221 123 82 75 114 339 70 204 44 REPL_VAL Transfer substitute value to ACCU1 22 13 9 7 13 13 8 8 46 STP Force CPU into STOP mode cannot be measured -- -- -- -- -- -- -- -- 47 WAIT Delay program execution in addition to waiting time 15 8 7 5 6-9 6-9 3-5 3-5 48 SNC_RTCB Synchronize slave clocks 19 12 8 7 12 45 7 32 49 LGC_GADR Find slot with logical address 40 25 17 14 25 25 14 14 50 RD_LGADR Find all logical addresses of a block (run-time entry for 1 DI 32 in the central rack) 103 61 41 34 62 62 35 35 1) When cancelling the last delay, the SFC 42 runtime depends on the priority class in which the SFC 42 is called. The specified runtime refers to the call in OB 1. It decreases while the priority class number increases. S7-400 Instruction List A5E00267845-02 116 System Functions Execution Time in ms SFC No. 51 SFC Name RDSYSST Function "Module identification" partial list CPU 412 CPU 414 CPU 416 CPU 417 CPU CPU CPU CPU 414-4H 414-4H 417-4H 417-4H solo redunsolo redundant dant 125 79 51 46 71 71 47 47 256 154 102 89 150 150 96 96 Display one data record (0112) 156 94 62 55 86 86 56 56 Display header information (0F12) 111 66 43 39 57 57 40 40 "Save" partial list Display header information (0F13) 135 90 59 53 81 81 54 54 Display one data record (0111) 51 RDSYSST "Module Identification" partial list Display all data records (0012) 51 RDSYSST S7-400 Instruction List A5E00267845-02 117 System Functions Execution Time in ms SFC No. 51 SFC Name RDSYSST Function CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU 414-4H 417-4H redunsolo dant CPU 417-4H redundant "System Areas" partial list Display all data records (0014) 146 91 60 52 83 83 53 53 Display header information (0F14) 100 66 43 38 56 56 38 38 51 RDSYSST "Block Types" partial list Display all data records (0015) 145 86 57 51 77 77 51 52 51 RDSYSST "Status of Module LEDs" partial list Display status of all LEDs (0019) 264 157 121 108 163 -- 113 -- Display header information (0F19) 182 113 80 69 126 -- 72 -- "Component Identification" partial list 199 118 77 70 124 275 74 164 Display one of the components (011C) 136 84 56 49 91 241 53 136 Display all components of a H-system CPU (021C) - - - - 126 276 76 154 Display a component of all redundant CPUs of the H-system (031C) - - - - 92 257 54 142 Display header information (0F1C) 99 69 45 40 75 99 44 99 "Interrupt status" partial list 171 103 68 60 95 95 63 63 51 RDSYSST Display all components (001C) 51 RDSYSST Display one data record (0222) S7-400 Instruction List A5E00267845-02 118 System Functions Execution Time in ms SFC No. 51 SFC Name RDSYSST Function "TPA /CPU assignment" partial list CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU 414-4H 417-4H redunsolo dant CPU 417-4H redundant 344 209 128 120 207 207 118 118 Assignment between a process image partition and the corresponding OB (0125) 121 78 51 45 81 81 42 42 Assignment between an OB and corresponding process image partitions (0225) 228 173 106 95 - - - - Auslesen der Kopfinfo (0F25) 118 70 46 41 - - - - "Status information communication" partial list 165 291 97 174 64 116 57 102 108 184 133 543 63 107 88 323 166 100 66 59 152 299 97 186 - - - - - 122 - 77 - - - - - 64 - 15 Assignment between all process image partitions and OBs (0025) 51 RDSYSST 51 RDSYSST Display status information of a communication unit (0132) 51 RDSYSST "Status information communication" partial list Display status information of a communication unit (0232) 51 RDSYSST "H-CPU group information" partial list Current status of the H system (0071) Header information (0F71) S7-400 Instruction List A5E00267845-02 119 System Functions Execution Time in ms SFC No. SFC Name 51 RDSYSST 51 RDSYSST Function "Modules LEDs" partial list CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU 414-4H 417-4H redunsolo dant CPU 417-4H redundant 182 124 88 77 139 165 80 160 - - - - - 131 - 76 Status of an LED (0174) "Switched DP slaves in the H system" partial list Communication status between the H system and a switched DP slave (0C75) S7-400 Instruction List A5E00267845-02 120 System Functions Execution Time in ms SFC No. 51 51 SFC Name RDSYSST RDSYSST Function "DP master system information" partial list All known DP master systems of the CPU (0090) A DP master system (0190) Header information (0F90) "Module status information" partial list Display status information of all inserted modules (n=number of DR) (0091) Display status information of all modules /racks with incorrect type indentification (0191) All faulty modules (0291) All unavailable modules (0391) All submodules of the host module (0591) S7-400 Instruction List A5E00267845-02 CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU 414-4H 417-4H redunsolo dant CPU 417-4H redundant 258 158 105 92 209 209 127 127 134 112 561 + n * 22 80 67 329 + n * 19 53 44 218 + n * 16 47 39 180 + n * 14 72 59 -- 72 59 -- 48 40 -- 49 40 -- 546 + n * 70 381 + 230 + n * 40 220 + n * 35 213 + n * 18 216 + n * 35 59 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 515 + n * 99 517 + n * 69 169 n * 60 371 + n * 22 376 + n * 60 102 246 + n * 18 249 + n * 40 67 121 System Functions Execution Time in ms SFC No. 51 CPU 412 CPU 414 Display the status information of all submodules of the host module in the specified rack (0991) 299 + n * 12 179 + n*7 118 + n*5 Central 182 118 236 SFC Name RDSYSST Function CPU 416 CPU 417 CPU 414-4H solo CPU CPU 414-4H 417-4H redunsolo dant CPU 417-4H redundant 103 + n*4 -- -- -- -- 78 69 121 182 70 125 150 99 87 154 232 89 145 116 95 63 55 202 250 133 150 -- -- -- -- 122 122 85 85 a module with logical basic address (0C91) Distributed a module with logical basic address (0C91) 51 RDSYSST "Module status information" partial list of a module (distributed) with logical basic address (4C91) First call "Module status information" partial list of a module (distributed) with logical basis address (4C91) Intermediate call S7-400 Instruction List A5E00267845-02 122 System Functions Execution Time in ms SFC No. SFC Name Function "Module status information" partial list CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU 414-4H 417-4H redunsolo dant CPU 417-4H redundant -- -- -- -- 138 138 92 92 303 + n* 23 178 + n* 16 118 + n* 10 88 + n*8 178 + n * 18 291 + n * 20 101 + n * 10 178 + n * 12 235 274 138 161 91 107 80 94 141 - 168 276 293 81 95 169 183 all assigned modules (0E91) 854 505 335 289 -- -- -- -- "Rack/station status information" partial list 128 87 57 51 89 114 52 78 694 387 257 219 389 421 222 247 of a module (distributed) with logical basic address (4C91) Last call 51 RDSYSST Central all modules in the specified rack (n=number DR) (0D91) Distributed all modules in the specified DP station (0D91) 51 RDSYSST central Display setpoint status of rack 0 (0092) distributed Display setpoint status of DP system 1 (0092) S7-400 Instruction List A5E00267845-02 123 System Functions Execution Time in ms SFC No. SFC Name Function CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU 414-4H 417-4H redunsolo dant CPU 417-4H redundant 51 RDSYSST Display setpoint value of DP system1 (via external DP interface) (4092) 248 146 96 86 158 222 92 140 51 RDSYSST Display activation status of DP master system 1 (via integrated DP interface) (0192) 676 398 264 226 442 464 238 247 51 RDSYSST central 129 87 57 51 89 115 53 61 677 417 277 239 398 431 242 254 Display the actual status of rack 0 (0292) distributed Display the actual status of DP system 1 (0292) 51 RDSYSST Display the actual status of the stations of a DP master system (via external DP interface) (4292) 250 147 97 86 159 231 93 141 51 RDSYSST Display the status of rack 0 battery buffer if at least one battery has failed (0392) 144 87 57 51 89 113 52 77 51 RDSYSST Display the status of the entire battery buffer of a CPU (0492) 129 87 57 51 89 114 52 78 S7-400 Instruction List A5E00267845-02 124 System Functions Execution Time in ms SFC No. SFC Name Function CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU 414-4H 417-4H redunsolo dant CPU 417-4H redundant 51 RDSYSST Display the status of the 24 V supply of all racks of a CPU (0592) 144 87 57 51 89 114 52 78 51 RDSYSST Central 280 168 111 96 170 195 96 121 811 487 323 273 497 531 288 314 Diagnostic status of the stations of a DP master system connected via an external DP interface (4692) First call 252 148 97 87 160 224 94 142 Intermediate call 140 84 55 49 91 91 53 53 Last call 157 94 62 55 101 101 59 59 "Advanced DP master system information" partial list 156 93 61 55 87 87 56 56 114 69 45 40 60 60 41 41 Display the diagnostic status of the expansion devices (0692) 51 RDSYSST Distributed Display the diagnostic status of the DP system 1 stations (via integrated DP interface) (0692) 51 51 RDSYSST RDSYSST Display advanced information via a DP master system (0195) Display header information (0F95) S7-400 Instruction List A5E00267845-02 125 System Functions Execution Time in ms SFC No. 51 SFC Name RDSYSST Function "Diagnostic buffer" partial list RDSYSST CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU 414-4H 417-4H redunsolo dant CPU 417-4H redundant 135 314 86 188 60 125 45 111 86 188 86 188 51 112 51 112 Display the latest entries (n = 1-23) (01A0) 135 + n* 7,8 86 + n* 4,4 57 + n* 3 50 + n* 3 86 + n* 4,4 86 + n* 4,4 51 + n* 3 51 + n* 3 Display the header information (0FA0) 115 75 49 43 75 75 45 45 "Diagnostic data DS 0" partial list 342 212 148 133 232 282 138 146 313 184 123 109 194 278 113 151 172 103 68 60 105 105 63 63 195 116 77 68 120 120 73 73 Display all deliverable event information in the current operating mode (max. 21) (00A0) 51 CPU 412 Display via logical basic address (00B1) Central 51 RDSYSST Distributed (00B1) first call Distributed (00B1) intermediate call, REQ = 0 Distributed (00B1) last call S7-400 Instruction List A5E00267845-02 126 System Functions Execution Time in ms SFC No. 51 SFC Name RDSYSST Function "Diagnostic data DR 1" partial list CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU 414-4H 417-4H redunsolo dant CPU 417-4H redundant 247 147 100 89 158 184 98 135 383 245 178 162 257 307 172 203 distributed first call (00B3) 312 183 122 108 185 231 112 151 distributed intermediate call (00B3) 173 102 68 59 104 104 61 61 distributed last call (00B3) 214 127 84 74 131 131 76 76 Display via physical address (00B2) Display a 16-byte long DR 1 51 RDSYSST "Diagnostic data DR 1" partial list Display via logical basic address (00B3) Display a 16-byte long DR 1 central DR = Data record S7-400 Instruction List A5E00267845-02 127 System Functions Execution Time in ms SFC No. 51 52 SFC Name RDSYSST WR_USMSG 54 RD_DPARAM 55 WR_PARM S7-400 Instruction List A5E00267845-02 CPU 412 CPU 414 CPU 416 CPU 417 CPU CPU CPU CPU 414-4H 414-4H 417-4H 417-4H solo redunsolo redundant dant "Diagnostic Data DP Slave" partial list Display via configured diagnostic address (00B4) First call 311 182 122 108 197 233 115 147 Intermediate call, REQ = 0 (00B4) 174 101 67 59 109 109 64 64 Last call (6 - 240 bytes) (00B4) 263 157 106 94 160 160 96 96 Write user entry in diagnostic buffer write with message 151 93 66 54 76 101 33 59 without message 87 53 36 30 56 91 32 58 Read dynamic parameters local AI 8*13 bits 154 85 57 50 94 127 55 74 distributed AI 8*12 bits (DS1 = 14 bytes) 167 101 68 59 107 107 62 62 Write dynamic parameters local AI 8*13 bits 359 228 164 146 243 309 156 194 distributed First call AI 8*12 bits (14 - 240 bytes) 308 182 123 107 195 242 114 145 distributed Intermediate/last call, REQ = 0 138 82 55 48 89 89 51 51 Function 128 System Functions Execution Time in ms SFC No. 56 57 SFC Name WR_DPARM PARM_MOD S7-400 Instruction List A5E00267845-02 CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU CPU 414-4H 417-4H 417-4H redunsolo redundant dant Write predefined dynamic parameters AI 8*13 bits local 404 272 203 184 280 348 196 232 distributed First call AI 8*12 bits (2 - 240 bytes) 248 146 98 85 158 204 93 124 Intermediate/last call 121 72 48 41 79 79 46 46 Assign module parameters local Module/DS number/DS lengths in bytes AI 8*13 bits 695 459 349 318 480 582 332 390 distributed AO 8*12 bits First call (16 - 240 bytes) 245 144 97 84 156 204 92 123 distributed Intermediate/last call 118 70 47 41 77 77 46 46 Function 129 System Functions Execution Time in ms SFC No. 58 SFC Name WR_REC S7-400 Instruction List A5E00267845-02 CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU CPU 414-4H 417-4H 417-4H redunsolo redundant dant Write parameter data record local (n = number of bytes) 279 + n*3 170 + n* 2,5 120 + n* 2,3 107 + n* 2,2 183 + n * 2,6 246 + n * 2,6 109 + n * 2,2 120 + n * 2,2 First call, integrated DP interface module (n = number of bytes) 283 + n* 0,1 168 + n* 0,04 113 + 97 + n* n* 0,03 0,03 180 + n* 0,06 226 + n* 0,06 104 + n* 0,06 136 + n* 0,06 Intermediate call, REQ = 0 integrated DP interface module 112 66 45 38 74 74 42 42 Last call, integrated DP interface module 114 67 45 38 75 75 43 43 First call, external DP interface module (n = number of bytes) 277 + n* 0,06 163 + n* 0,06 109 + n* 0,04 96 + n* 0,03 185 + n* 0,06 185 + n* 0,06 98 + n* 0,03 98 + n* 0,03 Intermediate call, REQ = 0 external DP interface module 113 67 45 40 71 71 42 42 Last call, external DP interface module 115 68 46 40 72 72 42 42 Function 130 System Functions Execution Time in ms SFC No. 59 60 CPU 412 CPU 414 CPU 416 CPU 414-4H solo CPU CPU CPU 414-4H 417-4H 417-4H redunsolo redundant dant Read data record local (n = number of bytes) 278 + n* 3,2 169 + n* 2,7 119 + 106 + n* n* 2,4 2,3 220 + n * 2,8 280 + n *2,9 116 + n * 2,3 132 + n * 2,4 First call, integrated DP interface module 264 Intermediate call, REQ = 0 integrated DP interface module 112 156 105 91 167 224 97 129 66 45 38 74 74 42 42 Last call, integrated DP interface module (n = number of bytes) 201 + n* 0,04 119 + 81 + n* n* 0,04 0,03 70 + n* 0,03 125 + n* 0,13 125 + n* 0,13 73 + n* 0,13 73 + n* 0,13 First call, external DP interface module 255 151 101 88 164 164 96 96 Intermediate call, REQ = 0 external DP interface module 113 67 45 40 74 74 45 45 Last call, external DP interface module (n = number of bytes) 196 + n* 0,06 116 + 78 + n* n* 0,06 0,03 68 + n* 0,03 121 + n * 0,1 121 + n * 0,1 71 + n* 0,05 71 + n* 0,05 Send GD packet 1 byte 207 124 83 72 -- -- -- -- 32 bytes 553 331 212 183 -- -- -- -- SFC Name RD_REC GD_SND S7-400 Instruction List A5E00267845-02 Function CPU 417 131 System Functions Execution Time in ms SFC No. SFC Name Function CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU CPU 414-4H 417-4H 417-4H redunsolo redundant dant 61 GD_RCV Receive GD package (1 - 32 Byte) 100 60 41 35 -- -- -- -- 62 CONTROL Check status of the connection belonging to a local communication-SFB-instance 104 63 44 35 74 112 40 69 64 TIME_TCK Display millisecond timer 19 11 8 6 11 45 7 27 65 X_SEND Transmit data to external partner First call, establish a connection (1 - 76 bytes) REQ = 1 641 458 412 355 -- -- -- -- First call, connection present (1-76 bytes) 509 293 195 168 -- -- -- -- Intermediate call (1-76 bytes) 150 87 58 49 -- -- -- -- Last call, BUSY = 0 254 150 100 87 -- -- -- -- Receive data from external partner Test reception (1-76 bytes) 89 49 33 28 -- -- -- -- Read data (1-76 bytes) 270 155 107 87 -- -- -- -- 66 X_RCV S7-400 Instruction List A5E00267845-02 132 System Functions Execution Time in ms SFC No. 67 68 CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU CPU 414-4H 417-4H 417-4H redunsolo redundant dant Read data from external partner First call, establish a connection (1-76 bytes) REQ = 1 572 416 384 332 -- -- -- -- First call, connection present (1-76 bytes) 444 252 167 144 -- -- -- -- Intermediate call (1-76 bytes) 153 89 60 50 -- -- -- -- Last call BUSY = 0 364 214 142 123 -- -- -- -- Write data to external partner First call, establish a connection (1-76 bytes) REQ = 1 651 462 415 357 -- -- -- -- First call, connection present (1-76 bytes) 519 297 198 170 -- -- -- -- Intermediate call (1-76 bytes) 155 89 60 51 -- -- -- -- Last call, BUSY = 0 259 151 101 87 -- -- -- -- SFC Name X_GET X_PUT S7-400 Instruction List A5E00267845-02 Function 133 System Functions Execution Time in ms SFC No. 69 72 73 CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU CPU 414-4H 417-4H 417-4H redunsolo redundant dant Abort connection to external partner First call, REQ = 1 239 139 88 78 -- -- -- -- Intermediate call 109 64 43 36 -- -- -- -- Last call, BUSY = 0 228 219 254 219 -- -- -- -- Read data from internal partner First call, establish a connection (1-76 bytes) REQ = 1 732 442 401 346 -- -- -- -- First call, connection present (1-76 bytes) 425 225 170 153 -- -- -- -- Intermediate call (1-76 bytes) 175 93 62 53 -- -- -- -- Last call, BUSY = 0 407 218 145 126 -- -- -- -- Write data to internal partner First call, establish a connection (1-76 bytes) REQ = 1 539 843 304 486 204 431 172 372 -- -- -- -- First call, connection present (1-76 bytes) 539 301 201 178 -- -- -- -- Intermediate call (1-76 bytes) 172 94 63 53 -- -- -- -- Last call, BUSY = 0 252 155 103 90 -- -- -- -- SFC Name X_ABORT I_GET I_PUT S7-400 Instruction List A5E00267845-02 Function 134 System Functions Execution Time in ms SFC No. 74 CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU CPU 414-4H 417-4H 417-4H redunsolo redundant dant Abort connection to internal partner First call, REQ = 1 192 131 88 82 -- -- -- -- Intermediate call 103 62 42 35 -- -- -- -- Last call, without / with connection BUSY = 0 226 62 / 217 48 / 253 37 / 217 -- -- -- -- SFC Name I_ABORT Function 79 SET 1) Set bit array in I/O area n = number of bits to set at 1 31 + n* 0,25 20 + n* 0,2 14 + n* 0,2 11 + n* 0,2 37 + n * 1,0 75 + n * 1,1 22 + n * 0,7 44 + n * 0,7 80 RSET 1) Delete bit array in I/O area n = number of bits to set at 0 31 + n* 0,25 19 + n* 0,2 14 + n* 0,2 11 + n* 0,2 38 + n * 1,0 76 + n * 1,1 23 + n * 0,7 44 + n * 0,7 81 UBLKMOV Copy variable without interruption n = number of bytes to copy 39 + n* 0,08 23 + n* 0,05 16 + n* 0,03 12 + n* 0,03 24 + n* 0,05 24 + n* 0,05 13 + n* 0,03 13 + n* 0,03 87 C_DIAG Determine current connection status MODE = 0 28 17 12 9 22 69 13 44 Mode = 1, 2, 3 129 136 167 146 185 567 206 664 90 H_CTRL Influence processes involving fault-tolerant systems -- -- -- -- 12 12 8 8 1) Measured with I/O modules of the type "Binary Simulator C79459-A1002-A1, Release 1" in the central rack S7-400 Instruction List A5E00267845-02 135 System Functions Execution Time in ms SFC No. 100 103 104 CPU 412 CPU 414 CPU 416 CPU 417 CPU CPU CPU CPU 414-4H 414-4H 417-4H 417-4H solo redunsolo redundant dant Set time-of-day and clock status MODE = 1 192 112 75 66 266 828 169 501 MODE = 2 109 62 41 36 166 431 102 264 MODE = 3 189 115 75 69 270 842 171 506 Detemine bus topology in a DP master system first call, REQ = 1 272 160 109 96 174 319 103 184 Intermediate call 46 27 19 16 28 28 17 17 Last call BUSY = 0 49 28 20 17 31 31 18 18 Controls the CiR procedure MODE = 0, information 19 11 8 6 15 - 9 - MODE = 1, Enable CiR procedure 19 11 8 6 15 - 9 - MODE = 2, Disable CiR procefure entirely 19 11 8 6 15 - 9 - MODE = 3, Disable CiR procedure partially 19 11 8 6 15 - 9 - SFC Name SET_CLKS DP_TOPOL CIR S7-400 Instruction List A5E00267845-02 Function 136 System Functions Execution Time in ms SFC No. 105 SFC Name READ_SI Function Read dynamically assigned system resources MODE = 0 MODE = 1 MODE = 2 MODE = 3 CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU 414-4H 417-4H redunsolo dant CPU 417-4H redundant 132 1185 80 988 53 1291 45 1168 81 1022 0) 81 1026 0) 47 1182 0) 47 1187 0) 0) 0) 0) 0) 161 1455 93 1185 62 1535 53 1392 110 1250 1) 284 1426 1) 47 1188 1) 187 1557 1) 1) 1) 1) 1) 161 1273 94 1026 63 1322 53 1201 111 1055 1) 285 1231 1) 65 1197 1) 188 1326 1) 1) 1) 1) 1) 163 1459 94 1179 63 1526 54 1390 112 1241 2) 275 1417 2) 64 1418 2) 187 1546 2) 2) 2) 2) 2) 0) Depending on the size of the SYS_INST target area and on the number of the system resources to be read 1) Depending on the number of active messages (assigned system resources) 2) Depending on the number of active messages (assigned system resources) and on the number of assigned instances with the desired CMP_ID. S7-400 Instruction List A5E00267845-02 137 System Functions Execution Time in ms SFC No. 106 CPU 412 CPU 414 CPU 416 CPU 417 CPU CPU CPU CPU 414-4H 414-4H 417-4H 417-4H solo redunsolo redundant dant 198 1016 111 821 75 1035 65 923 145 2442 1) 1) 1) 1) 1) 201 970 113 824 76 1035 67 925 1) 1) 1) 1) 198 1012 112 826 75 1043 65 927 2) 2) 2) 2) Acknowledgeable block-related messages create first call, SIG = 0 -> 1 285 170 120 101 221 326 110 191 Call (without message) 133 79 53 44 82 162 46 96 SFC Name DEL_SI Function Enable dynamically assigned system resources MODE = 1 MODE = 2 MODE = 3 107 ALARM_DQ 492 12556 85 2817 1) 1) 332 14262 1) 147 875 1) 496 1226 1) 86 930 1) 334 1179 1) 146 2466 2) 494 12571 86 2854 2) 334 14315 2) 2) 1) Depending on the number of active messages (assigned system resources) 2) Depending on the number of active messages (assigned system resources) and on the number of assigned instances with the desired CMP_ID. S7-400 Instruction List A5E00267845-02 138 System Functions Execution Time in ms SFC No. 108 SFC Name ALARM_D CPU 412 CPU 414 CPU 416 CPU 417 CPUs CPU CPU CPU 414-4H 414-4H 417-4H 417-4H solo redunsolo redundant dant Not acknowledgeable block-related messages create first call, SIG = 0 -> 1 273 163 108 91 223 336 106 187 Call (without message) 122 71 47 39 74 168 42 91 Function 126 SYNC_PI Update the process image partition of the inputs in a synchronous cycle 61 37 25 21 - - - - 127 SYNC_PO Update the process image partition of the outputs in a synchronous cycle 60 36 24 20 - - - - S7-400 Instruction List A5E00267845-02 139 System Function Blocks System Function Blocks The following table lists the system function blocks provided with the operating system of the S7-400 CPUs as well as the execution times of the individual CPUs (X: function exists, execution times were not available when manual was printed). Execution Time in ms SFC No. SFC Name Function CPU 412 CPU 414 CPU 416 CPU 417 CPU CPU CPU CPU 414-4H 414-4H 417-4H 417-4H solo redunsolo redundant dant 0 CTU Count up 4 3 1 1 4 4 1 1 1 CTD Count down 4 2 1 1 2 2 2 2 2 CTUD Count up and down 4 2 1 1 2 2 2 2 3 TP Generate pulse 26 15 10 8 16 49 9 28 4 TON Generate on-delay 25 15 10 8 16 48 10 29 5 TOF Generate off-delay 19 11 7 6 11 11 6 7 8 USEND Send data without coordination (one send parameter supplied) JOB activated (1 - 440 bytes) 426 448 245 260 164 174 139 153 256 282 375 408 147 165 216 233 JOB checked 147 86 57 49 88 122 50 73 JOB finished (DONE = 1) 147 84 56 48 85 125 48 72 S7-400 Instruction List A5E00267845-02 140 System Function Blocks Execution Time in ms SFC No. 9 12 13 CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU 414-4H 417-4H redunsolo dant CPU 417-4H redundant Receive data without coordination (one receive parameter supplied) JOB activated 136 77 50 44 79 119 45 72 JOB checked 133 78 50 43 79 109 45 68 JOB finished (NDR = 1; 1 - 440 bytes) 280 316 165 186 108 121 92 106 160 197 203 237 92 113 115 137 Send data block by block JOB activated (1 - 3000 bytes) 386 220 148 129 220 293 129 168 JOB checked 164 95 63 54 95 126 55 78 JOB finished (DONE = 1) 161 92 62 54 92 132 54 76 Receive data block by block JOB activated (1 - 3000 bytes) 187 108 71 62 112 153 65 88 JOB checked 186 109 71 61 111 142 65 87 JOB finished 163 94 61 53 94 131 53 76 SFC Name URCV BSEND BRCV S7-400 Instruction List A5E00267845-02 Function 141 System Function Blocks Execution Time in ms SFC No. 14 15 16 CPU 412 CPU 414 CPU 416 CPU 417 CPU CPU CPU CPU 414-4H 414-4H 417-4H 417-4H solo redunsolo redundant dant Read data from remote CPU (one area specified) JOB activated 335 186 129 113 192 269 113 157 JOB checked 149 86 57 49 88 121 51 74 JOB finished (NDR = 1; 1 - 450 bytes) 282 316 163 183 108 121 92 106 163 197 200 239 92 115 114 138 Write data to remote CPU JOB activated (1 - 404 bytes) 445 478 257 277 173 180 147 160 267 299 386 410 154 174 222 239 JOB checked 149 86 57 49 88 120 51 74 JOB finished (DONE = 1) 147 85 56 48 85 125 48 72 Send data to a printer JOB activated, REQ = 1 462 502 260 284 174 186 150 162 279 310 399 433 159 179 227 247 JOB checked 153 88 58 50 91 131 52 75 JOB finished, DONE = 1 152 86 57 49 87 127 50 73 SFC Name GET PUT PRINT S7-400 Instruction List A5E00267845-02 Function 142 System Function Blocks Execution Time in ms SFC No. 19 20 21 22 CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU 414-4H 417-4H redunsolo dant CPU 417-4H redundant Start remote device JOB activated, REQ = 1 443 251 164 147 261 330 148 191 JOB checked 155 90 60 52 92 122 53 76 JOB finished, DONE = 1 153 89 59 51 90 130 52 77 Stop remote device JOB activated, REQ = 1 411 242 157 136 244 319 143 187 JOB checked 156 90 59 51 92 132 53 76 JOB finished, DONE = 1 153 89 58 51 89 128 51 75 Restart remote device JOB activated, REQ = 1 434 246 159 142 249 330 148 193 JOB checked 157 90 59 52 92 124 53 76 JOB finished, DONE = 1 153 90 59 52 90 131 52 75 Query status of remote partner JOB activated, REQ = 1 279 160 109 97 164 233 97 135 JOB checked 153 88 58 50 91 123 53 75 JOB finished, NDR = 1 464 269 177 151 269 301 151 171 SFC Name START STOP RESUME STATUS S7-400 Instruction List A5E00267845-02 Function 143 System Function Blocks Execution Time in ms SFC No. 23 31 CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU 414-4H 417-4H redunsolo dant CPU 417-4H redundant Receive status of remote device without coordination JOB activated, NDR = 1 135 79 50 44 79 119 46 69 JOB checked 133 77 50 43 78 111 45 68 JOB finished 462 266 176 150 266 297 150 169 Generate block-related message without acknowledgment 543 588 309 331 207 220 178 191 315 349 470 506 181 202 273 293 JOB checked 206 118 78 67 118 155 67 89 SFC Name USTATUS NOTIFY_8P Function First call or JOB activated, SIG = 0-> 1 (1 - 420 bytes) JOB finished, DONE = 1 215 123 81 70 123 156 70 90 32 DRUM Implement sequencer 39 21 14 13 21 55 13 39 33 ALARM Generate block-related message with acknowledgment First call or JOB activated, SIG = 0-> 1 (1 - 420 bytes) 552 588 312 331 209 223 183 195 314 348 468 501 183 202 277 291 JOB checked 208 119 79 68 119 156 68 89 JOB finished, DONE = 1 215 123 81 70 123 156 70 89 S7-400 Instruction List A5E00267845-02 144 System Function Blocks Execution Time in ms SFC No. 34 35 36 CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU 414-4H 417-4H redunsolo dant CPU 417-4H redundant Generate block-related message without accompanying values for 8 signals First call or JOB activated, SIG = 0-> 1 (1 - 420 bytes) 433 246 165 144 246 359 144 208 JOB checked 206 118 78 68 118 152 68 89 JOB finished, DONE = 1 213 121 80 70 121 157 70 89 Generate block-related message with accompanying values for 8 signals First call or JOB activated, SIG = 0-> 1 (1 - 420 bytes) 549 582 306 326 209 222 182 190 316 347 468 502 182 202 270 292 JOB checked 205 118 78 68 118 156 68 89 JOB finished, DONE = 1 213 122 81 70 122 156 70 90 Generate block-related message without acknowledgment First call or JOB activated, SIG = 0-> 1 (1 - 420 bytes) 547 586 305 329 203 216 181 189 313 345 469 503 181 200 276 289 JOB checked 204 117 78 67 117 155 67 88 JOB finished, DONE = 1 213 121 81 70 121 157 70 90 SFC Name ALARM_8 ALARM_8P NOTIFY S7-400 Instruction List A5E00267845-02 Function 145 System Function Blocks Execution Time in ms SFC No. 37 52 52 CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU 414-4H 417-4H redunsolo dant CPU 417-4H redundant Send archive data First call or JOB activated, REQ = 1 (1 - 3000 bytes) 372 215 145 127 229 302 132 183 JOB checked 160 92 62 54 102 140 57 81 JOB finished, DONE = 1 160 91 61 54 102 140 57 81 Read data record from a DP slave via integrated DP interface, First call (2-16 bytes) 289 167 111 97 178 224 106 131 Intermediate call 128 74 49 43 80 80 47 47 Last call 221 127 86 76 131 131 78 78 Read data record from a DP slave via external DP interface, First call (4-16 bytes) 291 167 108 94 179 223 105 132 Intermediate call 128 74 49 43 80 80 46 46 Last call 218 123 82 71 131 131 78 78 SFC Name AR_SEND RDREC RDREC S7-400 Instruction List A5E00267845-02 Function 146 System Function Blocks Execution Time in ms SFC No. 53 53 CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU 414-4H 417-4H redunsolo dant CPU 417-4H redundant Write data record in a DP slalve via integrated DP interface, First call (1-10 bytes) 314 182 119 105 190 235 111 136 Intermediate call 130 76 50 43 81 81 47 47 Last call 132 77 51 45 83 83 48 48 Write data record in a DP slave via external DP interface, First call (2-14 bytes) 312 176 116 101 194 225 111 136 Intermediate call 130 76 50 43 80 80 47 47 SFC Name WRREC WRREC Function Last call 134 77 51 45 82 82 48 48 54 RALRM Receive interrupt from a DP slave Runtime measurement for non-I/O-dependent OBs, MODE = 1, OB 1 118 73 48 42 76 76 44 44 54 RALRM Receive interrupt from a DP slave Runtime measurement at integrated DP interface, MODE = 1, OB 40, OB 83, OB 86 242 141 92 81 230 230 123 123 OB 55 to OB 57, OB 82 245 145 95 83 238 238 128 128 OB 70 -- -- -- -- 228 228 121 121 S7-400 Instruction List A5E00267845-02 147 System Function Blocks Execution Time in ms SFC No. 54 54 CPU 412 CPU 414 CPU 416 CPU 417 CPU 414-4H solo CPU CPU 414-4H 417-4H redunsolo dant CPU 417-4H redundant Receive interrupt from a DP slave Runtime measurement at external DP interface, MODE = 1, OB 40, OB 83, OB 86 404 239 156 137 359 359 208 208 OB 55 to OB 57, OB 82 675 431 281 246 647 647 368 368 OB 70 -- -- -- -- 412 412 211 211 Receive interrupt from a DP slave Runtime measurement at central I/O, MODE = 1, OB 40, OB 82, OB 83, OB 86 195 117 77 67 123 123 71 71 OB 55 to OB 57 583 435 283 248 522 522 298 298 SFC Name RALRM RALRM S7-400 Instruction List A5E00267845-02 Function 148 Sublist of the System Status List (SSL) Sublist of the System Status List (SSL) SSL-ID Information Functions Module Identification 0111 One ident. data record only CPU Characteristics 0012 CPU features, all features 0112 Features of a group 0F12 Only SSL partial list header information User Memory Area 0F12 Only partial list header information User Memory Area 0113 Data record for specified memory area Work memory S7-400 Instruction List A5E00267845-02 149 Sublist of the System Status List (SSL) Sublist of the System Status List (SSL), continued SSL-ID Information Functions System Areas 0014 System areas, all system areas 0F14 Only partial list header information Block Types 0015 Block types, data records for all block types Status Module LEDs 0019 Status of all module LEDs 0F19 Only partial list header information Component Identification 001C Identification of all components 011C Identification of one component 021C Identification of all components of an H-system CPU 031C Identification of a component of all redundant CPUs of an H-system 0F1C Only SSL partial list header information Interrupt Status 0222 Data record for specified interrupt S7-400 Instruction List A5E00267845-02 150 Sublist of the System Status List (SSL) Sublist of the System Status List (SSL), continued SSL-ID Information Functions Assignment between process image partitions and OBs 0025 Assignment betweeen all process image partitions and OBs within the CPU 0125 Assignment between a process image partition and the corresponding OB 0225 Assignment between an OB and the corresponding process image partitions 0F25 Only SSL partial list header information Communication Status Data 0132 Status data for a communication unit 0232 Status data for a communication unit H CPU Group Information 0071 Information on the current status of the H system 0F71 Only partial list header information Status of the Module LEDs 0174 Status of one LED Switched DP Slaves in the H System 0C75 Communication status between the H system and a switched DP slave S7-400 Instruction List A5E00267845-02 151 Sublist of the System Status List (SSL) Sublist of the System Status List (SSL), continued SSL-ID Information Functions DP Master System Information 0090 Information about all the DP master systems known to the CPU 0190 Information about a DP master system 0F90 Only SSL partial list header information Module Status Information (A maximum of 27 data records are supplied) 0091 Module status information of all inserted modules/submodules 0191 Status information of all modules/racks with incorrect type IDs. 0291 Module status information of all faulty modules 0391 Module status information of all unavailable modules 0591 Module status information of all submodules of the host module 0991 Status information of all submodules in the host module in the rack 0C91 Status information of a module in the central rack or connected to an integrated DP interface module via the logical base address 4C91 Status information of a module connected to an external DP interface module via the logical base address 0D91 Status information of all modules in the specified rack 0E91 Status information of all assigned modules S7-400 Instruction List A5E00267845-02 152 Sublist of the System Status List (SSL) Sublist of the System Status List (SSL), continued SSL-ID Information Functions Rack/Station Status Information 0092 Expected status of the central racks/stations of a DP master system 4092 Expected status of the stations of a DP master system which is connected via an external DP interface module 0192 Activation status of the stations of a DP master system which is connected via an external DP interface module 0292 Actual status of the central racks/stations of a DP master system 4292 Actual status of the stations of a DP master system which is connected via an external DP interface module 0392 Status of the back-up battery of a CPU rack if at least one battery fails 0492 Status of the entire back-up batteries of all racks of the a CPU 0592 Actual status of the racks in the central configuration/stations of DP master system which is connected via an external DP interface module. 0692 OK status of the expansion units in the central configuration/stations of a DP master system which is connected via an integrated DP interface module. 4692 OK status of the stations of a DP master system which is connected via an external DP interface module. Addtional DP Master System Information 0195 Additional information on a DP master system 0F95 Only partial list header information S7-400 Instruction List A5E00267845-02 153 Sublist of the System Status List (SSL) Sublist of the System Status List (SSL), continued SSL-ID Information Functions Diagnostic Buffer (A maximum of 21 data records are supplied) 00A0 All current diagnostic entries available in current operating mode 01A0 Last x entries. X is listed in index 0FA0 Only partial list header information Module Diagnostic Data 00B1 First four diagnostic bytes of a module (DS0) 00B2 All diagnostic data of a module (v 220 bytes, DS1) (no DP module) 00B3 All diagnostic data of a module (v 220 bytes, DS1) 00B4 Diagnostic data of a DP slave with logical base address S7-400 Instruction List A5E00267845-02 154 Alphabetical Index of Instructions Alphabetical Index of Instructions Instruction Page Instruction Page ) )MCR + +AR1 +AR2 +D +I +R -D -I -R *D *I *R /D /I /R = ==D ==I ==R 29 97 70 71 71 63 61 65 63 61 65 63 62 65 64 62 65 40 73 72 74 <=D <=I <=R <D <I <R <>D <>I >=D >=I >=R >D >I >R ABS ACOS ASIN ATAN CAD CAR 73 72 74 73 72 74 73 72 73 72 74 73 72 74 66 69 69 69 79 58 S7-400 Instruction List A5E00267845-02 155 Alphabetical Index of Instructions Instruction Page Instruction Page CDB CU CD BE BEC BEU BLD BTD BTI CALL CC CLR COS DEC DTB DTR ENT EXP FN FP FR INC INVD INVI 90 45 46 89 89 89 81 82 82 86 87 41 69 80 83 82 79 68 38 38 44 46 80 85 85 ITB ITD JBI JBIN JCN JC JCB JNB JL JM JMZ JN JO JP JPZ JOS JU L 83 82 92 92 91 91 92 92 96 94 95 94 93 94 95 93 91 47 48 49 50 51 52 53 59 60 57 57 53 S7-400 Instruction List A5E00267845-02 LAR1 LAR2 LC 156 Alphabetical Index of Instructions Instruction Page Instruction Page LEAVE LN LOOP MCR( MCRA MCRD MOD NEGD NEGI NEGR NOP NOT O O( OD ON ON( OPN OW POP PUSH R RLD RLDA 79 68 96 97 98 98 64 85 85 66 81 41 26 30 32 35 36 37 28 34 26 32 35 36 37 28 88 33 79 79 39 44 45 77 78 RND RND+ RND- RRD RRDA SAVE SF SE SET SI SIN SLD SLW SQR SQRT SRD SRW S SS SSD SSI T 84 84 84 77 78 41 43 42 41 42 69 75 75 67 67 76 75 39 45 43 76 76 54 55 56 59 S7-400 Instruction List A5E00267845-02 157 Alphabetical Index of Instructions Instruction Page Instruction Page TAK TAN TAR1 TAR2 TRUNC U U( UC UN 79 69 58 58 84 25 31 35 36 37 28 87 25 31 35 36 37 UN( AW X X( XN XN( XOD XOW AD 28 33 27 32 35 36 37 28 27 32 35 36 37 28 34 33 34 S7-400 Instruction List A5E00267845-02 158