2KBP01G - Fuji Electric - Datasheet.Live

Februa ry 198 4

Revised October 2003

MM74HC4046 CMOS Phase Lock Loop

MM74HC4046

CMOS Phase Lock Loop

General Description

The MM74HC4046 is a low power phase lo ck loop utilizing

advanced silicon-gate CMOS technology to obtain high fre-

quency ope ration both in the phase comparator and VCO

sections. This device contains a low power linear voltage

controlled oscillator (VCO), a source follower, and three

phase comparators. The three phase comparators have a

common signal input and a common comparator input. The

signal input has a self bi asing amplifie r allowing signals to

be either capacitively coupled to the phase comparators

with a small signal or directly coupled with standard input

logic levels. This device is similar to the CD4046 except

that the Zener diode of the metal gate CMOS device has

been replaced with a third phase comparator.

Phase Comparator I is an exclusive OR (XOR) gate. It pro-

vides a digital err or signal that maintains a 90 phase shift

between the VCO’s center frequency and the input signal

(50% duty cycle input waveforms). This phase detector is

more susceptible to locking onto harmonics of the input fre-

quency than ph ase comp arator I, but provide s bet ter noise

rejection.

Phase com par ato r III is an S R fl ip -flop gate. It can b e us ed

to provid e t he p ha se co mp arator fun cti on s an d is similar to

the first comparator in performance.

Phase com parator II is an edge se nsitive digital seque ntial

network. Two signal outputs are provided, a comparator

output and a phase pulse output. The comparator output is

a 3-ST ATE output that provides a signal that locks the VCO

output sign al to th e i n pu t sign al w ith 0 ph ase sh if t b etwe en

them. This comparator is more suscep tible to noise throw-

ing the loop out of lock, but is less likely to lock onto har-

monics than the other two comparators.

In a typical application any one of the three comparators

feed an extern al fi lt er network whic h in tur n f eeds the VCO

input. This input is a very high impedance CMOS input

which also drives the source follower. The VCO’s operating

frequency is set by three external components connected

to the C1A, C1B, R1 and R2 pins. An inhibit pin is provided

to disable the VCO and the source follower, providing a

method of putt ing the IC in a low power state.

The source follower is a MOS transistor whose gate is con-

nected to the VCO input and whose drain connects the

Demod ulator output. This output normally i s used by tying

a resi stor from pin 10 to grou nd, and provides a means of

looking at the VCO input without loading down modifying

the characteristics of the PLL filter.

Features

■Low dynamic pow er c onsu mp tion : (VCC = 4.5V)

■Maximu m VCO ope ra ting fre que ncy:

12 MHz (VCC = 4.5V)

■Fast comparator response time (VCC = 4.5V)

Compa rat or I: 25 ns

Compa rat or II: 30 ns

Comparat or III: 25 ns

■VCO has high linearity and high temperature stability

Ordering Code:

Devices also available in Tape and R eel. Speci fy by appending the s uffix let t er “X” to the ordering code.

Order Num ber Package Number Package Description

MM74HC4046M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

MM74HC4046SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

MM74HC4046MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

MM74HC4046N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

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MM74HC4046

Connection Diagram

Pin Assignments for DIP, SOIC, SOP and TSSOP

Block Diagram

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MM74HC4046

Absolute Maximum Ratings(Note 1)

(Note 2) Recommended Operating

Conditions

Note 1: Maximu m Ratings are those v alues beyo nd which damage to t he

device may occur.

Note 2: Unless otherwise specified all voltages are referenced to ground.

Note 3: Power Dis sipation te mperature d erating — plas tic “N” package: −

12 mW/°C from 65°C to 85°C.

DC Electrical Characteristics (Note 4)

Note 4: For a power supply of 5V ±10% the worst case output voltages (VOH, and VOL) occ ur for HC at 4.5V. Thus the 4. 5V valu es shou ld be u sed when

designi ng with t his s upply. Wors t c as e VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-

rent (IIN, ICC, and IOZ) occu r fo r C M OS at the h igher vol ta ge and so the 6. 0V values s hould be used.

Supply Voltage (VCC)−0.5 to + 7.0V

DC Input Voltage (VIN)−1.5 to VCC +1.5V

DC Output Voltage (VOUT)−0.5 to VCC + 0.5V

Clamp Diode Current (IIK, IOK)±20 mA

DC Output Current per pin (IOUT)±25 mA

DC VCC or GND Current, per pin (ICC)±50 mA

Stora ge Temper atu re R ang e (TSTG)−65°C +150°C

Power Di ssipa ti on (PD)

(Note 3) 600 mW

S.O. Package only 500 mW

Lead Temperature (TL)

(Soldering 10 seco nds) 260°C

Min Max Units

Supply Voltage (VCC)26V

DC Input or Output Voltage

(VIN, VOUT)0V

CC V

Operati ng Temper atu re Range (TA)−40 +85 °C

Input Rise or Fall Times

(tr, tf) VCC = 2.0V 1000 ns

VCC = 4.5V 500 ns

VCC = 6.0V 400 ns

Symbol Parameter Conditions VCC TA = 25°CT

A = −40 to 85°CT

A = −55 to 125°CUnits

Typ Guaranteed Limits

VIH Minimum HIGH Level 2.0V 1.5 1.5 1.5 V

Input Voltage 4.5V 3.15 3.15 3.15 V

6.0V 4.2 4.2 4.2 V

VIL Maximum LOW Level 2.0V 0.5 0.5 0.5 V

Input Voltage 4.5V 1.35 1.35 1.35 V

6.0V 1.8 1.8 1.8 V

VOH Minimum HIGH Level VIN = VIH or VIL

Output Voltage |IOUT| ≤ 20 µA 2.0V 2.0 1.9 1.9 1.9 V

4.5V 4.5 4.4 4.4 4.4 V

6.0V 6.0 5.9 5.9 5.9 V

VIN = VIH or VIL

|IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 3.7 V

|IOUT| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 5.2 V

VOL Maximum Low Level VIN = VIHor VIL

Output Voltage |IOUT| ≤ 20 µA 2.0V 0 0.1 0.1 0.1 V

4.5V 0 0.1 0.1 0.1 V

6.0V 0 0.1 0.1 0.1 V

VIN = VIH or VIL

|IOUT| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 0.4 V

|IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 0.4 V

IIN Maximum Input Current (Pins 3,5,9) VIN = VCCor GND 6.0V ±0.1 ±1.0 ±1.0 µA

IIN Maximum Input Current (Pin 14) VIN = VCC or GND 6.0V 20 50 80 100 µA

IOZ Maxim um 3-STATE Output VOUT = VCC or GND 6.0V ±0.5 ±5.0 ±10 µA

Leakage Current (Pin 13)

ICC Maximum Quiescent VIN = VCC or GND 6.0V 30 80 130 160 µA

Supply Current IOUT = 0 µA

VIN = VCC or GND 6.0V 600 1500 2400 3000 µA

Pin 14 Open

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MM74HC4046

AC Electrical Characteristics VCC = 2.0 to 6.0V, CL = 50 pF, tr = tr = 6 ns (u nless otherwise specified.)

Symbol Parameters Conditions VCC TA=25C TA = −40 to 85°CT

A = −55 to 125°CUnits

Typ Guar ant eed Lim its

AC Coupled C (series) = 100 pF 2.0V 25 100 150 200 mV

Input Sensitivity, fIN = 500 kHz 4.5V 50 150 200 250 mV

Signal In 6.0V 135 250 300 350 mV

tr, tfMaximum Output 2.0V 30 75 95 110 ns

Rise and Fall Time 4.5V 9 15 19 22 ns

6.0V 8 12 15 19 ns

CIN Maximum Input Capacitance 7 pF

Phase Comparator I

tPHL, tPLH Maximum 2.0V 65 200 250 300 ns

Propagation Delay 4.5V 25 40 50 60 ns

6.0V 20 34 43 51 ns

Phase Comparator II

tPZL Maximum 3-STATE 2.0V 75 225 280 340 ns

Enable Time 4.5V 25 45 56 68 ns

6.0V 22 38 48 57 ns

tPZH, tPHZ Maximum 3-STATE 2.0V 88 240 300 360 ns

Enable Time 4.5V 30 48 60 72 ns

6.0V 25 41 51 61 ns

tPLZ Maximum 3-STATE 2.0V 90 240 300 360 ns

Disable Time 4.5V 32 48 60 72 ns

6.0V 28 41 51 61 ns

tPHL, tPLH Maximum 2.0V 100 250 310 380 ns

Propagation Delay 4.5V 34 50 63 75 ns

HIGH-to-LOW to Phase Pulses 6.0V 27 43 53 64 ns

Phase Comparator III

tPHL, tPLH Maximum 2.0V 75 200 250 300 ns

Propagation Delay 4.5V 25 40 50 60 ns

6.0V 22 34 43 51 ns

CPD Maximum Power All Comparators 130 pF

Dissipation Capacitance VIN = VCC and GND

Voltage Controlled Oscillator (Specified to operate from VCC= 3.0V to 6.0V)

fMAX Maximum C1 = 50 pF

Operating R1 = 100Ω4.5V 7 4.5 MHz

Frequency R2 = ∞6.0V 11 7 MHz

VCOin = VCC

C1 = 0 pF 4.5V 12 MHz

R1 = 100Ω6.0 14 MHz

VCOin = VCC

Duty Cycle 50 %

Demodulator Output

Offset Voltage Rs = 20 kΩ4.5V 0.75 1.3 1.5 1.6 V

VCOin–Vdem

Offset Rs = 20 kΩ4.5V

Variation VCOin = 1.75V 0.65 V

2.25V 0.1

2.75V 0.75

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MM74HC4046

Typical Performance Characteristics

Ty pi cal C en ter Fr eq uen cy

vs R1, C1 VCC = 4.5V Typical Center Frequency

vs R1, C1 VCC = 6V

Typica l Offset Frequency

vs R2, C1 VCC = 4.5V Typical Offset Frequency

vs R2, C1 VCC = 6V

Typical VCO Power Dissipation

@ Center Frequency vs R1 Typical VCO Power

Dissipation @ fMIN vs R2

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MM74HC4046

Typical Performance Characteristics (Continued)

VCOin vs fout VCC = 4.5V VCOin vs fout VCC = 4.5V

VCOout vs

Temperature VCC = 4.5V VCOout vs

Temperature VCC = 6V

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MM74HC4046

Typical Performance Characteristics (Continued)

HC4046 Typica l Source Follower

Power Dissi pa tio n vs RS Typical fMAX/fMIN vs R2/R1

VCC = 4.5V & 6V fMAX/fMIN

Typical VCO Linaearity vs R1 & C1 Typical VCO Linearity vs R1 & C1

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MM74HC4046

Detailed Circuit Description

VOLTAGE CONTROLLED OSCILLATOR/SOURCE

FOLLOWER

The VCO requires two or three external components to

operate. These are R1, R2, C1. Resistor R1 and capacitor

C1 are selected to determine the center frequency of the

VCO. R1 controls the lock range. As R1’s resistance

decreases the range of fMIN to fMAX increases. Thus the

VCO’s gain increases. As C1 is changed the offset (if used)

of R2, and the center frequency is changed. (See typical

performance curves) R2 can be used to set the offset fre-

quency with 0V at VCO input. If R2 is omitted the VCO

range is from 0Hz. As R2 is decreased the offset frequency

is incr eased. The e ffect of R 2 is s hown in the des ign in for-

mation table and typical performance curves. By increasing

the value of R2 the lock range of the PLL is offset above

0Hz and the gain (Hz/Volt) does not change. In general,

when offset is desired, R2 and C1 should be ch osen first,

and then R 1 should be chosen to ob tain the proper center

frequency.

Internally the resistors set a current in a current mirror as

shown in Figur e 1. T he m irrored curre nt drives o ne side of

the capacit or once the capaci tor charges u p to the t hresh-

old of the schmitt trigger the oscillator logic flips the capaci-

tor over and cause s th e mir ror t o cha rge t he op posi te side

of the capacitor. The output from the internal logic is then

taken to pin 4.

VCO WITH OUT OFFSET

R2 = ∞VCO WITH OFFSET

FIGURE 1.

Comparator I Comparator II & III

R2= ∞R2≠∞ R2= ∞R2≠∞

•Given: f0•Given: f0 and fL•Given: fMAX •Given: fMIN and fMAX

•Use f0 with curve titled •Calculate fMIN from the •Calculate f0 from the •Use fMIN with curve titled

center frequency vs R1, C equation fMIN = fo − fLequation fo = fMAX/2 offset frequency vs R2,

to determine R1 and C1 •Use fMIN with curve titled •Use f0 with curve titled C to determine R2 and C1

offset frequency vs R2, C center frequency vs R1, C •Calculate fMAX/fMIN

to determine R2 and C1 to determine R1 and C1 •Use fMAX/fMIN with curve

•Calculate fMAX/fMIN from titled fMAX/fMIN vs R2/R1

the equation fMAX/fMIN =to determine ratio R2/R1

fo + fL/fo − fLto obtain R1

•Use fMAX/fMIN with curve

titled fMAX/fMIN vs R2/R1

to determine ratio R2/R1

to obtain R1

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MM74HC4046

Detailed Circuit Description (Continued)

FIGURE 2. Logic Diagram for VCO

The input to the VCO is a very high impedance CMOS

input and so it will not load down the loop filter, easing the

filters design. In order to make signals at the VCO input

accessible without degrading the loop performance a

source follower transistor is provided. This transistor can

be used by connecting a resistor to ground and its drain

output will follow the VCO input signal.

An inhibit signal is provided to allow disabling of the VCO

and the source follower. This is useful if the internal VCO is

not being used. A logic high on inhibit disables the VCO

and source follower.

The output of the VCO is a standard high speed CMOS

output with an equivalent LSTTL fanout of 10. The VCO

output is approximately a square wave. This output can

either dire ctly f eed the com pa rat or i n pu t of t he pha se co m-

parators or feed external prescalers (counters) to enable

frequency synthesis.

PHASE COMPARATORS

All three phase comparators share two inputs, Signal In

and Comparator In. The Signal In has a special DC bias

network that enables AC coupling of input signals. If the

signals are not AC coupled then this input requires logic

levels the sam e as standard 74HC . The Comparat or input

is a standar d digital input . Both input stru ctures are s hown

in Figure 3.

The out puts of the se com parato rs are essent ially sta ndard

74HC voltage outputs. (Comparator II is 3-STATE.)

FIGURE 3. Logic Diagram for Phase Comparator I and the common input circuit for all three comparators

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MM74HC4046

Detailed Circuit Description (Continued)

FIGURE 4. Typical Phase Comparator I. Waveforms

Thus in normal operation VCC and ground voltage levels

are fed to the loop filter. This differs from some phase

detectors which supply a current output to the loop filter

and this should be considered in the design. (The CD4046

also provides a voltage.)

Figure 5 shows the state tables for all three comparators.

PHASE COMPARATOR I

This comparator is a simple XOR gate similar to the

74HC86, and its operation is similar to an overdriven bal-

anced modulator. To maximize lock range the input fre-

quencies must have a 50% duty cycle. Typical input and

output w a vefo rm s ar e sh own i n Fig ure 4. T he out put of the

phase detector feeds the loop filter which averages the out-

put voltage. The frequency range upon which the PLL will

lock onto if initially out of lock is defined as the capture

range. The capture range for phase detector I is dependent

on the loop filter employed. The capture range can be as

large as the lock range which is equal to the VCO fre-

quency range.

To see how the detecto r operates r efer to Figur e 4. When

two sq uare wave inputs are applied to this com parator, an

output waveform whose duty cycle is dependent on the

phase difference between the two signals results. As the

phase d ifference i ncr eas es th e o utpu t du ty cyc l e incr ea ses

and the voltage after the loop filter increases. Thus in order

to achieve lock, when the PLL input frequency increases

the V CO in put volta ge mu st incre ase and th e phas e differ-

ence between co mparator in and signal in will increase. At

an input frequency equal fMIN, the VC O input is at 0V and

this re quir es the pha se de tector outpu t to be gro und hen ce

the two input signals must be in phase. When the input fre-

quency is fMAX then the VCO input must be VCC and the

phase detector inputs must be 180° out of phase.

The XO R is m ore sus cept ible to l ocking onto h armon ics of

the sign al input than th e digital p hase detecto r II. Thi s can

be seen by noticing that a signal 2 times the VCO fre-

quency results in the same output duty cycle as a signal

equal t he VCO freque ncy. The differen ce is t hat the out put

frequency of the 2f example is twice that of the other exam-

ple. The lo op filte r and the VCO range shou ld be designed

to prevent locking on to harmonics.

PHASE COMPARATOR II

This detector is a digital memory network. It consists of four

flip-flop s and s ome gating logi c, a th ree sta te outp ut an d a

phase pul se ou tput a s show n in Fig ure 6. Th is compa rator

acts on ly on the po sitive edges of the inpu t signals an d is

thus independent of signal duty cycle.

Phase comparator II operates in such a way as to force the

PLL into lock with 0 phase difference between the VCO

output and the signal input positive waveform edges. Fig-

ure 7 shows some typical loop waveforms. First assume

that the si g nal i n put pha se is lead i ng t he c om par ato r i np ut.

This me an s th at th e VCO’s frequency must be increased to

bring its leading edge into proper phase alignment. Thus

the phase detecto r II output is set high. This will ca use the

loop filter to charge up th e VCO input increa sing the VCO

frequency. Once the lea ding edge of t he comparato r input

is detected the output goes 3-STATE holding the VCO

input at the loop filter voltage. If th e VCO still lags the sig-

nal then the phase detector will again charge up to VCO

input for the ti m e be twee n the le adin g edg es of both wa ve-

forms.

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MM74HC4046

Detailed Circuit Description (Continued)

Phase Comparator State Diagrams

FIGURE 5. PLL State T ables

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MM74HC4046

Detailed Circuit Description (Continued)

FIGURE 6. Logic Diagram for Phase Comparator II

FIGURE 7. Typical Phase Comparator II Output Waveforms

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MM74HC4046

Detailed Circuit Description (Continued)

If the VCO le ads the signal then when the lea ding edge of

the VCO i s seen the ou tput of the ph ase compar ator goes

LOW. This discharges the loo p filter unti l the lead ing edge

of the sign al is detecte d at which tim e the output 3-STATE

itself again. This has the effect of slowing down the VCO to

again make the rising edges of both waveform coincident.

When the PLL is out of lock the VCO will be running either

slower or fa ster tha n the sign al inpu t. If it is runn ing slow er

the phase detector will see more signal rising edges and so

the output of the phase comparator will be HIGH a majority

of the time, ra ising the VC O’s frequency. Conve rsely, if the

VCO is running faster than the signal the output of the

detector will be LOW most o f the time a nd the VCO’s out-

put frequency will be decreased.

As one can see when the PLL is locked the output of phase

comparator II will be almost always 3-STATE except for

minor corrections at the leading edge of the waveforms.

When the detector is 3-STATE the phase pulse output is

HIGH. This ou tput can be used to det erm i ne when th e P LL

is in the locked condition.

This detector has several interesting characteristics. Over

the entire VCO frequency range there is no phase differ-

ence between the comparator input and the signal input.

The lock range of the PLL is the same as the capture

range. Minimal power is consumed in the loop filter since in

lock the detector output is a high impedance. Also when no

signal is present the detector will see only VCO leading

edges, and so the comparator outp ut will stay LOW forcing

the VCO to fMIN operating frequency.

Phase comparato r II is m ore susceptible to noise causing

the phase lock loop to unlo ck. If a noise pulse is seen on

the signal input, the comparator treats it as another positive

edge of the signal and will cause the output to go HIGH

until the V CO leading edge is seen, pote ntially for a whol e

signal input period. This would cause the VCO to speed up

during that time. When using the phase comparator I the

output of that phase detector would be disturbed for only

the shor t dura tion of the noise sp ike and wou ld c ause les s

upset.

PHASE COMPARATOR III

This comparator is a simple S-R Flip-Flop which can func-

tion as a phase comparator Figure 8. It has some similar

characteristics to the edge sensitive comparator. To see

how this detector works assume input pulses are applied to

the signal and comparator inputs as shown in Figure 9.

When the signal input leads the comparator input the flop is

set. This will charge up the loop filter and cause the VCO to

speed up , bri nging th e comp arato r into p hase w ith the sig-

nal input. When using short pulses as input this comparator

behaves very similar to the second comparator. But one

can see that if the signal input is a long pulse, the output of

the comparator will be forced to a one no matter how many

comparator input pulses are received. Also if the VCO input

is a square wave (as it is) and the signal input is pulse then

the VCO will force the comparator output LOW much of the

time. The refore it i s ideal to condi tion the signa l and com-

parator input to short pulses. This is most easily done by

using a series capacitor.

FIGURE 8. Phase Comparator III Logic Diagram

FIGURE 9. Typical W aveforms for Phase Comparator III

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MM74HC4046

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M16A

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MM74HC4046

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M16D

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MM74HC4046

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC16

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MM74HC4046 CMOS Phase Lock Loop

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N16E

Fairchild does not assume an y responsibility fo r use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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