FDMC86184 N-Channel Shielded Gate PowerTrench(R) MOSFET 100 V, 57 A, 8.5 m Features General Description Shielded Gate MOSFET Technology This N-Channel MV MOSFET is produced using ON Semiconductor's advanced PowerTrench(R) process that incorporates Shielded Gate technology. This process has been optimized to minimize on-state resistance and yet maintain superior switching performance with best in class soft body diode. Max rDS(on) = 8.5 m at VGS = 10 V, ID =21 A Max rDS(on) = 24.8 m at VGS = 6 V, ID = 10 A 50% Lower Qrr than Other MOSFET Suppliers Lowers Switching Noise/EMI Applications MSL1 Robust Package Design 100% UIL Tested Primary DC-DC MOSFET RoHS Compliant Synchronous Rectifier in DC-DC and AC-DC Motor Drive Solar Pin 1 Pin 1 S D D Top D S S S D S D S D G D G D Bottom MOSFET Maximum Ratings TA = 25 C unless otherwise noted. Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current -Continuous ID TC = 25 C TJ, TSTG 20 V (Note 5) 57 TC = 100 C (Note 5) 36 -Continuous TA = 25 C (Note 1a) 12 (Note 4) 266 (Note 3) 121 -Pulsed PD Units V -Continuous Single Pulse Avalanche Energy EAS Ratings 100 Power Dissipation TC = 25 C Power Dissipation TA = 25 C 54 (Note 1a) Operating and Storage Junction Temperature Range 2.3 -55 to +150 A mJ W C Thermal Characteristics RJC Thermal Resistance, Junction to Case RJA Thermal Resistance, Junction to Ambient 2.3 (Note 1a) 53 C/W Package Marking and Ordering Information Device Marking FDMC86184 Device FDMC86184 Package Power 33 Semiconductor Components Industries, LLC, 2016 June, 2017, Rev. 1.1 Reel Size 13 '' Tape Width 12 mm Quantity 3000 units Publication Order Number: FDMC86184/D 1 FDMC86184 N-Channel Shielded Gate PowerTrench(R) MOSFET www.onsemi.com Symbol Parameter Test Conditions Min. Typ. Max. Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 A, VGS = 0 V BVDSS TJ Breakdown Voltage Temperature Coefficient ID = 250 A, referenced to 25 C IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 A IGSS Gate to Source Leakage Current VGS = 20 V, VDS = 0 V 100 nA 4.0 V 100 V 59 mV/C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 110 A VGS(th) TJ Gate to Source Threshold Voltage Temperature Coefficient ID = 110 A, referenced to 25 C -9 VGS = 10 V, ID = 21 A 6.4 8.5 rDS(on) Static Drain to Source On Resistance VGS = 6 V, ID = 10 A 11 24.8 VGS = 10 V, ID = 21 A, TJ = 125 C 11 18 VDS = 5 V, ID = 21 A 49 gFS Forward Transconductance 2.0 3.1 mV/C m S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance VDS = 50 V, VGS = 0 V, f = 1 MHz 0.1 1490 2090 906 1270 pF pF 13 25 pF 0.4 1.2 Switching Characteristics td(on) Turn-On Delay Time 12 22 ns tr Rise Time 4 10 ns td(off) Turn-Off Delay Time 17 31 ns tf Fall Time 4 10 ns nC VDD = 50 V, ID = 21 A, VGS = 10 V, RGEN = 6 Qg Total Gate Charge VGS = 0 V to 10 V 21 30 Qg Total Gate Charge VGS = 0 V to 6 V 14 20 Qgs Gate to Source Charge Qgd Gate to Drain "Miller" Charge Qoss Output Charge VDD = 50 V, ID = 21 A VDD = 50 V, VGS = 0 V nC 6.5 nC 4.6 nC 61 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 2.1 A (Note 2) 0.7 1.2 VGS = 0 V, IS = 21 A (Note 2) 0.8 1.3 IF = 10 A, di/dt = 300 A/s IF = 10 A, di/dt = 1000 A/s V 27 44 ns 46 74 nC 21 34 ns 96 154 nC Notes: 1. RJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RCA is determined by the user's board design. a. 53 C/W when mounted on a 1 in2 pad of 2 oz copper b. 125 C/W when mounted on a minimum pad of 2 oz copper SS SF DS DF G SS SF DS DF G 2. Pulse Test: Pulse Width < 300 s, Duty cycle < 2.0%. 3. EAS of 121 mJ is based on starting TJ = 25 C; N-ch: L = 3 mH, IAS = 9 A, VDD = 100 V, VGS =10 V. 100% test at L = 0.3 mH, IAS = 21 A. 4. Pulsed Id please refer to Fig 11 SOA graph for more details. 5. Computed continuous current limited to Max Junction Temperature only, actual continuous current will be limited by thermal & electro-mechanical application board design. www.onsemi.com 2 FDMC86184 N-Channel Shielded Gate PowerTrench(R) MOSFET Electrical Characteristics TJ = 25 C unless otherwise noted. 200 4 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) VGS = 10 V VGS = 8 V 150 VGS = 6.5 V 100 VGS = 6 V VGS = 5.5 V 50 PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 0 0 1 2 3 4 VGS = 5.5 V VGS = 6 V 3 VGS = 6.5 V 2 VGS = 8 V 1 0 5 0 50 VDS, DRAIN TO SOURCE VOLTAGE (V) 150 200 Figure 2. Normalized On-Resistance vs. Drain Current and Gate Voltage 2.0 50 ID = 21 A VGS = 10 V 1.8 rDS(on), DRAIN TO 1.6 SOURCE ON-RESISTANCE (m) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 100 ID, DRAIN CURRENT (A) Figure 1. On-Region Characteristics 1.4 1.2 1.0 0.8 0.6 -75 PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 40 ID = 21 A 30 20 TJ = 125 oC 10 TJ = 25 oC 0 -50 -25 0 25 50 75 100 125 150 4 TJ, JUNCTION TEMPERATURE (oC) IS, REVERSE DRAIN CURRENT (A) PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 150 VDS = 5 V 100 TJ = 150 oC TJ = 25 oC TJ = -55 oC 0 2 4 6 8 6 7 8 9 10 Figure 4. On-Resistance vs. Gate to Source Voltage 200 50 5 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On- Resistance vs. Junction Temperature ID, DRAIN CURRENT (A) VGS = 10 V PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 200 100 VGS = 0 V 10 1 TJ = 150 oC 0.1 TJ = 25 oC 0.01 TJ = -55 oC 0.001 0.0 10 0.2 0.4 0.6 0.8 1.0 VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs. Source Current www.onsemi.com 3 1.2 FDMC86184 N-Channel Shielded Gate PowerTrench(R) MOSFET Typical Characteristics TJ = 25 C unless otherwise noted. 10000 ID = 21 A Ciss 8 VDD = 50 V 6 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 25 V VDD = 75 V 4 1000 Coss 100 10 2 0 0 6 12 18 f = 1 MHz VGS = 0 V Crss 1 0.1 24 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs. Drain to Source Voltage 60 50 o ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) RJC = 2.3 C/W TJ = 25 oC 10 TJ = 100 oC TJ = 125 oC 1 0.01 0.1 50 VGS = 10 V 40 30 20 VGS = 6 V 10 1 10 0 25 100 50 150 P(PK), PEAK TRANSIENT POWER (W) 10000 100 ID, DRAIN CURRENT (A) 125 Figure 10. Maximum Continuous Drain Current vs. Case Temperature 300 10 s 10 THIS AREA IS LIMITED BY rDS(on) 100 s SINGLE PULSE TJ = MAX RATED RJC = 2.3 oC/W TC = 25 oC 0.1 0.1 100 TC, CASE TEMPERATURE ( C) Figure 9. Unclamped Inductive Switching Capability 1 75 o tAV, TIME IN AVALANCHE (ms) 1 1 ms CURVE BENT TO MEASURED DATA 10 10 ms 100 ms 100 SINGLE PULSE RJC = 2.3 oC/W TC = 25 oC 1000 500 100 10 -5 10 -4 10 -3 10 -2 10 -1 10 t, PULSE WIDTH (sec) VDS, DRAIN to SOURCE VOLTAGE (V) Figure 11. Forward Bias Safe Operating Area Figure 12. Single Pulse Maximum Power Dissipation www.onsemi.com 4 1 FDMC86184 N-Channel Shielded Gate PowerTrench(R) MOSFET Typical Characteristics TJ = 25 C unless otherwise noted. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 2 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 0.01 0.001 -5 10 NOTES: SINGLE PULSE ZJC(t) = r(t) x RJC RJC = 2.3 oC/W Peak TJ = PDM x ZJC(t) + TC Duty Cycle, D = t1 / t2 -4 10 -3 -2 10 10 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Case Transient Thermal Response Curve www.onsemi.com 5 -1 10 1 FDMC86184 N-Channel Shielded Gate PowerTrench(R) MOSFET Typical Characteristics TJ = 25 C unless otherwise noted. 3 .4 0 3 .2 0 P KG CL 8 2 .3 7 M IN A (0.4 5) 8 B 5 PKG CL 3. 40 3. 20 P K G CL S YM CL 5 2 .1 5 M IN (0.4 0) (0 .65 ) 0 .7 0 M IN PI N 1 IND ICA TO R 1 4 1 4 0. 65 1 .95 SE E D E TAI L A 0 .42 M IN (8 X ) L A N D P A T TE RN R E C O M M E N D A TI O N 1. 95 0 .10 C A B 0 .37 (8X ) 0 .27 0. 65 1 4 0 .50 0 .30 P K G CL 2 .05 1 .85 8 (0. 34 ) (0 .5 2 TY P ) 5 NOTE S : U NL E SS OT HE RW IS E S P E CIFI ED A ) P A CK A GE S TA ND A RD RE FE RE NC E: JE D EC M O -24 0, IS SU E A , V A R. BA , DA TE D O CTO B E R 2 00 2. B ) A L L D IM E NS IO N S AR E IN MI LL IM ET ER S . C ) D IME N SI O NS D O NO T IN CLU DE B U RRS O R M O LD FL A SH . M O LD FL AS H O R B UR RS D OE S NOT EX C EE D 0. 10 MM . D ) D IME N SI O NIN G A ND TO L E RA NC ING PE R A S M E Y 14 .5M -19 94 . E ) D RA W IN G FIL E NA M E : P QFN 08 HRE V 1 (0 .3 3) TY P (2 .27 ) 0.1 0 C 0. 80 0. 70 0 .08 C 0.2 5 0.1 5 0. 05 0. 00 C S EA TI NG P L A NE D E TA IL A SC A LE : 2X ON Semiconductor and the ON Logo are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. www.onsemi.com 6 FDMC86184 N-Channel Shielded Gate PowerTrench(R) MOSFET Dimensional Outline and Pad Layout