ISL97645IRZ-T - Intersil - Datasheet.Live

FN6353.1

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

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ISL97645A

Boost + VON Slice + VCOM + Reset

The ISL97645A represents an integrated DC/DC regulator

for monitor and notebook applications with screen sizes up

to 20”. The device integrates a boost converter for

generating A VDD, a VON slice circuit, and a high performance

VCOM amplifier.

The boost converter features a 2.6A FET and has user

programmable soft-start and compensation. With efficiencies

up to 92%, the AVDD is user selectable from 7V to 20V.

The VON slice circuit can control gate voltages up to 30V.

High and low levels are programmable, as well as discharge

rate and timing.

The supply monitor can be used to monitor the input voltage

to prevent low voltage operation.

The integrated VCOM features high speed and drive

capability. With 30MHz bandwidth and 50V/µs slew rate, the

VCOM amplifier is capable of driving 400mA peaks, and

100mA continuous output curren t.

Features

• 2.7V to 5.5V Input

• 2.6A Integrated Boost for Up to 20V AVDD

• Integrated VON Slice

• RESET signal generated by Supply Monitor

• 600kHz/1.2MHz fS

•V

COM Amplifier

-30MHz BW

-50V/µs SR

- 400mA Peak Output Current

• UV and OT Protection

• 24 Ld 4x4 QFN

• Pb-Free (RoHS Compliant)

Applications

• LCD Monitors (15”+)

• Notebook Display (up to 16”)

Pinout

ISL97645A

(24 LD 4x4 QFN)

TOP VIEW

Ordering Information

PART

NUMBER

(Notes 1, 2, 3) PART

MARKING

TEMP.

RANGE

(°C) PACKAGE

(Pb-Free) PKG.

DWG. #

ISL97645AIRZ 976 45AIRZ -40 to +85 24 Ld 4x4 QFN L24.4x4D

NOTES:

1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details

on reel specifications.

2. These Intersil Pb-free plastic packaged products employ special Pb-

free material sets, molding compounds/die attach materials, and

100% matte tin plate plus anneal (e3 termination finish, which is

RoHS compliant and compatible with both SnPb and Pb-free

soldering operations). Intersil Pb-free products are MSL classified at

Pb-free peak reflow temperatures that meet or exceed the Pb-free

requirements of IPC/JEDEC J STD-020.

3. For Moisture Sensitivity Level (MSL), please see device

information page for ISL97645A. For more information on

MSL please see tech brie f TB363.

VGH

PGND

ENABLE

OUT

NEG

POS

AGND

CD2

VDIV

GND

VGH_M

VFLK

VDPM

VDD1

VDD2

VIN2

FREQ2

COMP

RESET

24 23 22 21 20 19

789101112

Data Sheet October 21, 2010

2FN6353.1

October 21, 2010

Pin Descriptions

PIN NUMBER NAME DESCRIPTION

1 GND Signal ground

2 VGH_M Gate Pulse Modulator Output

3 VFLK Gate Pulse Modulator Control input

4 VDPM Gate Pulse Modulator Enable. Connect a capacitor from VDPM to GND to set the delay time before GPM is

enabled. A 20µA current source charges CDPM. Power on delay time = 60.75k*CDPM.

5 VDD1 Gate Pulse Modulator Low Voltage Input

6 VDD2 VCOM Amplifier Supply

7 OUT VCOM Amplifier Output

8 NEG VCOM Amplifier Inverting input

9 POS VCOM Amplifier Non-invertin g input

10 AGND VCOM Amplifier Ground

1 1 CD2 V oltage detector rising edge delay . Connect a capacitor between this pin and GND to set the rising edge delay .

12 VDIV Voltage detector threshold. Connect to the center of a resistive divider between VIN and GND.

13 RESET Voltage detector reset output.

14 SS Boost Converter Soft-Start. Connect a capacitor between this pin and GND to set the soft-start time.

15 COMP Boost Converter Compensation pin. Connect a series resistor and capacitor between this pin and GND to

optimize transient response.

16 FREQ Boost Converter frequency select

17 VIN2 Boost Converter power supply

18 LX Boost Converter Switching Node

19 ENABLE Chip Enable pin. Connect to VIN1 for normal operation, GND for shutdown.

20 FB Boost Converter Feedback

21 PGND Boost Converter Power Ground

22 RE Gate Pulse Modulator Slew Control. Connect a resistor between this pin and GND to set the falling slew rate.

23 CE Gate Pulse Modulator Delay Control. Connect a capacitor between this pin and GND to set the delay time.

24 VGH Gate Pulse Modulator High Voltage Input

ISL97645A

3FN6353.1

October 21, 2010

Absolute Maximum Ratings Thermal Information

Lx to GND, AGND and PGND . . . . . . . . . . . . . . . . . . . . -0.5 to +25V

VDD2, OUT, NEG and POS

to GND, AGND and PGND. . . . . . . . . . . . . . . . . . . . . -0.5 to +25V

VDD1, VGH and VGH_M

to GND, AGND and PGND. . . . . . . . . . . . . . . . . . . . . -0.5 to +32V

Differential Voltage Between POS and NEG . . . . . . . . . . . . . . . ±6V

Voltage Between GND, AGND and PGND . . . . . . . . . . . . . . . ±0.5V

All Other Pins to GND, AGND and PGND. . . . . . . . . . -0.5 to +6.5V

Input, Output, or I/O Voltage . . . . . . . . . . .GND -0.3V to VIN + 0.3V

Recommended Operating Conditions

Input Voltage Range, VS . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V

Boost Output Voltage Range, AVDD. . . . . . . . . . . . . . . . . . 8V to 20V

Input Capacitance, CIN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22µF

Boost Inductor, L1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3µH to 10µH

Output Capacitance, COUT. . . . . . . . . . . . . . . . . . . . . . . .2µF x 22µF

Operating Ambient Temperature Range . . . . . . . . . .-40°C to +85°C

Operating Junction Temperature . . . . . . . . . . . . . . .-40°C to +125°C

Thermal Resistance θJA (°C/W) θJC (°C/W)

4x4 QFN Package (Notes 4, 5) . . . . . . 39 2.5

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Maximum Continuous Junction Temperature . . . . . . . . . . . +125°C

Power Dissipation

TA ≤ +25°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2.44W

TA = +70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.34W

TA = +85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.98W

TA = +100°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .0.61W

Pb-Free Reflow Profile see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTES:

4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

Brief TB379.

5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

Electrical Specifications VIN = ENABLE = 5V, VDD1 =V

DD2 = 14V, VGH = 25V, AVDD = 10V, TA= -40°C to +85°C

Unless Otherwise Noted. Boldface limits apply over the operating temperature range,

-40°C to +85°C.

SYMBOL PARAMETER TEST CONDITION MIN

(Note 6) TYP MAX

(Note 6) UNIT

GENERAL

VSVIN Input Voltage Range 2.7 3.3 5.5 V

IS_DIS VIN Supply Currents when Disabled ENABLE = 0V 1 3.5 µA

ISVIN Supply Currents ENABLE = 5V, LX not switching 1 mA

UVLO Under Voltage Lockout Threshold VIN2 Rising 2.3 2.45 2.6 V

VIN2 Falling 2.2 2.35 2.5 V

OTRThermal Shutdown Temperature Temperature Rising 140 °C

OTFTemperature Falling 100 °C

LOGIC INPUT CHARACTERISTICS - ENABLE, VFLK, FREQ, VDPM

VIL Low Voltage Threshold 0.8 V

VIH High Voltage Threshold 2.2 V

RIL Pull-Down Resistor Enabled, Input at VIN 150 250 400 kΩ

STEP-UP SWITCHING REGULATOR

AVDD Output Voltage Range VIN*1.25 20 V

ΔVBOOST/ΔIOUT Load Regulation 50mA < ILOAD < 250mA 0.2 %

ΔVBOOST/ΔVIN Line Regulation ILOAD = 150mA, 3.0 < VIN < 5.5V 0.15 0.25 %

ACCAVDD Overall Accuracy (Line, Load,

Temperature) 10mA < ILOAD < 300mA,

3.0 < VIN < 5.5V, 0°C < TA < +85°C -3 3 %

VFB Feedback Voltage (VFB)I

LOAD = 100mA, TA = +25°C 1.20 1.21 1.22 V

ILOAD = 100mA, T A = -40°C to +85°C 1.19 1.21 1.23 V

ISL97645A

4FN6353.1

October 21, 2010

IFB FB Input Bias Current 250 500 nA

rDS(ON) Switch ON-resistance 150 300 mΩ

EFF Peak Efficiency 92 %

ILIM Switch Current Limit 2.9 A

DMAX Max Duty Cycle 85 90 %

fOSC Oscillator Frequency FREQ = 0V 550 650 800 kHz

FREQ = VIN2 1.0 1.2 1.4 MHz

ISS Soft-Start Slew Current SS < 1V, TA = +25°C 2.75 µA

VCOM AMPLIFIER RLOAD =10k, C

LOAD = 10pF, Unless Otherwise Stated

VSAMP Supply Voltage 4.5 20 V

ISAMP Supply Current 3mA

VOS Offset Voltage 320 mV

IBNoninverting Input Bias Current 0 100 nA

CMIR Common Mode Input Voltage Range 0 VDD2 V

CMRR Common-Mode Rejection Ratio 50 70 dB

PSRR Power Supply Rejection Ratio 70 85 dB

VOH Output Voltage Swing High IOUT(source) = 5mA VDD2 - 50 mV

VOH Output Voltage Swing High IOUT(source) = 50mA VDD2 - 450 mV

VOL Output Voltage Swing Low IOUT(sink) = 5mA 50 mV

VOL Output Voltage Swing Low IOUT(sink) = 50mA 450 mV

ISC Output Short Circuit Current 250 400 mA

SR Slew Rate 50 V/µs

BW Gain Bandwidth -3dB gain point 30 MHz

GATE PULSE MODULATOR

VGH VGH Voltage 730V

VIH_VDPM VDPM Enable Threshold 1.18 1.215 1.25 V

IVGH VGH Input Current VFLK = 0 260 µA

RE = 33kΩ, VFLK = VDD1 40 µA

VDD1 VDD1 Voltage 3VGH - 2V

IVDD1 VDD1 Input Current -2 0.1 2µA

RONVGH VGH to VGH_M On Resistance 70 Ω

IDIS_VGH VGH_M Discharge Current RE = 33kΩ8mA

IDPM VDPM Charge Current 20 µA

tDEL DELAY Time CE = 470pF, RE = 33kΩ1.9 µs

Electrical Specifications VIN = ENABLE = 5V, VDD1 =V

DD2 = 14V, VGH = 25V, AVDD = 10V, TA= -40°C to +85°C

Unless Otherwise Noted. Boldface limits apply over the operating temperature range,

-40°C to +85°C. (Continued)

SYMBOL PARAMETER TEST CONDITION MIN

(Note 6) TYP MAX

(Note 6) UNIT

ISL97645A

5FN6353.1

October 21, 2010

SUPPLY MONITOR

VIH_VDIV VDIV High Threshold VDIV rising 1.18 V

VIL_VDIV VDIV Low Threshold VDIV falling 1.05 V

ICD2 CD2 Charge Current 10 µA

RIL_RESET RESET Pull-Down Resistance 750 Ω

tDELAY_RESET RESET Delay on the Rising Edge 121.5k*CD s

NOTE:

6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. T emperature limits established by characterization

and are not production tested.

Electrical Specifications VIN = ENABLE = 5V, VDD1 =V

DD2 = 14V, VGH = 25V, AVDD = 10V, TA= -40°C to +85°C

Unless Otherwise Noted. Boldface limits apply over the operating temperature range,

-40°C to +85°C. (Continued)

SYMBOL PARAMETER TEST CONDITION MIN

(Note 6) TYP MAX

(Note 6) UNIT

Typical Performance Curves

FIGURE 1. AVDD EFFICIENCY vs IAVDD FIGURE 2. AVDD LOAD REGULATION vs IAVDD

FIGURE 3. LINE REGULATION AVDD vs VIN FIGURE 4. BOOST CONVERTER TRANSIENT RESPONSE

100

0 200 400 600 800 1000 1200

IAVDD (mA )

EFFICIENCY (%)

fOSC = 1.2MHz

fOSC = 650kHz

-0.9

-0.8

-0.7

-0.6

-0.5

-0.4

-0.3

-0.2

-0.1

0 200 400 600 800 1000 1200

IAVDD (mA)

LOAD REGULATION (%)

fOSC = 1.2MHz

fOSC = 650kHz

10.15

10.2

10.25

10.3

10.35

10.4

10.45

10.5

3 3.5 4.0 4.5 5.0 5.5 6.0

VIN (V)

AVDD (V)

AVDD 500mA

AVDD 150mA IAVDD

AVDD (AC COUPLED)

L = 10µH, COUT = 40µF, CCOMP = 2.2nF, RCOMP = 10k

ISL97645A

6FN6353.1

October 21, 2010

FIGURE 5. GPM CIRCUIT WAVEFORM FIGURE 6. GPM CIRCUIT WAVEFORM

FIGURE 7. GPM CIRCUIT WAVEFORM FIGURE 8. GPM CIRCUIT WAVEFORM

FIGURE 9. VGHM FOLLOWS VGH WHEN THE SYSTEM

POWERS OFF FIGURE 10. VCOM RISING SLEW RATE

Typical Performance Curves (Continued)

VGH_M

VFLK

CE = 1pF, RE = 100k

VGH_M

VFLK

CE = 1000pF, RE = 100k

VGH_M

VFLK

CE = 10pF, RE = 100k

VGH_M

VFLK

CE = 10pF, RE = 150k

INPUT SIGNAL

OUTPUT SIGNAL

ISL97645A

7FN6353.1

October 21, 2010

FIGURE 11. VCOM BANDWIDTH MEASUREMEN T

Typical Performance Curves (Continued)

INPUT

OUTPUT

SIGNAL

(-3dB ATTENTUA TION

FROM INPUT SIGNAL)

ISL97645A

8FN6353.1

October 21, 2010

Block Diagram

FIGURE 12. ISL97645A BLOCK DIAGRAM

VFLK VGH CE REVGH_M

PGND

ENABLE

COMP

FREQ

OSCILLATION

SLOPE

COMPENSATION

GENERATOR

REFERENCE

GENERATOR

SUMMING

AMPLIFIER

START-UP AND

FAULT CONTROL

PWM

LOGIC

2.5µA

RESET

VIN

VDPM

OUT

VDD2

POS

NEG

GND

VDD1

GPM

CIRCUIT

20µA

10µA

CD2 VREF

VDIV VREF 750Ω

ISL97645A

9FN6353.1

October 21, 2010

Functional Block Diagram

Applications Information

The ISL97645A provides a complete power solution for TFT

LCD applications. The system consists of one boost

converter to generate A VDD voltage for column drivers, one

integrat ed VCOM buffer which can provide up to 400mA peak

current, and one supply monitor to generate the reset signal

when the input voltage is low. This part also integrates Gate

Pulse Modulator circuit that can help to optimize the picture

quality.

Enable Control

When enable pin is pulling dow n, the ISL97645A is shut

down reducing the supply current to <10µA. When the

voltage at enable pin reaches 2.2V, the ISL9 7645A is on.

Boost Converter

Frequency Selection

The ISL97645A switching frequency can be user selected to

operate at either constant 650kHz or 1.2MHz. Lower

switching frequency can save power dissipation, while

higher switching frequency can allow smalle r external

components like inductor and output capacitors, etc.

Connecting the FREQ pin to GND sets the PWM switching

frequency to 650kHz, or connecting FREQ pin to VIN for

1.2MHz.

Soft-Start

The soft-start is provided by an internal 2.5µA current source

to charge the external soft-start capacitor. The ISL97645A

ramps up current limit from 0A up to full value, as the voltage

at SS pin ramps from 0 to 1.2V. Hence the soft-start time is

4.8ms when the soft-start cap acitor is 10nF, 22.6ms for 47nF

and 48ms for 100nF.

FIGURE 13. FUNCTIONAL BLOCK DIAGRAM

BOOST

GPM

CIRCUIT

VON

AVDD

VSHDN

VGH

VDD1

VGH_M

VFLK

COMP

POS

CD2

VDIV

RESET

GND

VDPM

FREQ-

PGND

VDD2

AGND

VIN

NEG-

VGATE

REF

OUT

VIN

ISL97645A

10 FN6353.1

October 21, 2010

Operation

The boost converter is a current mode PWM converte r

operating at either a 650kHz or 1.2MHz. It can operate in

both discontinuous conduction mode (DCM) at light load and

continuous mode (CCM). In continuous current mode,

current flows continuously in the inductor during the entire

switching cycle in steady state operation. The voltage

conversion ratio in continuous current mode is given by

Equation 1:

Where D is the duty cycle of the switching MOSFET.

Figure 12 shows the block diagram of the boost regulator. It

uses a summing amplifier architecture consisting of gm

stages for voltage feedback, current feedback and slope

compensation. A comparator looks at the peak inductor

current cycle by cycle and terminates the PWM cycle if the

current limit is reached.

An external resistor divider is required to divide the output

voltage down to the nominal reference voltage. Current

drawn by the resistor network should be limited to maintain

the overall converter efficiency. The maximum value of the

resistor network is limited by the feedback input bias current

and the potential for noise being coupled into the feedback

pin. A resistor network in the order of 60kΩ is recommended.

The boost converter output voltage is determined by

Equation 2:

The current through the MOSFET is limited to 2.6APEAK.

This restricts the maximum output current (average) based

on Equation 3:

Where ΔIL is peak to peak inductor ripple current, and is set

by Equation 4:

where fS is the switching frequency (650kHz or 1.2MHz).

Table 2 gives typical values (margins are considered 10%,

3%, 20%, 10% and 15% on VIN, VO, L, fS and IOMAX).

Capacitor

An input capa ci to r is used to suppress the voltage ripple

injected into the boost converter. The ceramic capacitor with

capacitance larger than 10µF is recommended. The voltage

rating of input capacitor should be larger than the maximum

input voltage. Some capacitors are recommended in Table 1

for input capacitor.

VBoost

VIN

-------------------1

1D–

-------------

=(EQ. 1)

VBoost R1R2

---------------------VFB

×=(EQ. 2)

T ABLE 1. BOOST CONVERTER INPUT CAP ACITOR

RECOMMENDATION

CAPACITOR SIZE MFG PART NUMBER

10µF/16V 1206 TDK C3216X7R1C106M

10µF/10V 0805 Murata GRM21BR61A106K

22µF/10V 1210 Murata GRB32ER61A226K

IOMAX ILMT

ΔIL

--------

–

⎝⎠

⎛⎞

VIN

---------

×=(EQ. 3)

ΔILVIN

--------- D

----

×=(EQ. 4)

TABLE 2. MAXIMUM OUTPUT CURRENT CALCULATION

VIN (V) VO (V) L (µH) FS (MHz) IOMAX (mA)

3 9 10 0.65 636

3 12 10 0.65 419

3 15 10 0.65 289

5 9 10 0.65 1060

5 12 10 0.65 699

5 15 10 0.65 482

5 18 10 0.65 338

3 9 10 1.2 742

3 12 10 1.2 525

3 15 10 1.2 395

5 9 10 1.2 1236

5 12 10 1.2 875

5 15 10 1.2 658

5 18 10 1.2 514

ISL97645A

11 FN6353.1

October 21, 2010

Inductor

The boost inductor is a critical part which influences the

output voltage ripple, transient response, and efficiency.

Values of 3.3µH to 10µ H are used to match the internal

slope compensation. The inductor must be able to handl e

the following average and peak current are in Equation 5:

Some inductors are recommended in Table 3.

Rectifier Diode

A high-speed diode is necessary due to the high switching

frequency. Schottky dio des are recommended because of

their fast recovery time and low forward voltage. The reverse

voltage rating of this diode should be higher than the

maximum output voltage. The rectifier diode must meet the

output current and peak inductor current requirements. The

following table is some recommendations for boost converter

diode.

Output Capacitor

The output capacitor supplies the load directly and reduces

the ripple voltage at the output. Output ripple voltage

consists of two components:

1. the voltage drop due to the inductor ripple current flowing

through the ESR of output capacitor.

2. charging and discharging of the output capacitor.

For low ESR ceramic capacitors, the output ripple is

dominated by the charging and discharging of the output

capacitor. The voltage rating of the output capacitor should

be greater than the maximum output voltage.

Note: Capacitors have a voltage coefficient that makes their

effective capacitance drop as the voltage across then

increases. COUT in the equation above assumes the

effective value of the cap acitor at a particular voltage and not

the manufacturer’s stated value, measured at 0V.

Table 5 shows some selections of output capacitors.

Compensation

The boost converter of ISL97645A can be compensated by

a RC network connected from CM1 pin to ground. 4.7nF and

10k RC network is used in the demo board. The larger value

resistor and lower value capacitor can lower the transient

overshoot, however, at the expense of stability of the loop.

Cascaded MOSFET Application

An 20V N-Channel MOSFET is integrated in the boost

regulator. For the applications where the output voltage is

greater than 20V, an external cascaded MOSFET is needed

as shown in Figure 14. The voltage rating of the external

MOSFET should be greater than AVDD.

TABLE 3. BOOST INDUCTOR RECOMMENDATION

INDUCTOR DIMENSIONS

(mm) MFG PART NUMBER

6.8µH/3APEAK 7.3x6.8x3.2 TDK RLF7030T-6R8N3R0

10µH/4APEAK 8.3x8.3x4.5 Sumida CDR8D43-100NC

5.2µH/4.55APEAK 10x10.1x3.8 Cooper

Bussmann CD1-5R2

T ABLE 4. BOOST CONVERTER RECTIFIER DIODE

RECOMMENDATION

DIODE VR/IAVG RATING PACKAGE MFG

SS23 30V/2A SMB Fairchild

Semiconductor

MBRS340 40V/3A SMC International

Rectifier

SL23 30V/2A SMB Vishay

Semiconductor

ILAVG IO

1D–

-------------

ILPK ILAVG

ΔIL

--------

(EQ. 5)

VRIPPLE ILPK ESR VOVIN

–

------------------------IO

COUT

----------------1

----

××+×=(EQ. 6)

TABLE 5. BOOST OUTPUT CAPACITOR RECOMMENDATION

CAPACITOR SIZE MFG PART NUMBER

10µF/25V 1210 TDK C3225X7R1E106M

10µF/25V 1210 Murata GRM32DR61E106K

FIGURE 14. CASCADED MOSFET TOPOLOGY FOR HIGH

OUTPUT VOLTAGE APPLICATIONS

INTERSIL

ISL97645A

AVDD

VIN

ISL97645A

12 FN6353.1

October 21, 2010

Supply Monitor Circuit

The Supply Monitor circuit monitors the voltage on VDIV,

and sets open-drain output RESET low when VDIV is below

1.15V (rising) or 1.1V (falling).

There is a delay on the rising edge, controlled by a capacitor

on CD2. When VDIV exceeds 1.15V (rising), CD2 is charged

up from 0V to 1.215V by a 10µA current source. Once CD2

exceeds 1.215V, RESET will go tri-state. When VDIV falls

below 1.1V, RESET will become low with a 750 pull-down

resistance. The delay time is controlled by Equation 7:

For example, the delay time is 12.15ms if the CD2 = 100nF.

Figure 15 is the Supply Monitor Circuit timing diagram.

Gate Pulse Modulator Circuit

The gate pulse modulato r circuit functions as a three way

multiplexer, switching VGHM between ground, VDD1 and

VGH. Voltage selection is provided by digi tal inputs VDPM

(enable) and VFLK (control). High to low delay and slew

control is provided by external components on pins CE and

RE, respectively. A block diagram of the gate pulse

modulator circuit is shown in Figure 16.

When VDPM is LOW, the block is disabled and VGHM is

grounded. When the input voltage exceeds UVLO threshold,

VDPM starts to drive an external capacitor with 20μA. Once

VDPM exceeds 1.215V, the GPM circuit is enabled, and the

output VGH_M is determined by VFLK , RESET signal and

VGH voltage. If RESET signal is high, and when VFLK goes

high, VGHM is pulled to VGH by a 70Ω switch. When VFLK

goes low, there is a delay controlle d by capacitor CE,

following which VGHM is driven to VDD1, with a slew rate

controlled by resistor RE. Note that VDD1 is used only as a

reference voltage for an amplifier, thus does not have to

source or sink a significant DC current.

Low to high transition is determined primarily by the switch

resistance and the external capacitive load. High to low

transition is more complex. Take the case where the block is

already enabled (VDPM is H). When VFLK is H, pin CE is

grounded. On the falling edge of VFLK, a current is passed

into pin CE, to charge an external capacitor to 1.2V. This

creates a delay, equal to CE*4200. At this point, the output

begins to pull down from VGH to VDD1. Th e slew current is

equal to 300/(RE + 5000), and the dv/dt slew rate is

Isl/CLOAD.

where CLOAD is the load capacitance applied to VGHM.

When RESET signal changes to low, and VGH voltage is

above 2.5V, the VGH_M will be tied to VGH voltage until the

VGH voltage falls down to 2.5V. If the VGH voltage is lower

than 2.5V, GPM block will not work properly, and there is no

active control for VGH_M output. The following table shows

the VGH_M status based on VIN, VGH and RESET:

tdelay 121.5k CD2×=(EQ. 7)

FIGURE 15. SUPPLY MONITOR CIRCUIT TIMING DIAGRAM

VDIV

RESET

1.15V

1.1V

1.215V

CD2

RESET DELAY TIME IS

CONTROLLED BY CD2

CAPACITOR

ISL97645A

13 FN6353.1

October 21, 2010

FIGURE 16. GATE PULSE MODULATOR CIRCUIT BLOCK DIAGRAM

VGH_M

VGH

VGH_M

VDD1

VFLK

EnGPM1

VREF

CONTROL

TIMING

AND

x240

200µA

Vin

UVLO

Threshold

VDPM 1.215V

VFLK

VGH_M

VGH

VGL

VGH_M is forced to

VGH when RESET

go es to lo w A ND

VGH>2.5V

Dela y time is

controlled by CE

Pow er on delay tim e is

controlled b y CDPM

Slope is controlled

by RE

VGH

RESET

FIGURE 17. GATE PULSE MODULATOR TIMING DIAGRAM

ISL97645A

14 FN6353.1

October 21, 2010

S tart-Up Sequence

When VIN exceeds VLOR and ENABLE reaches the VIH

threshold value, Boost co nverter starts up, and gate pulse

modulator circuit output holds until VDPM is charged to

1.215V. Note that there is a DC path in the boost converter

from the input to the output through the inductor and diode,

hence the input voltage will be seen at output with a forward

voltage drop of diode before the part is enabled. If this

voltage is not desired, the following circuit can be inserted

between input and inductor to disconnect the DC path when

the part is disabled.

VCOM Amplifier

The VCOM amplifier is designed to control the voltage on the

back plate of an LCD display. This plate is capacitively

coupled to the pixel drive voltage which alternately cycles

positive and negative at the line rate for the display . Thus the

amplifier must be capable of sourcing and sinking capacitive

pulses of current, which can occasionally be quite large (a

few 100mA for typical applications).

The ISL97645A VCOM amplifier's output current is limited to

400mA. This limit level, which is roughly the same for

sourcing and sinking, is included to maintain reliable

operation of the part. It does not necessarily prevent a large

temperature rise if the current is maintained. (In this case the

whole chip may be shut down by the thermal trip to protect

functionality.) If the displ ay occasionally demands current

pulses higher than this limit, the reservoir capacitor will

provide the excess and the amplifier will top the reservoir

capacitor back up once the pulse has stopped. This will

happen on the µs time scale in practica l systems and for

pulses 2 or 3 times the current limit, the V COM voltage will

have settled again before the next line is processed.

Fault Protection

ISL97645A provides the overall fault protections including

over current protection and over-temperature protection.

An internal temperature sensor continuously monitors the

die temperature. In the event that die temp erature exceeds

the thermal trip point, the device will shut down and disable

itself. The upper and lower trip points are typically set to

+140°C and +100°C respectively.

TABLE 6. VGH_M STATUS TABLE

VIN VDPM RESET VGH VGH_M COMMENT

x x x <2.5V GROUND Will be grounded if VIN is above

a logic threshold. Could occur at

power-up or power-down

>VLOR <1.215V x >2.5V GROUND Start-up only condition: If either

VIN> VLOR or reset is H, but

VDPM < 1.215V, GND VGHM

x <1.215V High >2.5V GROUND

>VLOR >1.215V High >2.5V Switching

controlled by

VFLK

x x Low >2.5V VGH Power-down state. Could occur

at power-up if part starts with

VGH > 2.5V

FIGURE 18. CIRCUIT TO DISCONNECT THE DC PATH OF

BOOST CONVERTER

INPUT

ENABLE

TO INDUCTOR

ISL97645A

All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.

Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality

Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without

notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and

reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result

from its use. No lice nse is gran t ed by i mpli catio n or other wise u nder an y p a tent or patent rights of Intersil or its subsidiari es.

For information regarding Intersil Corporation and its products, see www.intersil.com

FN6353.1

October 21, 2010

Layout Recommendation

The device’s performance including efficiency, output noise ,

transient response and control loop stability is dramatically

affected by the PCB layout. PCB layout is critical, especially

at high switching frequency.

There are some general guidelines for layout:

1. Place the external power components (the input

capacitors, output capacitors, boost inductor and output

diodes, etc.) in close proximity to the device. Traces to

these components should be kept as short and wide as

possible to minimize parasitic inductance and resistance.

2. Place VIN and VDD bypass capacitors close to the pins.

3. Reduce the loop area with large AC amplitudes and fast

slew rate.

4. The feedback network should sense the output voltage

directly from the point of load, and be as far away from LX

node as possible.

5. The power ground (PGND) and signal ground (SGND)

pins should be connected at only one point.

6. The exposed die plate, on the underneath of the

package, should be soldered to an equivalent area of

metal on the PCB. This contact area should have multiple

via connections to the back of the PCB as well as

connections to intermediate PCB layers, if available, to

maximize thermal dissipation away from the IC.

7. To minimize the thermal resistance of the package when

soldered to a multi-layer PCB, the amount of copper track

and ground plane area connected to the exposed die

plate should be maximized and spread out as far as

possible from the IC. The bottom and top PCB areas

especially should be maximized to allow thermal

dissipation to the surrounding air.

8. A signal ground plane, separate from the power ground

plane and connected to the power ground pins only at the

exposed die plate, should be used for ground return

connections for control circuit.

9. Minimize feedback input track lengths to avoid switching

noise pick-up.

A demo board is available to illustrate the proper layout

implementation.

ISL97645A

16 FN6353.1

October 21, 2010

ISL97645A

Package Outline Drawing

L24.4x4D

24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 2, 10/06

0 . 90 ± 0 . 1

C0 . 2 REF

TYPICAL RECOMMENDED LAND PATTERN

0 . 05 MAX.

( 24X 0 . 6 )

DETAIL "X"

( 24X 0 . 25 )

0 . 00 MIN.

( 20X 0 . 5 )

( 2 . 50 )

SIDE VIEW

( 3 . 8 TYP )

BASE PLANE

TOP VIEW

BOTTOM VIEW

712

24X 0 . 4 ± 0 . 1

4.00

PIN 1 18

INDEX AREA

4.00 2.5

0.50

20X

SEE DETAIL "X"

- 0 . 05

+ 0 . 07

24X 0 . 23

2 . 50 ± 0 . 15

PIN #1 CORNER

(C 0 . 25)

SEATING PL AN E

0.08 C

0.10 C

0.10 M C A B

(4X) 0.15

located within the zone indicated. The pin #1 identifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.15mm and 0.30mm from the terminal tip.

Dimension b applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

either a mold or mark feature.

Dimensions are in millimeters.1.

NOTES: