Advanced Power Electronics Corp. AP1250CMP 2A Sink/Source Bus Termination Regulator Features Description The AP1250CMP is a simple, cost-effective and Ideal for DDR-I, DDR-II and DDR-III VTT Applications high-speed linear regulator designed to generate Sink and Source 2A Continuous Current termination voltage in double data rate (DDR) Integrated Power MOSFETs memory system to comply with the JEDEC SSTL_2 Generates Termination Voltage for SSTL_2, SSTL and SSTL_18 or other specific interfaces such as _18, HSTL, SCSI-2 and SCSI-3 Interfaces. HSTL, High Accuracy Output Voltage at Full-Load SCSI-2 and SCSI-3 etc. devices requirements. The regulator is capable of actively Output Adjustment by Two External Resistors sinking or sourcing up to 2A while regulating an Low External Component Count output Shutdown for Suspend to RAM (STR) Functionality voltage to within 40mV. The output termination voltage cab be tightly regulated to track with High-Impedance Output 1/2VDDQ by two external voltage divider resistors or Current Limiting Protection the desired output voltage can be pro-grammed by On-Chip Thermal Protection externally forcing the REFEN pin voltage. Available in ESOP-8 (Exposed Pad) Packages The AP1250CMP also incorporates a high-speed VIN and VCNTL No Power Sequence Issue differential amplifier to provide ultra-fast response in RoHS Compliant and 100% Lead (Pb)-Free line/load transient. Other features include extremely low initial offset voltage, excellent load regulation, current limiting in bi-directions and on-chip thermal shut-down protection. The AP1250CMP are available in the ESOP-8 (Exposed Pad) surface mount packages. Pin Configuration Application Desktop PCs, Notebooks, and Workstations Graphics Card Memory Termination Set Top Boxes, Digital TVs, Printers Embedded Systems Active Termination Buses DDR-I, DDR-II and DDR-III Memory Systems Block Diagram ESOP-8 (MP) (Top View) VIN GND REFEN VOUT 1 8 NC 2 7 GND 3 6 4 5 NC VCNTL NC Pin Description Pin Name Pin function VIN Power Input GND Ground VCNTL Gate Drive Voltage REFEN Reference Voltage input and Chip Enable VOUT Output Voltage 1 200901074 Advanced Power Electronics Corp. AP1250CMP Absolute Maximum Rating (1) Parameter Symbol Value Unit Input Voltage VIN 6 V Control Voltage VCNTL 6 V Power Dissipation PD Internally Limited -- Storage Temperature Range TS -65 to 150 C Lead Temperature (Soldering, 5 sec.) TLEAD 260 C Package Thermal Resistance JC 28 C/W Operating Rating(2) Parameter Symbol Value Units Input Voltage VIN 2.5 to 1.5 3% V Control Voltage VCNTL 5.5 or 3.3 5% V Ambient Temperature TA -40 to +85 Junction Temperature TJ -40 to +125 Electrical Characteristics VIN=2.5V/1.8V/1.5V, VCNTL=3.3V, VREFEN=1.25V/0.9V/0.75V, COUT=10F (Ceramic)), TA=25C, unless otherwise specified Parameter Symbol Test Conditions Min Typ Max Units VCNTL Operation Current ICNTL IOUT=0A -- 1 2.5 mA Standby Current ISTBY VREFEN < 0.2V (Shutdown),RLOAD = 180 -- 50 90 A VOS VLOAD IOUT= 0A -20 -- +20 mV IOUT= +2A -20 -- +20 2.2 -- -- Input Output (DDR / DDR II / DDR III) Output Offset Voltage(3) Load Regulation (4) IOUT= -2A Protection Current limit ILIM Thermal Shutdown Temperature TSD TSD 3.3V VCNTL 5V 125 170 -- 3.3V VCNTL 5V -- 35 -- VIH Enable 0.6 -- -- VIL Shutdown -- -- 0.2 Thermal Shutdown Hysteresis A REFEN Shutdown Shutdown Threshold V Note 1: Exceeding the absolute maximum rating may damage the device. Note 2: VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN Note 3: VOS offset is the voltage measurement defined as VOUT subtracted from VREFEN. Note 4: Regulation is measured at constant junction temperature by using a 5ms current pulse. Devices are tested for load regulation in the load range from 0A to 2A. 2 Advanced Power Electronics Corp. AP1250CMP Application Information Input Capacitor and Layout Consideration Thermal Consideration Place the input bypass capacitor as close as AP1250CMP regulators have internal thermal limiting possible to the AP1250CMP. A low ESR capacitor circuitry designed to protect the device during larger than 470uF is recommended for the input overload conditions.For continued operation, do not capacitor. Use short and wide traces to minimize exceed maximum operation junction temperature parasitic resistance and inductance. 125. The power dissipation definition in device is: Inappropriate layout may result in large parasitic PD = (VIN - VOUT) x IOUT + VIN x IQ inductance and cause undesired oscillation between AP1250CMP and the preceding power The maximum power dissipation depends on the converter. thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature Consideration while designs the resistance of difference between junction to ambient. The voltage divider maximum power dissipation can be calculated by Make sure the sinking current capability of following formula: pull-down NMOS if the lower resistance was PD(MAX) = ( TJ(MAX) -TA ) /JA chosen so that the voltage on VREFEN is below 0.2V. In addition, the capacitor and voltage divider form Where TJ(MAX) is the maximum operation junction the lowpass filter. There are two reasons doing this temperature 125, TA is the ambient temperature design; one is for output voltage soft-start while and the JA is the junction to ambient thermal another is for noise immunity. resistance. The junction to ambient thermal resistance (JA is layout dependent) for ESOP-8 package (Exposed Pad) is 75/W on standard JEDEC 51-7 (4 layers, 2S2P) thermal test board. The maximum power dissipation at TA = 25 can be calculated by following formula: PD(MAX) = (125 - 25) / 75/W = 1.33W The thermal resistance JA of ESOP-8 (Exposed Pad) is determined by the package design and the PCB design. However, the package design has been decided. If possible, it's useful to increase thermal performance by the PCB design. The thermal resistance can be decreased by adding copper under the expose pad of ESOP-8 package. We have to consider the copper couldn't stretch infinitely and avoid the tin overflow. 3 AP1250CMP Advanced Power Electronics Corp. Application Diagram R1 = R2 = 100K, RTT = 50/33/25 COUT, min = 10F (Ceramic) + 1000F under the worst case testing condition CSS = 1F, CIN = 470F(Low ESR), CCNTL = 47F 4 ADVANCED POWER ELECTRONICS CORP. Package Outline : ESOP-8 NOTES:Thermal Pad Dimemsions 2.25 0.1 Millimeters 8 7 6 5 A C 1 2 3 4 G SYMBOLS MIN NOM MAX A 5.80 6.00 6.20 B 4.80 4.90 5.00 C 3.80 3.90 4.00 D 0 4 8 E 0.40 0.65 0.90 F 0.19 0.22 0.25 M 0.00 0.08 0.15 H 0.35 0.42 0.49 L 1.35 1.55 1.75 J H B A2 0.375 REF. K 45 G 1.27 TYP. L I J 1.All Dimension Are In Millimeters. 2.Dimension Does Not Include Mold Protrusions. Part Marking Information & Packing : ESOP-8 Part Number Package Code 1250CMP YWWSSS Date Code (YWWSSS) YLast Digit Of The Year WWWeek SSSSequence 5