PCF8545 Universal LCD driver for multiplex rates up to 1:8 Rev. 1 -- 13 November 2013 Product data sheet 1. General description The PCF8545 is a peripheral device which interfaces to almost any Liquid Crystal Display (LCD)1 with low multiplex rates. It generates the drive signals for any multiplexed LCD containing up to eight backplanes, and up to 320 elements. The PCF8545 is compatible with most microcontrollers and communicates via the two-line bidirectional I2C-bus (PCF8545A) or a three line unidirectional SPI-bus (PCF8545B). Communication overheads are minimized using a display RAM with auto-incremented addressing. For a selection of NXP LCD segment drivers, see Table 40 on page 61. 2. Features and benefits Single-chip 320 elements LCD controller and driver Wide range for digital power supply: from 1.8 V to 5.5 V LCD supply range from 2.5 V up to 5.5 V LCD and logic supplies may be separated Low power consumption Selectable backplane drive configuration: 4, 6, or 8 backplane multiplexing Selectable display bias configuration 320-bit RAM for display data storage 400 kHz I2C-bus interface (PCF8545A) 5 MHz SPI-bus interface (PCF8545B) Programmable frame frequency in the range of 60 Hz to 300 Hz in steps of 10 Hz; factory calibrated 320 segments driven allowing: up to 40 7-segment alphanumeric characters up to 20 14-segment alphanumeric characters any graphics of up to 320 elements Manufactured in silicon gate CMOS process 3. Applications Industrial and consumer products 1. The definition of the abbreviations and acronyms used in this data sheet can be found in Section 21. PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 4. Ordering information Table 1. Ordering information Type number Interface Package type Name PCF8545ATT I2C-bus TSSOP56 plastic thin shrink small outline SOT364-1 package; 56 leads; body width 6.1 mm PCF8545BTT SPI-bus TSSOP56 plastic thin shrink small outline SOT364-1 package; 56 leads; body width 6.1 mm Description Version 4.1 Ordering options Table 2. Ordering options Product type number Sales item (12NC) Orderable part number IC revision Delivery form PCF8545ATT/A 935302987118 PCF8545ATT/AJ 1 tape and reel, 13 inch PCF8545BTT/A 935302988118 PCF8545BTT/AJ 1 tape and reel, 13 inch 5. Marking Table 3. Marking codes Type number PCF8545 Product data sheet Marking code PCF8545ATT/A PCF8545ATT PCF8545BTT/A PCF8545BTT All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 2 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 6. Block diagram 9'' %3WR%3 %3WR%3 6WR6 6WR6 9/&' %$&.3/$1( 2873876 /&' 92/7$*( 6(/(&725 ',63/$<6(*0(17 2873876 ',63/$<5(*,67(5 966 /&'%,$6 *(1(5$725 ',63/$<5$0 26&&/. 26&,//$725 $1'&/2&. 6(/(&7,21 32:(521 5(6(7 5(6(7 6&/ 6'$ 35(6&$/(5 $1'7,0,1* ,1387 ),/7(56 3&)$ &200$1' '(&2'(5 :5,7('$7$ &21752/ ,&%86 &21752//(5 DDD $ Fig 1. '$7$32,17(5 $872,1&5(0(17 Block diagram of PCF8545A PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 3 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 9'' %3WR%3 %3WR%3 6WR6 6WR6 9/&' %$&.3/$1( 2873876 /&' 92/7$*( 6(/(&725 ',63/$<6(*0(17 2873876 ',63/$<5(*,67(5 966 /&'%,$6 *(1(5$725 ',63/$<5$0 26&&/. 5(6(7 6&/ 6', 26&,//$725 $1'&/2&. 6(/(&7,21 35(6&$/(5 $1'7,0,1* 32:(521 5(6(7 3&)% &200$1' '(&2'(5 :5,7('$7$ &21752/ '$7$32,17(5 $872,1&5(0(17 63,%86 &21752//(5 DDD &( Fig 2. Block diagram of PCF8545B PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 4 of 72 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors Product data sheet PCF8545 7. Pinning information 7.1 Pinning 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 9/&' 26&&/. 6 6 6 %36 %36 5(6(7 %36 6'$ %36 %366 6&/ %366 6&/ %366 $ %366 &( %366 6%3 %366 6%3 %366 6%3 %366 6%3 6 6%3 6 6%3 6 6%3 6 6%3 6 6%36 6 6%36 6 6%36 6 6%36 6 6%36 6 6%36 6 6%36 6 6%36 6 6 6 6 6 6 6 6 6 6 6 6 %36 %36 3&)$77 %36 DDD 5(6(7 3&)%77 6', DDD Top view. For mechanical details, see Figure 45. Pin configuration for TSSOP56 (PCF8545ATT) 9'' 966 Top view. For mechanical details, see Figure 45. Fig 4. Pin configuration for TSSOP56 (PCF8545BTT) PCF8545 5 of 72 (c) NXP B.V. 2013. All rights reserved. 9'' 966 %36 Fig 3. 9/&' 26&&/. 6 Universal LCD driver for multiplex rates up to 1:8 Rev. 1 -- 13 November 2013 All information provided in this document is subject to legal disclaimers. 6 6 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 7.2 Pin description Table 4. Pin description of PCF8545ATT and PCF8545BTT Input or input/output pins must always be at a defined level (VSS or VDD) unless otherwise specified. Pin Symbol Type Description 1 to 11 S9 to S19 output LCD segment 20 to 31 S20 to S31 output LCD segment 43 RESET input active LOW reset input 44 VSS supply ground supply voltage 45 VDD supply supply voltage 46 OSCCLK input/output external clock input/internal oscillator output 47 VLCD[1] supply LCD supply voltage 48 to 56 S0 to S8 output LCD segment Pin layout depending on backplane swap configuration[2] BPS = 0[3] BPS = 1 12 BP0 S32 13 BP1 S33 14 BP2 S34 15 BP3 S35 16 BP4/S43 S36 17 BP5/S42 S37 18 BP6/S41 S38 19 BP7/S40 S39 32 S32 BP7/S40 33 S33 BP6/S41 34 S34 BP5/S42 35 S35 BP4/S43 36 S36 BP3 37 S37 BP2 38 S38 BP1 39 S39 BP0 output LCD backplane/LCD segment Pin layout depending on product and bus type PCF8545ATT PCF8545BTT 40 A0 CE 41 SCL SCL 42 SDA SDI PCF8545 Product data sheet input I2C-bus slave address selection input SPI-bus chip enable - active LOW input I2C-bus serial clock input SPI-bus serial clock input/output I2C-bus serial data input SPI-bus data input [1] VLCD must be equal to or greater than VDD. [2] Effect of backplane swapping is illustrated in Figure 5 on page 9. [3] Bit BPS is explained in Section 8.1.3 on page 8. All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 6 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 8. Functional description The PCF8545 is a versatile peripheral device designed to interface any microcontroller to a wide variety of LCDs. It can directly drive any multiplexed LCD containing up to eight backplanes and up to 44 segments. 8.1 Commands of PCF8545 The PCF8545 is controlled by 9 commands, which are defined in Table 5. Any other combinations of operation code bits that are not mentioned in this document may lead to undesired operation modes of PCF8545. Table 5. Commands of PCF8545 Command name Register selection RS[1:0][1] Bits Reference 7 6 5 4 3 2 1 0 initialize 0 0 0 0 0 1 0 1 1 0 Section 8.1.1 OTP-refresh 0 0 1 1 1 1 0 0 0 0 Section 8.1.2 mode-settings 0 0 0 1 0 1 BPS INV PD E Section 8.1.3 oscillator-control 0 0 0 0 0 1 1 EFR COE OSC Section 8.1.4 set-MUX-mode 0 0 0 0 0 0 0 0 M[1:0] Section 8.1.5 set-bias-mode 0 0 0 0 0 0 0 1 B[1:0] Section 8.1.6 frame-frequency 0 0 0 0 1 FD[4:0] load-data-pointer 0 0 1 0 DP[5:0] write-RAM-data 0 1 D[7:0] [1] Section 8.1.7 Section 8.1.8 Section 8.1.9 Information about control byte and register selection see Section 9.1 on page 36. 8.1.1 Command: initialize This command generates a chip-wide reset. It has the same function as the RESET pin. Reset takes 1 ms to complete. Table 6. Initialize - initialize command bit description Bit Symbol Value Description 7 to 0 - 00010110 fixed value 8.1.2 Command: OTP-refresh During production of the device, each IC is calibrated to achieve the specified accuracy of the frame frequency. This calibration is performed on EPROM cells called One Time Programmable (OTP) cells. The device reads these cells every time the OTP-refresh command is sent. The OTP-refresh command has to be sent after a reset has been made and before the display is enabled. This command will be completed after a maximum of 30 ms and requires either the internal or external clock to run. If the internal oscillator is not used, then a clock must be supplied to the OSCCLK pin. If the OTP-refresh instruction is sent and no clock is present, then the request is stored until a clock is available. Remark: It is recommended not to enter power-down mode during the OTP refresh cycle. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 7 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 Table 7. OTP-refresh - OTP-refresh command bit description Bit Symbol Value Description 7 to 0 - 11110000 fixed value 8.1.3 Command: mode-settings Table 8. Bit Symbol Value Description 7 to 4 - 0101 fixed value 3 BPS 2 1 0 8.1.3.1 Mode-settings - mode settings command bit description backplane swapping 0[1] backplane configuration 0 1 backplane configuration 1 INV set inversion mode 0[1][2] Driving scheme A: LCD line inversion mode 1 Driving scheme B: LCD frame inversion mode PD set power mode 1 power-down mode; backplane and segment outputs are connected to VSS and the internal oscillator is switched off 0[1] power-up mode E display switch [1] Default value. [2] See Section 8.1.3.2. 0[1] display disabled; backplane and segment outputs are connected to VSS 1 display enabled Backplane swapping Backplane swapping can be configured with the BPS bit (see Table 8). It moves the location of the backplane and the associated segment outputs from one side of the PCF8545 to the other. Backplane swapping is sometimes desirable to aid with the routing of PCBs that do not use multiple layers. The BPS bit has to be set to the required value before enabling the display. Failure to do so does not damage the PCF8545 or the display, however unexpected display content may appear. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 8 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 %3 6 %3 6 %3 6 %3 6 %36 6 %36 6 %36 6 6 %3 %36 6 6 %3 6 6 6 %3 6 6 6 %3 6 6 6 %36 6 6 6 %36 6 6 6 %36 6 6 6 %36 6 6 6 6 6 6 6 6 6 6 6 6 %36 %36 DDD Fig 5. Effect of backplane swapping 8.1.3.2 Line inversion (driving scheme A) and frame inversion (driving scheme B) The DC offset of the voltage across the LCD is compensated over a certain period: line-wise in line inversion mode (driving scheme A) or frame-wise in frame inversion mode (driving scheme B). With the INV bit (see Table 8), the compensation mode can be switched. In frame inversion mode, the DC value is compensated across two frames and not within one frame. Changing the inversion mode to frame inversion reduces the power consumption; therefore it is useful when power consumption is a key point in the application. Frame inversion may not be suitable for all applications. The RMS voltage across a segment is better defined; however, since the switching frequency is reduced, there is possibility for flicker to occur. The waveforms of Figure 14 on page 24 to Figure 17 on page 27 are showing line inversion mode. Figure 18 on page 28 shows an example of frame inversion. 8.1.3.3 Power-down mode The power-down bit (PD) allows the PCF8545 to be put in a minimum power configuration. To avoid display artifacts, enter power-down only after the display has been switched off by setting bit E to logic 0. During power-down, the internal oscillator is switched off. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 9 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 Table 9. Effect of the power-down bit (PD) Effect on function Mode settings Effect of setting PD 0 1 backplane output E=1 normal function VSS segment output E=1 normal function VSS internal oscillator OSC = 0, COE = 1 on off OSCCLK pin OSC = 0, COE = 1 output of internal oscillator frequency VDD OSCCLK pin OSC = 1 input clock clock input, can be logic 0, logic 1, or left floating With the following sequence, the PCF8545 can be set to a state of minimum power consumption, called power-down mode. 67$57 'LVDEOHGLVSOD\ E\VHWWLQJELW( ORJLF ([WHUQDOFORFN FDQEH UHPRYHGQRZ (QDEOHSRZHU GRZQPRGH ZLWK3' 6723 DDD Fig 6. Recommended power-down sequence Remarks: * It is necessary to run the power-down sequence before removing the supplies. Depending on the application, care must be taken that no other signals are present at the chip input or output pins when removing the supplies (see Section 10). Otherwise it may cause unwanted display artifacts. If an uncontrolled removal of the supply happens, the PCF8545 does not get damaged. * Static voltages across the liquid crystal display can build up when the external LCD supply voltage (VLCD) is on while the IC supply voltage is off, or the other way around. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 10 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 * A clock signal must always be supplied to the device when the display is active. Removing the clock may freeze the LCD in a DC state, which is not suitable for the liquid crystal. First disable the display and afterwards remove the clock signal. 8.1.3.4 Display enable The display enable bit (E) is used to enable and disable the display. When the display is disabled, all LCD outputs go to VSS. This function is implemented to ensure that no voltage can be induced on the LCD outputs as it may lead to unwanted displays of segments. Recommended start-up sequences are found in Section 8.2.3 Remark: Display enable is not synchronized to an LCD frame boundary. Therefore using this function to flash a display for prolonged periods is not recommended due to the possible build-up of DC voltages on the display. 8.1.4 Command: oscillator-control The oscillator-control command switches between internal and external oscillator and enables or disables the pin OSCCLK. It is also defines the external frequency. Table 10. Oscillator-control - oscillator control command bit description Bit Symbol Value 7 to 3 - 00011 2 EFR 1 0 [1] Description fixed value external clock frequency applied on pin OSCCLK 0[1] 9.6 kHz 1 230 kHz COE clock output enable for pin OSCCLK 0[1] clock signal not available on pin OSCCLK; pin OSCCLK is in 3-state 1 clock signal available on pin OSCCLK OSC oscillator source 0[1] internal oscillator running 1 external oscillator used; pin OSCCLK becomes an input; used in combination with EFR to determine input frequency Default value. The bits OSC, COE, and EFR control the source and frequency of the clock used to generate the LCD signals (see Figure 7). Valid combinations are shown in Table 11. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 11 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 &2( ()5 26&&/. SLQ ,QWHUQDORVFLOODWRU N+] 3URJUDPPDEOH GLYLGHU 26& /&'IUDPHIUHTXHQF\ VHOHFWLRQT /&'ZDYHIRUP JHQHUDWRU N+] DDD (1) Can only be used with the internal oscillator (OSC = 0). (2) Can only be used with an external oscillator (OSC = 1). (3) Nominal value for divide factor q is 24; source clock is 230 kHz (see Section 8.1.7). Fig 7. Oscillator selection Table 11. OSC COE EFR OSCCLK pin Clock source 0 0 not used inactive; may be left floating internal oscillator used 0 1 not used output of internal oscillator frequency (prescaler) internal oscillator used 1 not used 0 9.6 kHz input OSCCLK pin 1 not used 1 230 kHz input OSCCLK pin Table 12. 8.1.4.1 Valid combinations of bits OSC, EFR, and COE Typical use of bits OSC, EFR, and COE Usage OSC COE EFR LCD with internal oscillator 0 0 not used LCD with external oscillator (230 kHz) 1 not used 1 LCD with external oscillator (9.6 kHz) 1 not used 0 Oscillator The system is designed to operate from a 9.6 kHz or a 230 kHz clock. This clock can be sourced internally or externally. The internal logic and LCD drive signals of the PCF8545 are timed either by the internal oscillator or from the clock externally supplied. Internal clock: When the internal oscillator is used, all LCD signals are generated from it. The oscillator runs at nominal 230 kHz. The relationship between this frequency and the LCD frame frequency is detailed in Section 8.1.7. Control over the internal oscillator is made with the OSC bit (see Section 8.1.4). It is possible to make the internal oscillator signal available on pin OSCCLK by using the oscillator-control command (see Table 10) and configuring the clock output enable (COE) bit. If not required, the pin OSCCLK should be left open or connected to VSS. At power-on the signal at pin OSCCLK is disabled and pin OSCCLK is in 3-state. Clock output is only valid when using the internal oscillator. The signal appears on the OSCCLK pin. An intermediate clock frequency is available at the OSCCLK pin. The duty cycle of this clock varies with the chosen divide ratio. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 12 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 Table 13. OSCCLK pin state depending on configuration PD OSC COE EFR OSCCLK pin[1] power-down n.a. off n.a. 3-state[2] power-down n.a. on n.a. VDD power-up internal oscillator off n.a. 3-state on n.a. 9.6 kHz output[3] n.a. 9.6 kHz 9.6 kHz input 230 kHz 230 kHz input external oscillator [1] When RESET is active, the pin OSCCLK is in 3-state. [2] In this state, an external clock may be applied, but it is not a requirement. [3] 9.6 kHz is the nominal frequency with q = 24, see Table 14. External clock: In applications where an external clock must be applied to the PCF8545, bit OSC (see Table 10) has to be set logic 1. In this case pin OSCCLK becomes an input. The OSCCLK signal must switch between the VSS and the VDD voltage supplied to the chip. The EFR bit determines the external clock frequency (230 kHz or 9.6 kHz). The clock frequency (fclk(ext)) in turn determines the LCD frame frequency, see Table 14. Remark: If an external clock is used, then this clock signal must always be supplied to the device when the display is on. Removing the clock may freeze the LCD in a DC state which damages the LCD material. 8.1.4.2 Timing and frame frequency The timing of the PCF8545 organizes the internal data flow of the device. This includes the transfer of display data from the display RAM to the display segment outputs. The timing also generates the LCD frame frequency which it derives as an integer division of the clock frequency (see Table 14). The frame frequency is a fixed division of the internal clock or of the frequency applied to pin OSCCLK when an external clock is used. Table 14. LCD frame frequencies Frame frequency Typical external Nominal frame frequency (Hz) frequency (Hz) EFR bit Value of q[1] f clk ext 9600 f fr LCD = ----------------48 200 0 - f clk ext 230000 f fr LCD = ----------------48 q 200 1 24 [1] Other values of the frame frequency prescaler see Table 18. When the internal clock is used, or an external clock with EFR = 1, the LCD frame frequency can be programmed by software in steps of approximately 10 Hz in the range of 60 Hz to 300 Hz (see Table 18). Furthermore the internal oscillator is factory calibrated, see Table 34 on page 50. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 13 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 8.1.5 Command: set-MUX-mode The multiplex drive mode is configured with the bits described in Table 15. Table 15. Set-MUX-mode - set multiplex drive mode command bit description Bit Symbol Value Description 7 to 2 - 000000 fixed value M[1:0] 00[1], 1:8 multiplex drive mode; eight backplanes 1 to 0 [1] 01 10 1:6 multiplex drive mode; 6 backplanes 11 1:4 multiplex drive mode; 4 backplanes Default value. 8.1.6 Command: set-bias-mode The set-bias-mode command allows setting the bias level. Table 16. Set-bias-mode - set bias mode command bit description Bit Symbol Value 7 to 2 - 000001 fixed value B[1:0] 00[1]. 1 4 bias 11 1 3 bias 10 1 2 bias 1 to 0 [1] 01 Description Default value. 8.1.7 Command: frame-frequency With the frame-frequency command, the frame frequency for the display can be configured. The clock frequency determines the frame frequency. Table 17. Frame-frequency - frame frequency and output clock frequency command bit description Bit Symbol Value Description 7 to 5 - 001 fixed value 4 to 0 FD[4:0] see Table 18 frequency prescaler When using an external clock it can be either a 230 kHz or a 9.6 kHz clock signal. The EFR bit (see Table 10) has to be set according to the external clock frequency. When EFR is set to 9.6 kHz, then the LCD frame frequency is calculated with Equation 1: f clk ext f fr LCD = ----------------48 (1) When EFR is set to 230 kHz, then the LCD frame frequency is calculated with Equation 2: f clk ext f fr LCD = ----------------48 q (2) where q is the frequency divide factor (see Table 18). Remark: fclk(ext) is the external input clock frequency to pin OSCCLK. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 14 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 When the internal oscillator is used, the intermediate frequency may be output on the OSCCLK pin. Its frequency is given in Table 18. Table 18. Frame frequency prescaler values for 230 kHz clock operation FD[4:0] Nominal LCD frame frequency (Hz)[1] Divide factor, q Intermediate clock frequency (Hz) 00000 59.9 80 2875 00001 70.5 68 3382 00010 79.9 60 3833 00011 90.4 53 4340 00100 99.8 48 4792 00101 108.9 44 5227 00110 119.8 40 5750 00111 129.5 37 6216 01000 140.9 34 6765 01001 149.7 32 7188 01010 159.7 30 7667 01011 171.1 28 8214 01100 177.5 27 8519 01101 191.7 25 9200 01110[2] 199.7 24 9583 01111 208.3 23 10000 10000 217.8 22 10455 10001 228.3 21 10952 10010 239.6 20 11500 10011 252.2 19 12105 10100 266.2 18 12778 10101 281.9 17 13529 10110 299.5 16 14375 10111 to 11111 not used [1] Nominal frame frequency calculated for the default clock frequency of 230 kHz. [2] Default value. 8.1.8 Command: load-data-pointer The load-data-pointer command defines the start address of the display RAM. The data pointer is auto incremented after each RAM write. The size of the display RAM is dependent on the current multiplex drive mode setting, see Table 19. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 15 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 Table 19. Load-data-pointer - load data pointer command bit description Bit Symbol Value Description 7 to 6 - 10 fixed value 000000[1] to 100111 6-bit binary value of 0 to 39 000000[1] to 101001 6-bit binary value of 0 to 41 000000[1] to 101011 6-bit binary value of 0 to 43 Multiplex drive mode 1:8 5 to 0 DP[5:0] Multiplex drive mode 1:6 5 to 0 DP[5:0] Multiplex drive mode 1:4 5 to 0 [1] DP[5:0] Default value. Remark: Data pointer values outside of the valid range are ignored and no RAM content is transferred until a valid data pointer value is set. Filling of the display RAM is described in Section 8.9. 8.1.9 Command: write-RAM-data This command initiates the transfer of data to the display RAM. Data is written into the address defined by the load-data-pointer command. RAM filling is described in Section 8.9. Table 20. Write-RAM-data - write RAM data command bit description[1] Bit Symbol Value Description 7 to 0 D[7:0] 00000000 to 11111111 writing data byte-wise to RAM [1] For this command to be effective bit RS[1:0] of the control byte has to be set logic 01, see Table 25 on page 36. 8.2 Start-up and shut-down 8.2.1 Reset and Power-On Reset (POR) After a reset and at power-on the PCF8545 resets to starting conditions as follows: 1. The display is disabled. 2. All backplane outputs are set to VSS. 3. All segment outputs are set to VSS. 4. Selected drive mode is: 1:8 with 14 bias. 5. The data pointers are cleared (set logic 0). 6. RAM data is not initialized. Its content can be considered to be random. 7. The internal oscillator is running; no clock signal is available on pin OSCCLK; pin OSCCLK is in 3-state. The reset state is as shown in Table 21. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 16 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 Table 21. Reset state Reset state of configurable bits shown in the command table format for clarity. Associated command Bits 7 6 5 4 3 2 1 0 mode-settings - - - - BPS = 0 INV = 0 PD = 0 E=0 oscillator-control - - - - - EFR = 0 COE = 0 OSC = 0 set-MUX-mode - - - - - - M[1:0] = 00 - - B[1:0] = 00 set-bias-mode - - - - frame-frequency - - - FD[4:0] = 01110 load-data-pointer - - DP[5:0] = 000000 The first command sent to the device after the power-on event must be the initialize command (see Section 8.1.1). After Power-On Reset (POR) and before enabling the display, the RAM content should be brought to a defined state by writing meaningful content (for example, a graphic) otherwise unwanted display artifacts may appear on the display. 8.2.2 RESET pin function The RESET pin of the PCF8545 sets all the registers to their default state. The reset state is given in Table 21. The RAM contents remains unchanged. After the reset signal is removed, the PCF8545 will behave in the same manner as after Power-On Reset (POR). See Section 8.2.1 for details. 8.2.3 Recommended start-up sequences This chapter describes how to proceed with the initialization of the chip in different application modes. In general, the sequence should always be: 1. Power-on the device, 2. set the display and functional modes, 3. fill the display memory and then 4. turn on the display. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 17 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 67$57 3RZHURQ9'' DQG9/&' WRJHWKHU 7RJJOH5(6(7 SLQ :DLWPLQLPXP PV 6HQG 273UHIUHVK 6HW PRGHVHWWLQJV%36DQG,19 PXOWLSOH[GULYHUPRGH ELDVPRGH /&'IUDPHIUHTXHQF\ 6HQGGLVSOD\ FRQWHQW (QDEOH WKHGLVSOD\ 6723 DDD (1) Alternatively, it is possible to send the initialize command. Fig 8. PCF8545 Product data sheet Recommended start-up sequence when using the internal oscillator All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 18 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 67$57 3RZHURQ9'' DQG9/&' WRJHWKHU 7RJJOH5(6(7 SLQ :DLWPLQLPXP PV ([WHUQDOFORFN FDQEHDSSOLHG QRZ 6HQG 273UHIUHVK 6HW 0RGHVHWWLQJV%36DQG,19 6HOHFWH[WHUQDOFORFN 0XOWLSOH[GULYHUPRGH %LDVPRGH /&'IUDPHIUHTXHQF\ 6HQGGLVSOD\ FRQWHQW ([WHUQDOFORFN PXVWEH DSSOLHGE\QRZ (QDEOH WKHGLVSOD\ 6723 DDD (1) Alternatively, it is possible to send the initialize command. Fig 9. PCF8545 Product data sheet Recommended start-up sequence when using an external clock signal All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 19 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 8.3 Possible display configurations The PCF8545 is a versatile peripheral device designed to interface between any microcontroller to a wide variety of LCD segment or dot matrix displays (see Figure 10). It can drive multiplexed LCD with 4, 6, or 8 backplanes and up to 44 segments. The display configurations possible with the PCF8545 depend on the required number of active backplane outputs. A selection of possible display configurations is given in Table 22. GRWPDWUL[ VHJPHQWZLWKGRW VHJPHQWZLWKGRWDQGDFFHQW DDD Fig 10. Example of displays suitable for PCF8545 Table 22. Selection of display configurations Number of Backplanes Digits/Characters Segments Icons 7 segment[1] 14 segment[2] Dot matrix/ Elements 8 40 320 40 20 320 6 42 252 31 15 252 4 44 176 22 11 176 [1] 7 segment display has 8 elements including the decimal point. [2] 14 segment display has 16 elements including decimal point and accent dot. All of the display configurations in Table 22 can be implemented in the typical systems shown in Figure 11 and Figure 12. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 20 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 9'' 9/&' 5 WU &E 6'$ +267 0,&52 &21752//(5 9'' 6&/ 9/&' 3&)$ $ WRVHJPHQW GULYHV WREDFNSODQHV /&'3$1(/ XSWR HOHPHQWV 966 DDD 966 Fig 11. Typical system configuration for the I2C-bus 9'' 9/&' 6', +267 0,&52 &21752//(5 6&/ 9'' 9/&' 3&)% &( WRVHJPHQW GULYHV WREDFNSODQHV /&'3$1(/ XSWR HOHPHQWV 966 DDD 966 Fig 12. Typical system configuration for the SPI-bus The host microcontroller maintains the two line I2C-bus or a three line SPI-bus communication channel with the PCF8545. The appropriate biasing voltages for the multiplexed LCD waveforms are generated internally. The only other connections required to complete the system are the power supplies (VDD, VSS, VLCD) and the LCD panel selected for the application. The minimum recommended values for external capacitors on VDD and VLCD are 100 nF respectively. Decoupling of VLCD helps to reduce display artifacts. The decoupling capacitors should be placed close to the IC with short connections to the respective supply pin and VSS. 8.4 LCD voltage selector The LCD voltage selector coordinates the multiplexing of the LCD in accordance with the selected LCD drive configuration. The operation of the voltage selector is controlled by the set-bias-mode command (see Table 16) and the set-MUX-mode command (see Table 15). Fractional LCD biasing voltages are obtained from an internal voltage divider. The biasing configurations that apply to the preferred modes of operation, together with the biasing characteristics as functions of VLCD and the resulting discrimination ratios (D), are given in Table 23. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 21 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 Discrimination is a term which is defined as the ratio of the on and off RMS voltage across a segment. It can be thought of as a measurement of contrast. Table 23. Preferred LCD drive modes: summary of characteristics LCD bias configuration V off RMS ----------------------V LCD V on RMS ---------------------V LCD VLCD[2] V on RMS D = ----------------------- [1] V off RMS 3 1 2 0.433 0.661 1.527 2.309Voff(RMS) 4 1 3 0.333 0.577 1.732 3.0Voff(RMS) 5 1 4 0.331 0.545 1.646 3.024Voff(RMS) 3 1 2 0.456 0.612 1.341 2.191Voff(RMS) LCD multiplex drive mode Number of: Backplanes Levels 1:4 [3] 4 1:4 4 1:4 [3] 1:6 [3] 4 6 1:6 6 4 1 3 0.333 0.509 1.527 3.0Voff(RMS) 1:6 6 5 1 4 0.306 0.467 1.527 3.266Voff(RMS) 1:8 [3] 8 3 1 2 0.467 0.586 1.254 2.138Voff(RMS) 4 1 3 0.333 0.471 1.414 3.0Voff(RMS) 5 1 4 0.293 0.424 1.447 3.411Voff(RMS) 1:8 [3] 1:8 8 8 [1] Determined from Equation 5. [2] Determined from Equation 4. [3] In these examples, the discrimination factor and hence the contrast ratios are smaller. The advantage of these LCD drive modes is a reduction of the LCD voltage VLCD. A practical value for VLCD is determined by equating Voff(RMS) with a defined LCD threshold voltage (Vth(off)), typically when the LCD exhibits approximately 10 % contrast. 1 Bias is calculated by ------------- , where the values for a are 1+a a = 1 for 12 bias a = 2 for 13 bias a = 3 for 14 bias The RMS on-state voltage (Von(RMS)) for the LCD is calculated with Equation 3 V on RMS = V LCD a 2 + 2a + n -----------------------------2 n 1 + a (3) where VLCD is the resultant voltage at the LCD segment and where the values for n are n = 4 for 1:4 multiplex drive n = 6 for 1:6 multiplex drive n = 8 for 1:8 multiplex drive The RMS off-state voltage (Voff(RMS)) for the LCD is calculated with Equation 4: V off RMS = V LCD a 2 - 2a + n -----------------------------2 n 1 + a (4) Discrimination is the ratio of Von(RMS) to Voff(RMS) and is determined from Equation 5: PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 22 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 V on RMS D = ----------------------- = V off RMS 2 a + 2a + n --------------------------2 a - 2a + n (5) VLCD is sometimes referred to as the LCD operating voltage. 8.4.1 Electro-optical performance Suitable values for Von(RMS) and Voff(RMS) are dependent on the LCD liquid used. The RMS voltage, at which a pixel gets switched on or off, determine the transmissibility of the pixel. For any given liquid, there are two threshold values defined. One point is at 10 % relative transmission (at Vth(off)) and the other at 90 % relative transmission (at Vth(on)), see Figure 13. For a good contrast performance, the following rules should be followed: V on RMS V th on (6) V off RMS V th off (7) Von(RMS) and Voff(RMS) are properties of the display driver and are affected by the selection of a, n (see Equation 3 to Equation 5) and the VLCD voltage. Vth(off) and Vth(on) are properties of the LCD liquid and can be provided by the module manufacturer. Vth(off) is sometimes named Vth. Vth(on) is sometimes named saturation voltage Vsat. It is important to match the module properties to those of the driver in order to achieve optimum performance. 5HODWLYH7UDQVPLVVLRQ 9WK RII 2)) 6(*0(17 9WK RQ *5(< 6(*0(17 9506>9@ 21 6(*0(17 DDD Fig 13. Electro-optical characteristic: relative transmission curve of the liquid PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 23 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 8.5 LCD drive mode waveforms 8.5.1 1:4 Multiplex drive mode When four backplanes are provided in the LCD, the 1:4 multiplex drive mode applies, as shown in Figure 14. This drawing is also showing the case of line inversion (see Section 8.1.3.2). 7IU %3 9/&' 9/&' 9/&' 966 %3 9/&' 9/&' 9/&' 966 %3 9/&' 9/&' 9/&' 966 %3 9/&' 9/&' 9/&' 966 6Q 9/&' 9/&' 9/&' 966 6Q 9/&' 9/&' 9/&' 966 6Q 9/&' 9/&' 9/&' 966 6Q 9/&' 9/&' 9/&' 966 VWDWH 9/&' 9/&' 9/&' 9 9/&' 9/&' 9/&' VWDWH 9/&' 9/&' 9/&' 9 9/&' 9/&' 9/&' /&'VHJPHQWV VWDWH VWDWH D :DYHIRUPVDWGULYHU E 5HVXOWDQWZDYHIRUPV DW/&'VHJPHQW DDD Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = VSn(t) VBP1(t). Von(RMS)(t) = 0.577VLCD. Voff(RMS)(t) = 0.333VLCD. Fig 14. Waveforms for the 1:4 multiplex drive mode with 13 bias and line inversion PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 24 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 8.5.2 1:6 Multiplex drive mode When six backplanes are provided in the LCD, the 1:6 multiplex drive mode applies. The PCF8545 allows use of 13 bias or 14 bias in this mode as shown in Figure 15 and Figure 16. These waveforms are drawn for the case of line inversion (see Section 8.1.3.2). 7IU %3 9/&' 9/&' 9/&' 966 %3 9/&' 9/&' 9/&' 966 %3 9/&' 9/&' 9/&' 966 %3 9/&' 9/&' 9/&' 966 %3 9/&' 9/&' 9/&' 966 %3 9/&' 9/&' 9/&' 966 6Q 9/&' 9/&' 9/&' 966 6Q 9/&' 9/&' 9/&' 966 /&'VHJPHQWV VWDWH VWDWH D :DYHIRUPVDWGULYHU VWDWH VWDWH 9/&' 9/&' 9/&' 966 9/&' 9/&' 9/&' 9/&' 9/&' 9/&' 966 9/&' 9/&' 9/&' E 5HVXOWDQWZDYHIRUPVDW/&'VHJPHQW DDO Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = VSn +1 (t) VBP0(t). Von(RMS)(t) = 0.509VLCD. Voff(RMS)(t) = 0.333VLCD. Fig 15. Waveforms for 1:6 multiplex drive mode with bias 13 and line inversion PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 25 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 7IU /&'VHJPHQWV 9/&' 9/&' VWDWH %3 VWDWH 9/&' 966 9/&' 9/&' %3 9/&' 966 9/&' 9/&' %3 9/&' 966 9/&' 9/&' %3 9/&' 966 9/&' 9/&' %3 9/&' 966 9/&' 9/&' %3 9/&' 966 9/&' 6Q 9/&' 966 9/&' 6Q 9/&' 966 D :DYHIRUPVDWGULYHU 9/&' 9/&' VWDWH 9/&' 966 9/&' 9/&' 9/&' 9/&' 9/&' 9/&' 9/&' 966 VWDWH 9/&' 9/&' 9/&' 9/&' E 5HVXOWDQWZDYHIRUPVDW/&'VHJPHQW DDO Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = VSn + 1(t) VBP0(t). Von(RMS)(t) = 0.467VLCD. Voff(RMS)(t) = 0.306VLCD. Fig 16. Waveforms for 1:6 multiplex drive mode with bias 14 and line inversion PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 26 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 8.5.3 1:8 Multiplex drive mode 9/&' 9/&' 7IU /&'VHJPHQWV VWDWH %3 VWDWH 9/&' 966 9/&' 9/&' %3 9/&' 966 9/&' 9/&' %3 9/&' 966 9/&' 9/&' %3 9/&' 966 9/&' 9/&' %3 /&' 966 9/&' 9/&' %3 9/&' 966 9/&' 9/&' %3 9/&' 966 9/&' 9/&' %3 9/&' 966 9/&' 9/&' 6Q 966 9/&' 6Q 9/&' 966 D :DYHIRUPVDWGULYHU 9/&' 9/&' VWDWH 9/&' 966 9/&' 9/&' 9/&' VWDWH 9/&' 9/&' 9/&' 9/&' 966 9/&' 9/&' 9/&' 9/&' E 5HVXOWDQWZDYHIRUPVDW/&'VHJPHQW DDO Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = VSn + 1(t) VBP0(t). Von(RMS)(t) = 0.424VLCD. Voff(RMS)(t) = 0.293VLCD. Fig 17. Waveforms for 1:8 multiplex drive mode with bias 14 and line inversion PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 27 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 9/&' 9/&' %3 7IU IUDPHQ 7IU IUDPHQ /&'VHJPHQWV VWDWH VWDWH 9/&' 966 9/&' 9/&' %3 9/&' 966 9/&' 9/&' %3 9/&' 966 9/&' 9/&' %3 9/&' 966 9/&' 9/&' %3 9/&' 966 9/&' 9/&' %3 9/&' 966 9/&' 9/&' %3 9/&' 966 9/&' 9/&' %3 9/&' 966 9/&' 6Q 9/&' 966 9/&' 6Q 9/&' 966 D :DYHIRUPVDWGULYHU VWDWH 9/&' 9/&' 9/&' 9/&' 966 9/&' 9/&' 9/&' 9/&' VWDWH 9/&' 9/&' 9/&' 9/&' 966 9/&' 9/&' 9/&' 9/&' E 5HVXOWDQWZDYHIRUPVDW/&'VHJPHQW DDP Vstate1(t) = VSn(t) VBP0(t). Vstate2(t) = VSn + 1(t) VBP0(t). Von(RMS)(t) = 0.424VLCD. Voff(RMS)(t) = 0.293VLCD. Fig 18. Waveforms for 1:8 multiplex drive mode with bias 14 and frame inversion PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 28 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 8.6 Display register The display register holds the display data while the corresponding multiplex signals are generated. 8.7 Backplane outputs The LCD drive section includes eight backplane outputs: BP0 to BP7. The backplane output signals are generated based on the selected LCD multiplex drive mode. * In 1:8 multiplex drive mode: BP0 to BP7 must be connected directly to the LCD. * In 1:6 multiplex drive mode: BP0 to BP5 must be connected directly to the LCD. * In 1:4 multiplex drive mode: BP0 to BP3 must be connected directly to the LCD. 8.8 Segment outputs The LCD drive section includes up to 44 segment outputs (S0 to S43) which must be connected directly to the LCD. The segment output signals are generated based on the multiplexed backplane signals and with data resident in the display register. When less segment outputs are required, the unused segment outputs must be left open-circuit. The number of available segments depends on the multiplex drive mode selected. Table 24. Backplane and active segment combinations Multiplex drive mode Active BPs Active segments 1:8 BP0 to BP7 S0 to S39 1:6 BP0 to BP5 S0 to S41 1:4 BP0 to BP3 S0 to S43 8.9 Display RAM The display RAM stores the LCD data. Depending on the multiplex drive mode, the arrangement of the RAM is changed. * multiplex drive 1:8: RAM is 40 8 bit * multiplex drive 1:6: RAM is 42 6 bit * multiplex drive 1:4: RAM is 44 4 bit PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 29 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 'LVSOD\5$0DGGUHVVHV FROXPQV VHJPHQWRXWSXWV 6 0XOWLSOH[GULYHPRGH 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 %3 %3 %3 %3 %3 'LVSOD\5$0ELWV URZV EDFNSODQHRXWSXWV %3 %3 %3 %3 0XOWLSOH[GULYHPRGH %3 %3 %3 %3 %3 %3 0XOWLSOH[GULYHPRGH %3 %3 %3 %3 DDD The display RAM bitmap shows the direct relationship between the display RAM column and the segment outputs and between the bits in a RAM row and the backplane outputs. Fig 19. Display RAM bitmap Logic 1 in the RAM bit map indicates the on-state (Von(RMS)) of the corresponding LCD element; similarly, logic 0 indicates the off-state (Voff(RMS)). For more information on Von(RMS) and Voff(RMS), see Section 8.4. There is a one-to-one correspondence between * the bits in the RAM bitmap and the LCD elements, * the RAM columns and the segment outputs, * the RAM rows and the backplane outputs. The display RAM bit map, Figure 19, shows row 0 to row 7 and column 0 to column 43. Row 0 to row 7 correspond with the backplane outputs BP0 to BP7. Column 0 to column 43 correspond with the segment outputs S0 to S43. In multiplexed LCD applications, the data of each row of the display RAM is time-multiplexed with the corresponding backplane (row 0 with BP0, row 1 with BP1, and so on). PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 30 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 When display data is transmitted to the PCF8545, the display bytes received are stored in the display RAM in accordance with the selected LCD multiplex drive mode. The data is stored as it arrives and depending on the current multiplex drive mode, data is stored in quadruples, sextuples or bytes. 8.9.1 Data pointer The addressing mechanism for the display RAM is realized using the data pointer. This allows the loading of an individual display data byte, or a series of display data bytes, into any location of the display RAM. The sequence commences with the initialization of the data pointer by the load-data-pointer command (see Table 19). Following this command, an arriving data byte is stored starting at the display RAM address indicated by the data pointer. The data pointer is automatically incremented in accordance with the chosen LCD multiplex drive mode configuration. That is, after each byte is stored, the contents of the data pointer are incremented * by two (1:4 multiplex drive mode), * by one or two (1:6 multiplex drive mode), * by one (1:8 multiplex drive mode). Multiplex drive 1:6 is a special case and is described later on. When the address counter reaches the end of the RAM, it stops incrementing after the last byte is transmitted. Redundant bits of the last byte and subsequent bytes transmitted are discarded until the pointer is reset. To send new RAM data, the data pointer must be reset. If an I2C-bus or SPI-bus data access is terminated early, then the state of the data pointer is unknown. The data pointer must then be rewritten before further RAM accesses. 8.9.2 RAM filling in 1:4 multiplex drive mode In the 1:4 multiplex drive mode the RAM is organized in four rows and 44 columns. The eight transmitted data bits are placed in two successive display RAM columns of four rows (see Figure 20). In order to fill the whole four RAM rows, 22 bytes need to be sent to the PCF8545. After the last byte sent, the data pointer must be reset before the next RAM content update. Additional data bytes sent and any data bits that spill over the RAM are discarded. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 31 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 &ROXPQV 'LVSOD\5$0DGGUHVVHV FROXPQV VHJPHQWRXWSXWV 6 E E E E 5RZV E E 'LVSOD\5$0 ELWV URZV EDFNSODQHRXWSXWV %3 E E E E E E E E E E 06% /6% 7UDQVPLWWHGGDWDE\WH DDD Fig 20. Display RAM filling order in 1:4 multiplex drive mode Depending on the start address of the data pointer, there is the possibility for a boundary condition. This occurs when more data bits are sent than fit into the remaining RAM. The additional data bits are discarded. See Figure 21. &ROXPQV 'LVSOD\5$0DGGUHVVHV FROXPQV VHJPHQWRXWSXWV 6 5RZV 'LVSOD\5$0 ELWV URZV EDFNSODQHRXWSXWV %3 E E E E 'LVFDUGHG E E E E E E E E 06% /6% 7UDQVPLWWHGGDWDE\WH DDD Fig 21. Boundary condition in 1:4 multiplex drive mode 8.9.3 RAM filling in 1:6 multiplex drive mode In the 1:6 multiplex drive mode the RAM is organized in six rows and 42 columns. The eight transmitted data bits are placed in such a way, that a column is filled up (see Figure 22). PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 32 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 &ROXPQV 'LVSOD\5$0DGGUHVVHV FROXPQV VHJPHQWRXWSXWV 6 D D E F 5RZV 'LVSOD\5$0 ELWV URZV EDFNSODQHRXWSXWV %3 D D E F D E E F D E E F D E F F D E F F 06% /6% D D D D D D D D E E E E E E E E F F F F F F F F 7UDQVPLWWHGGDWDE\WHV DDD Fig 22. Display RAM filling order in 1:6 multiplex drive mode The remaining bits are wrapped over into the next column. In order to fill the whole RAM, 31 and a half bytes need to be sent to the PCF8545. After the last byte sent, the data pointer must be reset before the next RAM content update. Additional data bytes sent and any data bits that spill over the RAM are discarded. Depending on the start address of the data pointer, there are three possible boundary conditions. See Figure 23. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 33 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 &ROXPQV 'LVSOD\5$0DGGUHVVHV FROXPQV VHJPHQWRXWSXWV 6 E E E E E E 'LVFDUGHG 5RZV 'LVSOD\5$0ELWV URZV EDFNSODQHRXWSXWV %3 E E E E E E E E 06% /6% 7UDQVPLWWHGGDWDE\WH E E E E 'LVFDUGHG E E E E E E E E 06% /6% 7UDQVPLWWHGGDWDE\WH E E 'LVFDUGHG E E E E E E E E 06% /6% 7UDQVPLWWHGGDWDE\WH DDD Fig 23. Boundary condition in 1:6 multiplex drive mode 8.9.4 RAM filling in 1:8 multiplex drive mode In the 1:8 multiplex drive mode the RAM is organized in eight rows and 40 columns. The eight transmitted data bits are placed into eight rows of one display RAM column (see Figure 24). In order to fill the whole RAM, 40 bytes need to be sent to the PCF8545. After the last byte sent, the data pointer must be reset before the next RAM content update. Additional data bytes sent are discarded. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 34 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 &ROXPQV 'LVSOD\5$0FROXPQVVHJPHQWRXWSXWV 6 E E E 5RZV 'LVSOD\5$0URZV EDFNSODQHRXWSXWV %3 E E E E E E E E E E E E E /6% 06% 7UDQVPLWWHGGDWDE\WH DDD Fig 24. Display RAM filling order in 1:8 multiplex drive mode There are no boundary conditions in 1:8 multiplex drive mode. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 35 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 9. Bus interfaces 9.1 Control byte and register selection After initiating the communication over the bus and sending the slave address (I2C-bus, see Section 9.2) or subaddress (SPI-bus, see Section 9.3), a control byte follows. The purpose of this byte is to indicate both, the content for the following data bytes (RAM, or command) and to indicate that more control bytes will follow. Typical sequences could be: * Slave address/subaddress - control byte - command byte - command byte - command byte - end * Slave address/subaddress - control byte - RAM byte - RAM byte - RAM byte - end * Slave address/subaddress - control byte - command byte - control byte - RAM byte end In this way, it is possible to send a mixture of RAM and command data in one access or alternatively, to send just one type of data in one access. Table 25. Control byte description Bit Symbol 7 CO 6 to 5 4 to 0 Value Description continue bit 0 last control byte 1 control bytes continue RS[1:0] register selection - 00 command register 01 RAM data 10, 11 unused - 06% &2 unused 56>@ /6% QRWUHOHYDQW DDD Fig 25. Control byte format PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 36 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 9.2 I2C-bus interface The I2C-bus is for bidirectional, two-line communication between different ICs or modules. The two lines are a Serial DAta line (SDA) and a Serial CLock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy. 9.2.1 Bit transfer One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time is interpreted as a control signal (see Figure 26). 6'$ 6&/ GDWDOLQH VWDEOH GDWDYDOLG FKDQJH RIGDWD DOORZHG PED Fig 26. Bit transfer 9.2.2 START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW change of the data line, while the clock is HIGH, is defined as the START condition (S). A LOW-to-HIGH change of the data line, while the clock is HIGH, is defined as the STOP condition (P). The START and STOP conditions are shown in Figure 27. 6'$ 6'$ 6&/ 6&/ 6 3 67$57FRQGLWLRQ 6723FRQGLWLRQ PEF Fig 27. Definition of START and STOP conditions 9.2.3 System configuration A device generating a message is a transmitter, a device receiving a message is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves. The system configuration is shown in Figure 28. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 37 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 0$67(5 75$160,77(5 5(&(,9(5 6/$9( 75$160,77(5 5(&(,9(5 6/$9( 5(&(,9(5 0$67(5 75$160,77(5 5(&(,9(5 0$67(5 75$160,77(5 6'$ 6&/ PJD Fig 28. System configuration 9.2.4 Acknowledge The number of data bytes transferred between the START and STOP conditions from transmitter to receiver is unlimited. Each byte of 8 bits is followed by an acknowledge cycle. * A slave receiver which is addressed must generate an acknowledge after the reception of each byte. * Also a master receiver must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. * The device that acknowledges must pull-down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse (set-up and hold times must be considered). * A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition. Acknowledgement on the I2C-bus is shown in Figure 29. GDWDRXWSXW E\WUDQVPLWWHU QRWDFNQRZOHGJH GDWDRXWSXW E\UHFHLYHU DFNQRZOHGJH 6&/IURP PDVWHU 6 67$57 FRQGLWLRQ FORFNSXOVHIRU DFNQRZOHGJHPHQW PEF Fig 29. Acknowledgement on the I2C-bus 9.2.5 I2C-bus controller The PCF8545 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or transmit data to an I2C-bus master receiver. Device selection depends on the I2C-bus slave address. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 38 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 9.2.6 Input filters To enhance noise immunity in electrically adverse environments, RC low-pass filters are provided on the SDA and SCL lines. 9.2.7 I2C-bus slave address Device selection depends on the I2C-bus slave address. Two different I2C-bus slave addresses can be used to address the PCF8545 (see Table 26). Table 26. I2C slave address byte Slave address Bit 7 6 5 4 3 2 1 0 1 1 1 0 0 A0 R/W MSB 0 LSB The least significant bit of the slave address byte is bit R/W (see Table 27). Table 27. R/W-bit description R/W Description 0 write data 1 read data Bit 1 of the slave address is defined by connecting the input A0 to either VSS (logic 0) or VDD (logic 1). Therefore, two instances of PCF8545 can be distinguished on the same I2C-bus. 9.2.8 I2C-bus protocol The I2C-bus protocol is shown in Figure 30. The sequence is initiated with a START condition (S) from the I2C-bus master which is followed by one of the two PCF8545 slave addresses available. All PCF8545 with the corresponding A0 level acknowledge in parallel to the slave address. But any PCF8545 with the alternative A0 level ignore the whole I2C-bus transfer. After acknowledgement, a control byte follows (see Section 9.1 on page 36). The display bytes are stored in the display RAM at the address specified by the RAM data pointer. The acknowledgement after each byte is made only by the addressed PCF8545. After the last data byte, the I2C-bus master issues a STOP condition (P). Alternatively a START may be issued to RESTART an I2C-bus access. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 39 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 5: VODYHDGGUHVV FRQWUROE\WH 5 5 $ & 6 6 6 $ 2 5$0FRPPDQGE\WH / 0 6 3 $ 6 % % (;$03/(6 D WUDQVPLWWZRE\WHRI5$0GDWD 6 $ $ 5$0'$7$ $ 5$0'$7$ $ $ &200$1' $ $ &200$1' $ 3 $ $ 5$0'$7$ $ $ 3 E WUDQVPLWWZRFRPPDQGE\WHV 6 $ $ F WUDQVPLWRQHFRPPDQGE\WHDQGWZR5$0GDWHE\WHV $ 6 $ $ $ &200$1' 5$0'$7$ $ 3 DDD Fig 30. I2C-bus protocol write mode 9.2.8.1 Status read out Status read out for I2C-bus operation only. This command initiates the read-out of a fixed value plus the slave address bit A0 from the PCF8545. The read-out function allows the I2C master to confirm the existence of the device on the I2C-bus. Table 28. Status read out value Bit Symbol Value Description 7 to 1 - 0101010 fixed value 0 A0 0 read back value is 01010100 1 read back value is 01010101 If a readout is made, the R/W bit must be logic 1 and then the next data byte following is provided by the PCF8545 as shown in Figure 31. 5: UHDGRXWE\WH VODYHDGGUHVV 6 $ $ $ $ 3 DFNQRZOHGJH DFNQRZOHGJH IURPPDVWHU DDD (1) From PCF8545. Fig 31. I2C-bus protocol read mode In the unlikely case that the chip has entered the internal test mode, detection of this state is possible by using the modified status read-out detailed in Table 29. The read out value is modified to indicate that the chip has entered an internal test mode. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 40 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 Table 29. Modified status read out value Bit Symbol Value Description 7 to 1 - 1111000 fixed value 0 A0 0 read back value is 1111 0000 1 read back value is 1111 0001 EMC detection: The PCF8545 is ruggedized against EMC susceptibility; however it is not possible to cover all cases. To detect if a severe EMC event has occurred, it is possible to check the responsiveness of the device by reading its register. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 41 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 9.3 SPI-bus interface Data transfer to the device is made via a 3 line SPI-bus (see Table 30). There is no output data line. The SPI-bus is initialized whenever the chip enable line pin CE is inactive. Table 30. Serial interface Symbol Function Description input[1]; CE chip enable SCL serial clock input input may be higher than VDD SDI serial data input input may be higher than VDD; input data is sampled on the rising edge of SCL [1] active LOW when HIGH, the interface is reset The chip enable must not be wired permanently LOW. 9.3.1 Data transmission The chip enable signal is used to identify the transmitted data. Each data transfer is a byte with the Most Significant Bit (MSB) sent first. The transmission is controlled by the active LOW chip enable signal CE. The first byte transmitted is the subaddress byte. GDWDEXV 68%$''5(66 '$7$ '$7$ '$7$ &( DDD Fig 32. Data transfer overview The subaddress byte opens the communication with a read/write bit and a subaddress. The subaddress is used to identify multiple devices on one SPI-bus. Table 31. Subaddress byte definition Bit Symbol 7 R/W 6 to 5 SA[1:0] 4 to 0 - Value Description data read or write selection 0 write data 1 read data 01 subaddress; other codes cause the device to ignore data transfer unused After the subaddress byte, a control byte follows (see Section 9.1 on page 36). PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 42 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 5: VXEDGGUHVV FRQWUROE\WH 5 5 & 6 6 2 5$0FRPPDQGE\WH 0 / 6 6 % % (;$03/(6 D WUDQVPLWWZRE\WHVRIGLVSOD\5$0GDWD 5$0'$7$ 5$0'$7$ E WUDQVPLWWZRFRPPDQGE\WHV &200$1' &200$1' F WUDQVPLWRQHFRPPDQGE\WHDQGWZRGLVSOD\5$0GDWHE\WHV &200$1' 5$0'$7$ 5$0'$7$ DDD Data transfers are terminated by de-asserting CE (set CE to logic 1). Fig 33. SPI-bus write example 5: E 6$ E E XQXVHG E E E FRPPDQGE\WH E E E E E E E E %LDVV\WHP %>@ E E E E E E E E E E 6&/ 6', &( DDD In this example, the bias system is set to 13. The transfer is terminated by CE returning to logic 1. After the last bit is transmitted, the state of the SDI line is not important. Fig 34. SPI-bus example PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 43 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 10. Internal circuitry 9'' $5(6(7 26&&/. 966 9/&'9'' 6&/6'$ 9/&' 966 %3WR%3 6WR6 966 DDD Fig 35. Device protection diagram for PCF8545A 9'' &(5(6(7 26&&/. 6',6&/ 9/&'9'' 966 9/&' 966 %3WR%3 6WR6 966 DDD Fig 36. Device protection diagram for PCF8545B 11. Safety notes CAUTION This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling electrostatic sensitive devices. Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or equivalent standards. CAUTION Static voltages across the liquid crystal display can build up when the LCD supply voltage (VLCD) is on while the IC supply voltage (VDD) is off, or vice versa. This may cause unwanted display artifacts. To avoid such artifacts, VLCD and VDD must be applied or removed together. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 44 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 12. Limiting values Table 32. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDD Conditions Min Max Unit supply voltage 0.5 +6.5 V IDD supply current 50 +50 mA VLCD LCD supply voltage 0.5 +6.5 V IDD(LCD) LCD supply current 50 +50 mA VI input voltage 0.5 +6.5 V 0.5 +6.5 V 10 +10 mA on pins S0 to S39, BP0 to BP7 0.5 +6.5 V on pin SDA 0.5 +6.5 V 10 +10 mA PCF8545ATT on pins SDA, OSCCLK, SCL, A0, RESET PCF8545BTT on pins CE, OSCCLK, SCL, SDI, RESET II input current VO output voltage IO output current ISS ground supply current 50 +50 mA Ptot total power dissipation - 400 mW P/out power dissipation per output VESD electrostatic discharge voltage - 100 mW HBM [1] - 3500 V CDM [2] - 1250 V Ilu latch-up current [3] - 200 mA Tstg storage temperature [4] 65 +150 C Tamb ambient temperature 40 +85 C operating device [1] Pass level; Human Body Model (HBM), according to Ref. 6 "JESD22-A114". [2] Pass level; Charge Device Model (CDM), according to Ref. 7 "JESD22-C101". [3] Pass level; latch-up testing according to Ref. 8 "JESD78" at maximum ambient temperature (Tamb(max)). [4] According to the store and transport requirements (see Ref. 12 "UM10569") the devices have to be stored at a temperature of +8 C to +45 C and a humidity of 25 % to 75 %. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 45 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 13. Static characteristics Table 33. Static characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 5.5 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit 1.8 2.5 - 5.5 V - 5.5 [1] V - 0.5 2 A external 9.6 kHz clock [2] - 10 25 A internal oscillator [2] - 30 60 A power-down, see Figure 38 [1][3] - 7 15 A [4] - 55 140 A VSS 0.5 - VDD + 0.5 V Supplies VDD supply voltage VLCD LCD supply voltage VLCD VDD IDD(pd) power-down mode supply current IDD supply current IDD(LCD) see Figure 37 LCD supply current display active, see Figure 39 Logic VI input voltage VIL LOW-level input voltage on pins OSCCLK, A0 and RESET - - 0.3VDD V VIH HIGH-level input voltage on pins OSCCLK, A0 and RESET 0.7VDD - - V VO output voltage 0.5 - VDD + 0.5 V VOH HIGH-level output voltage driving load of 50 A on pins OSCCLK 0.8VDD - - V VOL LOW-level output voltage driving load of 50 A on pins OSCCLK - - 0.2VDD V IOH HIGH-level output current output source current; VOH = VDD 0.4 V VDD = 1.8 V 0.7 1.6 - mA VDD 3.3 V 1.5 4.0 - mA VDD = 1.8 V 3 4 - mA VDD 3.3 V 5 10 - mA 1 - +1 A on pin OSCCLK IOL LOW-level output current output sink current; VOL = 0.4 V on pin OSCCLK IL leakage current PCF8545 Product data sheet Vi = VDD or VSS; on pin OSCCLK All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 46 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 Table 33. Static characteristics ...continued VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 5.5 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit I2C-bus[5] On pins SCL and SDA VI input voltage VSS 0.5 - 5.5 V VIL LOW-level input voltage - - 0.3VDD V VIH HIGH-level input voltage 0.7VDD - - V VO output voltage 0.5 - +5.5 V IL leakage current VI = VDD or VSS 1 - +1 A LOW-level output current output sink current VDD = 1.8 V 3 5.5 - mA VDD = 3.3 V 5 9 - mA on pin SCL VSS 0.5 - 5.5 V on pins CE and SDI VSS 0.5 - VDD + 0.5 V On pin SDA IOL SPI-bus input voltage VI On pins SCL, CE and SDI VIL LOW-level input voltage - - 0.3VDD V VIH HIGH-level input voltage 0.7VDD - - V IL leakage current 1 - +1 A VI = VDD or VSS LCD outputs VO output voltage variation on pins BP0 to BP7 [6] - 2.5 +10 mV on pins S0 to S43 [7] - 2.5 +10 mV VLCD = 5.5 V; on pins BP0 to BP7 [8] - 0.9 5.0 k VLCD = 5.5 V; on pins S0 to S43 [8] - 1.5 6.0 k output resistance RO [1] Power-down mode is enabled; I2C-bus or SPI-bus inactive. [2] 1:8 multiplex drive mode; 14 bias; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; inputs at VSS or VDD; default display prescale factor; I2C-bus or SPI-bus inactive. [3] Strongly linked to VLCD voltage. See Figure 38. [4] 1:8 multiplex drive mode; 14 bias; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; default display prescale factor. [5] The I2C-bus interface of PCF8545 is 5 V tolerant. [6] Variation between any two backplanes on a given voltage level; static measured. [7] Variation between any two segments on a given voltage level; static measured. [8] Outputs measured one at a time. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 47 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 DDD ,'' $ 7DPE & 1:8 multiplex drive mode; 14 bias; internal oscillator; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; inputs at VSS or VDD; default display prescale factor; I2C-bus or SPI-bus inactive. Typical is defined at VDD = 3.3 V, 25 C. Fig 37. Typical IDD with respect to temperature DDD ,'' /&' $ 9/&' 9 7DPE & Power-down mode is enabled; I2C-bus or SPI-bus inactive. Typical is defined at 25 C. Fig 38. Typical IDD(LCD) in power-down mode with respect to temperature PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 48 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 DDD ,'' /&' $ 9/&' 9 7DPE & 1:8 multiplex drive mode; 14 bias; display enabled; LCD outputs are open circuit; RAM is all written with logic 1; default display prescale factor. Typical is defined at 25 C. Fig 39. Typical IDD(LCD) when display is active with respect to temperature PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 49 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 14. Dynamic characteristics Table 34. Dynamic characteristics VDD = 1.8 V to 5.5 V; VSS = 0 V; VLCD = 2.5 V to 5.5 V; Tamb = 40 C to +85 C; unless otherwise specified. Symbol Parameter Conditions [1] Min Typ Max Unit 7800 9600 11040 Hz fclk clock frequency output on pin OSCCLK; VDD = 3.3 V fclk(ext) external clock frequency EFR = 0 - - 250000 Hz t(RESET_N) RESET_N pulse width LOW time 400 - - ns External clock source used on pin OSCCLK tclk(H) clock HIGH time 33 - - s tclk(L) clock LOW time 33 - - s [1] Frequency present on OSCCLK with default display frequency division factor. DDD IFON N+] 9'' 9 (1) 40 C. (2) 25 C. (3) 85 C. Fig 40. Typical clock frequency with respect to VDD and temperature WFON + IFON H[W WFON / 9'' 26&&/. 9'' DDD External clock source used on pin OSCCLK. Fig 41. Driver timing waveforms PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 50 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 W5(6(7 / 5(6(7 9'' DDD Fig 42. RESET timing Table 35. Timing characteristics: I2C-bus VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C; unless otherwise specified. All timing values are valid within the operating supply voltage and temperature range and referenced to VIL and VIH with an input voltage swing of VSS to VDD. Timing waveforms see Figure 43. Symbol Parameter Conditions Min Typ Max Unit - - 400 kHz Pin SCL [1] fSCL SCL clock frequency tLOW LOW period of the SCL clock 1.3 - - s tHIGH HIGH period of the SCL clock 0.6 - - s tSU;DAT data set-up time 100 - - ns tHD;DAT data hold time 0 - - ns Pin SDA Pins SCL and SDA tBUF bus free time between a STOP and START condition 1.3 - - s tSU;STO set-up time for STOP condition 0.6 - - s tHD;STA hold time (repeated) START condition 0.6 - - s tSU;STA set-up time for a repeated START condition 0.6 - - s tr rise time of both SDA and SCL signals fSCL = 400 kHz - - 0.3 s fSCL = 100 kHz - - 1.0 s - - 0.3 s tf fall time of both SDA and SCL signals tVD;ACK data valid acknowledge time [2] 0.6 - - s tVD;DAT data valid time [3] 0.6 - - s Cb capacitive load for each bus line - - 400 pF - - 50 ns [4] pulse width of spikes that must be suppressed by the input filter tSP [1] The minimum SCL clock frequency is limited by the bus time-out feature, which resets the serial bus interface if either the SDA or SCL is held LOW for a minimum of 25 ms. The bus time-out feature must be disabled for DC operation. [2] tVD;ACK = time for acknowledgement signal from SCL LOW to SDA output LOW. [3] tVD;DAT = minimum time for valid SDA output following SCL LOW. [4] Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 51 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 SURWRFRO 67$57 FRQGLWLRQ 6 W6867$ ELW 06% $ W/2: ELW $ W+,*+ I ELW 5: DFNQRZOHGJH $ 6723 FRQGLWLRQ 3 6&/ 6&/ W%8) WU WI 6'$ W+'67$ W68'$7 W9''$7 W+''$7 W9'$&. W68672 DDD Fig 43. I2C-bus timing waveforms Table 36. Timing characteristics: SPI-bus VDD = 1.8 V to 5.5 V; VSS = 0 V; Tamb = 40 C to +85 C. All timing values are valid within the operating supply voltage and temperature range and referenced to VIL and VIH with an input voltage swing of VSS to VDD. Timing waveforms see Figure 44. Symbol Parameter Conditions VDD < 2.7 V VDD 2.7 V Min Max Min Max Unit fclk(SCL) SCL clock frequency - 2 - 5 MHz tSCL SCL time 500 - 200 - ns tclk(H) clock HIGH time 200 - 80 - ns tclk(L) clock LOW time 200 - 80 - ns tr rise time for SCL signal - 100 - 100 ns tf fall time for SCL signal - 100 - 100 ns tsu(CE_N) CE_N set-up time 150 - 80 - ns th(CE_N) CE_N hold time 0 - 0 - ns trec(CE_N) CE_N recovery time 100 - 100 - ns tsu set-up time set-up time for SDI data 10 - 5 - ns th hold time hold time for SDI data 25 - 10 - ns PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 52 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 &( WVX &(B1 WU W6&/ WFON + WI WUHF &(B1 WK &(B1 6&/ WFON / WVX WK 6', E E E DDD Fig 44. SPI-bus timing PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 53 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 15. Package outline 76623SODVWLFWKLQVKULQNVPDOORXWOLQHSDFNDJHOHDGVERG\ZLGWKPP 627 ( ' $ ; F +( \ Y 0 $ = 4 $ $ $ SLQLQGH[ $ /S / GHWDLO; Z 0 ES H PP VFDOH ',0(16,216 PPDUHWKHRULJLQDOGLPHQVLRQV 81,7 $ PD[ $ $ $ ES F ' ( H +( / /S 4 Y Z \ = PP R R 1RWHV 3ODVWLFRUPHWDOSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 3ODVWLFLQWHUOHDGSURWUXVLRQVRIPPPD[LPXPSHUVLGHDUHQRWLQFOXGHG 287/,1( 9(56,21 627 5()(5(1&(6 ,(& -('(& -(,7$ 02 (8523($1 352-(&7,21 ,668('$7( Fig 45. Package outline SOT364-1 (TSSOP56) PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 54 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 16. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 55 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 17. Packing information 17.1 Tape and reel information 7239,(: ' 3 : SLQ % \ 3 $ ' . [ GLUHFWLRQRIIHHG 2ULJLQDOGLPHQVLRQVDUHLQPP )LJXUHQRWGUDZQWRVFDOH DDD Fig 46. Tape and reel details for PCF8545ATT and PCF8545BTT Table 37. Carrier tape dimensions of PCF8545ATT and PCF8545BTT Symbol Description Value Unit Compartments A0 pocket width in x direction 8.65 to 8.9 mm B0 pocket width in y direction 14.4 to 15.8 mm K0 pocket depth 1.5 to 1.8 mm P1 pocket hole pitch 12 mm D1 pocket hole diameter 1.5 to 2.05 mm Overall dimensions PCF8545 Product data sheet W tape width 24 mm D0 sprocket hole diameter 1.5 to 1.55 mm P0 sprocket hole pitch 4 mm All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 56 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 18. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description". 18.1 Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 18.2 Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: * Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: * * * * * * Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 18.3 Wave soldering Key characteristics in wave soldering are: * Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave * Solder bath specifications, including temperature and impurities PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 57 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 18.4 Reflow soldering Key characteristics in reflow soldering are: * Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 47) than a SnPb process, thus reducing the process window * Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board * Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 38 and 39 Table 38. SnPb eutectic process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 < 2.5 235 220 2.5 220 220 Table 39. Lead-free process (from J-STD-020D) Package thickness (mm) Package reflow temperature (C) Volume (mm3) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 47. PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 58 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 MSL: Moisture Sensitivity Level Fig 47. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description". PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 59 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 19. Footprint information for reflow soldering )RRWSULQWLQIRUPDWLRQIRUUHIORZVROGHULQJRI76623SDFNDJH 627 +[ *[ 3 +\ *\ %\ $\ & ' [ ' 3 *HQHULFIRRWSULQWSDWWHUQ 5HIHUWRWKHSDFNDJHRXWOLQHGUDZLQJIRUDFWXDOOD\RXW VROGHUODQG RFFXSLHGDUHD ',0(16,216LQPP 3 3 $\ %\ & ' ' *[ *\ +[ +\ VRWBIU Fig 48. Footprint information for reflow soldering of SOT364-1 (TSSOP56) package PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 60 of 72 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx NXP Semiconductors Product data sheet PCF8545 20. Appendix 20.1 LCD segment driver selection Table 40. Selection of LCD segment drivers Type name Number of elements at MUX VDD (V) VLCD (V) ffr (Hz) 1:1 1:2 1:3 1:4 1:6 1:8 1:9 VLCD (V) VLCD (V) Tamb (C) charge temperature pump compensat. Interface Package AECQ100 PCA8561AHN[5] 18 36 54 72 - - - 1.8 to 5.5 1.8 to 5.5 32 to 256[1] N N 40 to 105 I2C HVQFN32 Y PCA8561BHN[5] 18 36 54 72 - - - 1.8 to 5.5 1.8 to 5.5 32 to 256[1] N N 40 to 105 SPI HVQFN32 Y PCF8566TS 24 48 72 96 - - - 2.5 to 6 N N 40 to 85 I2C VSO40 N 40 to 85 I2C TSSOP48 N I2C TSSOP48 Y PCF85162T 32 64 96 128 - - - 2.5 to 6 69 1.8 to 5.5 2.5 to 6.5 82 N N 32 64 96 128 - - - 1.8 to 5.5 2.5 to 8 110 N N 40 to 95 PCA85262ATT 32 64 96 128 - - - 1.8 to 5.5 2.5 to 8 200 N N 40 to 105 I2C TSSOP48 Y TSSOP48 N TSSOP48 N PCF8551ATT[5] PCF8551BTT[5] 36 36 72 72 108 144 108 144 - - - 1.8 to 5.5 1.8 to 5.5 32 to 128[1] N N 40 to 85 I2C 1.8 to 5.5 1.8 to 5.5 32 to 128[1] N N 40 to 85 SPI 256[1] I2C TSSOP48 Y PCA8551ATT[5] 36 72 108 144 - - - 1.8 to 5.5 1.8 to 5.5 32 to N N 40 to 105 PCA8551BTT[5] 36 72 108 144 - - - 1.8 to 5.5 1.8 to 5.5 32 to 256[1] N N 40 to 105 SPI TSSOP48 Y PCF85176T 40 80 120 160 - - - 1.8 to 5.5 2.5 to 6.5 82 N N 40 to 85 I2C TSSOP56 N N 40 to 95 I2C TSSOP56 Y N N 40 to 105 I2C TSSOP56 Y N N 40 to 85 I2C TQFP64 N N 40 to 95 I2C TQFP64 Y TSSOP56 N PCA85176T 40 80 120 160 - - - 1.8 to 5.5 2.5 to 8 110 PCA85276ATT 40 80 120 160 - - - 1.8 to 5.5 2.5 to 8 PCF85176H 40 80 120 160 - - - 1.8 to 5.5 2.5 to 6.5 82 PCA85176H PCF8553ATT[5] 40 40 80 80 120 160 120 160 - - - 1.8 to 5.5 2.5 to 8 N 200 82 N 1.8 to 5.5 1.8 to 5.5 32 to 128[1] N N 40 to 85 I2C 128[1] 40 80 120 160 - - - 1.8 to 5.5 1.8 to 5.5 32 to N N 40 to 85 SPI TSSOP56 N PCA8553ATT[5] 40 80 120 160 - - - 1.8 to 5.5 1.8 to 5.5 32 to 256[1] N N 40 to 105 I2C TSSOP56 Y - 1.8 to 5.5 1.8 to 5.5 32 to 256[1] N N 40 to 105 SPI TSSOP56 Y 1.8 to 5.5 2.5 to 9 60 to 300[1] N N 40 to 95 I2C TSSOP56 Y 300[1] N N 40 to 95 SPI TSSOP56 Y Y Y[3] 40 to 95 I2C TQFP64 Y Y Y[3] 40 to 95 SPI TQFP64 Y N 40 to 85 I2C LQFP80 N N 40 to 95 I2C LQFP80 Y PCA8553BTT[5] PCA8546ATT[5] 40 - 80 - 120 160 - 176 - - - 61 of 72 (c) NXP B.V. 2013. All rights reserved. PCA8546BTT[5] - - - 176 - - - 1.8 to 5.5 2.5 to 9 60 to PCA8547AHT[5] 44 88 - 176 - - - 1.8 to 5.5 2.5 to 9 60 to 300[1] 1.8 to 5.5 2.5 to 9 300[1] PCA8547BHT[5] PCF85134HL PCA85134H 44 60 60 88 - 176 - 120 180 240 120 180 240 - - - 60 to 1.8 to 5.5 2.5 to 6.5 82 1.8 to 5.5 2.5 to 8 82 N N PCF8545 PCF8553BTT[5] Universal LCD driver for multiplex rates up to 1:8 Rev. 1 -- 13 November 2013 All information provided in this document is subject to legal disclaimers. PCA85162T xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Selection of LCD segment drivers ...continued Type name Number of elements at MUX VDD (V) VLCD (V) ffr (Hz) VLCD (V) VLCD (V) Tamb (C) charge temperature pump compensat. 60 to 300[1] Y Y 1:1 1:2 1:3 1:4 1:6 1:8 1:9 40 to 105 I2C LQFP80 Y 120 - 240 - PCF8545ATT[5] - - - 176 252 320 - 1.8 to 5.5 2.5 to 5.5 60 to 300[1] N N 40 to 85 I2C TSSOP56 N PCF8545BTT[5] - - - 176 252 320 - 1.8 to 5.5 2.5 to 5.5 60 to 300[1] N N 40 to 85 SPI TSSOP56 N 176 252 320 - 60 to 300[1] N N 40 to 85 I2C TSSOP56 N 300[1] - - 2.5 to 5.5 2.5 to 9 AECQ100 60 - - Package PCA8543AHL PCF8536AT[4] - Interface 1.8 to 5.5 2.5 to 9 PCF8536BT[4] - - - 176 252 320 - 1.8 to 5.5 2.5 to 9 60 to N N 40 to 85 SPI TSSOP56 N PCA8536AT[4] - - - 176 252 320 - 1.8 to 5.5 2.5 to 9 60 to 300[1] N N 40 to 95 I2C TSSOP56 Y 1.8 to 5.5 2.5 to 9 60 to 300[1] N N 40 to 95 SPI TSSOP56 Y 60 to 300[1] Y Y[3] 40 to 85 I2C TQFP64 300[1] PCA8536BT[4] PCF8537AH 44 88 - 176 252 320 176 276 352 - 1.8 to 5.5 2.5 to 9 N 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to Y 40 to 85 SPI TQFP64 N PCA8537AH 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300[1] Y Y[3] 40 to 95 I2C TQFP64 Y PCA8537BH 44 88 - 176 276 352 - 1.8 to 5.5 2.5 to 9 60 to 300[1] Y Y[3] 40 to 95 SPI TQFP64 Y 2.5 to 5.5 2.5 to 9 60 to 300[1] Y Y[3] 40 to 105 I2C LQFP80 Y 60 to 300[1] Y Y[3] 40 to 105 I2C bare die Y - 1.8 to 5.5 1.8 to 5.5 32 to 128[1] N N 40 to 85 I2C, SPI bare die N - 256[1] N 40 to 105 I2C, bare die Y N 40 to 85 I2C bare die N I2C 60 120 - PCA9620U 60 120 - PCF8552DUG[5] 36 72 PCA8552DUG[5] PCF8576DU 36 40 72 80 240 320 480 240 320 480 - 108 144 108 144 120 160 - - - 2.5 to 5.5 2.5 to 9 1.8 to 5.5 1.8 to 5.5 32 to 1.8 to 5.5 2.5 to 6.5 77 N N SPI PCF8576EUG 40 80 120 160 - - - 1.8 to 5.5 2.5 to 6.5 77 N N 40 to 85 bare die N PCA8576FUG[5] 40 80 120 160 - - - 1.8 to 5.5 2.5 to 8 N N 40 to 105 I2C bare die Y N 40 to 85 I2C bare die N N 40 to 95 I2C bare die Y I2C PCF85133U PCA85133U 80 80 160 240 320 160 240 320 - PCA85233U 80 PCA8530DUG[5] 102 204 - PCF85132U PCA85132U 160 240 320 408 - 160 320 480 640 160 320 480 640 160 320 480 640 - PCF8538UG[5] 102 204 - PCA8538UG 102 204 - - - 1.8 to 5.5 2.5 to 6.5 82, 110[2] 1.8 to 5.5 2.5 to 8 110[2] 82, N N 40 to 105 bare die Y Y Y[3] 40 to 105 I2C, SPI bare die Y N 40 to 85 I2C bare die N N 40 to 95 I2C bare die Y N N 40 to 95 I2C bare die Y Y Y[3] 40 to 85 I2C, SPI[2] bare die N Y Y[3] 40 to 105 I2C, Y - 1.8 to 5.5 2.5 to 8 150, - - 2.5 to 5.5 4 to 12 45 to 300[1] - - 1.8 to 5.5 1.8 to 8 1.8 to 5.5 1.8 to 8 1.8 to 5.5 1.8 to 8 60 to 90[1] 60 to 90[1] 117 to 176[1] 408 612 816 918 2.5 to 5.5 4 to 12 45 to 300[1] 408 612 816 918 2.5 to 5.5 4 to 12 300[1] [1] Can be selected by command. [2] Can be selected by pin configuration. 45 to N 220[2] - N N N SPI[2] bare die PCF8545 62 of 72 (c) NXP B.V. 2013. All rights reserved. PCA85232U - 200 Universal LCD driver for multiplex rates up to 1:8 Rev. 1 -- 13 November 2013 All information provided in this document is subject to legal disclaimers. PCF8537BH Y[3] PCA9620H NXP Semiconductors Product data sheet PCF8545 Table 40. xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Extra feature: Temperature sensor. [4] Extra feature: 6 PWM channels. [5] In development. NXP Semiconductors Product data sheet PCF8545 [3] PCF8545 63 of 72 (c) NXP B.V. 2013. All rights reserved. Universal LCD driver for multiplex rates up to 1:8 Rev. 1 -- 13 November 2013 All information provided in this document is subject to legal disclaimers. PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 21. Abbreviations Table 41. Acronym PCF8545 Product data sheet Abbreviations Description CDM Charged-Device Model CMOS Complementary Metal-Oxide Semiconductor DC Direct Current EMC ElectroMagnetic Compatibility EPROM Erasable Programmable Read-Only Memory ESD ElectroStatic Discharge HBM Human Body Model I2C Inter-Integrated Circuit bus IC Integrated Circuit LCD Liquid Crystal Display LSB Least Significant Bit MSB Most Significant Bit MSL Moisture Sensitivity Level MUX Multiplexer OTP One Time Programmable PCB Printed-Circuit Board POR Power-On Reset RC Resistance-Capacitance RAM Random Access Memory RGB Red Green Blue RMS Root Mean Square SCL Serial CLock line SDA Serial DAta line SPI Serial Peripheral Interface All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 64 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 22. References [1] AN10365 -- Surface mount reflow soldering description [2] AN11267 -- EMC and system level ESD design guidelines for LCD drivers [3] IEC 60134 -- Rating systems for electronic tubes and valves and analogous semiconductor devices [4] IEC 61340-5 -- Protection of electronic devices from electrostatic phenomena [5] IPC/JEDEC J-STD-020D -- Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface-Mount Devices [6] JESD22-A114 -- Electrostatic Discharge (ESD) Sensitivity Testing Human Body Model (HBM) [7] JESD22-C101 -- Field-Induced Charged-Device Model Test Method for Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components [8] JESD78 -- IC Latch-Up Test [9] JESD625-A -- Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices [10] SNV-FA-01-02 -- Marking Formats Integrated Circuits [11] UM10204 -- I2C-bus specification and user manual [12] UM10569 -- Store and transport requirements PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 65 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 23. Revision history Table 42. Revision history Document ID Release date Data sheet status Change notice Supersedes PCF8545 v.1 20131113 Product data sheet - - PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 66 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 24. Legal information 24.1 Data sheet status Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term `short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 24.2 Definitions Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification -- The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet. 24.3 Disclaimers Limited warranty and liability -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. NXP Semiconductors takes no responsibility for the content in this document if provided by an information source outside of NXP Semiconductors. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors' aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. PCF8545 Product data sheet Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors and its suppliers accept no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products, and NXP Semiconductors accepts no liability for any assistance with applications or customer product design. It is customer's sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer's applications and products planned, as well as for the planned application and use of customer's third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer's applications or products, or the application or use by customer's third party customer(s). Customer is responsible for doing all necessary testing for the customer's applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer's third party customer(s). NXP does not accept any liability in this respect. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer's general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 67 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products -- Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors' warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors' specifications such use shall be solely at customer's own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors' standard warranty and NXP Semiconductors' product specifications. Translations -- A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. 24.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V. 25. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 68 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 26. Tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Ordering information . . . . . . . . . . . . . . . . . . . . .2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . .2 Marking codes . . . . . . . . . . . . . . . . . . . . . . . . . .2 Pin description of PCF8545ATT and PCF8545BTT . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Commands of PCF8545 . . . . . . . . . . . . . . . . . .7 Initialize - initialize command bit description . . .7 OTP-refresh - OTP-refresh command bit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 Mode-settings - mode settings command bit description . . . . . . . . . . . . . . . . . . . . . . . . . .8 Effect of the power-down bit (PD). . . . . . . . . . .10 Oscillator-control - oscillator control command bit description . . . . . . . . . . . . . . . . . 11 Valid combinations of bits OSC, EFR, and COE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Typical use of bits OSC, EFR, and COE . . . . .12 OSCCLK pin state depending on configuration 13 LCD frame frequencies. . . . . . . . . . . . . . . . . . .13 Set-MUX-mode - set multiplex drive mode command bit description . . . . . . . . . . . . . . . . .14 Set-bias-mode - set bias mode command bit description . . . . . . . . . . . . . . . . . . . . . . . . .14 Frame-frequency - frame frequency and output clock frequency command bit description . . . .14 Frame frequency prescaler values for 230 kHz clock operation . . . . . . . . . . . . . . . . . . . . . . . .15 Load-data-pointer - load data pointer command bit description. . . . . . . . . . . . . . . . . .16 Write-RAM-data - write RAM data command bit description[1] . . . . . . . . . . . . . . . .16 Reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Selection of display configurations . . . . . . . . . .20 Preferred LCD drive modes: summary of characteristics. . . . . . . . . . . . . . . . . . . . . . . . . .22 Backplane and active segment combinations. .29 Control byte description . . . . . . . . . . . . . . . . . .36 I2C slave address byte . . . . . . . . . . . . . . . . . . .39 R/W-bit description . . . . . . . . . . . . . . . . . . . . . .39 Status read out value . . . . . . . . . . . . . . . . . . . .40 Modified status read out value . . . . . . . . . . . . .41 Serial interface . . . . . . . . . . . . . . . . . . . . . . . . .42 Subaddress byte definition . . . . . . . . . . . . . . . .42 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .45 Static characteristics . . . . . . . . . . . . . . . . . . . .46 Dynamic characteristics . . . . . . . . . . . . . . . . . .50 Timing characteristics: I2C-bus . . . . . . . . . . . .51 Timing characteristics: SPI-bus . . . . . . . . . . . .52 Carrier tape dimensions of PCF8545ATT and PCF8545BTT . . . . . . . . . . . . . . . . . . . . . .56 SnPb eutectic process (from J-STD-020D) . . .58 Lead-free process (from J-STD-020D) . . . . . .58 Selection of LCD segment drivers . . . . . . . . . .61 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .64 Revision history . . . . . . . . . . . . . . . . . . . . . . . .66 PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 69 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 27. Figures Fig 1. Fig 2. Fig 3. Fig 4. Fig 5. Fig 6. Fig 7. Fig 8. Fig 9. Fig 10. Fig 11. Fig 12. Fig 13. Fig 14. Fig 15. Fig 16. Fig 17. Fig 18. Fig 19. Fig 20. Fig 21. Fig 22. Fig 23. Fig 24. Fig 25. Fig 26. Fig 27. Fig 28. Fig 29. Fig 30. Fig 31. Fig 32. Fig 33. Fig 34. Fig 35. Fig 36. Fig 37. Fig 38. Fig 39. Fig 40. Fig 41. Fig 42. Block diagram of PCF8545A . . . . . . . . . . . . . . . . .3 Block diagram of PCF8545B . . . . . . . . . . . . . . . . .4 Pin configuration for TSSOP56 (PCF8545ATT). . .5 Pin configuration for TSSOP56 (PCF8545BTT) . .5 Effect of backplane swapping . . . . . . . . . . . . . . . .9 Recommended power-down sequence . . . . . . . .10 Oscillator selection. . . . . . . . . . . . . . . . . . . . . . . .12 Recommended start-up sequence when using the internal oscillator . . . . . . . . . . . . . . . . .18 Recommended start-up sequence when using an external clock signal . . . . . . . . . . . . . . .19 Example of displays suitable for PCF8545 . . . . .20 Typical system configuration for the I2C-bus . . . .21 Typical system configuration for the SPI-bus. . . .21 Electro-optical characteristic: relative transmission curve of the liquid . . . . . . . . . . . . . .23 Waveforms for the 1:4 multiplex drive mode with 13 bias and line inversion . . . . . . . . . . . . . . .24 Waveforms for 1:6 multiplex drive mode with bias 13 and line inversion. . . . . . . . . . . . . . . . . . .25 Waveforms for 1:6 multiplex drive mode with bias 14 and line inversion. . . . . . . . . . . . . . . . . . .26 Waveforms for 1:8 multiplex drive mode with bias 14 and line inversion. . . . . . . . . . . . . . . . . . .27 Waveforms for 1:8 multiplex drive mode with bias 14 and frame inversion . . . . . . . . . . . . . . . . .28 Display RAM bitmap . . . . . . . . . . . . . . . . . . . . . .30 Display RAM filling order in 1:4 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Boundary condition in 1:4 multiplex drive mode .32 Display RAM filling order in 1:6 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 Boundary condition in 1:6 multiplex drive mode .34 Display RAM filling order in 1:8 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 Control byte format . . . . . . . . . . . . . . . . . . . . . . .36 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Definition of START and STOP conditions. . . . . .37 System configuration . . . . . . . . . . . . . . . . . . . . . .38 Acknowledgement on the I2C-bus . . . . . . . . . . . .38 I2C-bus protocol write mode . . . . . . . . . . . . . . . .40 I2C-bus protocol read mode. . . . . . . . . . . . . . . . .40 Data transfer overview . . . . . . . . . . . . . . . . . . . . .42 SPI-bus write example . . . . . . . . . . . . . . . . . . . . .43 SPI-bus example . . . . . . . . . . . . . . . . . . . . . . . . .43 Device protection diagram for PCF8545A . . . . . .44 Device protection diagram for PCF8545B . . . . . .44 Typical IDD with respect to temperature . . . . . . . .48 Typical IDD(LCD) in power-down mode with respect to temperature. . . . . . . . . . . . . . . . . . . . .48 Typical IDD(LCD) when display is active with respect to temperature. . . . . . . . . . . . . . . . . . . . .49 Typical clock frequency with respect to VDD and temperature . . . . . . . . . . . . . . . . . . . . . . . . .50 Driver timing waveforms . . . . . . . . . . . . . . . . . . .50 RESET timing . . . . . . . . . . . . . . . . . . . . . . . . . . .51 PCF8545 Product data sheet I2C-bus timing waveforms . . . . . . . . . . . . . . . . . . 52 SPI-bus timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Package outline SOT364-1 (TSSOP56) . . . . . . . 54 Tape and reel details for PCF8545ATT and PCF8545BTT . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Fig 47. Temperature profiles for large and small components. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Fig 48. Footprint information for reflow soldering of SOT364-1 (TSSOP56) package . . . . . . . . . . . . . 60 Fig 43. Fig 44. Fig 45. Fig 46. All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 70 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 28. Contents 1 2 3 4 4.1 5 6 7 7.1 7.2 8 8.1 8.1.1 8.1.2 8.1.3 8.1.3.1 8.1.3.2 8.1.3.3 8.1.3.4 8.1.4 8.1.4.1 8.1.4.2 8.1.5 8.1.6 8.1.7 8.1.8 8.1.9 8.2 8.2.1 8.2.2 8.2.3 8.3 8.4 8.4.1 8.5 8.5.1 8.5.2 8.5.3 8.6 8.7 8.8 8.9 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 Functional description . . . . . . . . . . . . . . . . . . . 7 Commands of PCF8545 . . . . . . . . . . . . . . . . . . 7 Command: initialize . . . . . . . . . . . . . . . . . . . . . 7 Command: OTP-refresh . . . . . . . . . . . . . . . . . . 7 Command: mode-settings . . . . . . . . . . . . . . . . 8 Backplane swapping. . . . . . . . . . . . . . . . . . . . . 8 Line inversion (driving scheme A) and frame inversion (driving scheme B) . . . . . . . . . . . . . . . . . . . . . . 9 Power-down mode . . . . . . . . . . . . . . . . . . . . . . 9 Display enable . . . . . . . . . . . . . . . . . . . . . . . . 11 Command: oscillator-control . . . . . . . . . . . . . 11 Oscillator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Timing and frame frequency . . . . . . . . . . . . . . 13 Command: set-MUX-mode . . . . . . . . . . . . . . . 14 Command: set-bias-mode . . . . . . . . . . . . . . . 14 Command: frame-frequency . . . . . . . . . . . . . . 14 Command: load-data-pointer . . . . . . . . . . . . . 15 Command: write-RAM-data . . . . . . . . . . . . . . 16 Start-up and shut-down. . . . . . . . . . . . . . . . . . 16 Reset and Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 RESET pin function . . . . . . . . . . . . . . . . . . . . 17 Recommended start-up sequences . . . . . . . . 17 Possible display configurations . . . . . . . . . . . 20 LCD voltage selector . . . . . . . . . . . . . . . . . . . 21 Electro-optical performance . . . . . . . . . . . . . . 23 LCD drive mode waveforms . . . . . . . . . . . . . . 24 1:4 Multiplex drive mode. . . . . . . . . . . . . . . . . 24 1:6 Multiplex drive mode. . . . . . . . . . . . . . . . . 25 1:8 Multiplex drive mode. . . . . . . . . . . . . . . . . 27 Display register . . . . . . . . . . . . . . . . . . . . . . . . 29 Backplane outputs . . . . . . . . . . . . . . . . . . . . . 29 Segment outputs. . . . . . . . . . . . . . . . . . . . . . . 29 Display RAM . . . . . . . . . . . . . . . . . . . . . . . . . . 29 8.9.1 8.9.2 Data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . RAM filling in 1:4 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.9.3 RAM filling in 1:6 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 8.9.4 RAM filling in 1:8 multiplex drive mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Bus interfaces . . . . . . . . . . . . . . . . . . . . . . . . . 9.1 Control byte and register selection . . . . . . . . 9.2 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . 9.2.1 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.2 START and STOP conditions. . . . . . . . . . . . . 9.2.3 System configuration . . . . . . . . . . . . . . . . . . . 9.2.4 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.5 I2C-bus controller . . . . . . . . . . . . . . . . . . . . . . 9.2.6 Input filters . . . . . . . . . . . . . . . . . . . . . . . . . . . 9.2.7 I2C-bus slave address . . . . . . . . . . . . . . . . . . 9.2.8 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 9.2.8.1 Status read out. . . . . . . . . . . . . . . . . . . . . . . . 9.3 SPI-bus interface . . . . . . . . . . . . . . . . . . . . . . 9.3.1 Data transmission . . . . . . . . . . . . . . . . . . . . . 10 Internal circuitry . . . . . . . . . . . . . . . . . . . . . . . 11 Safety notes. . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 13 Static characteristics . . . . . . . . . . . . . . . . . . . 14 Dynamic characteristics. . . . . . . . . . . . . . . . . 15 Package outline. . . . . . . . . . . . . . . . . . . . . . . . 16 Handling information . . . . . . . . . . . . . . . . . . . 17 Packing information . . . . . . . . . . . . . . . . . . . . 17.1 Tape and reel information . . . . . . . . . . . . . . . 18 Soldering of SMD packages . . . . . . . . . . . . . . 18.1 Introduction to soldering. . . . . . . . . . . . . . . . . 18.2 Wave and reflow soldering. . . . . . . . . . . . . . . 18.3 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . 18.4 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . 19 Footprint information for reflow soldering. . . . . . . . . . . . . . . . . . . . . 20 Appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20.1 LCD segment driver selection . . . . . . . . . . . . 21 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 22 References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Revision history . . . . . . . . . . . . . . . . . . . . . . . 24 Legal information . . . . . . . . . . . . . . . . . . . . . . 24.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 24.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 31 32 34 36 36 37 37 37 37 38 38 39 39 39 40 42 42 44 44 45 46 50 54 55 56 56 57 57 57 57 58 60 61 61 64 65 66 67 67 67 continued >> PCF8545 Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 1 -- 13 November 2013 (c) NXP B.V. 2013. All rights reserved. 71 of 72 PCF8545 NXP Semiconductors Universal LCD driver for multiplex rates up to 1:8 24.3 24.4 25 26 27 28 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information. . . . . . . . . . . . . . . . . . . . . Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 68 68 69 70 71 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'. (c) NXP B.V. 2013. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 November 2013 Document identifier: PCF8545 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: NXP: PCF8545BTT/AJ PCF8545ATT/AJ