*Optimized PCB Layout file downloadable from the Enpirion Website to assure first pass design success.
EN5366QI
6A Voltage Mode Synchronous Buck PWM
DC-DC Converter with Integrated Inductor
External Output Voltage Programming
RoHS Compliant
Halogen Free
Description
This Enpirion solution is a Power System on
Silicon DC-DC converter. It is specifically
designed to meet the precise voltage and fast
transient requirements of present and future
high-performance, low-power processor, DSP,
FPGA, ASIC, memory boards and system level
applications in a distributed power architecture.
Advanced circuit techniques, ultra high switching
frequency, and very advanced, high-density,
integrated circuit and proprietary inductor
technology deliver high-quality, ultra compact,
non-isolated DC-DC conversion. Operating this
converter requires as few as three external
components that include small value input and
output ceramic capacitors and a soft-start
capacitor.
The Enpirion integrated inductor solution
significantly helps in low noise system design
and productivity by offering greatly simplified
board design, layout and manufacturing
requirements.
All Enpirion products are RoHS compliant and
lead-free manufacturing environment compatible.
Typical Application Circuit
VOUT
VIN
XFB
47µF
47µF
15nF
VOUT
ENABLE
PGNDAGND
SS
PVIN
AVIN
PGND
1Ω
XOV
Figure 1. Simple Layout.
Features
• Integrated INDUCTOR, MOSFETS, Controller
• Footprint 1/3rd that of competing solutions.
• Low Part Count: only 3 MLCC Capacitors.
• Up to 20W continuous output power.
• Low output impedance optimized for ≤ 90 nm
• Master/slave configuration for paralleling.
• 5MHz operating frequency.
• High efficiency, up to 93%.
• Wide input voltage range of 2.375V to 5.5V.
• External resistor divider output voltage select.
• Output enable pin and Power OK signal.
• Programmable soft-start time.
• Optimized for low noise/EMI design.
• Thermal shutdown, short circuit, over-voltage
and under-voltage protection.
• RoHS compliant, MSL level 3, 260C reflow.
Applications
• Point of load regulation for low-power
processors, network processors, DSPs,
FPGAs, and ASICs
• ≤ 90 nm advanced process loads
• Notebook computers, servers, workstations
• Broadband, networking, LAN/WAN, optical
• Low voltage, distributed power architectures
with 2.5V, 3.3V or 5V rails
• DSL, STB, DVR, DTV, Industrial PC
• Ripple sensitive applications
Ordering Information
Part Number
Temp Rating
(°C) Package
EN5366QI-T -40 to +85 58-pin QFN
T&R
EN5366QI-E QFN Evaluation Board
September 2007 EN5366QI
©Enpirion 2007 all rights reserved, E&OE www.enpirion.com
2
Pin Configuration
Below is a top view diagram of the EN5366Q package.
NOTE: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage.
However, they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or
damage.
Figure 2. Pin Diagram, top view.
September 2007 EN5366QI
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Pin Descriptions
PIN NAME FUNCTION
1-3 NC
NO CONNECT: These pins should not be electrically connected to each other or to
any external signal, voltage, or ground. One or more of these pins may be connected
internally.
4-5 NC
NO CONNECT: These pins should not be electrically connected to each other or to
any external signal, voltage, or ground.
CAUTION!: Internally connected to switching node. Take care to route signals away
from these pins.
6-13 NC
NO CONNECT: These pins should not be electrically connected to each other or to
any external signal, voltage, or ground. One or more of these pins may be connected
internally.
14-20 VOUT
Regulated converter output. Decouple with output filter capacitor to PGND. Refer to
layout section for specific layout requirements
21-23 NC
NO CONNECT: These pins should not be electrically connected to each other or to
any external signal, voltage, or ground.
CAUTION!: Internally connected to switching node. Take care to route signals away
from these pins.
24-29 PGND Output power ground. Refer to layout section for specific layout requirements.
30-35 PVIN
Input power supply. Connect to input power supply. Decouple with input capacitor to
PGND. Refer to layout section for specific layout requirements
36-37 NC
NO CONNECT: These pins should not be electrically connected to each other or to
any external signal, voltage, or ground. One or more of these pins may be connected
internally.
38 ROCP
Optional Over Current Protection adjust pin. Used for diagnostic purposes only. Place
10kΩ resistor between this pin and AGND (pin 40) to raise the over current trip point
to approximately 200% of maximum rated current.
39 AVIN
Analog voltage input for the controller circuits.
Connect this pin to PVIN using a 1 Ohm resistor.
40 AGND Analog ground for the controller circuits.
41-42 NC
NO CONNECT: These pins should not be electrically connected to each other or to
any external signal, voltage, or ground. One or more of these pins may be connected
internally.
43 XFB Feedback pin for external voltage divider network.
44 XOV Over voltage programming feedback pin.
45 VS0 Voltage select line 0 input. See Table 1. This pin has internal pull-up
46 POK
Power OK is an open drain transistor for power system state indication. POK is a
logic high when VOUT is with -10% to +20% of VOUT nominal. Size pull-up resistor
to limit current to 4mA when POK is low.
47 NC
NO CONNECT: These pins should not be electrically connected to each other or to
any external signal, voltage, or ground. One or more of these pins may be connected
internally.
48 SS
Soft-Start node. The soft-start capacitor is connected between this pin and AGND.
The value of this capacitor determines the startup timing.
49 EAIN Optional Error Amplifier input. Allows for customization of the control loop.
50 EAOUT Optional Error Amplifier output. Allows for customization of the control loop.
51 COMP Optional Error Amplifier Buffer output. Allows for customization of the control loop.
52 ENABLE
Input Enable. Applying a logic high, enables the output and initiates a soft-start.
Applying a logic low disables the output.
September 2007 EN5366QI
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4
PIN NAME FUNCTION
53 PWM
PWM input/output. Used for optional master/slave configuration. When M/S pin is
asserted “low”, PWM will output the gate-drive PWM waveform. When the M/S pin is
asserted “high”, the PWM pin is configured as an input for PWM signal from the
“master” device. PWM pin can drive up to 3 slave devices.
NOTE: Leave this pin open when not using parallel mode.
54 NC
NO CONNECT: These pins should not be electrically connected to each other or to
any external signal, voltage, or ground. One or more of these pins may be connected
internally.
55 M/S
Optional Master/Slave select pin. Asserting pin “low” places device in Master Mode
for current sharing. PWM pin (53) will output PWM drive signal. Asserting pin “high”
will place the device in Slave Mode. PWM pin (53) will be configured to input (receive)
PWM drive signal from “Master” device.
NOTE: Leave this pin open when not using parallel mode.
56-58 NC
NO CONNECT: These pins should not be electrically connected to each other or to
any external signal, voltage, or ground. One or more of these pins may be connected
internally.
Block Diagram
(+)
(-)
Error
Amp
VOUT
P-Drive
N-Drive
UVLO
Thermal Limit
Current Limit
Soft Start
Sawtooth
Generator
(+)
(-)
PWM
Comp
PVIN
ENABLE
Compensation
Network
Bandgap
Reference
PGND
Voltage
Selector XFB
EAIN
EAOUT
ROCP
SS
Reference
Voltage
selector
COMP
Over Voltage
power
Good
Logic
Over
Voltage VOUT
POK
XOV
Figure 3. System block diagram.
September 2007 EN5366QI
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5
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond
recommended operating conditions is not implied. Stress beyond absolute maximum ratings may
cause permanent damage to the device. Exposure to absolute maximum rated conditions for
extended periods may affect device reliability.
PARAMETER SYMBOL MIN MAX UNITS
Input Supply Voltage VIN -0.5 7.0 V
Voltages on: ENABLE, -0.5 VIN V
Voltage on XFB, XOV -0.5 2.5 V
Voltages on: EAIN, EAOUT, COMP -0.5 2.5 V
Voltages on: SS, PWM -0.5 3.0 V
Voltages on: POK -0.5 VIN + 0.3 V
Storage Temperature Range TSTG -65 150 °C
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A 260 °C
ESD Rating (based on Human Body Model) 2000 V
Recommended Operating Conditions
PARAMETER SYMBOL MIN MAX UNITS
Input Voltage Range VIN 2.375 5.5 V
Output Voltage Range VOUT 0.75 3.3 V
Operating Ambient Temperature TA -40 +85 °C
Operating Junction Temperature TJ -40 +125 °C
Thermal Characteristics
PARAMETER SYMBOL TYP UNITS
Thermal Resistance: Junction to Ambient (0 LFM) (Note 1) θJA 20 °C/W
Thermal Resistance: Junction to Case (0 LFM) θJC 1.5 °C/W
Thermal Overload Trip Point TJ-TP +150 °C
Thermal Overload Trip Point Hysteresis 20 °C
NOTES:
1. Based on a four-layer board and proper thermal design in line with JEDEC EIJ/JESD 51 Standards.
September 2007 EN5366QI
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6
Electrical Characteristics
NOTE: VIN=5.5V over operating temperature range unless otherwise noted.
Typical values are at TA = 25°C.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Input Voltage VIN 2.375 5.5 V
Output Regulation
Feedback Pin
Voltage VOUT 2.375V ≤ VIN ≤ 5.5V,
ILOAD = 1A; TA = 25°C 0.735 0.750 0.765 V
Feedback Pin
Voltage VOUT
2.375V ≤ VIN ≤ 5.5V,
0A ≤ ILOAD ≤ 6A
-40 ºC ≤ TA ≤ +85 ºC
0.725 0.750 0.773 V
Transient Response (IOUT = 0% to 100% or 100% to 0% of Rated Load)
Peak Deviation ∆VOUT VIN = 5V, 1.2V < VOUT < 3.3V
COUT=50uF 3 %
Output Voltage Ripple
Peak-to-peak ∆VOUT-PP
VIN = 5.0V, VOUT = 1.2V, IOUT = 6A,
COUT = 5 x 10µF X5R or X7R
MLCC
<20 mV
Under Voltage Lockout
Under Voltage Lock
out threshold VUVLO VIN Increasing
VIN Decreasing 2.2
2.1 V
Switching Frequency
Switching
Frequency FSWITCH 5 MHz
Load Characteristics
Maximum
Continuous Output
Current
IOUT (Note 2) 6 A
Current Limit
Threshold IOCP_TH 9 A
Supply Current
Shut-Down Supply
Current IS ENABLE=0V 50 µA
Enable Operation
Disable Threshold VDISABLE Max voltage to ensure the
converter is disabled 0.8 V
Enable Threshold VENABLE 2.375V ≤ VIN ≤ 5.5V 1.8 V
Enable Pin Current IEN V
IN = 5.5V 50 µA
September 2007 EN5366QI
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PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Voltage Select Operation
Logic Low
Threshold VSX-Low Threshold voltage for Logic Low 0.8 V
Logic High
Threshold VSX-High
Threshold voltage for Logic High
(internally pulled high; can be left
floating to achieve logic high)
1.8 VIN V
VSx Pin Current IVSX
VIN = 5.5V
VSx = GND
VSx = VIN
VSx = Open
50
0
0
µA
Power OK Operation (Open Drain)
POK threshold High Percentage of VOUT Nominal 120 %
POK threshold low Percentage of VOUT Nominal 90 %
POK Low Voltage IPOK = 4 mA (Max sink Current) 0.4 V
POK High Voltage VIN %
Output Rise Time
VOUT Rise Time
Accuracy ∆TRISE
TRISE = Css* 75KΩ;
10nF ≤ CSS ≤30nF
(Note 3)
-25 +25 %
Parallel Operation
Current Balance ∆IOUT
With 2 – 4 converters in parallel,
the difference between any 2 parts.
∆VIN < 50mV; RTRACE < 10mΩ.
+/-10 %
NOTES:
2. Maximum output current may need to be de-rated, based on operating condition, to meet TJ requirements.
3. Parameter not production tested but is guaranteed by design. Rise time begins when AVIN > VUVLO and
Enable=HIGH.
Typical Performance Characteristics
50
55
60
65
70
75
80
85
90
95
00.511.522.533.544.555.5
Load Current (A)
Efficiency (%)
V
IN
=3.3V
V
OUT
=2.5V
V
OUT
=1.8V
V
OUT
=1.5V
V
OUT
=1.2V
50
55
60
65
70
75
80
85
90
95
00.511.522.533.544.555.5
Load Current (A)
Efficiency (%)
V
IN
=3.3V
V
OUT
=2.5V
V
OUT
=1.8V
V
OUT
=1.5V
V
OUT
=1.2V
Efficiency vs. Load, VIN = 3.3V.; Load = 0-6A. Efficiency vs. Load, VIN = 5.0V.; Load = 0-6A.
50
55
60
65
70
75
80
85
90
95
00.511.522.533.544.555.5
Load Current (A)
Efficiency (%)
V
IN
=5.0V
V
OUT
=3.3V
V
OUT
=2.5V
V
OUT
=1.8V
V
OUT
=1.5V
V
OUT
=1.2V
50
55
60
65
70
75
80
85
90
95
00.511.522.533.544.555.5
Load Current (A)
Efficiency (%)
V
IN
=5.0V
V
OUT
=3.3V
V
OUT
=2.5V
V
OUT
=1.8V
V
OUT
=1.5V
V
OUT
=1.2V
September 2007 EN5366QI
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8
Ripple Voltage, 5.0VIN/1.2VOUT, IOUT=6A, Ripple Voltage, 3.3VIN/1.2VOUT, IOUT=6A,
COUT = 5x10uF. COUT = 5x10uF.
Transient Response 5.5VIN/1.2VOUT, 0-6A, 10A/uS. Transient Response 5.5VIN/3.3VOUT, 0-6A, 10A/uS.
COUT=50uF. COUT=50uF
Start up waveforms VIN=5.0V, VOUT=1.2V, CSS=15nF, Start up waveforms VIN=5.0V, VOUT=3.3V, CSS=15nF,
Ch 1 = VOUT, Ch 3 = ENABLE, Ch 4 = POK. Ch 1 = VOUT, Ch 3 = ENABLE, Ch 4 = POK.
September 2007 EN5366QI
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9
Theory of Operation
Synchronous Buck Converter
The EN5366 is a synchronous, programmable
power supply with integrated power MOSFET
switches and integrated inductor. The nominal
input voltage range is 2.4-5.5V. The output
voltage is programmed using an external resistor
divider network. The feedback control loop is a
type III voltage-mode and the part uses a low-
noise PWM topology. Up to 6A of continuous
output current can be drawn from this converter.
The 5MHz operating frequency enables the use
of small-size input and output capacitors.
The power supply has the following protection
features:
• Programmable over-current protection (to
protect the IC from excessive load
current).
• Short Circuit protection.
• Thermal shutdown with hysteresis.
• Programmable over-voltage protection.
• Under-voltage lockout circuit to disable the
converter output when the input voltage is
less than approximately 2.2V
Additional features include:
• Soft-start circuit, to limit the in-rush current
when the converter is powered up.
• Power good circuit (POK) indicating
whether the output voltage is between
90% of nominal VOUT and the OVP trip
point.
Output Voltage Programming
The EN5366 output voltage is programmed using
a simple resistor divider network. Figure 4 shows
the resistor divider configuration.
The EN5366 output voltage and over voltage
thresholds are determined by the voltages
presented at the XFB and XOV pins respectively.
These voltages are set by way of resistor dividers
between VOUT and AGND with the midpoint going
to XFB and XOV.
It is recommended that Rb1 and Rb2 resistor
values be ~2kΩ. Use the following equation to
set the resistor Ra1 for the desired output
voltage:
V
RbVVout
Ra 75.0
1*)75.0(
1
−
=
If over-voltage protection is desired, use the
following equation to set the resistor Ra2 for the
desired OVP trip-point:
V
RbVOVPtrip
Ra 90.0
2*)90.0(
2
−
=
By design, if both resistor dividers are the same,
the OV trip-point will be 20% above the nominal
output voltage.
XFB
CSS
VOUT
POK
PGND
AGND
SS
PVIN
AVIN XOV
VOUT
VIN
47µF47µF
Ra1
Ra2
Rb1
Rb2
Figure 4. VOUT and OVP resistor divider networks.
Input Capacitor Selection
The EN5366QI requires between 40-80uF of
input capacitance. Low ESR ceramic capacitors
are required with X5R or X7R dielectric
formulation. Y5V or equivalent dielectric
formulations must not be used as these lose
capacitance with frequency, temperature and
bias voltage.
In some applications, lower value ceramic
capacitors maybe needed in parallel with the
larger capacitors in order to provide high
frequency decoupling.
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Table 1. Recommended input capacitors.
Description MFG P/N
22uF, 10V,
X5R, 1210 Murata GRM32ER71A226KE20L
Taiyo Yuden LMK325BJ226KM-T
47uF, 10V,
X5R, 1210 Murata GRM32ER71A476KE20L
Taiyo Yuden LMK325BJ476KM-T
Output Capacitor Selection
The EN5366QI has been optimized for use with
approximately 50µF of output capacitance. Low
ESR ceramic capacitors are required with X5R or
X7R dielectric formulation. Y5V or equivalent
dielectric formulations must not be used as these
lose capacitance with frequency, temperature
and bias voltage.
Table 2. Recommended output capacitors.
Description MFG P/N
10uF, 6.3V,
X5R, 1206 Murata GRM319R60J106KE19D
Taiyo Yuden LMK316BJ106KD-T
22uF, 6.3V,
X5R, 1206 Murata GRM31CR60J226KE19L
Taiyo Yuden LMK316BJ226KL-T
47uF, 6.3V,
X5R, 1206 Murata GRM31CR71A476ME19L
Taiyo Yuden LMK316BJ476KL-T
Output ripple voltage is primarily determined by
the aggregate output capacitor impedance. At
the 5MHz switching frequency output impedance,
denoted as Z, is comprised mainly of effective
series resistance, ESR, and effective series
inductance, ESL:
Z = ESR + ESL.
Placing output capacitors in parallel reduces the
impedance and will hence result in lower ripple
voltage.
nTotal ZZZZ
1
...
111
21
+++=
Typical ripple versus capacitor arrangement is
given below:
Table 3. Output ripple vs capacitor configuration.
Output Capacitor
Configuration
Typical Output Ripple (mVp-p)
(as measured on EN5366QI
Evaluation Board)
1 x 47uF <30
5 x 10 uF <20
Compensation
The EN5366 is internally compensated through
the use of a type 3 compensation network and is
optimized for use with about 50µF of output
capacitance and will provide excellent loop
bandwidth and transient performance for most
applications. Voltage mode operation provides
high noise immunity at light load. Further,
Voltage mode control provides superior
impedance matching to sub 90nm loads.
In some cases modifications to the compensation
may be required. The EN5366QI provides the
capability to modify the control loop to allow for
customization for a given application. For more
information, contact Enpirion Applications
Engineering support.
Enable Operation
The ENABLE pin provides a means to shut down
the device, or enable normal operation. A logic
low will disable the converter and cause it to shut
down. A logic high will enable the converter into
normal operation. When the ENABLE pin is
asserted high, the device will undergo a normal
soft start.
Soft-Start Operation
The SS pin in conjunction with a small capacitor
between this pin and AGND provides the soft
start function to limit the in-rush current during
start-up. During start-up of the converter the
reference voltage to the error amplifier is
gradually increased to its final level by an internal
current source of typically 10uA charging the soft
start capacitor. The typical soft-start time for the
output to reach regulation voltage, from when
AVIN > VUVLO and Enable crosses its logic high
threshold, is given by:
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11
TSS = CSS * 75KΩ (seconds)
Where the soft-start time TSS is in seconds and
the soft-start capacitance CSS is in Farads.
Typically, a capacitor of around 15 nF is
recommended.
During the soft-start cycle, when the soft-start
capacitor reaches 0.75V, the output has reached
its programmed regulation range. Note that the
soft-start current source will continue to operate,
and during normal operation, the soft-start
capacitor will charge up to a final value of 2.5V.
POK Operation
The POK signal is an open drain signal from the
converter indicating the output voltage is within
the specified range. The POK signal will be a
logic high when the output voltage is within 90% -
120% of the programmed output voltage. If the
output voltage goes outside of this range, the
POK signal will be a logic low until the output
voltage has returned to within this range. In the
event of an over-voltage condition the POK
signal will go low and will remain in this condition
until the output voltage has dropped to 95% of
the programmed output voltage before returning
to the high state.
The internal POK FET is designed to tolerate up
to 4mA. The pull-up resistor value should be
chosen to limit the current from exceeding this
value when POK is logic low.
Over-Current Protection
The current limit function is achieved by sensing
the current flowing through a sense P-MOSFET.
When the sensed current exceeds the current
limit, both NFET and PFET switches are turned
off. If the over-current condition is removed, the
over-current protection circuit will re-enable the
PWM operation. If the over-current condition
persists, the circuit will continue to protect the
load.
The OCP trip point is nominally set to 150% of
maximum rated load. For diagnostic purposes, it
is possible to increase the OCP trip point to
approximately 200% of the maximum rated load
by connecting a 10kΩ resistor between the
ROCP pin (pin 38) and AGND (pin 39). This is
intended for troubleshooting purposes only and
the specification is not guaranteed.
Over-Voltage Protection
When the output voltage exceeds 120% of the
programmed output voltage, the PWM operation
stops, the lower N-MOSFET is turned on and the
POK signal goes low. When the output voltage
drops below 95% of the programmed output
voltage, normal PWM operation resumes and
POK returns to its high state.
Thermal Overload Protection
Thermal shutdown will disable operation when
the Junction temperature exceeds approximately
150ºC. Once the junction temperature drops by
approx 20ºC, the converter will re-start with a
normal soft-start.
Input Under-Voltage Lock-Out
Circuitry is provided to ensure that when the
input voltage is below the required voltage level
(VUVLO) for normal operation, the converter will
not start-up. Circuits for hysteresis and input de-
glitch are included to ensure high noise immunity
and to prevent false tripping.
Parallel Device Operation
The EN5366QI is capable of paralleling up to a
total of four converters to provide up to 24A of
continuous current. Please refer to the Parallel
Operation Application note, available on the
Enpirion website www.enpirion.com, for details
on parallel operation.
September 2007 EN5366QI
©Enpirion 2007 all rights reserved, E&OE www.enpirion.com
12
Layout Recommendations
Slit separating
input local ground
from output
local ground
V
OUT
(+)
Copper
V
IN
(+)
Copper
Local
Ground
Copper
Slit separating
input local ground
from output
local ground
V
OUT
(+)
Copper
V
IN
(+)
Copper
Local
Ground
Copper
Figure 5. Layout of power and ground copper. Figure 6. Use of thermal & noise suppression vias.
Recommendation 1: Input and output filter
capacitors should be placed as close to the
EN5366QI package as possible to reduce EMI
from input and output loop currents. This
reduces the physical area of the Input and
Output AC current loops.
Recommendation 2: Place a slit in the
input/output capacitor ground copper starting
just below the common connection point of the
device GND pins as shown in figures 5 and 6.
Recommendation 3: The large thermal pad
underneath the component must be connected
to the system ground plane through as many
vias as possible. The drill diameter of the vias
should be less than 0.33mm, and the vias must
have at least 1 oz. copper plating on the inside
wall, making the finished hole size around
0.26mm. This connection provides the path for
heat dissipation from the converter. Please see
figures 6, 7, and 8.
Recommendation 4: Multiple small vias
should be used to connect ground terminal of
the input capacitor and output capacitors to the
system ground plane as shown in figure 6.
These vias can be the same size as the
thermal vias discussed in recommendation 3.
Recommendation 5: The system ground
plane referred to in recommendations 3 and 4
should be the first layer immediately below the
surface layer. This ground plane should be
continuous and un-interrupted below the
converter and the input/output capacitors
shown in figure 6.
Recommendation 6: As with any switch-mode
DC/DC converter, do not run sensitive signal or
control lines underneath the converter
package.
Please refer to the Gerber files and
summarized layout notes available on the
Enpirion website www.enpirion.com for more
layout details.
NOTE: Figures 5 and 6 show only the critical
components and traces for a minimum footprint
layout. ENABLE, Vout-programming, and
other small signal pins need to be connected
and routed according to the specific
application.
Compensation
Test Points
AGND
Test
Points
Thermal Pad
Vias and
Soldermask
Opening
High-Frequency
Noise Suppression
Vias
Vout
PGND
Copper
Slit
Vin
Compensation
Test Points
AGND
Test
Points
Thermal Pad
Vias and
Soldermask
Opening
High-Frequency
Noise Suppression
Vias
Vout
PGND
Copper
Slit
Vin
September 2007 EN5366QI
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13
Design Considerations for Lead-Frame Based Modules
Exposed Metal on Bottom Of Package
Lead frame offers many advantages in thermal performance, in reduced electrical lead resistance, ,
and in overall foot print. However, they do require some special considerations.
In the assembly process lead frame construction requires that, for mechanical support, some of the
lead-frame cantilevers be exposed at the point where wire-bond or internal passives are attached.
This results in several small pads being exposed on the bottom of the package.
Only the large thermal pad and the perimeter pads are to be mechanically or electrically connected to
the PC board. The PCB top layer under the EN5366QI should be clear of any metal except for the
large thermal pad. The “grayed-out” area in Figure 7 represents the area that should be clear of any
metal (traces, vias, or planes), on the top layer of the PCB.
Figure 8 demonstrates the recommended PCB footprint for the EN5366QI. Figure 9 shows the shape
and location of the exposed metal pads as well as the mechanical dimension of the large thermal pad
and the pins.
Ground copper my extend under this pad.
However, DO NOT CONNECT (NC)
Ground copper my extend under this pad.
However, DO NOT CONNECT (NC)
Figure 7. Lead-Frame exposed metal. Grey area highlights exposed metal that is not to be mechanically or
electrically connected to the PCB.
September 2007 EN5366QI
©Enpirion 2007 all rights reserved, E&OE www.enpirion.com
14
Figure 8. Recommended footprint for PCB.
September 2007 EN5366QI
©Enpirion 2007 all rights reserved, E&OE www.enpirion.com
15
Package Dimensions
Figure 9. Package dimensions.
September 2007 EN5366QI
©Enpirion 2007 all rights reserved, E&OE www.enpirion.com
16
TAPE AND REEL SPECIFICATION
Additional Products
Part Number Description
EP5352QI 500mA DCDC with integrated inductor; 5mm x 4mm x 1.1mm package
EP5362QI 600mA DCDC with integrated inductor; 5mm x 4mm x 1.1mm package
EP5382QI 800mA DCDC with integrated inductor; 5mm x 4mm x 1.1mm package
EQ5352DI 500mA DCDC regulator; tiny 3mm x 2mm x 0.9mm DFN package
EQ5362DI 600mA DCDC regulator; tiny 3mm x 2mm x 0.9mm DFN package
EQ5382DI 800mA DCDC regulator; tiny 3mm x2mm x0.9mm DFN package
EN5312QI 1A DCDC with integrated inductor; 5mm x 4mm x 1.1mm package
EN5335QI 3A DCDC with integrated inductor; 10mm x 7.5mm x 1.85mm QFN package
3-Pin VID VOUT programming
EN5336QI 3A DCDC with integrated inductor; 10mm x 7.5mm x 1.85mm QFN package
External resistor divider VOUT programming
EN5365QI 6A DCDC with integrated inductor; 12mm x 10mm x 1.85mm QFN package
3-Pin VID VOUT programming; Parallel Capable
September 2007 EN5366QI
©Enpirion 2007 all rights reserved, E&OE www.enpirion.com
17
Contact Information
Enpirion, Inc.
685 Route 202/206
Suite 305
Bridgewater, NJ 08807
Phone: 908-575-7550
Fax: 908-575-0775
Enpirion reserves the right to make changes in circuit design and/or specifications at any time without notice. Information furnished by Enpirion is
believed to be accurate and reliable. Enpirion assumes no responsibility for its use or for infringement of patents or other third party rights, which may
result from its use. Enpirion products are not authorized for use in nuclear control systems, as critical components in life support systems or equipment
used in hazardous environment without the express written authority from Enpirion.
