54ABT16373 16-Bit Transparent Latch with TRI-STATE (R) Outputs General Description Features The ABT16373 contains sixteen non-inverting latches with TRI-STATE outputs and is intended for bus oriented applications. The device is byte controlled. The flip-flops appear transparent to the data when the Latch Enable (LE) is HIGH. When LE is low, the data that meets the setup time is latched. Data appears on the bus when the Output Enable (OE) is LOW. When OE is HIGH, the outputs are in high Z state. n Separate control logic for each byte n 16-bit version of the ABT373 n High impedance glitch free bus loading during entire power up and power down cycle n Non-destructive hot insertion capability n Guaranteed latch-up protection n Standard Microcircuit Drawing (SMD) 5962-9320001 Ordering Code: Military Package Package Description Number 54ABT16373W-QML WA48A 48-Lead Cerpack Logic Symbol Connection Diagram Pin Assignment for Cerpack DS100201-1 Pin Description Pin Names Description OEn Output Enable Input (Active Low) LEn Latch Enable Input D0-D15 Data Inputs O0-O15 Outputs DS100201-2 TRI-STATE (R) is a registered trademark of National Semiconductor Corporation. (c) 1998 National Semiconductor Corporation DS100201 www.national.com 54ABT16373 16-Bit Transparent Latch with TRI-STATE Outputs July 1998 Functional Description Truth Tables The ABT16373 contains sixteen D-type latches with TRI-STATE standard outputs. The device is byte controlled with each byte functioning identically, but independent of the other. Control pins can be shorted together to obtain full 16-bit operation. The following description applies to each byte. When the Latch Enable (LEn) input is HIGH, data on the Dn enters the latches. In this condition the latches are transparent, i.e., a latch output will change states each time its D input changes. When LEn is LOW, the latches store information that was present on the D inputs a setup time preceding the HIGH-to-LOW transition of LEn. The TRI-STATE standard outputs are controlled by the Output Enable (OEn) input. When OEn is LOW, the standard outputs are in the 2-state mode. When OEn is HIGH, the standard outputs are in the high impedance mode but this does not interfere with entering new data into the latches. Inputs Outputs LE1 OE1 D0-D7 O0-O7 X H X Z H L L L H L H H L X (Previous) L Inputs Outputs LE2 OE2 D8-D15 O8-O15 X H X Z H L L L H L H H L L X (Previous) H = High Voltage Level L = Low Voltage Level X = Immaterial Z = High Impedance Previous = previous output prior to HIGH to LOW transition of LE Logic Diagrams DS100201-3 DS100201-4 www.national.com 2 Absolute Maximum Ratings (Note 1) (Across Comm Operating Range) Other Pins Over Voltage Latchup (I/O) Storage Temperature -65C to +150C Ambient Temperature under Bias -55C to +125C Junction Temperature under Bias Ceramic -55C to +175C VCC Pin Potential to Ground Pin -0.5V to +7.0V Input Voltage (Note 2) -0.5V to +7.0V Input Current (Note 2) -30 mA to +5.0 mA Voltage Applied to Any Output in the Disabled or Power-Off State -0.5V to +5.5V in the HIGH State -0.5V to VCC Current Applied to Output in LOW State (Max) twice the rated IOL (mA) -350 mA DC Latchup Source Current: OE Pin -500 mA 10V Recommended Operating Conditions Free Air Ambient Temperature Military Supply Voltage Military Minimum Input Edge Rate Data Input Enable Input -55C to +125C +4.5V to +5.5V (V/t) 50 mV/ns 20 mV/ns Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs. DC Electrical Characteristics Symbol Parameter ABT16373 Units VCC Conditions Min Typ Max VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage VOL Output LOW Voltage IIH Input HIGH Current 2.0 54ABT 2.5 54ABT 2.0 V 54ABT 0.8 V -1.2 V Recognized HIGH Signal Min Recognized LOW Signal IIN = -18 mA IOH = -3 mA IOH = -24 mA IOL = 48 mA 0.55 V Min 5 A Max 5 IBVI Input HIGH Current Breakdown Test 7 A Max IIL Input LOW Current -5 A Max V 0.0 -5 VID Input Leakage Test 4.75 VIN = 2.7V (Note 4) VIN = VCC VIN = 7.0V VIN = 0.5V (Note 4) VIN = 0.0V IID = 1.9 A All Other Pins Grounded VOUT = 2.7V; OE = 2.0V IOZH Output Leakage Current 50 A 0 - 5.5V IOZL Output Leakage Current -50 A 0 - 5.5V IOS Output Short-Circuit Current -275 mA Max ICEX Output High Leakage Current 50 A Max IZZ Bus Drainage Test 100 A 0.0 VOUT = 0.5V; OE = 2.0V VOUT = 0.0V VOUT = VCC VOUT = 5.5V; All Others GND ICCH Power Supply Current 2.0 mA Max All Outputs HIGH ICCL Power Supply Current 85 mA Max ICCZ Power Supply Current 2.0 mA Max All Outputs LOW OE = VCC ICCT Additional ICC/Input Outputs Enabled 2.5 mA Outputs TRI-STATE 2.5 mA Outputs TRI-STATE 2.5 mA ICCD Dynamic ICC -100 No Load mA/ (Note 4) 0.15 MHz All Others at VCC or GND VI = VCC - 2.1V Max Max Enable Input VI = VCC - 2.1V Data Input VI = VCC - 2.1V All Others at VCC or GND Outputs Open, LE = VCC OE = GND, (Note 3) One Bit Toggling, 50% Duty Cycle Note 3: For 8 bits toggling, ICCD < 0.8 mA/MHz. Note 4: Guaranteed, but not tested. 3 www.national.com AC Electrical Characteristics Symbol Parameter 54ABT TA = -55C to +125C VCC = 4.5V to 5.5V Units CL = 50 pF Min Max tPLH Propagation Delay 1.4 6.5 tPHL Dn to On 1.4 6.5 tPLH Propagation Delay 1.7 7.0 tPHL LE to On 1.4 6.3 tPZH Output Enable Time tPZL tPHZ Output Disable Time tPLZ 1.1 6.8 1.5 6.8 1.5 8.5 1.6 8.0 ns ns ns ns AC Operating Requirements Symbol Parameter 54ABT TA = -55C to +125C VCC = 4.5V to 5.5V Units CL = 50 pF Min ts(H) Setup Time, HIGH 2.4 ts(L) or LOW Dn to LE 2.4 th(H) Hold Time, HIGH 2.2 th(L) or LOW Dn to LE 2.2 Pulse Width, 3.3 tw(H) LE HIGH Capacitance Symbol Parameter Typ Units CIN Input Capacitance 5 pF Conditions (TA = 25C) VCC = 0V COUT (Note 5) Output Capacitance 11 pF VCC = 5.0V Note 5: COUT is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. www.national.com 4 Max ns ns ns AC Loading DS100201-6 *Includes jig and probe capacitance DS100201-11 FIGURE 1. Standard AC Test Load FIGURE 5. Propagation Delay, Pulse Width Waveforms DS100201-7 DS100201-10 FIGURE 6. TRI-STATE Output HIGH and LOW Enable and Disable Times FIGURE 2. Test Input Signal Levels Amplitude Rep. Rate tw tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements DS100201-9 FIGURE 7. Setup Time, Hold Time and Recovery Time Waveforms DS100201-8 FIGURE 4. Propagation Delay Waveforms for Inverting and Non-Inverting Functions 5 www.national.com 54ABT16373 16-Bit Transparent Latch with TRI-STATE Outputs Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead Cerpack NS Package Number WA48A LIFE SUPPORT POLICY NATIONAL'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and whose faildevice or system, or to affect its safety or effectiveness. ure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 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