LT1997-2
1
Rev 0
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TYPICAL APPLICATION
FEATURES DESCRIPTION
Precision, Wide Voltage
Range, Gain Selectable
Funnel Amplifier
The LT
®
1997-2 is an attenuating (funnel) difference ampli-
fier that can be used to translate large differential signals to
the low voltage range compatible with ADCs. It combines
a precision operational amplifier with highly-matched re-
sistors to form a one-chip solution to attenuate and level
shift voltages accurately using no external components.
It comes with three standard pin-selectable gain options
(0.1, 0.2 and 0.25), which can be further combined to
form gains from 0.0455 to 0.55 (attenuations of 1.82 to
22) with accuracy of 0.006% (60ppm). The LT1997-2 also
works across a very wide input common-mode voltage
range (±255V), enabling robust operation in demanding
industrial environments. Its excellent resistor matching
results in a common mode rejection ratio of greater than
105dB.
The resistors maintain their excellent matching over
temperature; the matching temperature coefficient is
guaranteed less than 1ppm/°C. The resistors are extremely
linear with voltage, resulting in a gain nonlinearity of less
than 2ppm.
The LT1997-2 is fully specified at 5V and ±15V supplies
and from –40°C to 125°C. The device is available in space
saving 16-lead MSOP and 4mm × 4mm DFN14 packages.
Interfacing a 20VP-P Ground-Referenced Input Signal to a 5V ADC LT1997-2 Driving LTC2364-16,
ADC, fIN = 1kHz, 32768-Point FFT
n Precision Attenuation: Gain = 0.1, 0.2, 0.25
n ±255V Common Mode Voltage Range
n 105dB Minimum CMRR (Gain = 0.1)
n 0.006% (60ppm) Maximum Gain Error
n 1ppm/°C Maximum Gain Error Drift
n 2ppm Maximum Gain Nonlinearity
n Wide Supply Voltage Range: 3.3V to 50V
n Rail-to-Rail Output
n 350µA Supply Current
n 80µV Maximum Op Amp Offset Voltage
n 1MHz –3dB Bandwidth (Gain=0.1)
n Low Power Shutdown: 20µA
n Space-Saving MSOP and DFN Packages
All registered trademarks and trademarks are the property of their respective owners.
APPLICATIONS
n High Voltage to Low Voltage Level Translation
n ADC Driver
n Bidirectional Wide Common Mode Range Voltage
and Current Sensing
n Industrial Data-Acquisition Front-Ends
n Replacement for Isolation Circuits
n Differential to Single-Ended Conversion
19972 TA01a
OUT
REF1
IN+
IN–
200Ω
8nF
IN OUT
GND
LT6657-5
VDD
LTC2364-16
0VDD
2.5V
1.8V TO 5V
REF GND
50k
REF2
250k
250k
100k
125k 50k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
5V
–
+
LT1997-2
+10V
–10V
47µF
5.5V TO 40V
5V
4.5V
0.5V
V
S
= 5V
V
OUT
= 4VP-P
HD2 = –104.3dBc
HD3 = –104.4dBc
SFDR = 104.3dB
SNR = 91.8dB
SINAD = 89.5dB
FREQUENCY (kHz)
0
25
50
75
100
125
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE (dBFS)
19972 TA01b
LT1997-2
2
Rev 0
For more information www.analog.com
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS
Supply Voltages (V+ to V–) ........................................ 60V
+INA, –INA, +INB, –INB,
+INC, –INC (Note 2) ......................................... V– ±270V
REF, REF1, REF2..................... (V– + 60V) to (V– – 0.3V)
SHDN ..................................... (V+ + 0.3V) to (V– – 0.3V)
Output Current (Continuous) (Note 6) ....................50mA
Output Short-Circuit Duration
(Note 3) ..........................................Thermally Limited
(Note 1)
1
3
4
5
6
7
+INA
+INB
NC
+INC
SHDN
REF
–INA
–INB
NC
–INC
V+
OUT
15
V–
14
12
11
10
9
8
TOP VIEW
DF PACKAGE
14(12)-LEAD (4mm × 4mm) PLASTIC DFN
TJMAX = 150°C, θJA = 45°C/W , θJC = 3°C/W
EXPOSED PAD (PIN 15) IS V–, MUST BE SOLDERED TO PCB
1
3
5
6
7
8
+INA
+INB
+INC
REF1
REF2
V–
16
14
12
11
10
9
–INA
–INB
–INC
V+
SHDN
OUT
TOP VIEW
MS PACKAGE
VARIATION: MS16 (12)
16-LEAD PLASTIC MSOP
TJMAX = 150°C, θJA = 130°C/W
ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION SPECIFIED
TEMPERATURE RANGE
LT1997IDF-2#PBF LT1997IDF-2#TRPBF 19972 14-Lead (4mm × 4mm) Plastic DFN –40°C to 85°C
LT1997HDF-2#PBF LT1997HDF-2#TRPBF 19972 14-Lead (4mm × 4mm) Plastic DFN –40°C to 125°C
LT1997IMS-2#PBF LT1997IMS-2#TRPBF 19972 16-Lead Plastic MSOP –40°C to 85°C
LT1997HMS-2#PBF LT1997HMS-2#TRPBF 19972 16-Lead Plastic MSOP –40°C to 125°C
*The temperature grade is identified by a label on the shipping container. Consult ADI Marketing for parts specified with wider operating temperature ranges.
Parts ending with PBF are RoHS and WEEE compliant.
Tape and reel specifications. Some packages are available in 500 unit reels through designated sales channels with #TRMPBF suffix.
Temperature Range (Notes 4, 5)
LT1997I-2.................................................–40 to 85°C
LT1997H-2 ............................................. –40 to 125°C
Maximum Junction Temperature .......................... 150°C
Storage Temperature Range ......................–65 to 150°C
MSOP Lead Temperature (Soldering, 10 sec) ........300°C
LT1997-2
3
Rev 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
∆G Gain Error VOUT=±2.8V
G=0.1
l
±0.001 ±0.006
±0.008
%
%
VOUT=±5.6V
G=0.2
l
±0.001 ±0.006
±0.008
%
%
VOUT=±7V
G=0.25
l
±0.001 ±0.006
±0.008
%
%
∆G/∆T Gain Drift vs Temperature (Note 6) VOUT=±7V l±0.2 ±1 ppm/°C
GNL Gain Nonlinearity VOUT=±7V
l
±1 ±2
±3
ppm
ppm
VOS Op Amp Offset Voltage (Note 9) V– < VCMOP < V+ – 1.75V
l
±20 ±80
±200
µV
µV
∆VOS/∆T Op Amp Offset Voltage Drift (Note 6) V– < VCMOP < V+ – 1.75V l±0.5 ±1.5 µV/°C
IBOp Amp Input Bias Current V– + 0.25V < VCMOP < V+ – 1.75V
l
–5
–15
±2 5
15
nA
nA
IOS Op Amp Input Offset Current V– + 0.25V < VCMOP < V+ – 1.75V
l
–3
–10
±0.5 3
10
nA
nA
RIN Input Impedance (Note 8) Common Mode
G=0.1
G=0.2
G=0.25
l
l
l
115
63
52
137.5
75
62.5
160
87
73
kΩ
kΩ
kΩ
Differential
G=0.1
G=0.2
G=0.25
l
l
l
420
210
168
500
250
200
580
290
232
kΩ
kΩ
kΩ
CMRR Common Mode Rejection Ratio,
Referred to Output, MS16 Package
G = 0.1, VCM = ±28V
l
105
103
120 dB
dB
G = 0.2, VCM = ±28V
l
101
99
118 dB
dB
G = 0.25, VCM = ±28V
l
101
98
118 dB
dB
CMRR Common Mode Rejection Ratio,
Referred to Output, DF14 Package
G = 0.1, VCM = ±28V
l
103
101
118 dB
dB
G = 0.1, VCM = ±255V, VS = ±25V
l
103
101
118 dB
dB
G = 0.2, VCM = ±28V
l
99
97
116 dB
dB
G = 0.2, VCM = ±140V, VS = ±25V
l
99
97
116 dB
dB
G = 0.25, VCM = ±28V
l
99
97
116 dB
dB
G = 0.25, VCM = ±115V, VS = ±25V
l
99
97
116 dB
dB
VCM Input Voltage Range (Note 7) +INA/–INA
+INB/–INB
+INC/–INC
l
l
l
–255
–140
–115
255
140
115
V
V
V
The l denotes the specifications which apply over the full operating
temperature range, –40°C < TA < 85°C for I-grade parts, –40°C < TA < 125°C for H-grade parts, otherwise specifications are at
TA=25°C. Difference Amplifier Configuration, V+ = 15V, V– = –15V, VCM = VOUT = VREF = VREF1 = VREF2 = 0V. VCMOP is the common
mode voltage of the internal op amp.
LT1997-2
4
Rev 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
∆R/R Reference Divider Matching Error
∆R
R=
R
REF1
– R
REF2
RREF1 +RREF2
2
⎛
⎝
⎜⎞
⎠
⎟
Available in MS16 Package Only
l
±0.002 ±0.009
±0.011
%
%
PSRR Power Supply Rejection Ratio (Note 9) VS=±1.65V to ±25V, VCM=VOUT=Mid-Supply l114 124 dB
eni Output Noise Voltage Density f=1kHz
G=0.1
G=0.2
G=0.25
37
39
40
nV/√Hz
nV/√Hz
nV/√Hz
Output Noise Voltage f=0.1Hz to 10Hz
G=0.1
G=0.2
G=0.25
0.9
0.95
1
µVP-P
µVP-P
µVP-P
VOL Output Voltage Swing Low (Referred
to V–)
No Load
ISINK=5mA
l
l
50
280
150
500
mV
mV
VOH Output Voltage Swing High (Referred
to V+)
No Load
ISOURCE=5mA
l
l
50
450
150
900
mV
mV
ISC Short-Circuit Output Current 50Ω to V+
50Ω to V–
l
l
10
10
30
32
mA
mA
SR Slew Rate ∆VOUT=±7V l0.45 0.75 V/µs
BW Small Signal –3dB Bandwidth G=0.1
G=0.2
G=0.25
1
1.2
1.1
MHz
MHz
MHz
tSSettling Time G=0.1
0.1%, ∆VOUT=10V
0.01%, ∆VOUT=10V
15
19
µs
µs
G=0.2
0.1%, ∆VOUT=10V
0.01%, ∆VOUT=10V
16.9
20.6
µs
µs
G=0.25
0.1%, ∆VOUT=10V
0.01%, ∆VOUT=10V
17.1
20.9
µs
µs
VSSupply Voltage
l
3
3.3
50
50
V
V
tON Turn-On Time 16 µs
VIL SHDN Input Logic Low (Referred to V+) l–2.5 V
VIH SHDN Input Logic High (Referred to V+)l–1.2 V
ISHDN SHDN Pin Current l–10 –15 µA
ISSupply Current Active, VSHDN ≥ V+ – 1.2V
Active, VSHDN ≥ V+ – 1.2V
Shutdown, VSHDN ≤ V+ – 2.5V
Shutdown, VSHDN ≤ V+ – 2.5V
l
l
350
20
400
600
25
70
µA
µA
µA
µA
The l denotes the specifications which apply over the full operating
temperature range, –40°C < TA < 85°C for I-grade parts, –40°C < TA < 125°C for H-grade parts, otherwise specifications are at
TA=25°C. Difference Amplifier Configuration, V+ = 15V, V– = –15V, VCM = VOUT = VREF = VREF1 = VREF2 = 0V. VCMOP is the common
mode voltage of the internal op amp.
LT1997-2
5
Rev 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, –40°C < TA < 85°C for I-grade parts, –40°C < TA < 125°C for H-grade parts, otherwise specifications are at
TA=25°C. Difference Amplifier Configuration, V+ = 5V, V– = 0V, VCM = VOUT = VREF = VREF1 = VREF2 = Mid-Supply. VCMOP is the
common mode voltage of the internal op amp.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
∆G Gain Error VOUT=1V to 4V
G=0.1
l
±0.001
±0.006
±0.008
%
%
G=0.2
l
±0.001 ±0.006
±0.008
%
%
G=0.25
l
±0.001 ±0.006
±0.008
%
%
∆G/∆T Gain Drift vs Temperature (Note 6) VOUT=1V to 4V l±0.2 ±1 ppm/°C
GNL Gain Nonlinearity VOUT=1V to 4V ±1 ppm
VOS Op Amp Offset Voltage (Note 9) V–<VCMOP<V+ – 1.75V
l
±20 ±80
±200
µV
µV
∆VOS/∆T Op Amp Offset Voltage Drift (Note 6) V–<VCMOP<V+ – 1.75V l±0.5 ±1.5 µV/°C
IBOp Amp Input Bias Current V– + 0.25V<VCMOP<V+ – 1.75V
l
–5
–15
±2 5
15
nA
nA
IOS Op Amp Input Offset Current V– + 0.25V<VCMOP<V+ – 1.75V
l
–3
–10
±0.5 3
10
nA
nA
RIN Input Impedance (Note 8) Common Mode
G=0.1
G=0.2
G=0.25
l
l
l
115
63
52
137.5
75
62.5
160
87
73
kΩ
kΩ
kΩ
Differential
G=0.1
G=0.2
G=0.25
l
l
l
420
210
168
500
250
200
580
290
232
kΩ
kΩ
kΩ
CMRR Common Mode Rejection Ratio, Referred to
Output, MS16 Package
G=0.1, VCM = –25V to 10.75V
l
104
102
120 dB
dB
G=0.2, VCM = –12.5V to 7V
l
100
98
118 dB
dB
G=0.25, VCM = –10V to 6.25V
l
100
98
118 dB
dB
CMRR Common Mode Rejection Ratio, Referred to
Output, DF14 Package
G=0.1, VCM = –25V to 10.75V
l
102
100
118 dB
dB
G=0.2, VCM = –12.5V to 7V
l
98
96
116 dB
dB
G=0.25, VCM = –10V to 6.25V
l
98
96
116 dB
dB
∆R/R Reference Divider Matching Error
∆R
R=
R
REF1
– R
REF2
RREF1 +RREF2
2
⎛
⎝
⎜⎞
⎠
⎟
Available in MS16 Package Only
l
±0.002 ±0.009
±0.011
%
%
PSRR Power Supply Rejection Ratio (Note 9) VS=±1.65V to ±25V, VCM=VOUT=Mid-Supply l114 124 dB
eni Output Noise Voltage Density f=1kHz
G=0.1
G=0.2
G=0.25
37
39
40
nV/√Hz
nV/√Hz
nV/√Hz
LT1997-2
6
Rev 0
For more information www.analog.com
ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Output Noise Voltage f=0.1Hz to 10Hz
G=0.1
G=0.2
G=0.25
0.9
0.95
1
µVP-P
µVP-P
µVP-P
VOL Output Voltage Swing Low (Referred to V–) No Load
ISINK=5mA
l
l
15
280 50
500 mV
mV
VOH Output Voltage Swing High (Referred to V+) No Load
ISOURCE=5mA
l
l
15
450 50
800 mV
mV
ISC Short-Circuit Output Current 50Ω to V+
50Ω to V–
l
l
10
10 30
28 mA
mA
SR Slew Rate ∆VOUT=3V l0.45 0.75 V/µs
BW Small signal –3dB Bandwidth G=0.1
G=0.2
G=0.25
1
1.2
1.1
MHz
MHz
MHz
tSSettling Time G=0.1
0.1%, ∆VOUT=2V
0.01%, ∆VOUT=2V
7.5
11.7
µs
µs
G=0.2
0.1%, ∆VOUT=2V
0.01%, ∆VOUT=2V
8.8
13.1
µs
µs
G=0.25
0.1%, ∆VOUT=2V
0.01%, ∆VOUT=2V
8.7
12.7
µs
µs
VSSupply Voltage
l
3
3.3 50
50 V
V
tON Turn-On Time 22 µs
VIL SHDN Input Logic Low (Referred to V+) l–2.5 V
VIH SHDN Input Logic High (Referred to V+)l–1.2 V
ISHDN SHDN Pin Current l–10 –15 µA
ISSupply Current Active, VSHDN ≥ V+ – 1.2V
Active, VSHDN ≥ V+ –1.2V
Shutdown, VSHDN ≤ V+ – 2.5V
Shutdown, VSHDN ≤ V+ – 2.5V
l
l
330
15
370
525
20
40
µA
µA
µA
µA
The l denotes the specifications which apply over the full operating
temperature range, –40°C < TA < 85°C for I-grade parts, –40°C < TA < 125°C for H-grade parts, otherwise specifications are at
TA=25°C. Difference Amplifier Configuration, V+ = 5V, V– = 0V, VCM = VOUT = VREF = VREF1 = VREF2 = Mid-Supply. VCMOP is the
common mode voltage of the internal op amp.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: See Common Mode Voltage Range in the Applications Information
section of this data sheet for other considerations when taking +INA/
–INA/+INB/–INB/+INC/–INC pins to ±270V.
Note 3: A heat sink may be required to keep the junction temperature
below absolute maximum. This depends on the power supply, input
voltages and the output current.
Note 4: The LT1997I-2 is guaranteed functional over the operating
temperature range of –40°C to 85°C. The LT1997H-2 is guaranteed
functional over the operating temperature range of –40°C to 125°C.
Note 5: The LT1997I-2 is guaranteed to meet specified performance
from –40°C to 85°C. The LT1997H-2 is guaranteed to meet specified
performance from –40°C to 125°C.
Note 6: This parameter is not 100% tested.
Note 7: The input voltage range is guaranteed by the ±25V CMRR tests.
The Input Voltage Range numbers specified in the table guarantee that the
internal op amp operates in its normal operating region. The Input voltage
range can be higher if the internal op amp operates in its Over-The-Top
®
operating region. See Common Mode Voltage Range in the Applications
Information section to determine the valid input voltage range under
various operating conditions.
Note 8: Input impedance is tested by a combination of direct
measurements and correlation to the CMRR and gain error tests.
Note 9: Offset voltage, offset voltage drift and PSRR are defined as
referred to the internal op amp. The following shows the calculation of
output offset: In the case of balanced source resistance, VOS,OUT = (VOS
• NOISEGAIN) + (IOS • 25k) + (IB • 25k • (1– RP/RN)) where RP and RN
are the total resistance at the op amp positive and negative terminal,
respectively.
LT1997-2
7
Rev 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Typical Distribution of CMRR,
Referred to Output (G=0.1)
Typical Distribution of CMRR,
Referred to Output (G=0.1)
Typical Distribution of CMRR,
Referred to Output (G=0.1)
Typical Distribution of CMRR,
Referred to Output (G=0.2)
Typical Distribution of CMRR,
Referred to Output (G = 0.2)
Typical Distribution of CMRR,
Referred to Output (G = 0.2)
TA = 25°C, VS=±15V, Difference Amplifier
configuration, unless otherwise noted.
Typical Distribution of CMRR,
Referred to Output (G = 0.25)
Typical Distribution of CMRR,
Referred to Output (G = 0.25)
Typical Distribution of CMRR,
Referred to Output (G = 0.25)
693 UNITS
FROM 2 RUNS
DF14(12)
V
S
= ±25V
V
CM
= ±255V
CMRR (µV/V = ppm)
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
0
25
50
75
100
125
150
NUMBER OF UNITS
19972 G01
714 UNITS
FROM 2 RUNS
DF14(12)
V
S
= ±15V
V
CM
= ±28V
CMRR (µV/V = ppm)
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
0
25
50
75
100
125
150
NUMBER OF UNITS
19972 G02
715 UNITS
FROM 2 RUNS
MS16(12)
V
S
= ±15V
V
CM
= ±28V
CMRR (µV/V = ppm)
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
0
25
50
75
100
125
150
NUMBER OF UNITS
19972 G03
693 UNITS
FROM 2 RUNS
DF14(12)
V
S
= ±25V
V
CM
= ±140V
CMRR (µV/V = ppm)
–10
–8
–6
–4
–2
0
2
4
6
8
10
0
25
50
75
100
125
150
NUMBER OF UNITS
19972 G04
714 UNITS
FROM 2 RUNS
DF14(12)
V
S
= ±15V
V
CM
= ±28V
CMRR (µV/V = ppm)
–10
–8
–6
–4
–2
0
2
4
6
8
10
0
25
50
75
100
125
150
NUMBER OF UNITS
19972 G05
715 UNITS
FROM 2 RUNS
MS16(12)
V
S
= ±15V
V
CM
= ±28V
CMRR (µV/V = ppm)
–10
–8
–6
–4
–2
0
2
4
6
8
10
0
25
50
75
100
125
150
NUMBER OF UNITS
19972 G06
693 UNITS
FROM 2 RUNS
DF14(12)
V
S
= ±25V
V
CM
= ±115V
CMRR (µV/V = ppm)
–10
–8
–6
–4
–2
0
2
4
6
8
10
0
25
50
75
100
125
150
NUMBER OF UNITS
19972 G07
715 UNITS
FROM 2 RUNS
MS16(12)
V
S
= ±15V
V
CM
= ±28V
CMRR (µV/V = ppm)
–10
–8
–6
–4
–2
0
2
4
6
8
10
0
25
50
75
100
125
150
NUMBER OF UNITS
19972 G09
714 UNITS
FROM 2 RUNS
DF14(12)
V
S
= ±15V
V
CM
= ±28V
CMRR (µV/V = ppm)
–10
–8
–6
–4
–2
0
2
4
6
8
10
0
25
50
75
100
125
150
NUMBER OF UNITS
19972 G08
LT1997-2
8
Rev 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Typical Distribution of Gain Error
(G = 0.1)
Typical Distribution of Gain Error
(G = 0.2)
Typical Distribution of Gain Error
(G = 0.25)
Typical Distribution of Op Amp
PSRR
Typical Distribution of Gain
Nonlinearity
Typical Distribution of Op Amp
Offset Voltage
TA = 25°C, VS=±15V, Difference Amplifier
configuration, unless otherwise noted.
1459 UNITS
FROM 4 RUNS
BOTH PACKAGES
V
S
= ±15V
V
OUT
= ±5.6V
GAIN ERROR (ppm)
–60
–40
–20
0
20
40
60
0
25
50
75
100
125
150
175
200
NUMBER OF UNITS
19972 G11
1459 UNITS
FROM 4 RUNS
BOTH PACKAGES
V
S
= ±15V
V
OUT
= ±7V
GAIN ERROR (ppm)
–60
–40
–20
0
20
40
60
0
25
50
75
100
125
150
175
200
225
250
NUMBER OF UNITS
19972 G12
1459 UNITS
FROM 4 RUNS
BOTH PACKAGES
V
S
= ±15V
V
OUT
= ±7V
G = 0.25
GAIN NONLINEARITY (ppm)
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
0
25
50
75
100
125
150
175
200
225
250
NUMBER OF UNITS
19972 G13
1459 UNITS
FROM 4 RUNS
BOTH PACKAGES
OFFSET VOLTAGE (µV)
–60
–40
–20
0
20
40
60
0
25
50
75
100
125
150
175
200
NUMBER OF UNITS
19972 G14
1459 UNITS
FROM 4 RUNS
BOTH PACKAGES
V
S
= ±1.65V to ±25V
PSRR (µV/V)
–1.5
–1
–0.5
0
0.5
1
1.5
0
50
100
150
200
250
300
350
400
450
500
NUMBER OF UNITS
19972 G15
G = 0.1
G = 0.2
G = 0.25
FREQUENCY (Hz)
10
100
1k
10k
100k
1M
10M
0
20
40
60
80
100
120
COMMON-MODE REJECTION RATIO (dB)
19972 G16
V
S
= ±18V
V
S
= ±15V
V
S
= ±10V
V
S
= ±12V
OUTPUT VOLTAGE (V)
–20
–16
–12
–8
–4
0
4
8
12
16
20
OUTPUT ERROR (2mV/DIV)
19972 G17
V
S
= ±18V
V
S
= ±15V
V
S
= ±10V
V
S
= ±12V
OUTPUT VOLTAGE (V)
–20
–16
–12
–8
–4
0
4
8
12
16
20
OUTPUT ERROR (2mV/DIV)
19972 G18
1459 UNITS
FROM 4 RUNS
BOTH PACKAGES
V
S
= ±15V
V
OUT
= ±2.8V
GAIN ERROR (ppm)
–60
–40
–20
0
20
40
60
0
50
100
150
200
250
300
NUMBER OF UNITS
19972 G10
Typical Gain Error for RL = 5kΩ,
(G=0.25) (Curves Offset for
Clarity)
Typical Gain Error for RL = 10kΩ,
(G=0.25) (Curves Offset for
Clarity)
CMRR vs Frequency, Referred to
Output
LT1997-2
9
Rev 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Gain Error vs Temperature
CMRR vs Temperature, Referred
to Output
TA = 25°C, VS=±15V, Difference Amplifier
configuration, unless otherwise noted.
Output Voltage vs Load Current
Maximum Power Dissipation vs
Temperature
Gain vs Frequency
Frequency Response vs
Capacitive Load (G = 0.1)
Frequency Response vs
Capacitive Load (G = 0.2)
V
S
= ±18V
V
S
= ±15V
V
S
= ±10V
V
S
= ±12V
OUTPUT VOLTAGE (V)
–20
–16
–12
–8
–4
0
4
8
12
16
20
OUTPUT ERROR (2mV/DIV)
19972 G19
V
S
= ±5V, R
L
= 10kΩ
V
S
= ±5V, R
L
= 1kΩ
V
S
= ±5V, R
L
= 2kΩ
V
S
= ±2.5V, R
L
= 1kΩ
OUTPUT VOLTAGE (V)
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
OUTPUT ERROR (2mV/DIV)
19972 G20
V
S
= ±15V
V
OUT
= ±7V
R
L
= 10kΩ
10 UNITS
G = 0.25
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
–100
–80
–60
–40
–20
0
20
40
60
80
100
–10
–8
–6
–4
–2
0
2
4
6
8
10
GAIN ERROR (ppm)
GAIN ERROR (m%)
19972 G21
V
S
= ±15V
10 UNITS
G = 0.25
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
–10
–8
–6
–4
–2
0
2
4
6
8
10
CMRR (µV/V = ppm)
19972 G22
130°C
85°C
25°C
–45°C
OUTPUT CURRENT (mA)
0
5
10
15
20
25
30
–20
–15
–10
–5
0
5
10
15
20
OUTPUT VOLTAGE (V)
19972 G23
DF14(12) θ
JA
= 45°C/W
MS16(12) θ
JA
= 130°C/W
AMBIENT TEMPERATURE (°C)
–60
–40
–20
0
20
40
60
80
100
120
140
160
0
1
2
3
4
5
MAXIMUM POWER DISSIPATION (W)
19972 G24
G = 0.25
G = 0.2
G = 0.1
FREQUENCY (MHz)
0.001
0.01
0.1
1
2
–40
–35
–30
–25
–20
–15
–10
–5
0
GAIN (dB)
19972 G25
20pF
220pF
390pF
560pF
FREQUENCY (MHz)
0.001
0.01
0.1
1
10
–40
–35
–30
–25
–20
–15
–10
–5
0
GAIN (dB)
19972 G26
20pF
220pF
390pF
560pF
FREQUENCY (MHz)
0.001
0.01
0.1
1
10
–40
–35
–30
–25
–20
–15
–10
–5
0
5
10
GAIN (dB)
19972 G27
Typical Gain Error for Low Supply
Voltages (G=0.25)
(Curves Offset for Clarity)
Typical Gain Error for RL=2kΩ
(G=0.25) (Curves Offset for
Clarity)
LT1997-2
10
Rev 0
For more information www.analog.com
TYPICAL PERFORMANCE CHARACTERISTICS
Settling Time
TA = 25°C, VS=±15V, Difference Amplifier
configuration, unless otherwise noted.
Large-Signal Step Response Small-Signal Step Response
Slew Rate vs Temperature
20pF
220pF
390pF
560pF
FREQUENCY (MHz)
0.001
0.01
0.1
1
10
–40
–35
–30
–25
–20
–15
–10
–5
0
5
10
GAIN (dB)
19972 G28
FREQUENCY (Hz)
1
10
100
1k
10k
100k
0
10
20
30
40
50
60
70
80
VOLTAGE NOISE DENSITY (nV/√Hz)
19972 G29
TIME (10s/DIV)
NOISE VOLTAGE (200nV/DIV)
19972 G30
G = 0.1
G = 0.2
G = 0.25
FREQUENCY (Hz)
10
100
1k
10k
100k
0
20
40
60
80
100
120
140
160
POWER SUPPLY REJECTION RATIO (dB)
19972 G31
G = 0.1
G = 0.2
G = 0.25
FREQUENCY (Hz)
10
100
1k
10k
100k
0
20
40
60
80
100
120
140
POWER SUPPLY REJECTION RATIO (dB)
19972 G32
R
L
= 10kΩ
RISING EDGE
FALLLING EDGE
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
SLEW RATE (V/µs)
19972 G33
G = 0.25
R
L
= 10kΩ
C
L
= 560pF
TIME (20µs/DIV)
VOLTAGE (5V/DIV)
19972 G34
C
L
= 20pF
C
L
= 560pF
C
L
= 270pF
G = 0.25
R
L
=10kΩ
C
L
= 390pF
TIME (µs)
0
5
10
15
20
25
30
35
40
–100
–80
–60
–40
–20
0
20
40
60
80
100
120
140
VOLTAGE (mV)
19972 G35
G = 0.25
OUTPUT VOLTAGE
ERROR VOLTAGE
TIME (10µs/DIV)
–1.0
–0.5
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
–14
–12
–10
–8
–6
–4
–2
0
2
4
6
ERROR VOLTAGE (mV)
OUTPUT VOLTAGE (V)
19972 G36
Output 0.1Hz to 10Hz Noise
(G = 0.25)
Positive PSRR vs Frequency
Output Noise Density vs
Frequency (G = 0.25)
Frequency Response vs
Capacitive Load (G = 0.25)
Negative PSRR vs Frequency
LT1997-2
11
Rev 0
For more information www.analog.com
Settling Time
Op Amp Offset Voltage vs
Temperature Quiescent Current vs Temperature
Thermal Shutdown vs Hysteresis
Quiescent Current vs Supply
Voltage
TYPICAL PERFORMANCE CHARACTERISTICS
Shutdown Quiescent Current vs
Supply Voltage
Minimum Supply Voltage
TA = 25°C, VS=±15V, Difference Amplifier
configuration, unless otherwise noted.
Quiescent Current vs SHDN
Voltage
G = 0.25
OUTPUT VOLTAGE
ERROR VOLTAGE
TIME (10µs/DIV)
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
–14
–12
–10
–8
–6
–4
–2
0
2
4
6
ERROR VOLTAGE (mV)
OUTPUT VOLTAGE (V)
19972 G37
20 UNITS
TEMPERATURE (°C)
–60
–40
–20
0
20
40
60
80
100
120
140
–200
–150
–100
–50
0
50
100
150
200
OP AMP OFFSET VOLTAGE (µV)
19972 G38
10 UNITS
TEMPERATURE (°C)
–75
–50
–25
0
25
50
75
100
125
150
175
200
250
300
350
400
450
500
550
QUIESCENT CURRENT (µA)
19972 G39
TEMPERATURE (°C)
145
150
155
160
165
170
0
100
200
300
400
500
600
SUPPLY CURRENT (µA)
19972 G40
T
A
= 150°C
T
A
= –55°C
PARAMETRIC SWEEP IN ~25°C
INCREMENTS
SUPPLY VOLTAGE (V)
0
10
20
30
40
50
0
100
200
300
400
500
600
QUIESCENT CURRENT (µA)
19972 G41
V
SHDN
= 0V
150°C
125°C
85°C
25°C
–40°C
–55°C
SUPPLY VOLTAGE (V)
0
10
20
30
40
50
0
10
20
30
40
50
QUIESCENT CURRENT (µA)
19972 G42
150°C
125°C
85°C
25°C
–40°C
–55°C
SHDN
VOLTAGE (V)
0
5
10
15
0
50
100
150
200
250
300
350
400
450
500
550
QUIESCENT CURRENT (µA)
19972 G43
V
S
= ±15V
T
A
= 125°C
T
A
= 25°C
T
A
= –45°C
TOTAL SUPPLY VOLTAGE (V)
0
1
2
3
4
5
–20
–15
–10
–5
0
5
10
15
20
CHANGE IN OP AMP OFFSET VOLTAGE (µV)
19972 G44
LT1997-2
12
Rev 0
For more information www.analog.com
PIN FUNCTIONS
V+ (Pin 9/Pin 11): Positive Supply Pin.
V– (EXPOSED PAD Pin 15/Pin 8): Negative Supply Pin.
OUT (Pin 8/Pin 9): Output Pin.
+INA (Pin 1/Pin 1): Noninverting Gain-of-0.1 Input Pin.
Connects a 250k internal resistor to the internal op amp’s
noninverting input.
+INB (Pin 3/Pin 3): Noninverting Gain-of-0.2 Input Pin.
Connects a 125k internal resistor to the internal op amp’s
noninverting input.
+INC (Pin 5/Pin 5): Noninverting Gain-of-0.25 Input Pin.
Connects a 100k internal resistor to the internal op amp’s
noninverting input.
–INA (Pin 14/Pin 16): Inverting Gain-of-0.1 input Pin.
Connects a 250k internal resistor to the internal op amp’s
inverting input.
–INB (Pin 12/Pin 14): Inverting Gain-of-0.2 input Pin.
Connects a 125k internal resistor to the internal op amp’s
inverting input.
–INC (Pin 10/Pin 12): Inverting Gain-of-0.25 input Pin.
Connects a 100k internal resistor to the internal op amp’s
inverting input.
REF (Pin 7/NA): Reference Input Pin. Sets the output level
when the difference between the inputs is zero.
REF1 (NA/Pin 6): Reference 1 Input Pin. With REF2, sets the
output level when the difference between the inputs is zero.
REF2 (NA/Pin 7): Reference 2 Input Pin. With REF1, sets the
output level when the difference between the inputs is zero.
SHDN (Pin 6/Pin 10): Shutdown Pin. Amplifier is active
when this pin is tied to V+ or left floating. Pulling the pin
more than 2.5V below V+ causes the amplifier to enter a
low power state.
(DFN/MSOP)
BLOCK DIAGRAM
MSOP
25k
50k
100k
125k
250k
10µA
100k
125k
250k
50k
–INC
–INA
–INB
REF2
SHDN
+INA
+INC
+INB
V
+
V
–
OUT
V
+
REF1
19972 BD01
DFN
25k
25k
100k
125k
250k
10µA
100k
125k
250k
–INC
–INA
–INB
SHDN
+INA
+INC
+INB
V
+
V
–
OUT
V
+
REF
19972 BD02
LT1997-2
13
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Figure 1. Difference Amplifier with Dual-Supply
Operation (Gain=0.1)
Introduction
The LT1997-2 is a precision, high voltage funnel ampli-
fier combined with a highly-matched resistor network. It
can easily be configured into many different gain circuits
without adding external components, as it will be shown
in this data sheet. The LT1997-2 provides the resistors
and op amp together in a small package in order to save
board space and reduce complexity. Highly accurate
measurement circuits can be easily constructed with the
LT1997-2. The circuits can be tailored to specific measure-
ment applications.
Common Mode Voltage Range
The common mode voltage range of the LT1997-2 is set
by the voltage range allowed on the LT1997-2’s input pins
and by the input voltage range of the internal op amp.
The internal op amp of LT1997-2 has 2 operating regions:
a) if the common-mode voltage at the inputs of the
internal op amp (VCMOP) is between V– and V+ – 1.75V,
the op amp operates in its normal region;
b) If VCMOP is between V+–1.75V and V– + 76V, the op
amp continues to operate, but in its Over-The-Top (OTT)
region with degraded performance (see Over-The-Top
Operation section of this data sheet for more detail).
The LT1997-2 will not operate correctly if the common-
mode voltage at the inputs of the internal op amp (VCMOP)
is below V–, but the part will not be damaged as long as
VCMOP is greater than V––25V and the junction tempera-
ture of the LT1997-2 does not exceed 150ºC.
The voltage on LT1997-2’s input pins should never be
higher than V–+270V or lower than V––270V under any
circumstances.
The common-mode voltage at the inputs of the internal
op amp (VCMOP) is determined by the voltages on pins
+INA, +INB, +INC and REF (see the Calculating Input Volt-
age Range section). This condition is true provided that
the internal op amp’s output is not clipped and feedback
maintains the internal op amp’s inputs at the same voltage.
In addition to the limits mentioned above, the common
mode input voltage of the amplifier should be chosen so
that the input resistors do not dissipate too much power.
The power dissipated in a 250k resistor must be less than
1.8W. It must be less than 0.9W for the 125k resistor and
less than 0.72W for the 100k resistor. For most applica-
tions, the pin voltage limitations will be reached before
the resistor power limitation is reached.
Calculating Input Voltage Range
Figure 2 shows the LT1997-2 in the generalized case
of a difference amplifier, with the inputs shorted for the
common mode calculation. The values of RF and RG are
dictated by how the positive inputs (+INA, +INB, +INC)
and REF pin are connected.
By superposition we can write:
VCMOP =VEXT •
R
F
RF+RG
+VREF •
R
G
RF+RG
Or, solving for VEXT:
V
EXT =VCMOP • 1+RG
RF
⎛
⎝
⎜⎞
⎠
⎟– V
REF •RG
RF
But valid VCMOP voltages are limited to VS+–1.75V (or
VS–+76V for OTT) on the high side and VS– on the low
side, so:
MAX V
EXT =VS+–1.75
( )
• 1+RG
R
F
⎛
⎝
⎜⎞
⎠
⎟– V
REF •RG
R
F
19972 F01
OUT
REF
250k
250k
100k
125k 25k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
V
S
+
VS–
V
OUT
VREF
V
–IN
V+IN
–
+
LT1997-2
LT1997-2
14
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
and:
MIN V
EXT =VS–
( )
• 1+RG
RF
⎛
⎝
⎜⎞
⎠
⎟– V
REF •RG
RF
VREF
RG
RG
VS+
VS–
VCMOP
VOUT
VEXT
–
+
RF
RF
19972 F02
Figure 2. Calculating the Common Mode Input Voltage Range
Exceeding the MAX VEXT limit will cause the amplifier to
transition into the Over-The-Top region. The maximum
input voltage for the Over-The-Top region is:
MAX V
EXTOTT =VS–+76
( )
• 1+RG
RF
⎛
⎝
⎜⎞
⎠
⎟– V
REF •RG
RF
Keep in mind that the above MAX and MIN values for input
voltage range should not exceed V– ±270V, the ABSMAX
voltage range specified earlier for LT1997-2’s input pins.
The negative inputs (–INA, –INB, –INC) are not limited by
the internal op amp common mode range (VCMOP) because
they do not affect it. They are limited by the output swing
of the amplifier (and obviously by the allowed voltage
range for the input pins).
Over-The-Top Operation
When the input common mode voltage of the internal op
amp (VCMOP) in the LT1997-2 is biased near or above the
V+ supply, the op amp is operating in the Over-The-Top
(OTT) region. The op amp continues to operate with an
input common mode voltage of up to 76V above V– (re-
gardless of the positive power supply voltage V+), but
its performance is degraded. The op amp’s input bias
currents change from under ±2nA to 14µA. The op amp’s
input offset current rises to ±50nA, which adds ±1.25mV
to the output offset voltage.
In addition, when operating in the Over-The-Top region,
the differential input impedance of the internal op amp
decreases from 1MΩ in normal operation to approximately
3.7kΩ in Over-The-Top operation. This resistance appears
across the summing nodes of the internal op amp and
boosts noise and offset while decreasing speed. Noise
and offset will increase by 80%. The bandwidth will be
reduced by 45%. For more detail on Over-The-Top opera-
tion, consult the LT6015 data sheet.
Difference Amplifiers
The LT1997-2 is ideally suited to be used as a difference
amplifier. Figure 3 shows the basic 4-resistor difference
amplifier and the LT1997-2. A difference gain of 0.2 (at-
tenuation = 5) is shown, but can be altered by additional
dashed connections. By connecting the 100k resistors in
parallel with the 25k feedback resistors, the gain is reduced
to 0.16 (attenuation = 6.25). Of course there are many
possible gains and Figure 4 shows circuit schematics of
some of those difference amplifier gains.
Note that the common mode voltage at the inputs of the
internal op amp (VCMOP) is set by the voltages at pins
+INA, +INB, +INC and REF.
Figure 3. The LT1997-2 Configured as a Difference Amplifier.
Gain Is Set by Connecting the Correct Resistors or Combinations
of Resistors. Gain of 0.2 (Attenuation = 5) Is Shown, with Dashed
Lines Modifying It to a Gain of 0.16 (Attenuation = 6.25)
19972 F03
OUT
REF
250k
250k
100k
125k 25k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
V+IN
V–IN
V+IN
RG
R
F
+
–
VOUT
RG
RF
DIFFERENCE AMPLIFIER CONFIGURATION
DIFFERENCE AMPLIFIER CONFIGURATION
IMPLEMENTED WITH THE LT1997-2, R
F = 25k, RG = 125k, GAIN = 0.2
ADDING THE DASHED CONNECTIONS CONNECT THE
100k RESISTOR IN PARALLEL WITH R
F, SO RF IS REDUCED TO 20k.
THE GAIN BECOMES 20k/125k = 0.16
VOUT = GAIN • (V+IN – V–IN
)
GAIN = RF/RG
LT1997-2
LT1997-2
15
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Figure 4. Many Difference Amplifier Gains Can Be Achieved by Strapping Pins
19972 F04
V
+IN V+IN
V+IN
V
+IN
V+IN V+IN
OUT
REF
250k
250k
100k
125k 25k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V
–IN
GAIN = 0.08
LT1997-2
OUT
REF
250k
250k
100k
125k 25k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
V
OUT
V–IN
GAIN = 0.1
LT1997-2
OUT
REF
250k
250k
100k
125k 25k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
GAIN = 0.083
LT1997-2
OUT
REF
250k
250k
100k
125k 25k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V
–IN
GAIN = 0.2
LT1997-2
V
+IN
OUT
REF
250k
250k
100k
125k 25k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V
–IN
GAIN = 0.3
LT1997-2
V+IN
OUT
REF
250k
250k
100k
125k 25k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
GAIN = 0.227
LT1997-2
V+IN
OUT
REF
250k
250k
100k
125k 25k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
V
OUT
V–IN
GAIN = 0.409
LT1997-2
V+IN
OUT
REF
250k
250k
100k
125k 25k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
V
OUT
V–IN
GAIN = 0.25
LT1997-2
V+IN
OUT
REF
250k
250k
100k
125k 25k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
GAIN = 0.35
LT1997-2
OUT
REF
250k
250k
100k
125k 25k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
GAIN = 0.45
LT1997-2
OUT
REF
250k
250k
100k
125k 25k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
GAIN = 0.55
LT1997-2
LT1997-2
16
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Difference Amplifier: Additional Gains Using Cross-
Coupling
Figure 5 shows the basic difference amplifier as well as
the LT1997-2 with cross-coupled inputs. The additional
dashed connections reduce the differential gain from 0.25
to 0.15. Using this method, additional gains are achievable
and a few example schematics of the difference amplifiers
using cross-coupling are shown in Figure 6. To summarize,
Table1 shows a complete list of all difference amplifier
gains (attenuations) and how they are constructed using
(both conventional or cross-coupling) pin strapping.
Note that there are 38 unique gains ranging from 0.0455
to 0.55 (corresponding to attenuations from 1.8182 to
22) which can be achieved with the LT1997-2 using no
external components.
Table1. Difference Amplifier Gains (Attenuations)
GAIN ATTENUATION V+IN V–IN GND (REF) OUT
0.0455 22 –INB, +INC +INB, –INC +INA –INA
0.05 20 –INB, +INC +INB, –INC
0.0556 18 –INB, +INC +INB, –INC –INA +INA
0.069 14.5 +INA –INA +INB, +INC –INB, –INC
0.08 12.5 +INA –INA +INC –INC
0.0833 12 +INA –INA +INB –INB
0.0952 10.5 +INA –INA –INB, +INC +INB, –INC
0.1 10 +INA –INA
0.1053 9.5 +INA –INA +INB, –INC –INB, +INC
0.125 8 +INA –INA –INB +INB
0.1333 7.5 +INA –INA –INC +INC
0.1481 6.75 +INB –INB +INA, +INC –INA, –INC
0.15 6.6667 –INA, +INC +INA, –INC
0.16 6.25 +INB –INB +INC –INC
0.1739 5.75 +INB –INB –INA, +INC +INA, –INC
0.1818 5.5 +INB –INB +INA –INA
0.1875 5.3333 –INA, +INC +INA, –INC –INB +INB
0.1923 5.2 +INC –INC +INA, +INB –INA, –INB
0.2 5 +INB –INB
0.2083 4.8 +INC –INC +INB –INB
0.2222 4.5 +INB –INB –INA +INA
0.2273 4.4 +INC –INC +INA –INA
0.24 4.1667 +INA, +INB –INA, –INB +INC –INC
0.25 4 +INC –INC
0.2667 3.75 +INB –INB –INC +INC
0.2778 3.6 +INC –INC –INA +INA
0.2917 3.4286 +INA, +INC –INA, –INC +INB –INB
0.3 3.3333 +INA, +INB –INA, –INB
0.3077 3.25 +INB –INB –INA, –INC +INA, +INC
0.3125 3.2 +INC –INC –INB +INB
0.35 2.8571 +INA, +INC –INA, –INC
0.3571 2.8 +INC –INC –INA, –INB +INA, +INB
0.4 2.5 +INA, +INB –INA, –INB –INC +INC
0.4091 2.4444 +INB, +INC –INB, –INC +INA –INA
0.4375 2.2857 +INA, +INC –INA, –INC –INB +INB
0.45 2.2222 +INB, +INC –INB, –INC
0.5 2 +INB, +INC –INB, –INC –INA +INA
0.55 1.8182 +INA, +INB,
+INC
–INA, –INB,
–INC
Figure 5. Cross-Coupling of the LT1997-2 Allows Additional
Gains to Be Constructed
19972 F05
OUT
REF
250k
250k
100k
125k 25k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V
–IN
V
+IN
V–IN
V+IN
RG
R
F
+
–
VOUT
RG
RF
DIFFERENCE AMPLIFIER CONFIGURATION
DIFFERENCE AMPLIFIER CONFIGURATION
IMPLEMENTED WITH THE LT1997-2, RF = 25k, RG = 100k, GAIN = 0.25
GAIN CAN BE ADJUSTED BY CROSS-COUPLING THE INPUTS.
MAKING THE DASHED CONNECTIONS REDUCES THE GAIN FROM 0.25 TO 0.15
VOUT = GAIN • (V+IN – V–IN)
GAIN = RF/RG
LT1997-2
LT1997-2
17
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
Amplifiers for a Single-Ended Input
All of the difference amplifier configurations discussed
in the preceding section can be used as noninverting or
inverting amplifiers if the input is single-ended. For ex-
ample, to achieve a positive attenuation for a single-ended
input using the LT1997-2, simply ground V–IN and connect
the input signal to V+IN. Similarly, to achieve a negative
attenuation for a single-ended input using the LT1997-2 ,
simply ground V+IN and connect the input signal to V–IN.
OUT
REF
250k
250k
100k
125k 25k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
GAIN = 0.05
OUT
REF
250k
250k
100k
125k 25k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V
–IN
GAIN = 0.0455
V+IN
V
+IN
LT1997-2 LT1997-2
19972 F06
OUT
REF
250k
250k
100k
125k 25k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
V
OUT
V–IN
GAIN = 0.15
V+IN
LT1997-2
Figure 6. Examples of More Difference Amplifier Gains That Can Be Achieved
Figure 7. The LT1997-2 Reference Resistors: Split Resistors in the MSOP Package, Single
Resistor in the DFN Package
Reference Resistors
In the preceding discussions, the Reference resistor is
shown as a single 25k resistor. This is true in the DFN
package. In the MSOP package the reference resistor is
split into two 50k resistors (Figure 7). Tying the REF1 and
REF2 pins to the same voltage produces the same reference
voltage as tying the VREF pin in the DFN package to that
voltage. Connecting REF1 and REF2 to different voltages
produces an effective reference voltage that is the average
of VREF1 and VREF2. This feature is especially useful when
the desired reference voltage is half way between the sup-
19972 F07
OUT
REF
250k
250k
100k
125k 25k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
VS+
VS–
VOUT
V–IN
V+IN
OUT
REF1
250k
250k
100k
125k 50k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
V
S
+
VS–
VOUT
V
REF
VREF1
V
–IN
V+IN
REF2
50k VREF2
LT1997-2 MSOP
LT1997-2 DFN
LT1997-2 LT1997-2
LT1997-2
18
Rev 0
For more information www.analog.com
APPLICATIONS INFORMATION
plies. Tying REF1 to VS+ and REF2 to VS– produces the
desired mid-supply voltage without the help of another
external reference voltage (Figure 7). The ratio of RREF1
to RREF2 is very precise:
∆R
R=RREF1 – RREF2
RREF1 +RREF2
2
⎛
⎝
⎜⎞
⎠
⎟
<90ppm
Shutdown
The LT1997-2 has a shutdown pin (SHDN). Under normal
operation this pin should be tied to V+ or allowed to float.
Tying this pin 2.5V or more below V+ will cause the part
to enter a low power state. The supply current is reduced
to less than 25µA and the op amp output becomes high
impedance. The voltages at the input pins can still be
present even in shutdown mode.
Supply Voltage
The positive supply pin of the LT1997-2 should be bypassed
with a small capacitor (typically 0.1µF) as close to the supply
pins as possible. When driving heavy loads, an additional
4.7µF electrolytic capacitor should be added. When using
split supplies, the same is true for the V– supply pin.
Output
The output of the LT1997-2 can typically swing to within
50mV of either rail with no load and is capable of sourcing
and sinking approximately 30mA at 25°C. The LT1997-2
is internally compensated to drive at least 0.5nF of ca-
pacitance under any output loading conditions. For larger
capacitive loads, a 0.22µF capacitor in series with a 150Ω
resistor between the output and ground will compensate
the amplifier to drive capacitive loads greater than 0.5nF.
Distortion
The LT1997-2 features excellent distortion performance
when the internal op amp is operating in the normal op-
erating region. Operating the LT1997-2 with the internal
op amp in the over the top region will increase distortion
due to the lower loop gain of the op amp. Operating the
LT1997-2 with input common mode voltages that go from
the normal to Over-The-Top operation will significantly
degrade the LT1997-2’s linearity as the op amp must
transition between two different input stages. Driving
resistive loads significantly smaller than the 25k internal
feedback resistor will also degrade the amplifier’s linearity
performance.
High Voltage Pin Spacing
For applications with very high input voltages, the
LT1997-2 pinout eases the printed circuit board (PCB)
layout burden. Voltages at +INA, –INA, +INB, and –INB
input pins are separated from other pins by virtue of
unpopulated pin locations, as illustrated in the Pin Con-
figuration section of this data sheet.
Power Dissipation Considerations
Because of the ability of the LT1997-2 to operate on power
supplies up to ±25V, to withstand very high input volt-
ages and to drive heavy loads, there is a need to ensure
the die junction temperature does not exceed 150°C. The
LT1997-2 is housed in DF14 (θJA = 45°C/W, θJC = 3°C/W)
and MS16 (θJA = 130°C/W) packages.
In general, the die junction temperature (TJ) can be es-
timated from the ambient temperature (TA), the device’s
power dissipation (PD) and the thermal resistance of the
device and board (θJA).
TJ = TA + PD • θJA
The thermal resistance from the junction to the ambient
environment (θJA) is the sum of the thermal resistance
from the junction to the exposed pad (θJC) and the thermal
resistance from the exposed pad to the ambient environ-
ment (θCA). The θCA value depends on how much PCB
metal is connected to the exposed pad in the board. The
more PCB metal that is used, the lower θCA and θJA will be.
Power is dissipated by the amplifier’s quiescent current, by
the output current driving a resistive load, and by the input
current driving the LT1997-2’s internal resistor network.
PD=VS+– VS–
( )
•IS
( )
+POD +PRESD
LT1997-2
19
Rev 0
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APPLICATIONS INFORMATION
For a given supply voltage, the worst-case output power
dissipation POD(MAX) occurs with the output voltage at half
of either supply voltage. POD(MAX) is given by:
POD(MAX) =VS2
( )
2
R
LOAD
The power dissipated in the internal resistors (PRESD)
depends on the manner the input resistors have been
configured as well as the input voltage, the output voltage
and the voltage on the REF pin. The following equations
and Figure 8 show the different components of PRESD
corresponding to the different groups of the LT1997-2’s
internal resistors, assuming that the LT1997-2 is used
with a dual supply configuration with REF pin at ground
(refer to Figure 3 for resistor terminologies used in equa-
tions below).
P
RESDA =V+IN
( )
2
RG+RF
P
RESDB =
V–IN – V+IN •RF
RG+RF
⎛
⎝
⎜⎞
⎠
⎟
2
RG
P
RESDC =
V+IN •RF
RG+RF
– VOUT
⎛
⎝
⎜⎞
⎠
⎟
2
RF
PRESD = PRESDA + PRESDB + PRESDC
In general, PRESD increases with higher input voltage and
lower output and REF pin voltages.
Example: For an LT1997-2 in a DFN package mounted on
a PC board with a thermal resistance of 45°C/W, operating
on ±25V supplies and driving a 2.5kΩ load to 12.5V with
V+IN=255V and REF=0V, the total power dissipation
is given by:
P
D=50 • 0.6mA
( )
+12.5
2
2.5k +255
2
275k
+
130 – 255
11
⎛
⎝
⎜⎞
⎠
⎟
2
250k +
255
11 – 12.5
⎛
⎝
⎜⎞
⎠
⎟
2
25k
=0.38W
Assuming a thermal resistance of 45°C/W, the die tem-
perature will experience an 17°C rise above ambient.
This implies that the maximum ambient temperature the
LT1997-2 should operate under the above conditions is:
TA = 150°C – 17°C = 133°C
It is recommended that the exposed pad of the DFN pack-
age have as much PCB metal connected to it as reasonably
available. The more PCB metal connected to the exposed
Figure 8. Power Dissipation Example
19972 F08
OUT
REF
250k
250k
100k
125k
25k
125k
100k 25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
V
S
+
= 25V
VS–
= –25V
VOUT =
12.5V
2.5k
V–IN = 255V – VOUT/0.1
= 130V
V+IN
= 255V
–
+
PRESDA
PRESDC
PRESDB
LT1997-2
LT1997-2
20
Rev 0
For more information www.analog.com
19973 TA03
OUT
REF2
50k
REF1
250k
250k
100k
125k 50k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V–
V+
V+
SHDN
–
+
LT1997-2
V–
V–
V–
V–
19972 F09
10µA
APPLICATIONS INFORMATION
pad, the lower the thermal resistance. Connecting a large
amount of PCB metal to the exposed pad can reduce the
θJA to even less than 45°C/W. Use multiple vias from the
exposed pad to the V– plane. The exposed pad is electrically
connected to the V– pin. In addition, a heat sink may be
necessary if operating near maximum junction temperature.
The MSOP package has no exposed pad and a higher
thermal resistance (θJA = 130°C/W). It should not be used
in applications which have a high ambient temperature,
require driving a heavy load, or require an extreme input
voltage.
Thermal Shutdown
For safety, the LT1997-2 will enter shutdown mode when
the die temperature rises to approximately 163°C. This
thermal shutdown has approximately 9°C of hysteresis
requiring the die temperature to cool 9°C before enabling
the amplifier again.
ESD Protection
The LT1997-2 is protected by a number of ESD structures.
The structures are shown in Figure 9.
The ESD structures serve to protect the internal circuitry
but also limit signal swing on certain nodes. The structures
on the internal op amp inputs limit the voltage on these
nodes to 0.3V below V– and 80V above V–. The voltage
on the REF (DFN), REF1 (MSOP) and REF2 (MSOP) pins
are limited to 0.3V below V– and 60V above V–. The volt-
age on the SHDN pin is limited to 0.3V below V– and 0.3V
above V+.
Direct Line Voltage Measurement
Since the LT1997-2 can withstand up to ±255V at its input
pins, configurations with the highest attenuation factors
allow for direct sensing of the 60Hz, 120VAC line voltage.
The circuit shown in Figure 10 directly measures the line
and neutral signals. The ground of the circuit can reason-
ably connect to earth ground. The neutral voltage level will
typically hover near earth. The ability of the LT1997-2 to
sense high voltages with varying common mode levels
enables this extremely simple implementation.
High Side Large Voltage Measurement
In some applications, an electrical potential develops
relative to a high line voltage. As an example, some LED
current control power conversion topologies place the
LED at the high voltage. Even more interestingly, the high
line may be moving. Off-line LED conversion such as in
modern light bulbs sometimes use LEDs pegged to the
rectified line voltage.
The circuit in Figure 11 uses the LT3590 to control LED
current. A LT1997-2 configured for a gain of 0.08V/V can
enable detection of an LED open circuit fault condition.
With the LED open circuited, the voltage across the LED
(which is being sensed by the LT1997-2) rises, and at
41.25V the LT1997-2 output rises above 3.3V, indicating
a fault condition.
A large voltage referred to the rectified AC mains can be
attenuated and shifted to a system’s low voltage circuitry.
Figure 12 shows this kind of function. Off-line LED lighting
that employs nonisolated buck power conversion is one
such example.
Figure 9. ESD Protection
LT1997-2
21
Rev 0
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APPLICATIONS INFORMATION
Figure 11. Detection of an LED Open Circuit Fault Condition
Figure 10. Direct Line Voltage (120VAC, 60Hz) Measurement
19972 F10
OUT
REF
250k
250k
100k
125k 25k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC
LT1997-2 CONFIGURED FOR GAIN = 0.069 (ATTENUATION = 14.5)
V–
V+
SHDN
15V
–15V
V
OUT
–
+
LT1997-2
NEUTRAL
EARTH
LINE
120V RMS
LINE
OUTPUT
TIME (ms)
0
10
20
30
40
50
–200
–160
–120
–80
–40
0
40
80
120
160
200
–15
–12
–9
–6
–3
0
3
6
9
12
15
DIFFERENTIAL AC LINE VOLTAGE (V)
OUTPUT VOLTAGE, V
OUT
(V)
19972 F10
19972 F11
OUT
REF
250k
250k
VREG
0.1µF
SW
470µF
QTLP690C
N = 16
CTRL
100k
125k 25k
125k
LT3590
GND
100k
25k
–INA –INB –INC
VIN
4Ω
1µF
LED
+INA +INB +INC V–
V+
SHDN
5V
V
OUT
–
+
LT1997-2
1µF
V
IN = 48V
LT1997-2 CONFIGURED FOR GAIN = 0.08 (ATTENUATION = 12.5)
LT1997-2
22
Rev 0
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APPLICATIONS INFORMATION
Figure 12. LED Common Mode Swings Relative to Rectified AC
19972 F12a
OUT
REF
250k
250k
470µF
0.05Ω
BSC42DN25NS3
GATE
DRIVE
CURRENT
SENSE
GSD2004W-V
RECTIFIED AC LINE
LEDN
LEDP
W5AP-LZMZ-5K8L
N = 5
100k
125k 25k
125k
100k
25k
–INA –INB –INC
330µF
+INA +INB +INC V–
V+
SHDN
15V
V
OUT
–
+
LT1997-2
0.01µF
–15V
10k
LT1997-2 CONFIGURED FOR GAIN = 0.069 (ATTENUATION = 14.5)
MOVING HIGH LINE (LEDP)
VOLTAGE BELOW LINE (LEDN)
LT1997–2 OUTPUT (VOUT)
DIFFERENCE VOLTAGE (LEDP – LEDN)
TIME (ms)
0
10
20
30
40
50
0
40
80
120
160
200
0
1
2
3
4
5
LED AND RECTIFIED AC (V)
VOLTAGES BASED ON
LT1997-2 OUTPUT (V)
19972 F12b
LT1997-2
23
Rev 0
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LT1997-2 Configured for Differential Output with Gain = 0.2
19972 TA02
OUT
REF
25k
250k
250k
100k
125k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
–
+
LT1997-2
V+
OUT
VOCM
V–
OUT
USE VOCM TO SET THE DESIRED
OUTPUT COMMON MODE LEVEL
10k
10k
–+
LT6015
V
S
+
VS–
V
+IN
V
–IN
Precision Over-The-Top Single-Supply Funnel Amplifier
19972 TA03
OUT
REF1
50k
REF2
250k
250k
100k
125k 50k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC V–
V+
SHDN
V
CM = –0.3V TO 2 • VBATTERY
V
BATTERY
= 3.3V TO 50V
V+IN
V–IN
–
+
LT1997-2
VCM
V
BATTERY
VOUT = + 0.25 • (V+IN – V–IN
)
VBATTERY
2
TYPICAL APPLICATIONS
LT1997-2
24
Rev 0
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PACKAGE DESCRIPTION
4.00 ±0.10
(4 SIDES)
NOTE:
1. PACKAGE OUTLINE DOES NOT CONFORM TO JEDEC MO-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
PIN 1
TOP MARK
(NOTE 6)
0.40 ±0.10
17
148
BOTTOM VIEW—EXPOSED PAD
1.70 ±0.10
0.75 ±0.05
R = 0.115
TYP
0.25 ±0.05
0.50 BSC
3.00 REF
3.38 ±0.10
0.200 REF
0.00 – 0.05
(DF14)(12) DFN 1113 REV 0
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
0.70 ±0.05
0.25 ±0.05
0.50 BSC
3.10 ±0.05
4.50 ±0.05
PACKAGE OUTLINE
PIN 1 NOTCH
0.35 × 45°
CHAMFER
1.70 ±0.05
3.38 ±0.05
3.00 REF
1.00
BSC
1.00
BSC
DF Package
14(12)-Lead Plastic DFN (4mm × 4mm)
(Reference LTC DWG # 05-08-1963 Rev Ø)
LT1997-2
25
Rev 0
For more information www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
PACKAGE DESCRIPTION
MSOP (MS12) 0213 REV B
0.53 ±0.152
(.021 ±.006)
SEATING
PLANE
0.18
(.007)
1.10
(.043)
MAX
0.17 –0.27
(.007 – .011)
TYP
0.86
(.034)
REF
1.0
(.0394)
BSC
0.50
(.0197)
BSC
16 14 121110
1 3 5 6 7 8
9
NOTE:
1. DIMENSIONS IN MILLIMETER/(INCH)
2. DRAWING NOT TO SCALE
3. DIMENSION DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
4. DIMENSION DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS.
INTERLEAD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.152mm (.006") PER SIDE
5. LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.102mm (.004") MAX
0.254
(.010) 0° – 6° TYP
DETAIL “A”
DETAIL “A”
GAUGE PLANE
5.10
(.201)
MIN
3.20 – 3.45
(.126 – .136)
0.889 ±0.127
(.035 ±.005)
RECOMMENDED SOLDER PAD LAYOUT
0.305 ±0.038
(.0120 ±.0015)
TYP
0.50
(.0197)
BSC
1.0
(.0394)
BSC
4.039 ±0.102
(.159 ±.004)
(NOTE 3)
0.1016 ±0.0508
(.004 ±.002)
3.00 ±0.102
(.118 ±.004)
(NOTE 4)
0.280 ±0.076
(.011 ±.003)
REF
4.90 ±0.152
(.193 ±.006)
MS Package
16 (12)-Lead Plastic MSOP with 4 Pins Removed
(Reference LTC DWG # 05-08-1847 Rev B)
LT1997-2
26
Rev 0
For more information www.analog.com
D16930-0-6/18(0)
www.analog.com
RELATED PARTS
TYPICAL APPLICATION
PART NUMBER DESCRIPTION COMMENTS
Difference Amplifiers
LT1997-3 Precision, Wide Voltage Range Gain Selectable Amplifier 3.3V to 50V Operation, CMRR > 91dB, Input Voltage = ±160V, Gain = 1, 3, 9
LT6375 ±270V Common Mode Voltage Difference Amplifier 3.3V to 50V Operation, CMRR > 97dB, Input Voltage = ±270V, Gain = 1
LT6376 ±230V Common Mode Voltage G = 10 Difference Amplifier 3.3V to 50V Operation, CMRR > 90dB, Input Voltage = ±230V, Gain = 10
LT1990 ±250V Input Range Difference Amplifier 2.7V to 36V Operation, CMRR > 70dB, Input Voltage = ±250V, Gain = 1, 10
LT1991 Precision, 100µA Gain Selectable Amplifier 2.7V to 36V Operation, 50μV Offset, CMRR > 75dB, Input Voltage = ±60V
LT1996 Precision, 100µA Gain Selectable Amplifier Micropower, Pin Selectable Up to Gain = 118
AD8275 G = 0.2, Level Translation, 16-Bit ADC Driver 3.3V to 15V Operation, CMRR > 86dB, Input Voltage = –35V to 40V, Gain = 0.2
AD8475 Precision, Selectable Gain, Fully Differential Funnel
Amplifier 3.3V to 10V Operation, CMRR > 86dB, Input Voltage = ±15V, Gain = 0.4, 0.8
Operational Amplifiers
LT6015/LT6016/
LT6017 Single, Dual, and Quad Over-The-Top Precision Op Amp 3.2MHz, 0.8V/µs, 50µV VOS, 3V to 50V VS, 0.335mA IS, RRIO
LT6018 33V, Ultralow Noise, Precision Op Amp VOS: 50µV, GBW: 15MHz, SR: 30V/µs, en: 1.2nV/√Hz, IS: 7.2mA
LTC6090/LTC6091 Single and Dual 140V Operational Amplifier 50pA IB, 1.6mV VOS, 9.5V to 140V VS, 4.5mA IS, RR Output
Current Sense Amplifiers
LT1999 High Voltage, Bidirectional Current Sense Amplifier –5V to 80V, 750µV, CMRR 80dB at 100kHz, Gain = 10, 20, 50
LT6108 High Side Current Sense Amplifier with Reference and
Comparator with Shutdown 2.7V to 60V, 125µV, Resistor Set Gain, ±1.25% Threshold Error
LT1787/LT1787HV Precision, Bidirectional High Side Current Sense Amplifier 2.7V to 60V Operation, 75μV Offset, 60μA Current Draw
LT6100 Gain-Selectable High Side Current Sense Amplifier 4.1V to 48V Operation,
Pin-Selectable Gain: 10V/V, 12.5V/V, 20V/V, 25V/V, 40V/V, 50V/V
LTC6101/
LTC6101HV High Voltage High Side Current Sense Amplifier 4V to 60V/5V to 100V Operation, External Resistor Set Gain, SOT23
LTC6102/
LTC6102HV Zero Drift High Side Current Sense Amplifier 4V to 60V/5V to 100V Operation, ±10μV Offset, 1μs Step Response,
MSOP8/DFN Packages
LTC6104 Bidirectional, High Side Current Sense 4V to 60V, Gain Configurable, 8-Pin MSOP Package
Funnel Instrumentation Amplifier for High Voltage Sensing
Input and Output Voltage Waveforms
ANALOG DEVICES, INC. 2018
19972 TA04a
OUT
REF
250k
250k
100k
125k 25k
125k
100k
25k
–INA –INB –INC
+INA +INB +INC
LT1997-2 CONFIGURED FOR GAIN = 0.0455 (ATTENUATION = 22)
V–
V+
SHDN
10V
–10V
65V
65V
–65V
–65V
VOUT
–
+
LT1997-2
–
+
–
+
1/2 LTC6091
1/2 LTC6091
1M
VAC
1M
V
OUT
V
AC
TIME (ms)
0
10
20
30
40
50
–150
–120
–90
–60
–30
0
30
60
90
120
150
–5
–4
–3
–2
–1
0
1
2
3
4
5
LINE VOLTAGE, V
AC
(V)
OUTPUT VOLTAGE, V
OUT
(V)
19972 TA04b