PRELIMINARY CY7C1006 CYPRESS Features Functional Description @ High speed tag = 12 ns e CMOS for optimum speed/power Low active power 256K x 4 Static RAM The CY7C1006 is a high-performance CMOS static RAM organized as 262,144 words by 4 bits. Easy memory expansion is provided by an active LOW chip enable (CE), an active LOW output enable (OE), and three-state drivers. The device has an 910 mW : automatic power-down feature that re- Low standby power duces power consumption by more than 275 mW 65% when deselected. @ 2,0V data retention (optional) Writing to the device is accomplished by 100 pw taking chip enable (CE) and write enable . (WE) inputs LOW. Data on the four 1/O automatic power-down when pins (1/Og through 1/O3) is then written TTL-compatible inputs and outputs pins (Ag through Aj7). into the location specified on the address Reading from the device is accomplished by taking chip enable (CE) and output en- able (OE) LOW while forcing write enable (WE) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the four [/O pins. The four input/output pins (1/Og through 1/O3) are placed in a high-impedance state when the device is deselected (CE HIGH), the outputs are disabled (OE HIGH), or during a write operation (CE and WE LOW). The CY7C1006 is available in standard 300-mil-wide DIPs and SOJs, Logic Block Diagram INPUT BUFFER A Ao oc VO3 A3 3 2 As 9 2 Wz ne w S12 x 512x4 S a 3 ARRAY 3 10 Ag Ag 1/Qp COLUMN OECODER oornanwrnonr Fedcccd dd Pin Configuration DIP/SOJ Top View x A: Ay DQ aa> 6AM Se PrPEP 1006-1 Selection Guide 7C1006~ 12 7100615 7C1006-20 7C1006 -25 Maximum Access Time (ns) 12 15 20 25 Maximum Operating Current (mA) Commercial 165 155 140 130 Military 165 150 140 Maximum Standby Current (mA) Commercial 50 40 30 30 Military 40 30 30 2-234CYPRESS PRELIMINARY CY7C1006 Maximum Ratings (Above which the useful life may be impaired. For user guidelines, Static Discharge Voltage ................0.000 00s >2001V not tested.) (per MIL-STD-883, Method 3015) Storage Temperature ................4- -65C to +150C Latch-Up Current .......-. 2.0 seer eee eee >200 mA Ambient Temperature with : Power Applied .......0...00c0cc0e eee -55Cto +125C Operating Range . i Vou Ambient Supply Voltage on Vcc Relative to GNDU] . -0.5V to +7.0V Range Temperaturel2| Vec DC Voltage Applied to Outputs - 2 in High Z Statel ee ee -0.5V to Vcc + 0.5V Commercial 0C to +70C SV + 10% DC Input Voltagell ooo... 0.5V to Voc + 0.5V Military 55C to +125C 5V + 10% Current into Outputs (LOW) .............0.0..0., 20 mA Electrical Characteristics Over the Operating Rangel?) 7C1006-12 | 7C1006-15 | 7C1006-20 | 7C100625 Parameter Description Test Conditions Min. | Max. | Min. | Max. | Min. | Max. | Min. | Max. | Unit Vou Output HIGH Vcc = Min., 2.4 2.4 2.4 2.4 v Voltage lou = 4.0mA VoL Output LOW Vec = Min., lop = 8.0mA 0.4 0.4 0.4 0.4 v Voltage Vin Input HIGH 2.2 Vcc 2.2 Vec 2.2 Vcc 2.2 Vec Vv Voltage +03 + 0.3 +03 +03 Vit Input LOW -03 | 08 |-03] 08 |-03 7 08 |-03] 08 Vv Voltage! '] Ix InputLoadCurrent | GND < V) < Vcc 1 +1 ~1 +1 1 +1 1 +1 pA loz Output Leakage GND < Vi < Vcc, -5 +5 -5 +5 5 +5 -5 +5 | pA Current Output Disabled los Output Short Vcc = Max., 300 300 -300 ~300 | mA Circuit Currentl4l | Vour = GND Icc Vcc Operating Vcc = Max., Com! 165 155 140 130 | mA Supply Current I = O0mA, PP f= tMax = I/trc | Mil 165 150 140 Isp Automatic CE Max. Vcc, Com! 50 40 30 30 | mA Power-Down CE > Vin, Current Vin > Vin or - TTL Inputs Vin < Vi, Mil 40 30 30 f = fax Isp2 Automatic CE Max. Vcc. Com) 2 2 2 2 mA Power-Down CE > Vec - 0.3V, Current Vin Voc - 0.3V Tyagi 2 3 3 CMOS Inputs [or Vin < 0.3V,f=0 Capacitancel5i Parameter Description Test Conditions Max. Unit Cin: Addresses Input Capacitance Ta = 25C, f = 1 MHz, 7 pF Cin: Controls Vcc = 5.0V 10 pF Cout Output Capacitance 10 pF Notes: . {. Viz (min.) = 2.0 for pulse durations of less than 20 ns. 4. Notmore than | output should be shorted at one time. Duration of the 2. Ta, is the instant on case temperature. 3. See the last page of this specification for Group A subgroup testingin- _ 5- formation, short circuit should not exceed 30 seconds, Tested initially and after any design or process changes that may affect these parameters.CYPRESS PRELIMINARY CY7C1006 AC Test Loads and Waveforms R1 4802 Ri 4802 ALL INPUT PULSES 5V BV 3.0V OUTPUT , OUTPUT 1 2 Re 5 pF 2 R2 GND 30 pF { 2559 P L {2552 INCLUDING = INCLUDING = = <3ns JIG AND JIG AND SCOPE SCOPE (a) Normal Load (b) High-Z Load 1006-3 C1006-4 Equivalent to: THEVENIN EQUIVALENT 1670 OUTPUT Owwe0_si1..73V Switching Characteristics Over the Operating Rangel? 6] 701006 12 7C100615 7C1006-20 701006 -25 Parameter Description Min. | Max. | Min. | Max. { Min. | Max. | Min. | Max. | Unit READ CYCLE tre Read Cycle Time 12 15 20 25 ns taa Address to Data Valid 12 15 20 25 ns toHA Data Hold from Address Change 3 3 3 3 ns TACE CE LOW to Data Valid 12 15 20 25 | ons tpok OE LOW to Data Valid 6 7 8 10 ns ILZ0E OE LOW to Low Z 0 0 0 0 ns {HZOE OE HIGH to High ZI7.8] 6 7 8 10 ns tLZCE CE LOW to Low Z11 3 3 3 3 ns tHZCE CE HIGH to High ZI? 81 6 7 8 10 ns 1PU CE LOW to Power-Up 0 0 0 0 ns tpp CE HIGH to Power-Down 12 15 20 25 ns WRITE CYCLE)? !0] twe Write Cycle Time 12 15 20 25 ns sce CE LOW to Write End 10 12 15 20 ns taw Address Set-Up to Write End 10 12 15 20 ns tHa Address Hold from Write End 0 0 0 0 ns tsa Address Set-Up to Write Start 0 0 0 ns tpwE WE Pulse Width 10 12 15 20 ns tsp Data Set-Up to Write End 7 8 10 15 ns tp Data Hold from Write End 0 0 0 0 ns tLZWE WE HIGH to Low ZI] 3 3 3 3 ns tHzwe WE LOW to High ZI7.81 6 7 8 10 ns Notes: 6. Test conditions assume signal transition time of 3nsorless, timingref- 9. erence levels of 1.5V, input pulse tevels of 0 to 3.0V, and output foading of the specified [o_/lon and 30-pF load capacitance. 7. tHzon, tyzce.and tyzwe are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured +500 mV from steady-state voltage. 10. 8. At any given temperature and voltage condition, tyzcr is less than (Lzces tHZ08 is less than (7208. and tyizwe is less than tL zwe for any given device. 2-236 The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of cither of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tyzwe and tsp.=p CYPRESS PRELIMINARY _ CY7C1006 Data Retention Characteristics Over the Operating Range (L Version Only) Commercial Military Parameter Description Conditions!!! Min. | Max. | Min. | Max. | Unit Vpr Vcc for Data Retention 2.0 2.0 Vv Iccpr Data Retention Current Vcc = Vor = 2.0V, 50 70 pA 5 - - - E> Vcc 0.3, tcpr) Chip Deselect to Data Retention Time Vin > Voc 0.3V or 0 0 ns tphl Operation Recovery Time Vin <0.3V trc tre ns Data Retention Waveform DATA RETENTION MODE w Voc 4.5V ht ta CC MLLLLLLLL IE PYXY 1006-5 Switching Waveforms Read Cycle No. #1! 33] tRC ADDRESS xK . x toHa yy DATA OUT PREVIOUS DATA VALID KKK DATA VALID C1006-6 Read Cycle No. 2 (OE Controlied)!!5- 14 ADDRESS cE took tLZ0E HIGH HIGH IMPEDANCE IMPEDANCE DATA OUT DATA VALID tLzceE Voc Ice SUPPLY eu CURRENT ISB 1006-7 Notes: e 11. No input may exceed Voc + 0.5V. 13. WE is HIGH for read cycle. 12. Device is continuously selected, OE and CE = Vi... 14, Address valid prior to or coincident with CE transition LOW.CYPRESS PRELIMINARY CY7C1006 Switching Waveforms (continued) Write Cycle No. 1 (CE Controlled)l!5: !6] AOORESS CE tewe pw tsp DATA I/O DATA VALID Crao68 Write Cycle No. 2 (WE Controlled, OE HIGH During Write)l 5. 16] ADDRESS SY = K cE SSS = LE Ls taw tia tsa tpwe We RQ OEY 7 tso tHo DATA VO xxx K DATA VALID - tHZ0E cio080 Notes: 15. 1fCEgoes HIGH simultaneously with WE going HIGH, theoutputre- 16. Data 1/O is high impedance if OF = Vig. mains in a high-impedance state. 2-238CYPRESS PRELIMINARY CY7C1006 Switching Waveforms Write Cycle No. 3 (WE Controlled, OF LOW)!!. !61 ADDRESS cE WE tsp DATA I/O DATA VALID Truth Table CE | OF | WE | 1/0 - V/O; Mode Power H | X X | HighZ Power-Down Standby (Isp) L L H | Data Out Read Active (Icc) L x L | DataIn Write Active (Icc) L H H High Z Selected, Outputs Disabled | Active (Icc) 2-239 C1006-10PRELIMINARY CY7C1006 CYPRESS Ordering Information Speed Package Operating (ns) Ordering Code Name Package Type Range 12 CY7C100612PC P21 28-Lead (300-Mil) Molded DIP Commercial CY7C1006-12VC V21 28-Lead (300-Mil) Molded SOJ 15 CY7C100615PC P21 28-Lead (300-Mil) Molded DIP Commercial CY7C1006~-15VC Vv21 28-Lead (300-Mil} Molded SOJ CY7C1006-15DMB D22 28-Lead (300-Mil) CerDIP Military 20 CY7C100620PC P21 28-Lead (300-Mil) Molded DIP Commercial CY7C 1006 -~ 20VC V2t 28-Lead (300-Mil) Molded SOF CY7C100620DMB D22 28-Lead (300-Mil) CerDIP Military 25 CY7C1006-25PC P21 28-Lead (300-Mil) Molded DIP Commercial CY7C1006-25VC V21 | 28-Lead (300-Mil) Molded SOJ CY7C100625DMB D22 | 28-Lead (300-Mil) CerDIP Military Contact factory for L version availability. MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Switching Characteristics Parameter Subgroups Parameter | Subgroups Vou 1,2,3 READ CYCLE VoL 1,2,3 tre 7, 8,9, 10, 11 Vin 1,2,3 taa 7, 8,9, 10, 11 Vip. Max. 1,2,3 toHA 7, 8, 9, 10, 11 lix 1,2,3 tacE 7,8,9, 10,11 loz 1, 2,3 tpoE 7, 8,9, 10,11 Icc 1, 2,3 WRITE CYCLE Ispi 1,2,3 two 7, 8,9, 10, 11 Isp2 1, 2,3 tscEe 7, 8,9, 10, 11 law 7, 8,9, 10, 11 THA 7, 8,9, 10, 11 Isa 7,8, 9, 10, 11 'pWE 7, 8,9, 10, 11 tsp 7,8, 9, 10, 12 typ 7, 8.9, 10, 11 Document #: 38-00201-B 2-240