Agilent HCPL-J314
0.6 Amp Output Current
IGBT Gate Drive Optocoupler
Data Sheet
Features
• 0.6 A maximum peak output
current
• 0.4 A minimum peak output
current
• High speed response:
0.7 µs max. propagation delay over
temp. range
• Ultra high CMR: min. 10 kV/µs at
VCM = 1.5 kV
• Bootstrappable supply current:
max. 3 mA
• Wide operating temp. range: -40°C
to 100°C
• Wide VCC operating range: 10 V to
30 V over temp. range
• Available in DIP8 (Single) and
SO16 (Dual) package
• Safety Approvals: UL Recognized,
3750 Vrms for 1 Minute. CSA
Approval IEC/EN/DIN EN 60747-
5-2 Approval. VIORM = 891 Vpeak
Applications
• Isolated IGBT/Power MOSFET
Gate Drive
• AC and brushless DC motor drives
• Inverters for appliances
• Industrial inverters
• Switch Mode Power Supplies
(SMPS)
• Uninterruptable Power Supplies
(UPS)
Functional Diagram
1
3
SHIELD
2
4
8
6
7
5
N/C
CATHODE
ANODE
N/C
V
CC
V
O
V
O
V
EE
HCPL-J314
A 0.1 µF bypass capacitor must be connected between pins VCC and VEE.
Description
The HCPL-J314 family of devices
consists of an AlGaAs LED
optically coupled to an
integrated circuit with a power
output stage. These optocouplers
are ideally suited for driving
power IGBTs and MOSFETs
used in motor control inverter
applications. The high operating
voltage range of the output stage
provides the drive voltages
required by gate controlled
devices. The voltage and current
supplied by this optocoupler
makes it ideally suited for
directly driving small or medium
power IGBTs. For IGBTs with
higher ratings the HCPL-3150
(0.6 A) or HCPL-3120 (2.5 A)
optocouplers can be used.
CAUTION: It is advised that normal static precautions be taken in handling and assembly of this
component to prevent damage and/or degradation which may be induced by ESD.
Truth Table
LED VO
OFF LOW
ON HIGH
2
Remarks: The notation “#” is used for existing products, while (new) products launched since 15th July 2001 and lead free option
will use “-”.
Selection Guide
Package Type Part Number Number of Channels
8-pin DIP (300 Mil) HCPL-J314 1
SO16 HCPL-314J 2
Ordering Information
Specify part number followed by option number (if desired).
Example :
HCPL-J314#XXXX
No option = Standard DIP package, 50 per tube.
300 = Gull Wing Surface Mount Option, 50 per tube.
500 = Tape and Reel Packaging Option.
XXXE = Lead Free Option.
HCPL-314J#YYYY
No option = SO16 Package.
500 = Tape and Reel Packaging Option.
XXXE = Lead Free Option.
3
HCPL-J314 Package Outline Drawings
Standard DIP Package
Gull Wing Surface Mount Option 300
1.080 ± 0.320
(0.043 ± 0.013) 2.54 ± 0.25
(0.100 ± 0.010)
0.51 (0.020) MIN.
0.65 (0.025) MAX.
4.70 (0.185) MAX.
2.92 (0.115) MIN.
5° TYP. 0.254 + 0.076
- 0.051
(0.010+ 0.003)
- 0.002)
7.62 ± 0.25
(0.300 ± 0.010)
6.35 ± 0.25
(0.250 ± 0.010)
9.80 ± 0.25
(0.386 ± 0.010)
1.78 (0.070) MAX.
1.19 (0.047) MAX.
HCPL-J314
YYWW
DATE CODE
DIMENSIONS IN MILLIMETERS AND (INCHES).
5678
4321
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
3.56 ± 0.13
(0.140 ± 0.005)
0.635 ± 0.25
(0.025 ± 0.010) 12° NOM.
9.65 ± 0.25
(0.380 ± 0.010)
0.51 ± 0.130
(0.020 ± 0.005)
7.62 ± 0.25
(0.300 ± 0.010)
5
6
7
8
4
3
2
1
9.80 ± 0.25
(0.386 ± 0.010)
6.350 ± 0.25
(0.250 ± 0.010)
1.02 (0.040)
1.27 (0.050)
10.9 (0.430)
2.0 (0.080)
LAND PATTERN RECOMMENDATION
1.080 ± 0.320
(0.043 ± 0.013)
3.56 ± 0.13
(0.140 ± 0.005)
1.780
(0.070)
MAX.
1.19
(0.047)
MAX.
2.540
(0.100)
BSC
0.255 (0.075)
0.010 (0.003)
NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
DIMENSIONS IN MILLIMETERS (INCHES).
TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01
xx.xxx = 0.005
LEAD COPLANARITY
MAXIMUM: 0.102 (0.004)
HCPL-J314
YYWW
MOLDED
4
Solder Reflow Temperature Profile
0
TIME (SECONDS)
TEMPERATURE (°C)
200
100
50 150100 200 250
300
0
30
SEC.
50 SEC.
30
SEC.
160°C
140°C
150°C
PEAK
TEMP.
245°C
PEAK
TEMP.
240°CPEAK
TEMP.
230°C
SOLDERING
TIME
200°C
PREHEATING TIME
150°C, 90 + 30 SEC.
2.5°C ± 0.5°C/SEC.
3°C + 1°C/–0.5°C
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
Recommended Pb-Free IR Profile
Regulatory Information
The HCPL-J314 has been
approved by the following
organizations:
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884
Teil 2):2003-01
UL
Approval under UL 1577,
component recognition program
up to VISO = 3750 Vrms. File
E55361.
CSA
Approved under CSA
Component Acceptance Notice
#5, File CA 88324.
217 °C
RAMP-DOWN
6 °C/SEC. MAX.
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
260 +0/-5 °C
t 25 °C to PEAK
60 to 150 SEC.
20-40 SEC.
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERA TURE
t
p
t
s
PREHEAT
60 to 180 SEC.
t
L
T
L
T
smax
T
smin
25
T
p
TIME
TEMPERATURE
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
T
smax
= 200 °C, T
smin
= 150 °C
5
OUTPUT POWER – P
S
, INPUT CURRENT – I
S
0
0
T
S
– CASE TEMPERATURE – °C
200
600
400
25
800
50 75 100
200
150 175
P
S
(mW)
125
100
300
500
700 I
S
(mA)
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics
Description Symbol Characteristic Unit
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤ 150 Vrms I - IV
for rated mains voltage ≤ 300 Vrms I - III
for rated mains voltage ≤ 600 Vrms I-II
Climatic Classification 55/100/21
Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage VIORM 891 Vpeak
Input to Output Test Voltage, Method b*
VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, VPR 1670 Vpeak
Partial discharge < 5 pC
Input to Output Test Voltage, Method a*
VIORM x 1.5 = VPR, Type and Sample Test, tm = 60 sec, VPR 1336 Vpeak
Partial discharge < 5 pC
Highest Allowable Overvoltage (Transient Overvoltage tini = 10 sec) VIOTM 6000 Vpeak
Safety-limiting values – maximum values allowed in the event of a failure.
Case Temperature TS175 °C
Input Current** IS,INPUT 400 mA
Output Power** PS, OUTPUT 1200 mW
Insulation Resistance at TS, VIO = 500 V RS>109Ω
*Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, IEC/EN/DIN
EN 60747-5-2 for a detailed description of Method a and Method b partial discharge test profiles.
** Refer to the following figure for dependence of PS and IS on ambient temperature.
6
Insulation and Safety Related Specifications
Parameter Symbol HCPL-J314 Units Conditions
Minimum External Air Gap L(101) 7.4 mm Measured from input terminals to output
(Clearance) terminals, shortest distance through air.
Minimum External Tracking L(102) 8.0 mm Measured from input terminals to output
(Creepage) terminals, shortest distance path along body.
Minimum Internal Plastic Gap 0.5 mm Through insulation distance conductor to
(Internal Clearance) conductor, usually the straight line distance
thickness between the emitter and detector.
Tracking Resistance CTI >175 V DIN IEC 112/VDE 0303 Part 1
(Comparative Tracking Index)
Isolation Group IIIa Material Group (DIN VDE 0110, 1/89, Table 1)
Absolute Maximum Ratings
Parameter Symbol Min. Max. Units Note
Storage Temperature TS-55 125 °C
Operating Temperature TA-40 100 °C
Average Input Current IF(AVG) 25 mA 1
Peak Transient Input Current IF(TRAN) 1.0 A
(<1 µs pulse width, 300pps)
Reverse Input Voltage VR3V
“High” Peak Output Current IOH(PEAK) 0.6 A 2
“Low” Peak Output Current IOL(PEAK) 0.6 A 2
Supply Voltage VCC - V EE -0.5 35 V
Output Voltage VO(PEAK) -0.5 VCC V
Output Power Dissipation PO260 mW 3
Input Power Dissipation PI105 mW 4
Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane
Solder Reflow Temperature Profile See Package Outline Drawings section
7
Electrical Specifications (DC)
Over recommended operating conditions unless otherwise specified.
Test
Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note
High Level Output Current IOH 0.2 A VO = VCC – 4 2 5
0.4 0.5 VO = VCC – 10 3 2
Low Level Output Current IOL 0.2 0.4 A VO = VEE + 2.5 5 5
0.4 0.5 VO = VEE+10 6 2
High Level Output Voltage VOH VCC-4 VCC-1.8 V IO = -100 mA 1 6,7
Low Level Output Voltage VOL 0.4 1 V IO = 100 mA 4
High Level Supply Current ICCH 0.7 3 mA IO = 0 mA 7,8 14
Low Level Supply Current ICCL 1.2 3 mA IO = 0 mA
Threshold Input Current Low to High IFLH 6mAI
O = 0 mA, 9,15
Threshold Input Voltage Low to High VFHL 0.8 V VO > 5 V
Input Forward Voltage VF1.2 1.5 1.8 V IF = 10 mA 16
Temperature Coefficient of Input DVF/DTA-1.6 mV/°C
Forward Voltage
Input Reverse Breakdown Voltage BVR5VI
R = 10 µA
Input Capacitance CIN 60 pF f = 1 MHz,
VF = 0 V
Recommended Operating Conditions
Parameter Symbol Min. Max. Units Note
Power Supply VCC - VEE 10 30 V
Input Current (ON) IF(ON) 812mA
Input Voltage (OFF) VF(OFF) -3.0 0.8 V
Operating Temperature TA-40 100 °C
8
Notes:
1. Derate linearly above 70 °C free air temperature at a rate of 0.3 mA/ °C.
2. Maximum pulse width = 10 µs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak
minimum = 0.4 A. See Application section for additional details on limiting IOL peak.
3. Derate linearly above 85 °C, free air temperature at the rate of 4.0 mW/°C.
4. Input power dissipation does not require derating.
5. Maximum pulse width = 50 µs, maximum duty cycle = 0.5%.
6. In this test, VOH is measured with a DC load current. When driving capacitive load VOH will approach VCC as IOH approaches zero amps.
7. Maximum pulse width = 1 ms, maximum duty cycle = 20%.
8. In accordance with UL 1577, each HCPL-J314 optocoupler is proof tested by applying an insulation test voltage ≥ 5000 Vrms for 1 second (leakage
detection current limit II-O ≤ 5 µA). This test is performed before 100% production test for partial discharge (method B) shown in the IEC/EN/DIN
EN 60747-5-2 Insulation Characteristics Table, if applicable.
9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together.
10. PDD is the difference between tPHL and tPLH between any two parts or channels under the same test conditions.
11. Common mode transient immunity in the high state is the maximum tolerable |dVcm/dt| of the common mode pulse VCM to assure that the
output will remain in the high state (i.e. Vo > 6.0 V).
12. Common mode transient immunity in a low state is the maximum tolerable |dVCM/dt| of the common mode pulse, VCM, to assure that the output
will remain in a low state (i.e. Vo < 1.0 V).
13. This load condition approximates the gate load of a 1200 V/25 A IGBT.
14. For each channel. The power supply current increases when operating frequency and Qg of the driven IGBT increases.
15. Device considered a two terminal device: Channel one output side pins shorted together, and channel two output side pins shorted together.
Switching Specifications (AC)
Over recommended operating conditions unless otherwise specified.
Test
Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note
Propagation Delay Time to High Output tPLH 0.1 0.2 0.7 µs Rg = 47 Ω, Cg = 3 nF, 10,11, 14
Level f = 10 kHz, 12,13,
Propagation Delay Time to Low Output tPHL 0.1 0.3 0.7 µsDuty Cycle = 50%, 14,17
Level f = 10 kHz, IF = 8 mA,
Propagation Delay Difference PDD -0.5 0.5 µsVCC = 30 V 10
Between Any Two Parts or Channels
Rise Time tR50 ns
Fall Time tF50 ns
Output High Level Common Mode |CMH| 10 30 kV/µsT
A = 25°C, 18 11
Transient Immunity VCM = 1.5 kV
Output Low Level Common Mode |CML| 10 30 kV/µs1812
Transient Immunity
Package Characteristics
For each channel unless otherwise specified.
Test
Parameter Symbol Min. Typ. Max. Units Conditions Fig. Note
Input-Output Momentary Withstand VISO 3750 Vrms TA = 25°C, 8,9
Voltage RH < 50% for 1 min.
Output-Output Momentary Withstand VO-O 1500 Vrms 15
Voltage
Input-Output Resistance RI-O 1012 ΩVI-O = 500 V 9
Input-Output Capacitance CI-O 1.2 pF Freq = 1 MHz
9
Figure 1. VOH vs. Temperature. Figure 2. IOH vs. Temperature. Figure 3. VOH vs. IOH.
Figure 4. VOL vs. Temperature. Figure 5. IOL vs. Temperature. Figure 6. VOL vs. IOL.
Figure 7. ICC vs. Temperature. Figure 8. ICC vs. VCC. Figure 9. IFLH vs. Temperature.
(V
OH
-V
CC
) – HIGH OUTPUT VOLTAGE DROP – V
-50
-2.5
T
A
– TEMPERATURE – °C
125-25
0
0 25 75 10050
-2.0
-1.5
-1.0
-0.5
I
OH
– OUTPUT HIGH CURRENT – A
-50
0.30
T
A
– TEMPERATURE – °C
125-25
0.40
0 25 75 10050
0.32
0.34
0.36
0.38
0
-6
I
OH
– OUTPUT HIGH CURRENT – A
0.6
0
0.2 0.4
-5
-4
-3
-1
(V
OH
-V
CC
) – OUTPUT HIGH VOLTAGE DROP – V
-2
V
OH
V
OL
– OUTPUT LOW VOLTAGE – V
-50
0.39
T
A
– TEMPERATURE – °C
125-25
0.44
0 25 75 10050
0.40
0.41
0.42
0.43
I
OL
– OUTPUT LOW CURRENT – A
-50
0.440
T
A
– TEMPERATURE – °C
125-25
0.470
0 25 75 10050
0.450
0.455
0.460
0.465
0.445
ICC – SUPPLY CURRENT – mA
-50
0
TA – TEMPERATURE – °C
125-25
1.4
0 25 75 10050
0.4
0.6
0.8
1.2
0.2
1.0
ICCL
ICCH
I
CC
– SUPPLY CURRENT – mA
10
0
V
CC
– SUPPLY VOLTAGE – V
3015
1.2
20 25
0.4
0.8
0.2
0.6
1.0
I
CC
L
I
CC
H
I
FLH
– LOW TO HIGH CURRENT THRESHOLD – mA
-50
1.5
T
A
– TEMPERATURE – °C
125-25
3.5
0 25 75 10050
2.0
2.5
3.0
V
OL
– OUTPUT LOW VOLTAGE – V
0
0
I
OL
– OUTPUT LOW CURRENT – mA
700100
25
400 500
5
20
200 300 600
15
10
10
Figure 10. Propagation Delay vs. VCC. Figure 11. Propagation Delay vs. IF. Figure 12. Propagation Delay vs.
Temperature.
Figure 13. Propagation Delay vs. Rg. Figure 14. Propagation Delay vs. Cg. Figure 15. Transfer Characteristics.
Figure 16. Input Current vs. Forward Voltage.
T
P
– PROPAGATION DELAY – ns
6
0
I
F
– FORWARD LED CURRENT – mA
18
400
91512
100
200
300
-50
0
T
A
– TEMPERATURE – °C
125-25
500
0 25 75 10050
100
200
300
400
T
P
– PROPAGATION DELAY – ns
T
PLH
T
PHL
T
P
– PROPAGATION DELAY – ns
0
200
Rg – SERIES LOAD RESISTANCE – Ω
200
400
50 150100
250
300
350
T
PLH
T
PHL
IF – FORWARD CURRENT – mA
1.2
0
VF – FORWARD VOLTAGE – V
1.8
25
1.4 1.6
5
10
15
20
T
P
– PROPAGATION DELAY – ns
0
0
Cg – LOAD CAPACITANCE – nF
100
400
20 8060
100
200
300
T
PLH
T
PHL
40
T
P
– PROPAGATION DELAY – ns
10
0
V
CC
– SUPPLY VOLTAGE – V
30
400
15 2520
100
200
300
T
PLH
T
PHL
V
O
– OUTPUT VOLTAGE – V
0
-5
I
F
– FORWARD LED CURRENT – mA
6
25
15
1
35
234
5
5
0
10
20
30
11
Figure 17. Propagation Delay Test Circuit and Waveforms.
Figure 18. CMR Test Circuit and Waveforms.
0.1 µF VCC = 15
to 30 V
47 Ω
1
3
IF = 7 to 16 mA
VO
+
–
+
–
2
4
8
6
7
5
10 KHz
50% DUTY
CYCLE
500 Ω
3 nF
IF
VOUT
tPHL
tPLH
tf
tr
10%
50%
90%
0.1 µF
VCC = 30 V
1
3
IF
VO+
–
+
–
2
4
8
6
7
5
A
+
–
B
VCM = 1500 V
5 V
VCM
∆t
0 V
VO
SWITCH AT B: IF = 0 mA
VO
SWITCH AT A: IF = 10 mA
VOL
VOH
∆t
VCM
δV
δt=
12
Applications Information
Eliminating Negative IGBT Gate
Drive
To keep the IGBT firmly off,
the HCPL-J314 has a very low
maximum VOL specification of
1.0 V. Minimizing Rg and
the lead inductance from the
HCPL-J314 to the IGBT gate and
emitter (possibly by mounting
the HCPL-J314 on a small PC
board directly above the IGBT)
can eliminate the need for
negative IGBT gate drive in
many applications as shown in
Figure 19. Care should be taken
with such a PC board design to
avoid routing the IGBT collector
or emitter traces close to the
HCPL-J314 input as this can
result in unwanted coupling of
transient signals into the input
of HCPL-J314 and degrade
performance. (If the IGBT
drain must be routed near the
HCPL-J314 input, then the LED
should be reverse biased when
in the off state, to prevent the
transient signals coupled from
the IGBT drain from turning on
the HCPL-J314.)
Figure 19. Recommended LED Drive and Application Circuit for HCPL-J314.
+ HVDC
3-PHASE
AC
- HVDC
0.1 µF V
CC
= 15 V
1
3
+
–
2
4
8
6
7
5
HCPL-J314
Rg
Q1
Q2
270 Ω
+5 V
CONTROL
INPUT
74XXX
OPEN
COLLECTOR
13
Selecting the Gate Resistor (Rg)
Step 1: Calculate Rg minimum from the IOL peak specification. The
IGBT and Rg in Figure 19 can be analyzed as a simple RC circuit with
a voltage supplied by the HCPL-J314.
VCC – VOL
Rg ≥————————
IOLPEAK
24 V – 5 V
= ————————
0.6A
= 32 Ω
The VOL value of 5 V in the previous equation is the VOL at the peak
current of 0.6A. (See Figure 6).
Step 2: Check the HCPL-J314 power dissipation and increase Rg if
necessary. The HCPL-J314 total power dissipation (PT) is equal to
the sum of the emitter power (PE) and the output power (PO).
PT = PE + PO
PE = IF 6 VF 6 Duty Cycle
PO = PO(BIAS) + PO(SWITCHING) = ICC 6 VCC + ESW (Rg,Qg) 6 f
= (ICCBIAS + KICC 6 Qg 6 f) 6 VCC + ESW (Rg,Qg) 6 f
where KICC 6 Qg 6 f is the increase in ICC due to switching and KICC is
a constant of 0.001 mA/(nC*kHz). For the circuit in Figure 19 with IF
(worst case) = 10 mA, Rg = 32 Ω, Max Duty Cycle = 80%,
Qg = 100 nC, f = 20 kHz and TAMAX = 85°C:
PE = 10 mA 6 1.8 V 6 0.8 = 14 mW
PO = (3 mA + (0.001 mA/(nC 6 kHz)) 6 20 kHz 6 100 nC) 6 24 V +
0.4
µ
J 6 20 kHz = 80 mW
< 260 mW (PO(MAX) @ 85°C)
The value of 3 mA for ICC in the previous equation is the max. ICC
over entire operating temperature range.
Since PO for this case is less than PO(MAX), Rg = 32 Ω is all right for
the power dissipation.
Figure 20. Energy Dissipated in the
HCPL-J314 and for Each IGBT Switching
Cycle.
LED Drive Circuit Considerations for
Ultra High CMR Performance
Without a detector shield, the
dominant cause of optocoupler
CMR failure is capacitive
coupling from the input side of
the optocoupler, through the
package, to the detector IC
as shown in Figure 21. The
HCPL-J314 improves CMR
performance by using a detector
IC with an optically transparent
Faraday shield, which diverts
the capacitively coupled current
away from the sensitive IC
circuitry. However, this shield
does not eliminate the capacitive
coupling between the LED and
optocoupler pins 5-8 as shown in
Figure 22. This capacitive
coupling causes perturbations in
the LED current during common
mode transients and becomes
the major source of CMR failures
for a shielded optocoupler. The
main design objective of a high
CMR LED drive circuit becomes
keeping the LED in the proper
state (on or off) during common
mode transients. For example,
the recommended application
circuit (Figure 19), can achieve
10 kV/µs CMR while minimizing
component complexity.
Techniques to keep the LED in
the proper state are discussed in
the next two sections.
Esw – ENERGY PER SWITCHING CYCLE – µJ
0
0
Rg – GATE RESISTANCE – Ω
100
1.5
20
4.0
40
1.0
60 80
3.5 Qg = 50 nC
Qg = 100 nC
Qg = 200 nC
Qg = 400 nC
3.0
2.0
0.5
2.5
14
Figure 21. Optocoupler Input to Output Capacitance Model
for Unshielded Optocouplers.
Figure 22. Optocoupler Input to Output Capacitance Model
for Shielded Optocouplers.
Figure 23. Equivalent Circuit for Figure 17 During Common Mode
Transient.
Figure 24. Not Recommended Open Collector Drive Circuit. Figure 25. Recommended LED Drive Circuit for Ultra-High CMR IPM Dead
Time and Propagation Delay Specifications.
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
C
LEDO1
C
LEDO2
Rg
1
3
V
SAT
2
4
8
6
7
5
+
V
CM
I
LEDP
C
LEDP
C
LEDN
SHIELD
* THE ARROWS INDICATE THE DIRECTION
OF CURRENT FLOW DURING –dV
CM
/dt.
+5 V
+
–V
CC
= 18 V
• • •
• • •
0.1
µF
+
–
–
1
3
2
4
8
6
7
5
C
LEDP
C
LEDN
SHIELD
+5 V
Q1 I
LEDN
1
3
2
4
8
6
7
5
CLEDP
CLEDN
SHIELD
+5 V
15
CMR with the LED On (CMRH)
A high CMR LED drive circuit
must keep the LED on during
common mode transients. This is
achieved by overdriving the LED
current beyond the input
threshold so that it is not pulled
below the threshold during a
transient. A minimum LED
current of 8 mA provides
adequate margin over the
maximum IFigure 26. Minimum
LED Skew for Zero Dead
Time.Figure 27. Waveforms for
Dead Time. of 5 mA to achieve
10 kV/µs CMR.
CMR with the LED Off (CMRL)
A high CMR LED drive
circuit must keep the LED off
(VF ≤ VF(OFF)) during common
mode transients. For example,
during a -dVCM/dt transient in
Figure 23, the current flowing
through CLEDP also flows
through the RSAT and VSAT of
the logic gate. As long as the low
state voltage developed across
the logic gate is less than
VF(OFF) the LED will remain off
and no common mode failure
will occur.
The open collector drive circuit,
shown in Figure 24, can not
keep the LED off during a
+dVCM/dt transient, since all
the current flowing through
CLEDN must be supplied by the
LED, and it is not recommended
for applications requiring ultra
high CMR1 performance. The
alternative drive circuit which
like the recommended
application circuit (Figure 19),
does achieve ultra high CMR
performance by shunting the
LED in the off state.
IPM Dead Time and Propagation
Delay Specifications
The HCPL-J314 includes a
Propagation Delay Difference
(PDD) specification intended to
help designers minimize “dead
time” in their power inverter
designs. Dead time is the time
high and low side power
transistors are off. Any overlap
in Ql and Q2 conduction will
result in large currents flowing
through the power devices from
the high-voltage to the low-
voltage motor rails. To minimize
dead time in a given design, the
turn on of LED2 should be
delayed (relative to the turn off
of LED1) so that under worst-
case conditions, transistor Q1
has just turned off when
transistor Q2 turns on, as
shown in Figure 26. The amount
of delay necessary to achieve
this condition is equal to the
maximum value of the
propagation delay difference
specification, PDD max, which is
specified to be 500 ns over the
operating temperature range of
-40° to 100°C.
Delaying the LED signal by the
maximum propagation delay
difference ensures that the
minimum dead time is zero, but
it does not tell a designer what
the maximum dead time will be.
The maximum dead time is
equivalent to the difference
between the maximum and
minimum propagation delay
difference specification as
shown in Figure 27. The
maximum dead time for the
HCPL-J314 is 1 µs (= 0.5 µs -
(-0.5 µs)) over the operating
temperature range of
-40°C to 100°C.
Note that the propagation delays
used to calculate PDD and dead
time are taken at equal
temperatures and test conditions
since the optocouplers under
consideration are typically
mounted in close proximity to
each other and are switching
identical IGBTs.
Figure 26. Minimum LED Skew for Zero Dead Time.
Figure 27. Waveforms for Dead Time.
t
PLH
MIN
MAXIMUM DEAD TIME
(DUE TO OPTOCOUPLER)
= (t
PHL MAX
-
t
PHL MIN
) + (t
PLH MAX
-
t
PLH MIN
)
= (t
PHL MAX
-
t
PLH MIN
) – (t
PHL MIN
-
t
PLH MAX
)
= PDD* MAX – PDD* MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION
DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
V
OUT1
I
LED2
V
OUT2
I
LED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
t
PHL MIN
t
PHL MAX
t
PLH MAX
PDD* MAX
(t
PHL-
t
PLH
)
MAX
tPHL MAX
tPLH MIN
PDD* MAX = (tPHL- tPLH)MAX = tPHL MAX - tPLH MIN
*PDD = PROPAGATION DELAY DIFFERENCE
NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS
ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS.
VOUT1
ILED2
VOUT2
ILED1
Q1 ON
Q2 OFF
Q1 OFF
Q2 ON
www.agilent.com/semiconductors
For product information and a complete list of
distributors, please go to our web site.
For technical assistance call:
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(916) 788-6763
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Data subject to change.
Copyright © 2005 Agilent Technologies, Inc.
Obsoletes 5989-2140EN
April 24, 2005
5989-2942EN
