2004 Microchip Technology Inc. DS21095J-page 1
24LC21
Features:
• Single supply with operation down to 2.5V
• Completely implements DDC1™/DDC2™ interface
for monitor identification
• Low-power CMOS technology:
- 1 mA active current typical
-10 µA standby current typical at 5.5V
• 2-wire serial interface bus, I2C™ compatible
• Self-timed write cycle (including auto-erase)
• Page-write buffer for up to 8 bytes
• 100 kHz (2.5V) and 400 kHz (5V) compatibility
• Factory programming (QTP) available
• 1,000,000 erase/write cycles ensured
• Data retention > 200 years
• 8-pin PDIP and SOIC package
• Available for extended temperature ranges
Description:
The Microchip Technology Inc. 24LC21 is a 128 x 8 bit
Electrically Erasable PROM. This device is designed
for use in applications requiring storage and serial
transmission of configuration and control information.
Two modes of operation have been implemented:
Transmit-only mode and Bidirectional mode. Upon
power-u p, the device will be i n the Tra nsmit-only mod e,
sending a serial bit stream of the entire memory array
contents, clocked by the VCLK pin. A valid high-to-low
transiti on on the SCL pin will caus e the de vi ce to en ter
the Bidirectional mode, with byte selectable read/write
cap ability of the memory array . The 24LC21 is available
in a standard 8-pin PDIP and SOIC package, in both
commercial and industrial temperature ranges.
Package Types
Block Diagram
Com mer cial (C): 0°C to +70°C
Industri al (I): -40°C to +85°C
24LC21
NC
NC
NC
VSS
1
2
3
4
8
7
6
5
VCC
VCLK
SCL
SDA
24LC21
NC
NC
NC
VSS
1
2
3
4
8
7
5
5
VCC
VCLK
SCL
SDA
PDIP
SOIC
HV Gener a to r
EEPROM
Array
Page Latches
YDEC
XDEC
Sense Amp
R/W Control
Memory
Control
Logic
I/O
Control
Logic
VCLK
SDA SCL
VCC
VSS
1K 2.5V Dual Mode I2C™ Serial EEPROM
I2C is a trademark of Philips Corporation.
DDC is a trademark of the Video Electronics Standards Association.
Not recommended for new designs –
Please use 24LCS21A.
24LC21
DS21095J-page 2 2004 Microchip Technology Inc.
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................7.0V
All inputs and outputs w.r.t. VSS ........................................................................................................ -0.6V to VCC + 1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................ -40°C to +125°C
Soldering temperature of leads (10 seconds) .......................................................................................................+300°C
ESD protection on all pins ......................................................................................................................................................≥ 4 kV
TABLE 1-1: DC CHARACTERISTICS
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device . This i s a stres s ratin g only and functio nal ope ration of the device at thes e or any other co nditio ns abov e those
indicated in the operational listings of this specification is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
DC CHARACTERISTICS VCC = +2.5V to 5.5V
Commercial (C): TA = 0°C to +70°C
Industrial (I): TA = -40°C to +85°C
Parameter Symbol Min Max Units Conditions
SCL and SDA pins:
High-level input voltage
Low-level input voltage
VIH
VIL .7 VCC
——
.3 VCC V
V—
—
Input levels on VCLK pin:
High-level input voltage
Low-level input voltage
VIH
VIL 2.0
—.8
.2 VCC V
VVCC ≥ 2.7V (Note 1)
VCC < 2.7V (Note 1)
Hysteresis of Schmitt Trigger inputs VHYS .05 VCC —V(Note 1)
Low-level output voltage VOL1—.4VIOL = 3 mA, VCC = 2.5V (Note 1 )
Low-level output voltage VOL2—.6VIOL = 6 mA, VCC = 2.5V
Input leakage current ILI -10 10 µAVIN = .1V to VCC
Output lea kage curre nt ILO -10 10 µAVOUT = .1V to VCC
Pin capacitance (all inputs/outputs) CIN, COUT —10pFVCC = 5.0V (Note1),
TA = 25°C, FCLK = 1 MHz
Operati ng current ICC Write
ICC Read —
—3
1mA
mA VCC = 5.5V, SCL = 400 kHz
Standby current ICCS —
—30
100 µA
µAVCC = 3.0V, SDA = SCL = VCC
VCC = 5.5V, SDA = SCL = VCC
(Note 2)
Note 1: This parameter is periodically sampled and not 100% tested.
2: VLCK must be grounded.
2004 Microchip Technology Inc. DS21095J-page 3
24LC21
TABLE 1-2: AC CHARACTERISTICS
Parameter Symbol Standard Mode Vcc= 4.5 - 5.5V
Fast Mode Units Remarks
Min Max Min Max
Clock frequency FCLK —100—400kHz—
Clock high time THIGH 4000 — 600 — ns —
Clock low time TLOW 4700 — 1300 — ns —
SDA and SCL rise time TR— 1000 — 300 ns (Note 1)
SDA and SCL fall time TF— 300 — 300 ns (Note 1)
Start condition hold time THD:STA 4000 — 600 — ns After this pe riod the first cloc k
puls e is generat ed
Start condition setup time TSU:STA 4700 — 600 — ns Only relevant for repeated
Start condition
Data input hold time THD:DAT 0—0—ns(Note 2)
Data input setup time TSU:DAT 250 — 100 — ns —
Stop condition setup time TSU:STO 4000 — 600 — ns —
Output valid from clock TAA — 3500 — 900 ns (Note 2)
Bus free time TBUF 4700 — 1300 — ns Time the bus must be free
before a new transmission
can st a rt
Output fall time from VIH
min. to VIL max. TOF — 250 20 + .1
CB250 ns (Note 1), CB ≤ 100 pF
Input filter spike suppres-
sion (SDA and SCL pins) TSP —50—50ns(Note 3)
Write cycle ti me TWR — 10 — 10 ms By te or Page mode
Transmit-only Mode Parameters
Output valid from VCLK TVAA — 2000 — 1000 ns —
VCLK high time TVHIGH 4000 — 600 — ns —
VCLK low time TVLOW 4700 — 1300 — ns —
Mode transition time TVHZ — 500 — 500 ns —
Transmit-only power-up
time TVPU 0—0—ns—
Endurance — 1M — 1M — cycles 25°C, VCC = 5.0V, Block
mode (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a TI specification fo r standard oper ation.
4: This parameter is not tested but ensur ed by characterization. For endurance estimat es in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at: www.microchip.com
24LC21
DS21095J-page 4 2004 Microchip Technology Inc.
2.0 FUNCTIONAL DESCRIPTION
The 24LC 21 opera tes in tw o mod es, the Transmit-only
mode and the Bidirectional mode. There is a sepa rate
two wire pr otocol to su pport ea ch mod e, each havin g a
separate clock input and sharing a common data line
(SDA). The device enters the T ransmit-only mode upon
power-up. In this mode, the device transmits data bits
on the SDA pin in response to a clock signal on the
VCLK pin. The device will remain in this mode until a
valid high-to-low transition is placed on the SCL input.
When a valid transition on SCL is recognized, the
device will switch into the Bidirectional mode. The only
way to switch the device back to the Transmit-only
mode is to remove power from the device.
2.1 Transmit-only Mode
The device will power-up in the Transmit-only mode.
This mode supports a unidirectional two wire protocol
for transmission of the contents of the memory array.
This device requires that it be initialized prior to valid
data being sent in the Transmit-only mode (see Initial-
ization Procedure, below). In this mode, data is trans-
mitted on the SDA pin in 8-bit bytes, each followed by
a ninth, null bit (see Figure 2-1). The clock source for
the Transmit-only mode is provided on the VCLK pin,
and a data bit is output on the rising edge on this pin.
The eigh t b its in ea ch byte are transmitted M os t Si gni f-
icant bit first. Eac h byte within the mem ory array will be
output in sequence. When the last byte in the memory
array is transmitted, the output will wrap around to the
first location and continue. The Bidirectional mode
Clock (SCL) pin must be held high for the device to
remain in the Transmit-only mode.
2.2 Initialization Procedure
After VCC has st abilized, th e device w ill be in the Tr ans-
mit-only mo de. Nine clo ck cy cl es on th e V CLK pin must
be give n to t he device f or it to p erform i nternal syn chro-
nization. During this period, the SDA pin will be in a
high-impedance state. On the rising edge of the tenth
clock cycle, the device will output the first valid data bit
which will be the Most Significant bit of a byte. The
device w ill po w er-up at an i nde term in ate by te address.
(Figure 2-2).
FIGURE 2-1: TRANSMIT-ONLY MODE
FIGURE 2-2: DEVICE INITIALIZATION
SCL
SDA
VCLK
TVAA TVAA
Bit 1 (LSB)
Null Bit
Bit 1 (MSB) Bit 7
TVLOWTVHIGH
TVAA TVAA
Bit 8 Bit 7High-impedance for 9 clock cycles
TVPU
12 891011
SCL
SDA
VCLK
VCC
2004 Microchip Technology Inc. DS21095J-page 5
24LC21
3.0 BIDIRECTIONAL MODE
The 24LC21 can be switched into the Bidirectional
mode (see Figure 3-1) by applying a valid high-to-low
transition on the Bidirectional mode clock (SCL). When
the device has been switched into the Bidirectional
mode, the VCLK input is d isregarded, with the exception
that a logic high level is required to enable write capa-
bility. This mode supports a two wire bidirectional data
transmission protocol. In this protocol, a device that
sends data on the bus is defined to be the transmitter,
and a devic e that rec eives data from the bus is de fined
to be the receiver. The bus must be controlled by a
master device that generates the Bidirectional mode
clock (SCL), controls access to the bus and generates
the S t art and S top condition s, while the 24L C21 acts as
the slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
3.1 Bidirectional Mode Bus
Characteristics
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stab le whene ver the cl ock lin e is high . Change s in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (se e Figur e 3-2).
3.1.1 BUS NOT BUSY (A)
Both data and clock lines remain high.
3.1.2 START DATA TRANSFER (B)
A hig h- to - lo w t ran si t i on of t h e SD A l in e whi l e t h e c lo ck
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.1.3 STOP DATA TRANSFER (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
FIGURE 3-1: MODE TRAN SITION
FIGURE 3-2: DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
SDA
VCLK
Bidirectional mode
TVHZ
Transmit-only mode
(A) (B) (D) (D) (A
)
(C)
Start
Condition Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
SCL
SDA
24LC21
DS21095J-page 6 2004 Microchip Technology Inc.
3.1.4 DATA VALID (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of t he cl oc k si gna l. There is one clock puls e per
bit of data.
Each da t a tra nsfer is init iate d with a Start cond ition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
theoretically unlimited, although only the last eight will
be stored when doing a write operation. When an
overwr ite does occur, it will replace dat a in a first in first
out fashion.
3.1.5 ACKNOWLEDGE
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The mast er device mus t ge nera te a n ext ra c lock
pulse which is associated with this Acknowledge bit.
The device that acknowledges has to pull down the
SDA line d uring th e ackn owledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by no t g ene rati ng an Acknowledge bi t on the las t
byte that has been clocked out of the slave. In this
case, the slave must leave the data line high to enable
the master to generate the Stop condition.
FIGURE 3-3: BUS TIMING START/STOP
FIGURE 3-4: BUS TIMING DATA
Note: The 24LC21 does not generate any
Acknowledge bits if an internal program-
ming cycle is in prog res s.
TSU:STA THD:STA
VHYS
TSU:STO
Start Stop
SCL
SDA
TSU:STA
TF
TLOW
THIGH
TR
THD:DAT TSU:DAT TSU:STO
THD:STA TBUF
TAA
TAA
TSP
THD:STA
SCL
SDA
IN
SDA
OUT
2004 Microchip Technology Inc. DS21095J-page 7
24LC21
3.1.6 SLAVE ADDRESS
After gene rating a S tart condit ion, the bus master trans-
mits the slave address co nsisting of a 7-bi t devic e code
‘1010’ for the 24LC21, followed by three “don’t care”
bits.
The eighth bit of slav e address determine s if the master
device wants to read or write to the 24LC21 (Figure 3-5).
The 24LC21 monitors the bus for its corresponding
slave address all the time. It generates an
Acknowledge bit if the slave address was true and it is
not in a pr ogramming mode.
FIGURE 3-5: CONTROL BYTE
ALLOCATION
4.0 WRITE OPERATION
4.1 Byte Write
Following the Start signal from the master, the slave
address (4 bits), the “don’t care” bits (3 bits) and the
R/W bit which is a logic low, is placed onto the bus by
the master transmitter. This indicates to the
addressed slave receiver that a byte with a word
address will fol low after it has gener ated an Ackn owl-
edge bit during the ninth clock cycle. Therefore, the
next byte transmitted by the master is the word
address and will be written into the address pointer of
the 24LC21. After receiving another Acknowledge
signal from the 24LC21 the master device will transmit
the data w ord to be wr itten into th e addressed mem-
ory location. The 24LC21 acknowledges again and
the master generates a Stop condition. This initiates
the internal write cycle, and during this time the
24LC21 will not generate Acknowledge signals
(Figure 4-1).
It is required that VCLK be held at a logic high level in
order to program the device. This applies to byte write
and page write operation. Note that VCLK can go low
while the device is in its self-timed program operation
and not affect programming.
4.2 Page Write
The write control byte, word address and the first data
byte are tran smitt ed to th e 24LC21 in the sam e way as
in a byte write. But instead of generating a Stop condi-
tion the master transmits up to eight data bytes to the
24LC21, which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a Stop condition. After the
receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order five bits of the word address remains
const a nt. If the ma ste r s hou ld transmit more tha n eight
words prior to generating the Stop condition, the
address counter will roll over and the previously
receive d dat a will be overwri tten. As w ith the byte w rite
operation, once the Stop condition is received an
internal write cycle will begin (Figure 4-3).
Operation Control Code Chip Select R/W
Read 1010 xxx 1
Write 1010 xxx 0
SLAVE ADDRESS
1010xxx
R/W A
Start Read/Write
24LC21
DS21095J-page 8 2004 Microchip Technology Inc.
It is required that VCLK be held at a logic high level in
order to program the device. This applies to byte write
and page write operation. Note that VCLK can go low
while the device is in its self-timed program operation
and not affect programming.
FIGURE 4-1: BYTE WRITE
FIGURE 4-2: BYTE WRITE
Note: Page write opera tions are lim ited to wr iting
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘pag e s iz e’ ) an d end at addresses tha t a r e
integer multiples of [page size - 1]. If a
page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being w ritte n to the next page as might be
expected. It is therefore necessary for the
application software to prevent page write
operations that would attempt to cross a
page boundary.
S P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
Control
Byte Word
Address Data
A
C
K
A
C
K
A
C
K
VCLK
S P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
Control
Byte Word
Address Data
A
C
K
A
C
K
A
C
K
VCLK
2004 Microchip Technology Inc. DS21095J-page 9
24LC21
FIGURE 4-3: PAG E WRITE
S P
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
TControl
Byte Word
Address Data (n) Data (n + 15)
S
T
O
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
Data (n + 1)
VCLK
24LC21
DS21095J-page 10 2004 Microchip Technology Inc.
5.0 ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
comma nd has been is sued from the master , the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If the cycle is complete, then the device will return the
ACK and the master can then proceed with the next
Read or Write command. See Figure 5-1 for the flow
diagram.
FIGURE 5-1: ACKNOWLEDGE
POLLING FLOW
6.0 WRITE PROTECTION
When using the 24LC21 in the Bidirectional mode, the
VCLK pin operates as the write-protect control pin.
Setting VCLK h igh allo ws norma l write operations , whil e
setting VCLK low prevents writing to any location in the
array. Connecting the VCLK pin to VSS would allow the
24LC21 to operate as a serial ROM, although this
configuration would prevent using the device in the
Transmit- onl y mod e.
Send
Write Command
Send Stop
Condit ion to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
Next
Operation
No
Yes
2004 Microchip Technology Inc. DS21095J-page 11
24LC21
7.0 READ OPERATION
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operat ions: current addr ess read , rand om rea d
and sequential read.
7.1 Current Address Read
The 24LC21 contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by one. Therefore, if the previous
access (either a read or write operation) was to
address n, the next current address read operation
would ac ce ss d ata from a ddress n + 1. U pon rec ei pt of
the slave address with R/W bit set to ‘1’, the 24LC21
issues an a cknowl edge and tran smits the eig ht bit dat a
word. Th e master w ill n ot acknowl edge th e trans fer but
does generate a Stop condition and the 24LC21
discontinues transmission (Figure 7-1).
7.2 Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this typ e of re ad ope ration, first the w o rd ad dres s must
be set. This is done b y sending the word address to the
24LC21 as part of a write operation. After the word
address is sent, the master genera tes a Start co nditio n
following the acknowledge. This terminates the write
operatio n, but not bef ore the internal addr ess pointe r is
set. Then the master issues the control byte again but
with the R/W bit set to a ‘1’. The 24LC21 w ill then is sue
an ac k n owl e dg e an d t r an s mi ts t h e ei ght b i t da ta wor d .
The master will not acknowledge the transfer but does
generate a Stop condition and the 24LC21
discontinues transmission (Figure 7-2).
7.3 Sequentia l Read
Sequential reads are initiated in the same way as a
random re ad except that after the 24LC21 transmit s the
first data byte, the master issues an acknowledge as
opposed to a Stop condition in a random read. This
directs the 24LC21 to transmit the next sequentially
addressed 8-bit word (see Figure 7-3).
To provide sequential reads the 24LC21 contains an
internal address poin ter which is inc remented by o ne at
the com ple tio n o f each ope rati on. Thi s a ddre ss po int er
allows the entire memory contents to be serially read
during one operation.
7.4 Noise Protection
The 24LC21 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5 volts at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation even on a noisy bus.
FIGURE 7-1: CURRENT ADDRESS READ
SP
BUS ACT IV IT Y
MASTER
SDA LINE
BUS ACT IV IT Y
S
T
A
R
T
Control
Byte Data (n)
A
C
K
N
O
A
C
K
S
T
O
P
24LC21
DS21095J-page 12 2004 Microchip Technology Inc.
FIGURE 7-2: RANDOM READ
FIGURE 7-3: SEQUENTIAL READ
S P
S
BUS ACTIVITY
MASTER
SDA LINE
BUS ACTIVITY
S
T
A
R
T
S
T
O
P
Control
Byte Word
Address Da ta (n)
A
C
K
A
C
K
N
O
A
C
K
Control
Byte
A
C
K
S
T
A
R
T
P
BUS ACT IV IT Y
MASTER
SDA LINE
BUS ACT IV IT Y
S
T
O
P
Control
Byte
A
C
K
N
O
A
C
K
Data (n) Data (n + 1) Data (n + 2) Data (n + X)
A
C
K
A
C
K
A
C
K
2004 Microchip Technology Inc. DS21095J-page 13
24LC21
8.0 PIN DESCRIPTIONS
TABLE 8-1: PIN FUNCTION TABLE
8.1 SDA
This p in is use d to transfer addresses and data into and
out of the device , when the devi ce is in th e Bidirectiona l
mode. In the Transmit-only mode, which only allows
data to be read from the device, dat a is also tr ansferred
on the SDA pin. This pin is an open drain terminal,
therefore the SDA bus requires a pull-up resistor to
VCC (typical 10KΩ for 100 kHz, 2KΩ for 400 kHz).
For normal data transfer in the Bidirection al mode, SDA
is allowed to change only during SCL low. Changes
during SCL high are reserved for indicating the Start
and Stop conditions.
8.2 SCL
This pin is the clock input for the Bidirectional mode,
and is used to synchronize data transfer to and from the
device. It is also used as the signaling input to switch
the device from the Transmit-only mode to the
Bidirectional mode. It must remain high for the chip to
continue operation in the Transmit-only mode.
8.3 VCLK
This pin is the clock input for the Transmit-only mode.
In the Transmit-only mode, each bit is clocked out on
the risin g edge of this si gnal. In the Bidire ct ional mod e,
a high logic level is required on this pin to enable write
capability.
Name Function
VSS Ground
SDA Serial Address/Data I/O
SCL Serial Clock (Bidirectional mode)
VCLK Seri al Clock (Trans mit- only mode)
VCC +2.5V to 5.5V Power Supply
NC No Connection
24LC21
DS21095J-page 14 2004 Microchip Technology Inc.
9.0 PACKAGING INFORMATION
9.1 Package Marking Information
XXXXXNNN
8-Lead PDIP
XXXXXXXX
YYWW 017
Example
24LC21
0410
8-Lead SOIC (.150”)
XXXXXXXX
XXXXYYWW
NNN
Example
24LC21
/SN0410
017
2004 Microchip Technology Inc. DS21095J-page 15
24LC21
8-Lead Plastic Dual In-line (P) – 300 mil Body (PDIP)
B1
B
A1
A
L
A2
p
α
E
eB
β
c
E1
n
D
1
2
Units INCHES* MILLIMETERS
Dime nsion Limits MIN NOM MAX MIN NOM MAX
Number of Pins n88
Pitch p.100 2.54
Top to Seating Plane A .140 .155 .170 3.56 3.94 4.32
Molded Package Thickness A2 .115 .130 .145 2.92 3.30 3.68
Base to Seating Plane A1 .015 0.38
Shoulder to Shoulder Width E .300 .313 .325 7.62 7.94 8.26
Molded Package Width E1 .240 .250 .260 6.10 6.35 6.60
Overall Length D .360 .373 .385 9.14 9.46 9.78
Tip to Seating Plane L .125 .130 .135 3.18 3.30 3.43
Lead Thickness c.008 .012 .015 0.20 0.29 0.38
Upper Lead Width B1 .045 .058 .070 1.14 1.46 1.78
Lower Lead Width B .014 .018 .022 0.36 0.46 0.56
Overall Row Spacing § eB .310 .370 .430 7.87 9.40 10.92
Mold Draft Angle Top α51015 51015
Mold Draft Angle Bottom β51015 51015
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
JEDEC Equivalent: MS-001
Drawing No. C04-018
.010” (0.254mm) per side.
§ Significant Characteristic
24LC21
DS21095J-page 16 2004 Microchip Technology Inc.
8-Lead Plastic Small Outline (SN) – Narrow, 150 mil Body (SOIC)
Foot A ngle φ048048
1512015120
β
Mold Draft Angle Bottom 1512015120
α
Mold Draft Angle Top 0.510.420.33.020.017.013BLead Width 0.250.230.20.010.009.008
c
Lead Thickness
0.760.620.48.030.025.019LFoot Length 0.510.380.25.020.015.010hChamfer Distance 5.004.904.80.197.193.189DOverall Length 3.993.913.71.157.154.146E1Molded Pa ckag e Width 6.206.025.79.244.237.228EOverall Width 0.250.180.10.010.007.004A1Standoff § 1.551.421.32.061.056.052A2Mold ed Packag e Thickness 1.751.551.35.069.061.053AOverall Height 1.27.050
p
Pitch 88
n
Numb er of Pin s MAXNOMMINMAXNOMMINDimension Limits MILLIMETERSINCHES*Units
2
1
D
n
p
B
E
E1
h
L
β
c
45°
φ
A2
α
A
A1
* Controlling Parameter
Notes:
Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed
.010” (0.254mm) per side.
JEDEC Equivalent: MS-012
Drawing No. C04-057
§ Significant Characteristic
2004 Microchip Technology Inc. DS21095J-page 17
24LC21
APPENDIX A: REVISION HISTORY
Revision J
Added note to page 1 header (Not recommended for
new designs).
Added Section 9.0: Package Marking Information.
Added On-li ne Supp ort p ag e.
Updated document format.
24LC21
DS21095J-page 18 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. DS21095J-page 15
24LC21
ON-LINE SUPPORT
Microchip provides on-line support on the Microchip
World Wide Web site.
The web site is used b y Micr ochip as a me ans to mak e
files and information easily available to customers. To
view t he site, the user must have acce ss to the In ternet
and a web browser, such as Netscape® or Microsoft®
Internet Explorer. Files are also available for FTP
download from our FTP site.
Connecting to the Microchip Internet
Web S ite
The Microchip web site is available at the following
URL:
www.microchip.com
The file transfer site is available by using an FTP
service to connect to:
ftp://ftp.microchip.com
The web site and file transfer site provide a variety of
services. Users may download files for the latest
Development Tools, Data Sheets, Application Notes,
User's Guides, Articles and Sample Programs. A vari-
ety of Microchip specific business information is also
available, including listings of Microchip sales offices,
distributors and factory representatives. Other data
available for consideration is:
• Latest Microchip Press Releases
• Technical Support Section with Frequently Asked
Questions
• Design Tips
• Device Errat a
• Job Postin gs
• Mic roch ip Co nsultant Program Member Listing
• Links to other useful web sites related to
Microchip Products
• Confere nces for prod ucts, Dev elopment Systems,
technical information and more
• Listing of seminars and events
SYSTEMS INFORMATION AND
UPGRADE HOT LINE
The Systems Information and Upgrade Line provides
system users a listing of the latest versions of all of
Microchip's development systems software products.
Plus, this line provides information on how customers
can receive the most current upgrade kit s. The Hot Line
Numbe rs are:
1-800-755-2345 for U.S. and most of Canada, and
1-480-792-7302 for the rest of the world.
042003
24LC21
DS21095J-page 16 2004 Microchip Technology Inc.
READER RESPONSE
It is ou r intention to provi de you wit h th e b es t do cu me nt ation po ss ib le to e ns ure suc c es sfu l u se of y ou r M icr oc hip pro d-
uct. If you wi sh to prov ide you r comment s on org anizatio n, clar ity, su bject m atter , a nd ways in whic h our doc umenta tion
can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
To: Technical Publications Manager
RE: Reader Response Total Pages Sent ________
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Address
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Telephone: (_______) _________ - _________
Application (optional):
Would you like a reply? Y N
Device: Literature Number:
Questions:
FAX: (______) _________ - _________
DS21095J24LC21
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
2004 Microchip Technology Inc. DS21095J-page 17
24LC21
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Sales and Support
PART NO. X/XX XXX
PatternPackageTemperature
Range
Device
Device 24LC21: Dual Mode I2C™ Serial EEPROM
24LC21T: Dual Mode I2C™ Serial EEPROM (Tape and Reel)
Temperatu re R ang e Blank = 0°C to +7 0°C
I= -40°C to +85°C
Packag e P = Plastic DIP (300 mi l Body ), 8-le ad
SN = Plastic SOIC (150 mil Body), 8-lead
Data Sheets
Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and
recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following:
1. Your local Microchip sales office
2. The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277
3. The Microchip Worldwide Site (www.microchip.com)
Please specify which device, revision of silicon and Dat a Sheet (include Literature #) you are using.
New Customer Notification System
Register on our web site (www.microchip.com/cn) to receive the most current information on our products.
24LC21
DS21095J-page 18 2004 Microchip Technology Inc.
NOTES:
2004 Microchip Technology Inc. DS21095J-page 19
Information contained in this publication regarding device
applications and the like is intended through sug gestion only
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
No representation or warranty is given and no liability is
assumed by Microc hip Technology Incorporated with respect
to the accuracy or use of such inf orm ation, or inf ringement of
patents or other intellectual property rights arising from such
use or otherwise. Use of Microchip’s products as critical
components in life support systems is not authorized except
with express written approval by Microchip. No licenses are
conveyed, implicitly or otherwise, under any intellectual
property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICST ART,
PRO MATE, PowerSmart, rfPIC, and SmartShunt are
registered trademarks of Microchip Technology Incorporated
in the U.S.A. and other countries.
AmpLab, FilterLab, MX DE V, MXLAB, PICMASTER, SEEV AL,
SmartSensor and The Embedded Control Solutions Company
are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, dsPICDEM,
dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR,
FanSense, FlexROM, fuzzyLAB, In-Circuit Serial
Programming, ICSP, ICEPIC, Migratable Memory, MPA SM ,
MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net,
PICLAB, PICtail, PowerCal, PowerInfo, PowerMate,
PowerTool, rfLAB, rfPICD EM, Select Mode, Smart Serial,
SmartTel and Total Endurance are trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2004, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that it s family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microchip are com mitted to continuously improving the code protect ion f eatures of our
products. Attempts to break Microchip’ s code protection f eature may be a violati on of t he Digit al Millennium Copyright Act. If such act s
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 quality system certification for
its worldwide headquarters, design and wafer fabrication facilities in
Chandler and Tempe, Arizona and Mountain View, California in
October 2003. The Company’s quality system processes and
procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping
devices, Serial EEPROMs, micro peripherals, nonvolat ile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21095J-page 20 2004 Microchip Technology Inc.
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