TC58BVG0S3HBAI4 - TOSHIBA - Datasheet.Live

TC58BVG0S3HBAI4

2019-10-01C

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MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

1 GBIT (128M  8 BIT) CMOS NAND E2PROM

DESCRIPTION

The TC58BVG0S3HBAI4 is a single 3.3V 1Gbit (1,107,296,256 bits) NAND Electrically Erasable and

Programmable Read-Only Memory (NAND E2PROM) organized as (2048  64) bytes  64 pages  1024 blocks.

The device has a 2112-byte static register which allows program and read data to be transferred between the register

and the memory cell array in 2112-bytes increments. The Erase operation is implemented in a single block unit (128

Kbytes  4 Kbytes: 2112 bytes  64 pages).

The TC58BVG0S3HBAI4 is a serial-type memory device which utilizes the I/O pins for both address and data

input/output as well as for command inputs. The Erase and Program operations are automatically executed, making

the device most suitable for applications such as solid-state file storage, voice recording, image file memory for still

cameras and other systems which require high-density non-volatile memory data storage.

The TC58BVG0S3HBAI4 has ECC logic on the chip and 8bit read errors for each 528Bytes can be corrected

internally.

FEATURES

 Organization x8

Memory cell array 2112  64K  8

Register 2112 8

Page size 2112 bytes

Block size (128K  4K) bytes

 Modes

Read, Reset, Auto Page Program, Auto Block Erase, Status Read, Page Copy, ECC Status Read

 Mode control

Serial input/output

Command control

 Number of valid blocks

Min 1004 blocks

Max 1024 blocks

 Power supply

VCC  2.7V to 3.6V

 Access time

Cell array to register 40 s typ.

Read Cycle Time 25 ns min (CL=50pF)

 Program/Erase time

Auto Page Program 330 s/page typ.

Auto Block Erase 2.5 ms/block typ.

 Operating current

Read (25 ns cycle) 30 mA max

Program (avg.) 30 mA max

Erase (avg.) 30 mA max

Standby 50 A max

 Package

P-TFBGA63-0911-0.80CZ (Weight: 0.15 g typ.)

 8bit ECC for each 528Bytes is implemented on a chip.

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PIN ASSIGNMENT (TOP VIEW)

1

2

3

4

5

6

7

8

9

10

A

NC

B

NC

C

WP

--------

ALE

VSS

CE

--------

WE

--------

RY/BY

--------

D

NC

RE

--------

CLE

NC

E

NC

F

NC

G

NC

H

NC

I/O1

NC

VCC

J

NC

I/O2

NC

VCC

I/O6

I/O8

K

VSS

I/O3

I/O4

I/O5

I/O7

VSS

L

NC

M

NC

PIN NAMES

I/O1 to I/O8

I/O port

CE

--------

Chip enable

WE

--------

Write enable

RE

--------

Read enable

CLE

Command latch enable

ALE

Address latch enable

WP

--------

Write protect

RY / BY

--------

Ready/Busy

VCC

Power supply

VSS

Ground

NC

No Connection

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BLOCK DIAGRAM

ABSOLUTE MAXIMUM RATINGS

SYMBOL

RATING

VALUE

UNIT

VCC

Power Supply Voltage

0.6 to 4.6

V

VIN

Input Voltage

0.6 to 4.6

V

VI/O

Input /Output Voltage

0.6 to VCC  0.3 ( 4.6 V)

V

PD

Power Dissipation

0.3

W

TSTG

Storage Temperature

55 to 125

°C

TOPR

Operating Temperature

-40 to 85

°C

Note: Avoid locations where the device may be exposed to water (wet, rain, dew condensation, etc.)

CAPACITANCE *(Ta  25°C, f  1 MHz)

SYMBOL

PARAMETER

CONDITION

MIN

MAX

UNIT

CIN

Input

VIN  0 V



10

pF

COUT

Output

VOUT  0 V



10

pF

* This parameter is periodically sampled and is not tested for every device.

I/O

Control circuit

Status register

Command register

Column buffer

Column decoder

Data register 0

Sense amp

Memory cell array

Control circuit

HV generator

Row address decoder

Logic control

RY / BY

--------

VCC

I/O1

VSS

CLE

ALE

Row address buffer

decoder

to

ECC Logic

Address register

Data register 1

I/O8

CE

--------

WE

--------

WP

--------

RE

--------

RY / BY

--------

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VALID BLOCKS

SYMBOL

PARAMETER

MIN

TYP.

MAX

UNIT

NVB

Number of Valid Blocks

1004



1024

Blocks

NOTE: The device occasionally contains unusable blocks. Refer to Application Note (13) toward the end of this document.

The first block (Block 0) is guaranteed to be a valid block at the time of shipment.

The specification for the minimum number of valid blocks is applicable over lifetime.

DC OPERATING CONDITIONS

SYMBOL

PARAMETER

MIN

TYP.

MAX

UNIT

VCC

Power Supply Voltage

2.7



3.6

V

VIH

High Level Input Voltage

VCC x 0.8



VCC  0.3

V

VIL

Low Level Input Voltage

0.3*



VCC x 0.2

V

* 2 V (pulse width lower than 20 ns)

DC CHARACTERISTICS (Ta  -40 to 85°C, VCC  2.7 to 3.6V)

SYMBOL

PARAMETER

CONDITION

MIN

TYP.

MAX

UNIT

IIL

Input Leakage Current

VIN  0 V to VCC



10

A

ILO

Output Leakage Current

VOUT  0 V to VCC





10

A

ICCO1

Serial Read Current

CE

--------  VIL, IOUT  0 mA, tRC  25 ns



30

mA

ICCO2

Programming Current







30

mA

ICCO3

Erasing Current



30

mA

ICCS

Standby Current

CE

--------  VCC  0.2 V, WP

--------  0 V/VCC



50

A

VOH

High Level Output Voltage

IOH  0.1 mA

VCC – 0.2



V

VOL

Low Level Output Voltage

IOL  0.1 mA



0.2

V

IOL

(RY / BY

--------)

Output Current of RY / BY

-------- pin

VOL  0.2 V



4



mA

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AC CHARACTERISTICS AND OPERATING CONDITIONS

(Ta  -40 to 85°C, VCC  2.7 to 3.6V)

SYMBOL

PARAMETER

MIN

MAX

UNIT

tCLS

CLE Setup Time

12



ns

tCLH

CLE Hold Time

5



ns

tCS

CE

-------- Setup Time

20



ns

tCH

CE

-------- Hold Time

5



ns

tWP

Write Pulse Width

12



ns

tALS

ALE Setup Time

12



ns

tALH

ALE Hold Time

5



ns

tDS

Data Setup Time

12



ns

tDH

Data Hold Time

5



ns

tWC

Write Cycle Time

25



ns

tWH

WE

-------- High Hold Time

10



ns

tWW

WP

-------- High to WE

-------- Low

100



ns

tRR

Ready to RE

-------- Falling Edge

20



ns

tRW

Ready to WE

-------- Falling Edge

20



ns

tRP

Read Pulse Width

12



ns

tRC

Read Cycle Time

25



ns

tREA

RE

-------- Access Time



20

ns

tCEA

CE

-------- Access Time



25

ns

tCLR

CLE Low to RE

-------- Low

10



ns

tAR

ALE Low to RE

-------- Low

10



ns

tRHOH

RE

-------- High to Output Hold Time

25



ns

tRLOH

RE

-------- Low to Output Hold Time

5



ns

tRHZ

RE

-------- High to Output High Impedance



60

ns

tCHZ

CE

-------- High to Output High Impedance



20

ns

tCSD

CE

-------- High to ALE or CLE Don’t Care

0



ns

tREH

RE

-------- High Hold Time

10



ns

tIR

Output-High-Impedance-to-RE

-------- Falling Edge

0



ns

tRHW

RE

-------- High to WE

-------- Low

30



ns

tWHC

WE

-------- High to CE

-------- Low

30



ns

tWHR

WE

-------- High to RE

-------- Low

60



ns

tWB

WE

-------- High to Busy



100

ns

tRST

Device Reset Time (Ready/Read/Program/Erase)



5/5/10/500

s

*1: tCLS and tALS cannot be shorter than tWP.

*2: tCS should be longer than tWP + 8ns.

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AC TEST CONDITIONS

PARAMETER

CONDITION

VCC: 2.7 to 3.6V

Input level

VCC-0.2V, 0.2V

Input pulse rise and fall time

3 ns

Input comparison level

VCC / 2

Output data comparison level

VCC / 2

Output load

CL (50 pF)  1 TTL

Note: Busy to ready time depends on the pull-up resistor tied to the RY / BY

-------- pin.

(Refer to Application Note (9) toward the end of this document)

PROGRAMMING / ERASING / READING CHARACTERISTICS

(Ta  -40 to 85°C, VCC  2.7 to 3.6V)

SYMBOL

PARAMETER

MIN

TYP.

MAX

UNIT

NOTES

tPROG

Average Programming Time



330

700

s

N

Number of Partial Program Cycles in the Same Page



4

(1)

tBERASE

Block Erasing Time



2.5

5

ms

tR

Memory Cell Array to Starting Address



40

120

s

(1) Refer to Application Note (12) toward the end of this document.

Data Output

When tREH is long, output buffers are disabled by /RE=High, and the hold time of data output depends on

tRHOH (25ns MIN). Under this condition, the waveforms look like Normal Serial Read mode.

When tREH is short, output buffers are not disabled by /RE=High, and the hold time of data output depends on

tRLOH (5ns MIN). Under this condition, output buffers are disabled by the rising edge of CLE, ALE, /CE or the

falling edge of /WE, and waveforms look like Extended Data Output Mode.

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TIMING DIAGRAMS

Latch Timing Diagram for Command/Address/Data

Command Input Cycle Timing Diagram

CLE

ALE

CE

--------

WE

--------

Hold Time

tDH

Setup Time

tDS

I/O

: VIH or VIL

tCS

tDH

tDS

tALS

tALH

tWP

tCLS

tCH

tCLH

: VIH or VIL

CE

--------

CLE

WE

--------

ALE

I/O

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Address Input Cycle Timing Diagram

Data Input Cycle Timing Diagram

PA8 to 15

CA8 to 11

: VIH or VIL

tDH

tDS

tCLS

CLE

tALS

tALH

tWP

tWH

tWP

CA0 to 7

tDH

tDS

tCS

ALE

I/O

tDH

tDS

tWP

tWH

tDH

tDS

tWP

tWH

tWC

PA0 to 7

tCLH

tCH

CE

--------

WE

--------

tWP

tWH

tWP

tALS

tWC

tDH

tDS

DIN0

DIN

1

tCLH

tCH

ALE

CLE

I/O

DIN

2111

tDH

tDS

tDH

tDS

tCS

tCLS

tCH

tCS

tALH

WE

--------

CE

--------

TC58BVG0S3HBAI4

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Serial Read Cycle Timing Diagram

Status Read Cycle Timing Diagram

tREH

tCHZ

tRHZ

tREA

tRC

tRR

tRHZ

tREA

tRHZ

tREA

I/O

tRHOH

tRP

: VIH or VIL

tCEA

RE

--------

RY / BY

--------

CE

--------

: VIH or VIL

* 70h represents the hexadecimal number

tWHR

tDH

tDS

tCLS

t

CLR

tCS

tCLH

tCH

tWP

Status

output

70h*

tWHC

tIR

tREA

tRHZ

tCHZ

CE

--------

CLE

I/O

tRHOH

tCEA

WE

--------

RE

--------

RY / BY

--------

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ECC Status Read Cycle Timing Diagram

* ECC Status output should be read for all 4 sector information.

** 7Ah command can be input to the device from [after RY / BY

--------

returns to High] to [before Dout or Next command input].

: VIH or VIL

tWHR

tDH

tDS

tCLS

tCLR

tCS

tCLH

tCH

tWP

Status

output

7Ah*

tWHC

tIR

tREA

CLE

I/O

tCEA

Status

output

tREA

Status

output

tREA

Status

output

tREA

Sector1

Sector2

Sector3

Sector4

WE

--------

RE

--------

CE

--------

RY / BY

--------

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Read Cycle Timing Diagram

Read Cycle Timing Diagram: When Interrupted by CE

--------

tCLR

PA8

to 15

PA0

to 7

CA8

to 11

CA0

to 7

I/O

tCS

tCLS

tCLH

tCH

tDH

tDS

tWC

tALS

tALH

CLE

ALE

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tALH

tR

tDH

tDS

tWB

tCS

tCLS

tCLH

tCH

tALS

tRC

tRR

tREA

Col. Add. N

Data out from

Col. Add. N

00h

DOUT

N

DOUT

N  1

tCLR

30h

70h

00h

status

output

WE

--------

RE

--------

CE

--------

RY / BY

--------

tCLR

30h

PA8

to 15

PA0

to 7

CA8

to 11

CA0

to 7

I/O

tCS

tCLS

tCLH

tCH

tDH

tDS

tWC

tALS

tALH

CLE

ALE

tDH

tDS

tDH

tDS

tDH

tDS

tDH

tDS

tALH

tR

tDH

tDS

tWB

tCS

tCLS

tCLH

tCH

tALS

tRC

tRR

tREA

Col. Add. N

00h

DOUT

N

DOUT

N  1

tCHZ

tRHZ

tRHOH

Data out from

Col. Add. N

tCSD

70h

00h

status

output

WE

--------

RE

--------

CE

--------

RY / BY

--------

TC58BVG0S3HBAI4

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Column Address Change in Read Cycle Timing Diagram (1/2)

I/O

tCS

tCLS

tCLH

tCH

tWC

tALS

tALH

tR

CLE

ALE

tDH

tDS

tDH

tDS

tALH

tWB

tCS

tCLS

tCLH

tCH

tALS

Page address

P

00h

CA0

to 7

tDH

tDS

CA8

to 11

tDH

tDS

PA0

to 7

tDH

tDS

PA8

to 15

tDH

tDS

30h

Continues from of next page

1

Page address

P

Data out from

Column address A

DOUT

A

DOUT

A + 1

70h

Status

Output

00h

tRC

1

DOUT

A +N

tREA

tCLR

Column address

A

WE

--------

RE

--------

CE

--------

RY / BY

--------

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Column Address Change in Read Cycle Timing Diagram (2/2)

I/O

tCS

tCLS

tCLH

tCH

05h

CA0

to 7

CA8

to 11

tWC

tALS

tALH

CLE

ALE

tDH

tDS

tDH

tDS

tDH

tDS

Column address

B

E0h

tDH

tDS

tALH

tCS

tCLS

tCLH

tCH

tALS

tREA

DOUT

A  N

tRHW

Page address

P

Data out from

Column address B

tRC

tCLR

tCEA

tIR

DOUT

B  N’

DOUT

B  1

DOUT

B

1

Continues from of previous page

1

RY / BY

--------

tWHR

WE

--------

RE

--------

CE

--------

TC58BVG0S3HBAI4

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Data Output Timing Diagram

Command

I/O

tDH

tRP

CLE

ALE

tRLOH

tREH

tREA

tRHZ

tREA

tCS

tCLS

tCLH

tCH

tRP

tRR

tRLOH

tDS

tCHZ

tRHOH

tCEA

Dout

tALH

tREA

tRC

Dout

WE

--------

RE

--------

CE

--------

RY / BY

--------

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Auto-Program Operation Timing Diagram

: VIH or VIL

: Do not input data while data is being output.

* M: up to 2111

I/O

Column address

N

CA0

to 7

tCLS

tALS

tDS

tDH

CLE

ALE

tCLH

tCH

tCS

tDS

tDH

tALH

tCS

tDH

tDS

tDH

tPROG

tWB

tDS

tALH

tALS

CA8

to 11

D

IN

N

D

IN

M*

10h

70h

Status

output

PA0

to 7

PA8

to 15

80h

DIN

N+1

tRW

WE

--------

RE

--------

CE

--------

RY / BY

--------

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Auto Block Erase Timing Diagram

tCS

60h

PA8

to 15

CLE

CE

--------

ALE

RE

--------

RY / BY

--------

: VIH or VIL

tCLS

tCLH

tCLS

PA0

to 7

tDS

tDH

tALS

: Do not input data while data is being output.

Auto Block

Erase Setup

command

I/O

D0h

70h

tWB

tBERASE

Busy

Status Read

command

Erase Start

command

Status

output

tALH

WE

--------

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Copy Back Program with Random Data Input

WE

CLE

RE

I/Ox

ALE

CE

tWC

tWB

RY/BY

Col

Add1

00h

35h

Col

Add2

Row

Add1

Row

Add2

Col

Add1

Col

Add2

Row

Add1

Data1

DataN

10h

70h

I/O

Row

Add2

tR

Busy

tWB

tWHR

Copy Back Program Data

Input Command

I/O1=0 Successful Program

I/O1=1 Error in Program

Status Read command

Column Address

Row Address

Column Address

Row Address

70h

00h

t

I/O

Data1

Data N

85h

I/O1=0 Successful Read

I/O1=1 Error in Read

tPROG

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ID Read Operation Timing Diagram

: VIH or VIL

WE

--------

CLE

RE

--------

tCEA

CE

--------

ALE

I/O

tAR

ID Read

command

Address

00

Maker code

Device code

tREA

tCLS

tCS

tDS

tCH

tALH

tALS

tCLS

tCS

tCH

tALH

tDH

90h

00h

98h

tREA

F1h

tREA

See

Table 5

See

Table 5

tREA

If Fail

See

Table 5

3rd Data

4th Data

5th Data

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PIN FUNCTIONS

The device is a serial access memory which utilizes time-sharing input of address information.

Command Latch Enable: CLE

The CLE input signal is used to control loading of the operation mode command into the internal command

register. The command is latched into the command register from the I/O port on the rising edge of the WE

--------

signal while CLE is High.

Address Latch Enable: ALE

The ALE signal is used to control loading address information into the internal address register. Address

information is latched into the address register from the I/O port on the rising edge of WE

-------- while ALE is High.

Chip Enable: CE

--------

The device goes into a low-power Standby mode when CE

-------- goes High while the device is in Ready state.

The CE

-------- signal is ignored when the device is in Busy state (RY / BY

--------  L), such as during a Program, Erase

or Read operation, and will not enter Standby mode even if the CE

-------- input goes High.

Write Enable: WE

--------

The WE

-------- signal is used to control the acquisition of data from the I/O port.

Read Enable: RE

--------

The RE

-------- signal controls serial data output. Data is available tREA after the falling edge of RE

--------.

The internal column address counter is also incremented (Address = Address + 1) on this falling edge.

I/O Port: I/O1 to 8

The I/O1 to 8 pins are used as a port for transferring address, command and input/output data to and from

the device.

Write Protect: WP

--------

The WP

-------- signal is used to protect the device from accidental programming or erasing. The internal voltage

regulator is reset when WP

-------- is Low. This signal is usually used to protect the data during the power-on/off

sequence when input signals are invalid.

Ready/Busy: RY / BY

--------

The RY / BY

-------- output signal is used to indicate the operating condition of the device. The RY / BY

-------- signal is

in Busy state (RY / BY

-------- = L) during the Program, Erase and Read operations and will return to Ready state

(RY / BY

-------- = H) after completion of the operation. The output buffer for this signal is an open drain and has to

be pulled up to VCC with an appropriate resistor.

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Schematic Cell Layout and Address Assignment

The Program operation works on page units while the Erase operation works on block units.

A page consists of 2112 bytes in which 2048 bytes are

used for main memory storage and 64 bytes are for

redundancy or for other uses.

1 page  2112 bytes

1 block  2112 bytes  64 pages  (128K  4K) bytes

Capacity  2112 bytes  64 pages  1024 blocks

An address is read in via the I/O port over four

consecutive clock cycles, as shown in Table 1.

Table 1. Addressing

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

CA0 to CA11: Column address

PA0 to PA5: Page address in block

PA6 to PA15: Block address

First cycle

CA7

CA6

CA5

CA4

CA3

CA2

CA1

CA0

Second cycle

L

CA11

CA10

CA9

CA8

Third cycle

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

Fourth cycle

PA15

PA14

PA13

PA12

PA11

PA10

PA9

PA8

2112

65536

pages

1024 blocks

2048

64

Page Buffer

Data Cache

I/O8

I/O1

64 Pages1 block

8I/O

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Operation Mode: Logic and Command Tables

The operation modes such as Program, Erase, Read and Reset are controlled by command operations

shown in Table 3. Address input, command input and data input/output are controlled by the CLE, ALE, CE

--------,

WE

--------, RE

--------, and WP

-------- signals, as shown in Table 2.

Table 2. Logic Table

CLE

ALE

CE

--------

WE

--------

RE

--------

WP

--------*1

Command Input

H

L

H

*

Data Input

L

H

Address Input

L

H

L

H

*

Serial Data Output

L

H

*

During Program (Busy)

*

H

During Erase (Busy)

*

H

During Read (Busy)

*

H

*

L

H (*2)

*

Program, Erase Inhibit

*

L

Standby

*

H

*

0 V/VCC

H: VIH, L: VIL, *: VIH or VIL

*1: When the WP

-------- signal goes Low, Program or Erase operation is inhibited (Refer to Application Note (10) toward the end of this document).

*2: If CE

-------- is Low during Read Busy, WE

-------- and RE

-------- must be held High to avoid unintended command/address input to the device or read to

the device. Reset or Status Read command can be input during Read Busy.

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Table 3. Command table (HEX)

First Set

Second Set

Acceptable while Busy

Serial Data Input

80



Read

00

30

Column Address Change in Serial Data Output

05

E0

Auto Page Program

80

10

Column Address Change in Serial Data Input

85



Read for Copy-Back

00

35

Copy-Back Program

85

10

Auto Block Erase

60

D0

ID Read

90



Status Read

70





ECC Status Read

7A



Reset

FF





Table 4. Read mode operation states

CLE

ALE

CE

--------

WE

--------

RE

--------

I/O1 to I/O8

Power

Output Select

L

H

L

Data output

Active

Output Deselect

L

H

High impedance

Active

H: VIH, L: VIL

HEX data bit assignment

(Example)

1

0

8

7

6

5

4

3

2

I/O1

Serial Data Input: 80h

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DEVICE OPERATION

Read Mode

Read mode is set when the "00h" and “30h” commands are issued to the Command register. Between the

two commands, a start address for the Read mode needs to be issued. After the initial power-on sequence,

“00h” command is latched into the internal command register. Then the Read operation after the power-on

sequence is executed by the setting of only four address cycles and “30h” command. The sequence of the

block diagram are shown below (Refer to the detailed timing chart).

Random Column Address Change in Read Cycle

During the serial data output from the register, the column

address can be changed by inputting a new column address

using the 05h and E0h commands. The data is read out in serially

starting at the new column address. Random Column Address

Change operation can be done multiple times within the same

page.

Start-address input

WE

--------

RE

--------

RY / BY

--------

CLE

00h

CE

--------

ALE

I/O

Busy

30h

Page Address N

Column Address M

Start-address input

M

M+1

M+2

Page Address N

tR

Status

70h

00h

A data transfer operation from the cell array to the Data Cache

via Page Buffer starts on the rising edge of WE

--------

in the 30h

command input cycle (after the address information has been

latched). The device will be in the Busy state during this transfer

period.

After the transfer period, the device returns to Ready state.

Serial data can be output synchronously with the RE

--------

clock from

the start address designated in the address input cycle.

Cell array

Select page

N

M

m

Data Cache

Page Buffer

I/O1 to 8: m  2111

WE

--------

RE

--------

RY / BY

--------

CLE

00h

CE

--------

ALE

I/O

Col. M

Page N

Busy

30h

Start from Col. M

Page N

05h

E0h

Col. M’

M



1

M’



1

M’

2

M’

3

M’



4

Page N

Col. M

Start from Col. M’

tR

M



2

M



3

70h

Statu

s

00h

Select page

N

M

M’

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ECC & Sector definition for ECC

Internal ECC logic generates Error Correction Code during busy time in program operation. The ECC logic

manages 9bit error detection and 8bit error correction in each 528Bytes of main data and spare data.

A section of main field (512Bytes) and spare field (16Bytes) are paired for ECC. During Read operation, the

device executes ECC of itself. Once Read operation is executed, Status Read Command (70h) can be

issued to check the read status. The read status remains until other valid commands are executed.

To use ECC function, below limitation must be considered.

- A sector is the minimum unit for program operation and the number of program per page must not

exceed 4.

2KByte Page Assignment

1st

Main

2nd

Main

3rd

Main

4th

Main

1st

Spare

2nd

Spare

3rd

Spare

4th

Spare

512B

16B

Note) Internal ECC manages all data of Main area and Spare area.

Definition of 528Byte Sector

Sector

Column Address (Byte)

Main Field

Spare Field

1st Sector

0 to 511

2,048 to 2,063

2nd Sector

512 to 1,023

2,064 to 2,079

3rd Sector

1,024 to 1,535

2,080 to 2,095

4th Sector

1,536 to 2,047

2,096 to 2,111

Note) The ECC parity code generated by internal ECC is stored in column addresses 2112-2175 and the user cannot access

to these specific addresses.

While using the Partial Page Program, the user must program the data to main field and spare field simultaneously

by the definition of sector.

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Auto Page Program Operation

The device carries out an Auto Page Program operation when it receives a "10h" Program command after

the address and data have been input. The sequence of command, address and data input is shown below

(Refer to the detailed timing chart).

Random Column Address Change in Auto Page Program Operation

The column address can be changed by the 85h command during the data input sequence of the Auto

Page Program operation.

Two address input cycles after the 85h command are recognized as a new column address for the data

input. After the new data is input to the new column address, the 10h command initiates the actual data

program into the selected page automatically. The Random Column Address Change operation can be

repeated multiple times within the same page.

80h

Page N

Col. M

85h

Din

10h

Status

Din

Col. M’

Din

70h

Busy

WE

--------

RY / BY

--------

Busy

CLE

80h

ALE

I/O

Page P

CE

--------

Col. M

Din

10h

70h

Din

Data

Status

Out

RE

--------

The data is transferred (programmed) from the Data Cache via the

Page Buffer to the selected page on the rising edge of WE

--------

following

input of the “10h” command. After programming, the programmed

data is transferred back to the Page Buffer to be automatically verified

by the device. If the programming does not succeed, the

Program/Verify operation is repeated by the device until success is

achieved or until the maximum loop number set in the device is

reached.

Selected

page

Program

Data input

Read & verification

Data input

Selected

page

Read & verification

Program

Col. M

Col. M’

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Auto Block Erase

The Auto Block Erase operation starts on the rising edge of WE

-------- after the Erase Start command “D0h”

which follows the Erase Setup command “60h”. This two-cycle process for Erase operations acts as an extra

layer of protection from accidental erasure of data due to external noise. The device automatically executes

the Erase and Verify operations.

Pass

I/O

Fail

60

D0

70

Block Address

input: 2 cycles

Status Read

command

Busy

Erase Start

command

RY / BY

--------

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READ FOR COPY-BACK WITH DATA OUTPUT TIMING GUIDE

Copy-Back operation is a sequence execution of Read for Copy-Back and of Copy-Back Program with the

destination page address. A Read operation with “35h” command and the address of source page moves

the whole 2112 bytes data into the internal data buffer. Bit errors are checked by sequential reading the data

or by reading the status in read after read busy time (tR) to check if uncorrectable error occurs. In the case

of there is no bit error or no uncorrectable error, the data don’t need to be reloaded. Therefore Copy-Back

Program operation is initiated by issuing Page-Copy Data-Input command (85h) with the destination page

address. Actual programming operation begins after Program Confirm command (10h) is issued. Once the

program process starts, the Status Read command (70h) may be entered to read the status register. The

system controller can detect the completion of a program cycle by monitoring the RY / BY

-------- output, or the

Status Bit (I/O7) of the Status Register. When the Copy-Back Program is completed, the Write Status Bit

(I/O1) may be checked. The command register remains in Status Read mode until another valid command

is written to the command register. During Copy-Back Program, the data modification is possible using

Random Data Input command (85h) as shown below.

Page Copy-Back Program Operation

Page Copy-Back Program Operation with Random Data Input

I/Ox

I/O1

Pass

tR

tPROG

”0”

I/O1

”0”

Pass

Col. Add.1,2 & Page Add.1,2

Source Address

”1”

Col. Add.1,2 & Page Add.1,2

Destination Address

”1”

Fail

00h

Add.(4 Cycles)

35h

70h

Add.(4 Cycles)

00h

10h

70h

85h

Data Output

RY / BY

--------

Col. Add.1,2 & Page Add.1,2

Source Address

I/Ox

00h

Add.(4Cycles)

tR

35h

I/Ox

Col. Add.1,2 & Page Add.1,2

Destination Address

tPROG

Data Output

85h

Add.(4Cycles)

Data

85h

Add.(2Cycles)

Data

10h

70h

Col. Add.1,2

There is no limitation for the number of repetition.

I/O1

Pass

Fail

”1”

”0”

70h

A

00h

RY / BY

--------

RY / BY

--------

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ID Read

The device contains ID codes which can be used to identify the device type, the manufacturer, and

features of the device. The ID codes can be read out under the following timing conditions:

Table 5. Code table

Description

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

Hex Data

1st Data

Maker Code

1

0

1

0

98h

2nd Data

Device Code

1

0

1

F1h

3rd Data

Chip Number, Cell Type

1

0

80h

4th Data

Page Size, Block Size

0

1

0

1

0

1

15h

5th Data

District Number

1

0

1

0

F2h

3rd Data

Description

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

Internal Chip Number

1

2

4

8

0

1

0

1

0

1

Cell Type

2 level cell

4 level cell

8 level cell

16 level cell

0

1

0

1

0

1

Reserved

1

0

4th Data

5th Data

90h

00h

98h

F1h

See

table 5

See

table 5

CLE

RE

--------

tCEA

CE

--------

ALE

I/O

tAR

tREA

ID Read

command

Address 00

Maker code

Device code

See

table 5

3rd Data

WE

--------

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4th Data

Description

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

Page Size

(without redundant area)

1 KB

2 KB

4 KB

8 KB

0

1

0

1

0

1

Block Size

(without redundant area)

64 KB

128 KB

256 KB

512 KB

0

1

0

1

0

1

I/O Width

x8

x16

0

1

Reserved

0

1

5th Data

Description

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

I/O2

I/O1

District Number

1 District

2 Districts

4 Districts

8 Districts

0

1

0

1

0

1

ECC engine on chip

With ECC engine

1

Reserved

1

0

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Status Read

The device automatically implements the execution and verification of the Program and Erase operations.

The Status Read function is used to monitor the Ready/Busy status of the device, determine the result

(Pass/Fail) of a Program or Erase operation, and determine whether the device is in Protect mode. The

device status is output via the I/O port using RE

-------- after a “70h” command input. The Status Read command

can also be used during a Read operation to monitor the Ready/Busy status and to find out the ECC result

(Pass/Fail).

The resulting information is outlined in Table 6.

Table 6. Status output table

Definition

Page Program

Block Erase

Read

I/O1

Chip Status

Pass: 0 Fail: 1

Pass/Fail

Pass/Fail(Uncorrectable)

I/O2

Not Used

Invalid

I/O3

Not Used

0

I/O4

Chip Read Status

Normal or uncorrectable: 0

Recommended to rewrite : 1

0

Normal or uncorrectable /

Recommended to rewrite

I/O5

Not Used

0

I/O6

Ready/Busy

Ready: 1 Busy: 0

Ready/Busy

I/O7

Ready/Busy

Ready: 1 Busy: 0

Ready/Busy

I/O8

Write Protect

Not Protected :1 Protected: 0

Not Protected/Protected

The Pass/Fail status on I/O1 is only valid during a Program/Erase/Read operation when the device is in the Ready state.

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ECC Status Read

The ECC Status Read function is used to monitor the Error Correction Status. The device can correct up

to 8bit errors. ECC can be performed on the NAND Flash main and spare areas.

The ECC Status Read function can also show the number of errors in a sector as a result of an ECC check

during a Read operation.

8

7

6

5

4

3

2

I/O1

Sector Information

ECC Status

I/O4 to I/O1

ECC Status

0000

No Error

0001

1bit error(Correctable)

0010

2bit error(Correctable)

0011

3bit error(Correctable)

0100

4bit error(Correctable)

0101

5bit error(Correctable)

0110

6bit error(Correctable)

0111

7bit error(Correctable)

1000

8bit error(Correctable)

1111

Uncorrectable Error

Sector Information

I/O8 to I/O5

Sector Information

0000

1st Sector (Main and Spare area)

0001

2nd Sector (Main and Spare area)

0010

3rd Sector (Main and Spare area)

0011

4th Sector (Main and Spare area)

Other

Reserved

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Reset

The Reset mode stops all operations. For example, in case of a Program or Erase operation, the internally

generated voltage is discharged to 0 volts and the device enters the Wait state.

The response to a “FFh” Reset command input during the various device operations is as follows:

When a Reset (FFh) command is input during Program operation

Internal

generated voltage

80

10

FF

00

tRST (max 10 s)

RY / BY

--------

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When a Reset (FFh) command is input during Erase operation

When a Reset (FFh) command is input during Read operation

When a Reset (FFh) command is input during Ready

When a Status Read command (70h) is input after a Reset

When two or more Reset commands are input in succession

Internal

generated voltage

D0

FF

00

tRST (max 500 s)

RY / BY

--------

00

FF

00

tRST (max 5 s)

30

RY / BY

--------

00

tRST (max 5 s)

FF

RY / BY

--------

I/O status : Pass/Fail  Pass

: Ready/Busy  Ready

FF

70

RY / BY

--------

10

FF

(3)

(2)

(1)

The second command is invalid, but the third command is valid.

FF

RY / BY

--------

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APPLICATION NOTES AND COMMENTS

(1) Power-on/off sequence

The timing sequence shown in the figure below is necessary for the power-on/off sequence.

The device’s internal initialization starts after the power supply reaches an appropriate level during the

power-on sequence. During the initialization the device Ready/Busy signal indicates the Busy state as

shown in the figure below. In this time period, the acceptable commands are FFh or 70h.

The WP

-------- signal is useful for protecting against data corruption at power-on/off.

(2) Power-on Reset

The following sequence is necessary because some input signals may not be stable at power-on.

(3) Prohibition of unspecified commands

The operation commands are listed in Table 3. Input of a command other than those specified in

Table 3 is prohibited. Stored data may be corrupted if an unknown command is entered during the

command cycle.

(4) Restriction of commands while in the Busy state

During the Busy state, do not input any command except 70h and FFh.

FF

Reset

Power on

VIL

Operation

0 V

VCC

2.7 V

2.5 V

VIL

Don’t

care

Don’t

care

VIH

CE

--------, WE

--------, RE

--------

CLE, ALE

Invalid

RY / BY

--------

1 ms max

100 s max

Don’t

care

Invalid

1 ms max

100 s max

≥ 1ms

2.7 V

2.5 V

0.5 V

WP

--------

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(5) Acceptable commands after Serial Data Input command “80h”

Once the Serial Data Input command “80h” has been input, do not input any command other than the

Column Address Change in Serial Data Input command “85h”, Auto Page Program command “10h” or

the Reset command “FFh”.

If a command other than “85h”, “10h” or “FFh” is input, the Program operation is not performed and the

device operation is set to the mode that the input command specifies.

(6) Addressing for program operation

Within a block, the pages must be programmed consecutively from the LSB (least significant bit) page

of the block to the MSB (most significant bit) page of the block. Random page address programming is

prohibited.

DATA IN: Data (1)

Page 0

Data register

Page 2

Page 1

Page 31

Page 63

(1)

(2)

(3)

(32)

(64)

Data (64)

From the LSB page to MSB page

DATA IN: Data (1)

Page 0

Data register

Page 2

Page 1

Page 31

Page 63

(2)

(32)

(3)

(1)

(64)

Data (64)

e.g.) Random page program (Prohibition)

Command other than

“85h”, “10h” or “FFh”

80

Programming cannot be executed.

10

XX

Mode specified by the command.

80

FF

Address input

WE

--------

RY / BY

--------

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(7) Status Read during a Read operation

The device status can be read out by inputting the Status Read command “70h” in Read mode. Once

the device has been set to Status Read mode by a “70h” command, the device will not return to Read

mode unless the Read command “00h” is input during [A]. If the Read command “00h” is input during [A],

Status Read mode is reset, and the device returns to Read mode. In this case, data output starts

automatically from address N and address input is unnecessary

(8) Auto programming failure

(9) RY / BY

--------: termination for the Ready/Busy pin (RY / BY

--------)

A pull-up resistor needs to be used for termination because the RY / BY

-------- buffer consists of an open

drain circuit.

1.5 s

1.0 s

0.5 s

0

1 K

4 K

3 K

2 K

15 ns

10 ns

5 ns

tf

tr

R

tr

tf

V

CC

 3.3 V

Ta 

25°C

CL 

50 pF

tf

Ready

VCC

tr

Busy

Status Read

00

Address N

Command

CE

--------

[A]

Status Read

command input

Status output

70

00

30

WE

--------

RE

--------

RY / BY

--------

This data may vary from device to device.

We recommend to use this data as a

reference for selecting a resistor value.

VCC

Device

VSS

R

CL

RY / BY

--------

Fail

80

10

80

10

Address

M

Data

input

70

I/O

Address

N

Data

input

If the programming result for page address M is Fail, do not try to program the

page to address N in another block without the data input sequence.

Because the previous input data has been lost in the Data Cache, the same input

sequence of 80h command, address and data have to be executed.

10

80

M

N

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(10) Note regarding the WP

-------- signal

The Erase and Program operations are automatically reset when WP

-------- goes Low. The operations are

enabled and disabled as follows:

Enable Programming

Disable Programming

Enable Erasing

Disable Erasing

tWW (100 ns MIN)

80

10

DIN

WE

--------

WP

--------

RY / BY

--------

tWW (100 ns MIN)

80

10

DIN

WE

--------

WP

--------

RY / BY

--------

tWW (100 ns MIN)

60

D0

DIN

WE

--------

WP

--------

RY / BY

--------

tWW (100 ns MIN)

60

D0

DIN

WE

--------

WP

--------

RY / BY

--------

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(11) When five address cycles are input

Although the device may read in a fifth address, it is ignored inside the chip.

Read operation

Program operation

CLE

ALE

I/O

Address input

Ignored

80h

Data input

WE

--------

CE

--------

WE

--------

CE

--------

RY / BY

--------

CLE

Address input

00h

ALE

I/O

Ignored

30h

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(12) Several programming cycles on the same page (Partial Page Program)

ECC Parity Code is generated during program operation on Main area (512 byte) + Spare area (16byte).

While using the Partial Page Program, the user must program the data to main field and spare field

simultaneously by the definition of sector in section “ECC & Sector definition for ECC”.

For example, each segment can be programmed individually as follows:

Number of partial program cycles in the same page must not exceed 4.

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(13) Invalid blocks (bad blocks)

The device occasionally contains unusable blocks. Therefore, the following issues must be recognized:

Please do not perform an erase operation to bad blocks. It may be

impossible to recover the bad block’s information if the information is

erased.

Check if the device has any bad blocks after installation into the

system. Refer to the test flow for bad block detection. Bad blocks which

are detected by the test flow must be managed as unusable blocks by

the system.

A bad block does not affect the performance of good blocks because it

is isolated from the bit lines by select gates.

The number of valid blocks over the device lifetime is as follows:

MIN

TYP.

MAX

UNIT

Valid (Good) Block Number

1004



1024

Blocks

Bad Block Test Flow

Regarding invalid blocks, bad block mark is in whole pages.

Please read one column of any page in each block. If the data of the column is 00 (Hex), define the block as

a bad block.

For Bad Block Test Flow during Read Check, regardless of Status Read result (ECC Pass or Fail), use the

read data value to make judgement for Bad Block.

*1: No erase operation is allowed to detected bad blocks.

Bad Block

Pass

Read Check

Start

Entry Bad Block *1

Last Block

End

Yes

Fail

Block No  1

No

Block No.  Block No. 

1

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(14) Failure phenomena for Program, Erase and Read operations

The device may fail during a Program, Erase or Read operation.

The following possible failure modes should be considered when implementing a highly reliable system.

FAILURE MODE

DETECTION AND COUNTERMEASURE SEQUENCE

Block

Erase Failure

Status Read after Erase  Block Replacement

Page

Programming Failure

Status Read after Program  Block Replacement

Read

9bit Failure(uncorrectable error)

Check the ECC correction status by Status Read or ECC Status Read and take

appropriate measures such as rewrite in consideration of Wear Leveling before

uncorrectable ECC error occurs.

 ECC: Error Correction Code. 8 bit correction per 528Bytes is executed in a device.

 Block Replacement

Program

Erase

When an error occurs during an Erase operation, prevent future accesses to this bad block

(by creating a table within the system or by using another appropriate scheme).

(15) Do not turn off the power before the Write/Erase operation is completed. Avoid using the device when the

battery is low. Power shortage and/or power failure before the Write/Erase operation is completed will

cause loss of data and/or damage to data.

(16) Please refer to KIOXIA soldering temperature profile for detail.

When an error happens in Block A, try to reprogram the

data into another Block (Block B) by loading from an

external buffer. Then, prevent further system accesses

to Block A (by creating a bad block table or by using

another appropriate scheme).

Block A

Block B

Error occurs

Buffer

memory

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(17) Reliability Guidance

This reliability guidance is intended to notify some guidance related to using NAND Flash with 8 bit ECC

for each 512 bytes. NAND Flash memory cells are gradually worn out and the reliability level of memory

cells is degraded by repeating Write and Erase operation of ‘0’ data in each block. For detailed reliability

data, please refer to the reliability note for each product.

Although random bit errors may occur during use, it does not necessarily mean that a block is bad.

Generally, a block should be marked as bad when a program status failure or erase status failure is

detected.

The reliability of NAND Flash memory cells during the actual usage on system level depends on the

usage and environmental conditions. KIOXIA adopts the checker pattern data, 0x55 & 0xAA for alternative

Write/Erase cycles, for the reliability test.

 Write/Erase Endurance

Write/Erase endurance failures may occur in a cell, page, or block, and are detected by doing a Status

Read after either an Auto Page Program or Auto Block Erase operation. The cumulative bad block count

will increase along with the number of Write/Erase cycles.

 Data Retention

The data in NAND Flash memory may change after a certain amount of storage time. This is due to

charge loss or charge gain. After block erasure and reprogramming, the block may become usable again.

Data Retention time is generally influenced by the number of Write/Erase cycles and temperature.

Here is a graph plotting the relationship between Write/Erase Endurance and Data Retention.

 Read Disturb

A Read operation may disturb the data in NAND Flash memory. The data may change due to charge

gain. Usually, bit errors occur on other pages in the block, not the page being read. After a large number

of read cycles (between block erases), a tiny charge may build up and can cause a cell to be soft

programmed to another state. After block erasure and reprogramming, the block may become usable

again. Read Disturb capability is generally influenced by the number of Write/Erase cycles.

Write/Erase Endurance [Cycles]

Data Retention [Years]

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(18) NAND Management

NAND Management such as Bad Block Management, ECC treatment and Wear Leveling, but not limited

to these treatments, should be recognized and incorporated in the system design.

ECC treatment for read data is mandatory against random bit errors, and host should monitor ECC status

to take appropriate measures such as rewrite in consideration of Wear Leveling before uncorrectable

Error occurs. To realize robust system design, generally it is necessary to prevent the concentration of

Write/Erase cycles at the specific blocks by adopting Wear Leveling which manages to distribute

Write/Erase cycles evenly among NAND Flash memory. And also it is necessary to avoid dummy ‘0’ data

write, e.g. ‘0’ data padding, which accelerate block endurance degradation.

Continuous Write and Erase cycling with high percentage of '0' bits in data pattern can lead to faster block

endurance degradation.

Example: NAND cell array with ‘0’ data padding

0 1 0 0 1 0 0 0 0 0 0 0

0 1 0 1 1 0 0 0 0 0 0 0

1 0 1 0 0 0 0 0 0 0 0 0

1 1 0 0 1 0 0 0 0 0 0 0

0 0 1 1 0 0 0 0 0 0 0 0

1 0 1 0 1 0 0 0 0 0 0 0

0 1 0 1 0 0 0 0 0 0 0 0

1 0 1 0 1 0 0 0 0 0 0 0

0 1 0 0 1 1 1 1 1 1 1 1

0 1 0 1 1 1 1 1 1 1 1 1

1 0 1 0 0 1 1 1 1 1 1 1

1 1 0 0 1 1 1 1 1 1 1 1

0 0 1 1 0 1 1 1 1 1 1 1

1 0 1 0 1 1 1 1 1 1 1 1

0 1 0 1 0 1 1 1 1 1 1 1

1 0 1 0 1 1 1 1 1 1 1 1

: “1” data cell

: “0” data cell

1

0

User data area

Remaining area

(a) Accelerate block endurance degradation

by fixed dummy “0” data write

(b) “1” data for Remaining area

(Recommended)

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Package Dimensions

Weight: 0.15g (typ.)

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Revision History

Date

Rev.

Description

2012-06-15

0.10

Preliminary version

2012-07-13

0.20

Changed tBERASE. Revised ID Table. Corrected typo.

2012-10-01

1.00

Deleted TENTATIVE/TBD notation.

2018-06-01

1.10

Corrected typo, and described some notes.

Attached Reliability Guidance and NAND Management.

Changed “RESTRICTIONS ON PRODUCT USE”.

2019-10-01

2.00

Rebrand as "KIOXIA"

Corrected typo and described some notes.

Removed Soldering Temperature and added note in ABSOLUTE MAXIMUM

RATINGS, and added comments in APPLICATION NOTES AND

COMMENTS.

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RESTRICTIONS ON PRODUCT USE

KIOXIA Corporation and its subsidiaries and affiliates are collectively referred to as “KIOXIA”.

Hardware, software and systems described in this document are collectively referred to as “Product”.

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 This document and any information herein may not be reproduced without prior written permission from KIOXIA. Even with KIOXIA's written

permission, reproduction is permissible only if reproduction is without alteration/omission.

 Though KIOXIA works continually to improve Product's quality and reliability, Product can malfunction or fail. Customers are responsible for

complying with safety standards and for providing adequate designs and safeguards for their hardware, software and systems which

minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily injury or damage to

property, including data loss or corruption. Before customers use the Product, create designs including the Product, or incorporate the

Product into their own applications, customers must also refer to and comply with (a) the latest versions of all relevant KIOXIA information,

including without limitation, this document, the specifications, the data sheets and application notes for Product and the precautions and

conditions set forth in the "Reliability Information" in KIOXIA Corporation’s website and (b) the instructions for the application with which the

Product will be used with or for. Customers are solely responsible for all aspects of their own product design or applications, including but not

limited to (a) determining the appropriateness of the use of this Product in such design or applications; (b) evaluating and determining the

applicability of any information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any

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LIABILITY FOR CUSTOMERS' PRODUCT DESIGN OR APPLICATIONS.

 PRODUCT IS NEITHER INTENDED NOR WARRANTED FOR USE IN EQUIPMENTS OR SYSTEMS THAT REQUIRE

EXTRAORDINARILY HIGH LEVELS OF QUALITY AND/OR RELIABILITY, AND/OR A MALFUNCTION OR FAILURE OF WHICH MAY

CAUSE LOSS OF HUMAN LIFE, BODILY INJURY, SERIOUS PROPERTY DAMAGE AND/OR SERIOUS PUBLIC IMPACT

("UNINTENDED USE"). Except for specific applications as expressly stated in this document, Unintended Use includes, without limitation,

equipment used in nuclear facilities, equipment used in the aerospace industry, lifesaving and/or life supporting medical equipment,

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OF NONCOMPLIANCE WITH APPLICABLE LAWS AND REGULATIONS.