IDT72402L45SO - Integrated Device Technology, Inc.

JULY 2003

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

FAST is a trademark of National Semiconductor, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

IDT72401

IDT72402

IDT72403

IDT72404

CMOS PARALLEL FIFO

64 x 4 and 64 x 5

FEATURES:

••

•First-ln/First-Out Dual-Port memory

••

•64 x 4 organization (IDT72401/72403)

••

•64 x 5 organization (IDT72402/72404)

••

•RAM-based FIFO with low falI-through time

••

•Low-power consumption

— Active: 175mW (typ.)

••

•Maximum shift rate — 45MHz

••

•High data output drive capability

••

•Asynchronous and simultaneous read and write

••

•Fully expandable by bit width

••

•Fully expandable by word depth

••

•IDT72403/72404 have Output Enable pin to enable output data

••

•High-speed data communications applications

••

•High-performance CMOS technology

••

•Available in CERDIP, plastic DIP and SOIC

••

•Military product compliant to MlL-STD-883, Class B

••

•Standard Military Drawing #5962-86846 and

5962-89523 is listed on this function.

••

•Industrial temperature range (–40°°

°°

°C to +85°°

°°

°C) is available

(plastic packages only)

DESCRIPTION:

The IDT72401 and IDT72403 are asynchronous high-performance

First-ln/First-Out memories organized 64 words by 4 bits. The IDT72402 and

IDT72404 are asynchronous high-performance First-ln/First-Out memories

organized as 64 words by 5 bits. The IDT72403 and IDT72404 also have an

Output Enable (OE) pin. The FlFOs accept 4-bit or 5-bit data at the data input

(D0-D3, 4). The stored data stack up on a first-in/first-out basis.

A Shift Out (SO) signal causes the data at the next to last word to be shifted

to the output while all other data shifts down one location in the stack. The Input

Ready (IR) signal acts like a flag to indicate when the input is ready for new

data (IR = HIGH) or to signal when the FIFO is full (IR = LOW). The IR signal

can also be used to cascade multiple devices together. The Output Ready (OR)

signal is a flag to indicate that the output remains valid data (OR = HIGH) or

to indicate that the FIFO is empty (OR = LOW). The OR can also be used to

cascade multiple devices together.

Width expansion is accomplished by logically ANDing the IR and OR signals

to form composite signals.

Depth expansion is accomplished by tying the data inputs of one device to

the data outputs of the previous device. The IR pin of the receiving device is

connected to the SO pin of the sending device and the OR pin of the sending

device is connected to the Shift In (SI) pin of the receiving device.

Reading and writing operations are completely asynchronous allowing the

FIFO to be used as a buffer between two digital machines of widely varying

operating frequencies. The 45MHz speed makes these FlFOs ideal for high-

speed communication and controller applications.

Military grade product is manufactured in compliance with the latest revision

of MIL-STD-883, Class B.

FUNCTIONAL BLOCK DIAGRAM

WRITE POINTER

INPUT

CONTROL

LOGIC

2747 drw01

DATA IN

MASTER

RESET

WRITE MULTIPLEXER

MEMORY

ARRAY

READ POINTER

READ MULTIPLEXER

0-3

(IDT72402

and IDT72404)

OUTPUT

ENABLE

DATA IN

MASTER

RESET

(IDT72402

and IDT72404)

0-3

(IDT72403

and IDT72404)

MILITARY AND COMMERCIAL

TEMPERATURE RANGES

IDT72401/72402/72403/72404

CMOS PARALLEL FIFO 64 x 4, 64 x 5

PIN CONFIGURATIONS

NOTES:

1. Pin 1: NC - No Connection IDT72401, OE - IDT72403

2. Pin 1: NC - No Connection IDT72402, OE - IDT72404

3. IDT72402 is not available in CERDIP (D18-1)

IDT72401/IDT72403

PLASTIC DIP (P18-1, ORDER CODE: P)

CERDIP (D18-1, ORDER CODE: D)

SOIC (SO18-1, ORDER CODE: SO)

TOP VIEW

IDT72402(3)/IDT72404

PLASTIC DIP (P16-1, ORDER CODE: P)

CERDIP (D16-1, ORDER CODE: D)

SOIC (SO16-1, ORDER CODE: SO)

TOP VIEW

Symbol Rating Commercial Military Unit

VTERM Terminal Voltage with –0.5 to +7.0 –0.5 to +7.0 V

Respect to GND

TSTG Storage Temp. –55 to +125 –65 to +150 °C

IOUT DC Output Current –50 to +50 –50 to +50 mA

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage Commercial/Military 4.5 5.0 5.5 V

GND Supply Voltage 0 0 0 V

VIH Input High Voltage 2.0 — — V

VIL(1) Input High Voltage — — 0.8 V

TAOperating Temperature Commercial 0 — 70 °C

TAOperating Temperature Military –55 — 125 °C

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5.0V ± 10%, TA = 0°C to +70°C; Military: V CC = 5.0V ± 10%, TA = –55°C t o +125°C)

IDT72401 IDT72401

IDT72402

IDT72403 IDT72403(5)

IDT72404 IDT72404(5)

Commercial Military

fIN = 45, 35, 25, 15, 10 MHz fIN = 35, 25, 15, 10 MHz

Symbol Parameter Test Conditions Min. Max. Min. Max. Unit

IIL Low-Level Input Current VCC = Max., GND ≤ VI ≤ VCC –10 — –10 — µ A

IIH High-Level Input Current VCC= Max., GND ≤ VI ≤ VCC —10—10µA

VOL Low-Level Output Voltage VCC= Min., IOL = 8m A — 0.4 — 0.4 V

VOH High-Level Output Voltage VCC= Min., IOH = –4mA 2.4 — 2.4 — V

IOS(1) Output Short-Circuit Current VCC= Max., VO = GN D –20 –110 –20 –110 m A

IHZ(2) HIGH Impedance Output Current VCC= Max., VO = 2.4V — 20 — 20 µA

ILZ(2) LOW Impedance Output Current VCC= Max., VO = 0.4V –20 — –20 — µA

ICC(3,4) Active Supply Current VCC= Max., f = 10MHz — 35 — 45 mA

NOTES:

1. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Guaranteed but not tested.

2. IDT72403 and IDT72404 only.

3. Tested with outputs open (IOUT = 0). OE is HIGH for IDT72403/72404.

4. For frequencies greater than 10MHz, ICC = 35mA + (1.5mA x [f –10MHz]) commercial, and ICC = 45mA + (1.5mA x [f –10MHz]) military.

5. Military availability for IDT72403 is 10MHz, 35MHz, for IDT72404 is 15MHz, 35MHz. IDT72401 is available for all MHz.

ABSOLUTE MAXIMUM RATINGS(1)

RECOMMENDED OPERATING

CONDITIONS

NC/OE

(1)

Vcc

GND

2747 drw 02

Vcc

GND

2747 drw 03

D0Q0

NC/OE

(2)

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional

operation of the device at these or any other conditions above those indicated in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect reliability.

NOTE:

1. 1.5V undershoots are allowed for 10ns once per cycle.

IDT72401/72402/72403/72404

CMOS PARALLEL FIFO 64 x 4, 64 x 5

MILITARY AND COMMERCIAL

TEMPERATURE RANGES

OPERATING CONDITIONS

(Commercial: VCC = 5.0V ± 10%, TA = 0°C t o +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C)

Commercial Commercial and Military(5)

IDT72401L45 IDT72401L35 IDT72401L25 IDT72401L15 IDT72401L10

IDT72402L45 IDT72402L35 IDT72402L25 IDT72402L15 IDT72402L10

IDT72403L45 IDT72403L35 IDT72403L25 IDT72403L15 IDT72403L10

IDT72404L45 IDT72404L35 IDT72404L25 IDT72404L15 IDT72404L10

Symbol Parameter Figure Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

tSIH(1) Shift in HIGH Time 2 9 — 9 — 11 — 11 — 11 — ns

tSIL Shift in LOW TIme 2 11 — 17 — 24 — 25 — 30 — ns

tIDS Input Data Set-up 2 0 — 0 — 0 — 0 — 0 — ns

tIDH Input Data Hold Time 2 13 — 15 — 20 — 30 — 40 — ns

tSOH(1) Shift Out HIGH Time 5 9 — 9 — 11 — 11 — 11 — ns

tSOL Shift Out LOW Time 5 11 — 17 — 24 — 25 — 25 — ns

tMRW Master Reset Pulse 8 20 — 25 — 25 — 25 — 30 — ns

tMRS Master Reset Pulse to SI 8 10 — 10 — 10 — 25 — 35 — ns

tSIR Data Set-up to IR 4 3 — 3 — 5 — 5 — 5 — ns

tHIR Data Hold from IR 4 13 — 15 — 20 — 30 — 30 — ns

tSOR(4) Data Set-up to OR HIGH 7 0 — 0 — 0 — 0 — 0 — ns

AC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5.0V ± 10%, TA = 0°C t o +70°C; Military: VCC = 5.0V ± 10%, TA = –55°C to +125°C)

Commercial Commercial and Military(5)

IDT72401L45 IDT72401L35 IDT72401L25 IDT72401L15 IDT72401L10

IDT72402L45 IDT72402L35 IDT72402L25 IDT72402L15 IDT72402L10

IDT72403L45 IDT72403L35 IDT72403L25 IDT72403L15 IDT72403L10

IDT72404L45 IDT72404L35 IDT72404L25 IDT72404L15 IDT72404L10

Symbol Parameter Figure Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit

fIN Shift In Rate 2 — 45 — 35 — 25 — 15 — 10 MHz

tIRL(1) Shift In to Input Ready LOW 2 — 18 — 18 — 21 — 35 — 40 ns

tIRH(1) Shift In to Input Ready HIGH 2 — 18 — 20 — 28 — 40 — 45 ns

fOUT Shift Out Rate 5 — 45 — 35 — 25 — 15 — 10 MHz

tORL(1) Shift Out to Output Ready LOW 5 — 18 — 18 — 19 — 35 — 40 ns

tORH(1) Shift Out to Output Ready HIGH 5 — 19 — 20 — 34 — 40 — 55 ns

tODH Output Data Hold (Previous Word) 5 5 — 5 — 5 — 5 — 5 — ns

tODS Output Data Shift (Next Word) 5 — 19 — 20 — 34 — 40 — 55 ns

tPT Data Throughput or "Fall-Through" 4, 7 — 30 — 34 — 40 — 65 — 65 ns

tMRORL Master Reset to OR LOW 8 — 25 — 28 — 35 — 35 — 40 ns

tMRIRH Master Reset to IR HIGH 8 — 25 — 28 — 35 — 35 — 40 ns

tMRQ Master Reset to Data Output LOW 8 — 20 — 20 — 25 — 35 — 40 ns

tOOE(3) Output Valid from OE LOW 9 — 12 — 15 — 20 — 30 — 35 ns

tHZOE(3,4) Output High-Z from OE HIGH 9 — 12 — 12 — 15 — 25 — 30 ns

tIPH(2,4) Input Ready Pulse HIGH 4 9 — 9 — 11 — 11 — 11 — ns

tOPH(2,4) Output Ready Pulse HIGH 7 9 — 9 — 11 — 11 — 11 — ns

NOTES:

1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding and decoupling

are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor supply decoupling and grounding.

A monolithic ceramic capacitor of 0.1µF directly between VCC and GND with very short lead length is recommended.

2. This parameter applies to FIFOs communicating with each other in a cascaded mode. IDT FIFOs are guaranteed to cascade with other IDT FIFOs of like speed grades.

3. IDT72403 and IDT72404 only.

4. Guaranteed by design but not currently tested.

5. Military availability for IDT72403 is 10MHz, 35MHz, for IDT72404 is 15MHz, 35MHz. IDT72401 is available for all MHz.

MILITARY AND COMMERCIAL

TEMPERATURE RANGES

IDT72401/72402/72403/72404

CMOS PARALLEL FIFO 64 x 4, 64 x 5

560Ω30pF*

1.1KΩ

OUTPUT

2747 drw 05

Input Pulse Levels GND to 3.0V

Input Rise/Fall Times 3ns

Input Timing Reference Levels 1.5V

Output Reference Levels 1.5V

Output Load See Figure 1

ALL INPUT PULSES:

SIGNAL DESCRIPTIONS

INPUTS:

DATA INPUT (D0-3, 4)

Data input lines. The IDT72401 and IDT72403 have a 4-bit data input. The

IDT72402 and IDT72404 have a 5-bit data input.

CONTROLS:

SHIFT IN (SI)

Shift In controls the input of the data into the FIFO. When SI is HIGH, data

can be written to the FIFO via the D0-3, 4 lines.

SHIFT OUT (SO)

Shift Out controls the output of data of the FIFO. When SO is HIGH, data can

be read from the FIFO via the Data Output (Q0-3, 4) lines.

MASTER RESET (MR)

Master Reset clears the FIFO of any data stored within. Upon power up, the

FIFO should be cleared with a MR. MR is active LOW.

INPUT READY (IR)

When Input Ready is HIGH, the FIFO is ready for new input data to be written

to it. When IR is LOW the FIFO is unavailable for new input data. IR is also used

to cascade many FlFOs together, as shown in Figures 10 and 11.

OUTPUT READY (OR)

When Output Ready is HIGH, the output (Q0-3, 4) contains valid data. When

OR is LOW, the FIFO is unavailable for new output data. OR is also used to

cascade many FlFOs together, as shown in Figures 10 and 11.

OUTPUT ENABLE (OE) (IDT72403 AND IDT72404 ONLY)

Output enable is used to read FIFO data onto a bus. OE is active LOW.

OUTPUTS:

DATA OUTPUT (Q0-3, 4)

Data Output lines. The IDT72401 and IDT72403 have a 4-bit data output.

The IDT72402 and IDT72404 have a 5-bit data output.

or equivalent circuit

Figure 1. AC Test Load

*Including scope and jig

Symbol Parameter Conditions Max. Unit

CIN Input Capacitance VIN = 0V 5 pF

COUT Output Capacitance VOUT = 0V 7 pF

NOTE:

1. Characterized values, not currently tested.

2747 drw 04

GND

3.0V 90%

10%

90%

10%

<3ns <3ns

AC TEST CONDITIONS

CAPACITANCE

(TA = +25°C, f = 1.0MHz)

IDT72401/72402/72403/72404

CMOS PARALLEL FIFO 64 x 4, 64 x 5

MILITARY AND COMMERCIAL

TEMPERATURE RANGES

FUNCTIONAL DESCRIPTION

These 64 x 4 and 64 x 5 FIFOs are designed using a dual port RAM

architecture as opposed to the traditional shift register approach. This FIFO

architecture has a write pointer, a read pointer and control logic, which allow

simultaneous read and write operations. The write pointer is incremented by

the falling edge of the Shift In (Sl) control; the read pointer is incremented by the

falling edge of the Shift Out (SO). The Input Ready (IR) signals when the FIFO

has an available memory location; Output Ready (OR) signals when there is

valid data on the output. Output Enable (OE) provides the capability of three-

stating the FIFO outputs.

FIFO RESET

The FIFO must be reset upon power up using the Master Reset (MR) signal.

This causes the FlFO to enter an empty state, signified by Output Ready (OR)

being LOW and Input Ready (IR) being HIGH. In this state, the data outputs

(Q0-3, 4) will be LOW.

DATA INPUT

Data is shifted in on the LOW-to-HlGH transition of Shift In (Sl). This loads

input data into the first word location of the FIFO and causes Input Ready (IR)

to go LOW. On the HlGH-to-LOW transition of SI, the write pointer is moved to

the next word position and IR goes HIGH, indicating the readiness to accept new

data. If the FIFO is full, IR will remain LOW until a word of data is shifted out.

DATA OUTPUT

Data is shifted out on the HlGH-to-LOW transition of Shift Out (SO). This causes

the internal read pointer to be advanced to the next word location. If data is

present, valid data will appear on the outputs and Output Ready (OR) will go

HIGH. If data is not present, OR will stay LOW indicating the FIFO is empty. The

last valid word read from the FIFO will remain at the FlFOs output when it is empty.

When the FIFO is not empty, OR goes LOW on the LOW-to-HIGH transition of

SO. Previous data remains on the output until the HIGH-to-LOW transition of

SO).

FALL THROUGH MODE

The FIFO operates in a fall-through mode when data gets shifted into an empty

FIFO. After a fall-through delay the data propagates to the output. When the

data reaches the output, the Output Ready (OR) goes HIGH. Fall-through mode

also occurs when the FIFO is completely full. When data is shifted out of the full

FIFO, a location is available for new data. After a fall-through delay, the Input

Ready (IR) goes HIGH. If Shift In (SI) is HIGH, the new data can be written

to the FIFO.

Since these FlFOs are based on an internal dual-port RAM architecture with

separate read and write pointers, the fall-through time (tPT) is one cycle long.

A word may be written into the FIFO on a clock cycle and can be accessed on

the next clock cycle.

Figure 3. The Mechanism of Shifting Data Into the FIFO

NOTES:

1. IR HIGH indicates space is available and a SI pulse may be applied.

2 . Input Data is loaded into the first word.

3. IR goes LOW indicating the first word is full.

4. The write pointer is incremented.

5. The FIFO is ready for the next word.

6 . If the FIFO is full then the IR remains LOW.

7. SI pulses applied while IR is LOW will be ignored (see Figure 4).

Figure 2. Input Timing

INPUT DATA

2747 drw 06

1/fIN

tSIH tSIL

tIDH

tIDS

1/fIN

tIRH

tIRL

INPUT DATA STABLE DATA

(2)

(3) (5)

2747 drw 07

(6)

(4)

(1)

(7)

MILITARY AND COMMERCIAL

TEMPERATURE RANGES

IDT72401/72402/72403/72404

CMOS PARALLEL FIFO 64 x 4, 64 x 5

Figure 6. The Mechanism of Shifting Data Out of the FIFO

NOTES:

1. OR HIGH indicates that data is available and a SO pulse may be applied.

2. SO goes HIGH causing the next step.

3. OR goes LOW.

4. The read pointer is incremented.

5. OR goes HIGH indicating that new data (B) is now available at the FIFO outputs.

6. If the FIFO has only one word loaded (A DATA) then OR stays LOW and the A DATA remains unchanged at the outputs.

7. SO pulses applied when OR is LOW will be ignored.

Figure 5. Output TIming

STABLE DATA

INPUT DATA

(2)

(3)

(1)

tIPH

tPT

(4)

(5)

2747 drw 08

tHIR

tSIR

NOTES:

1. FIFO is initially full.

2. SO pulse is applied.

3 . SI is held HIGH.

4. As soon as IR becomes HIGH the Input Data is loaded into the FIFO.

5. The write pointer is incremented. SI should not go LOW until (tPT + tIPH).

Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH

OUTPUT DATA A- DATA

(2)

(3) (5)

2747 drw 10

(6)

(4)

(1)

(7)

A or B

B- DATA

OUTPUT DATA

ORL

2747 drw 09

1/f

OUT

1/f

OUT

SOH

SOL

ODH

ORH

C-DATAB-DATAA-DATA

ODS

(2)

(1)

NOTES:

1. This data is loaded consecutively A, B, C.

2. Data is shifted out when SO makes a HIGH to LOW transition.

IDT72401/72402/72403/72404

CMOS PARALLEL FIFO 64 x 4, 64 x 5

MILITARY AND COMMERCIAL

TEMPERATURE RANGES

Figure 7. tPT and tOPH Specification

Figure 8. Master Reset Timing

Figure 9. Output Enable Timing, IDT72403 and IDT72404 Only

NOTE:

1. High-Z transitions are referenced to the steady-state VOH –500mV and VOL +500mV levels on the output. tHZOE is tested with 5pF load capacitance instead of 30pF as

shown in Figure 1.

2747 drw 14

SHIFT IN

INPUT READY

DATA IN

OUTPUT READY

SHIFT OUT

DATA OUT

NOTE:

1. FIFOs can be easily cascaded to any desired path. The handshaking and associated timing between the FIFOs are handled by the inherent timing of the devices.

Figure 10. 128 x 4 Depth Expansion

(1)

OPH

2747 drw 11

DATA OUTPUT DATA VALID

SOR

HZOE

2747 drw 13

DATA OUT

OOE

NOTE:

1. FIFO initially empty.

MRW

2747 drw 12

DATA OUTPUT

MRIRH

MRQ

(1)

MRORL

MRS

NOTE:

1. Worst case, FIFO initially full.

MILITARY AND COMMERCIAL

TEMPERATURE RANGES

IDT72401/72402/72403/72404

CMOS PARALLEL FIFO 64 x 4, 64 x 5

NOTES:

1. When the memory is empty, the last word will remain on the outputs until the MR is strobed or a new data word falls through to the output. However, OR will remain LOW,

indicating data at the output is not valid.

2. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data and stays LOW until the new data

has appeared on the outputs. Anytime OR is HIGH, there is valid stable data on the outputs.

3. If SO is held HIGH while the memory is empty and a word is written into the input, that word will appear at the output after a fall-through time. OR will go HIGH for one

internal cycle (at least tORL) and then go back LOW again. The stored word will remain on the outputs. If more words are written into the FIFO, they will line up behind the

first word and will not appear on the outputs until SO has been brought LOW.

4 . When the MR is brought LOW, the outputs are cleared to LOW, IR goes HIGH and OR goes LOW. If SI is HIGH when the MR goes HIGH, the data on the inputs will be

written into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LOW when the MR is ended, IR will go HIGH, but the data in the inputs will not

enter the memory until SI goes HIGH.

5. FIFOs are expandable on depth and width. However, in forming wider words, two external gates are required to generate composite Input and OR flags. This is due to the

variation of delays of the FIFOs.

Figure 11. 192 x 12 Depth and Width Expansion

2747 drw 15

SHIFT OUT

COMPOSITE

OUTPUT

READY

SHIFT IN

COMPOSITE

INPUT

READY

CORPORATE HEADQUARTERS for SALES: for Tech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 e-mail: fifohelp@idt.com

Santa Clara, CA 95054 fax: 408-492-8674 Phone: (408) 330-1753

www.idt.com

ORDERING INFORMATION

IDT XXXXX

Device Type

Speed

Power

Package

Process/

Temperature

Range

Blank

72401

72402

(1)

72403

72404

Commercial (0°C to+70°C)

Military (-55°C to+125°C)

Compliant to MIL-STD-883, Class B

Plastic DIP

CERDIP

Small Outline IC

Commercial Only

Commercial and Military>72401, 72403 & 72404 only

Commercial and Military>72401 only

Commercial and Military>72401 & 72404 only

Commercial and Military>72401 & 72403 only

Low Power

64 x 4 FIFO

64 x 5 FIFO

64 x 4 FIFO

64 x 5 FIFO

Shift Frequency (fs)

Speed in MHz

2747 drw 16

300 mil, P16-1

300 mil, D16-1

SOIC, SO16-1

300 mil, P18-1

300 mil, D18-1

SOIC, SO18-1

72401/72403 72402

(1)

/72404

NOTES:

1. IDT72402 is not available in Military and CERDIP.

2. Industrial temperature range is available by special order.

DATASHEET DOCUMENT HISTORY

07/10/2003 pgs. 2, 3, and 9.