NCP1030DR2 - ON Semiconductor

 Semiconductor Components Industries, LLC, 2002

June, 2002 – Rev. 0 1Publication Order Number:

NCP1030/D

NCP1030

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Bias Regulator with On

Chip Power Switch

The NCP1030 is a high voltage monolithic switching regulator with

on chip Power Switch and active Start–up Circuits. The NCP1030

integrates all the components necessary for implementing high

efficiency Voltage–Mode controlled DC–DC converters. It can be

easily configured for either primary or secondary side regulation

applications, such as a low power boost converter or a secondary side

controlled bias regulator. It is designed to operate from a 48 V supply,

typically found in telecommunication systems.

The NCP1030 fixed frequency oscillator is designed to operate up to

1 MHz and is capable of external frequency synchronization,

providing additional design flexibility. A minimum number of

external components are required to set the oscillator frequency, loop

compensation and the line under/over lockout thresholds. The

NCP1030 is available in the space saving S0–8 and Micro 8 packages,

making it a space efficient and cost saving solution.

Features

•On Chip High 200 V Power Switch Circuit and Startup Circuit

•External Frequency Synchronization up to 1 MHz

•Internal Startup Regulator with Auxiliary Winding Override

•Trimmed ±2% Internal Reference

•Line Under/Over Voltage Lockout

•Cycle by Cycle Current Limit

•Over Temperature Protection

•Internal Error Amplifier

•Primary or Secondary Regulation

Typical Applications

•Secondary Bias Supply for Isolated DC – DC Converters

•Stand Alone Low Power DC – DC Converter

•Low Power Boost Converter

This document contains information on a product under development. ON Semiconductor

reserves the right to change or discontinue this product without notice.

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Device Package Shipping

ORDERING INFORMATION

NCP1030DR2 S0–8 2500/Tape & Reel

NCP1030DMR2 Micro–8

S0–8

D SUFFIX

CASE 751

2500/Tape & Reel

MARKING

DIAGRAMS

A = Assembly Location

L = Wafer Lot

Y = Year

WW, W = Work Week

Micro 8

DM SUFFIX

CASE 846A

SCALE 1:1

P1030

ALYW

SCALE 2:1

TBD

YWW

GND 2

CT3

VFB 4

COMP

VCC

VDRAIN

(Top View)

PIN CONNECTIONS

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Figure 1. NCP1030 Functional Block Diagram

–

Thermal

Shutdown

One Shot

Pulse

–

Reset

Dominant

Latch

–

7.5 V/

10 V

6.5 V

2.5 V

–

LEB

Reset

Dominant

Latch

50 mV

–

2.5 V

–

5 mA

Internal Bias

16 V

10 V

5 V

GND

VFB

COMP

Disable

2.5 V/3.5 V+

–

PWM Latch

PWM Comparator

Error Amplifier

Current Limit

Comparator

VDRAIN

RSENSE

10 V

VCC

I2 = 3I1

CT Ramp

–

10 V

Functional Pin Description

Pin Name Function Description

1 GND Ground Ground reference pin for the circuit.

2 CTOscillator Frequency

Selection An external capacitor connected to this pin sets the oscillator frequency up to

1 MHz. The oscillator can be synchronized to a higher frequency by charging or

discharging CT to trip the internal 2.5 V/3.5 V comparator.

3 VFB Feedback Input The regulated voltage is scaled down to 2.5 V by means of a resistor divider. Regu-

lation is then achieved comparing the scaled regulated voltage to an internal 2.5 V

reference.

4 COMP Error Amplifier Compensation Requires external compensation network between COMP and VFB pins.

5 OV Line Overvoltage Shutdown Line voltage (Vin) is scaled down using an external resistor divider such that the OV

voltage reaches 2.5 V when line voltage reaches its maximum voltage.

6 UV Line Undervoltage Shutdown Line voltage is scaled down using an external resistor divider such that the UV volt-

age reaches 2.5 V when line voltage reaches its minimum voltage.

7 VCC Supply Voltage This pin is connected to an external capacitor for energy storage. During Turn–On,

the startup circuit sources current to initially charge the capacitor connected to this

pin. When the supply voltage reaches VCC(on), the startup circuit turns off and the

power switch is enabled. An external winding can be used to supply power after

initial startup. VCC should not exceed 16 V.

8 VDRAIN Power Switch and

Startup Circuits This pin connects directly to one of the transformer windings. The internal High Volt-

age Power Switch Circuit is connected between this pin and ground. Also, this pin

internally connects the Power Switch and Startup Circuits.

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Figure 2. Pulse Width Modulation Timing Diagram

CT Ramp

CT Charge

Signal

PWM

Comparator

Output

PWM Latch

Output

Power Switch

Circuit Gate Drive

Leading Edge

Blanking Output

COMP Voltage

Current Limit

Propagation Delay

Current Limit

Threshold

Normal PWM Operating Range Output Overload

Figure 3. Dynamic Self Supply with Fault Condition Timing Diagram

Out of

Regulation

VCC(on)

VCC(off)

VCC(reset)

0 V

0 mA

ISTART

0 V

VDRAIN

VFB

Reset Normal OperationNormal OperationInitial

Power–up

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MAXIMUM RATINGS (Note 1)

Rating Symbol Value Unit

Power Switch and Startup Circuit Voltage VDRAIN –0.3 to 200 V

COMP Voltage Range VCOMP –0.3 to 5 V

All Other Inputs/Outputs Voltage Range VIO –0.3 to 10 V

VCC Voltage Range VCC –0.3 to 16 V

Operating Junction Temperature TJ–40 to 125 °C

Storage Temperature Tstg –55 to 150 °C

Power Dissipation (TJ = 25°C)

D Suffix, Plastic Package Case 751

DM Suffix, Plastic Package Case 846A TBD

TBD

Thermal Resistance

D Suffix, Plastic Package Case 751

Junction to Case

Junction to Air, 2.0 Oz. Printed Circuit Copper Clad

0.36 Sq. Inch

1.0 Sq. Inch

DM Suffix, Plastic Package Case 846A

Junction to Case

Junction to Air, 2.0 Oz. Printed Circuit Copper Clad

0.36 Sq. Inch

1.0 Sq. Inch

RJC

RJA

RJC

RJA

TBD

°C/W

1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those

indicated may adversely affect device reliability. Functional operation under absolute maximum rated conditions is not implied. Functional

operation should be restricted to the Recommended Operating Conditions.

A.This device contains ESD protection circuitry and exceeds the following tests:

Pins 1–7: Human Body Model 2000V per MIL–STD–883, Method 3015.

Pins 1–7: Machine Model Method 100 V.

Pin 8 i s c onnected t o t he H igh Voltage Start–up a nd P ower S witch c ircuits a nd r ated o nly t o t he m aximum v oltage r ating o f t he part, or 200 V.

B.This device contains Latch–up protection and exceeds XX mA per JEDEC Standard JESD78.

DC ELECTRICAL CHARACTERISTICS (VDRAIN = 48 V, VCC = 12 V, CT = 560 pF, VUV = 3 V, VOV = 2 V, VFB = 2.3 V, TJ = –40°C

to 125°C, typical values shown are for TJ = 25°C unless otherwise noted.)

Characteristics Symbol Min Typ Max Unit

START–UP CONTROL

Start–up Circuit Output Current (VFB = VCOMP)

VCC = 0 V

VCC = VCC(on) – 0.2 V

ISTART 5.0

5.0 TBD

TBD TBD

TBD

VCC Supply Monitor (VFB = 2.7 V)

Start–Up Threshold Voltage (VCC Increasing)

Minimum Operating VCC After Turn–on (VCC Increasing)

Hysteresis Voltage

VCC(on)

VCC(off)

VCC(hys)

9.5

7.0

–

10.0

7.5

2.5

10.5

8.0

–

Undervoltage Lockout Threshold Voltage, VCC Decreasing (VFB = VCOMP) VCC(reset) TBD 6.5 TBD V

ERROR AMPLIFIER

Reference Voltage (VCOMP = VFB, Follower Mode)

TJ = 25°C

TJ = –40°C to 125°C

VREF TBD

TBD 2.5

2.5 TBD

TBD

Line Regulation (VCC = 7.5 V to 10 V, TJ = 25°C) REGLINE – 1.0 TBD mV

Input Bias Current (VFB = 0 V to 2.7 V) IVFB – 0.1 1.0 A

Comp Source Current (VCOMP = 2.5 V, VFB = 2.3 V) ISRC 50 100 150 A

Comp Sink Current (VCOMP = 2.5 V, VFB = 2.7 V) ISNK 500 – TBD A

Comp Maximum Voltage (ISRC = 100 A) VC(max) 5.0 – – V

Comp Minimum Voltage (ISNK = 100 A, VFB = 2.7 V) VC(min) – – 1.0 V

Open Loop Voltage Gain AVOL – 80 – dB

Gain Bandwidth Product GBW – 1.0 – MHz

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DC ELECTRICAL CHARACTERISTICS (VDRAIN = 48 V, VCC = 12 V, CT = 560 pF, VUV = 3 V, VOV = 2 V, VFB = 2.3 V, TJ = –40°C

to 125°C, typical values shown are for TJ = 25°C unless otherwise noted.)

Characteristics UnitMaxTypMinSymbol

LINE OV/UV LIMITER

Undervoltage Lockout (VFB = VCOMP)

Voltage Threshold (Vin Increasing)

Voltage Hysteresis

Input Bias Current

VUV

VUV(hys)

IUV

2.4

0.100

–

2.5

0.150

0.1

2.6

0.200

1.0

A

Overvoltage Lockout (VFB = VCOMP)

Voltage Threshold (Vin Increasing)

Voltage Hysteresis

Input Bias Current

VOV

VOV(hys)

IOV

2.4

0.100

–

2.5

0.150

0.1

2.6

0.200

1.0

A

OSCILLATOR

Frequency (CT = 560 pF)

TJ = 25°C

TJ = –40°C to 125°C

fOSC1 285

TBD 300

TBD 315

TBD

kHz

Frequency (CT = 100 pF)

TJ = 25°C

TJ = –40°C to 125°C

fOSC2 TBD

TBD 1000

TBD TBD

TBD

kHz

Externally Synchronized Frequency (Note 2) fSYNC fOSC – TBD kHz

PWM COMPARATOR

PWM Duty Cycle (Maximum) DCMAX TBD 75 TBD %

PWM Ramp

Peak

Valley Vrpk

Vrvly –

–3.5

2.5 –

–

POWER SWITCH CIRCUIT

Power Switch Circuit On–State Resistance (ID = 100 mA)

TJ = 25°C

TJ = 125°C

RDS(on) –

–6

TBD TBD



Power Switch Circuit and Startup Circuit Breakdown Voltage

(ID = 100 A, TJ = 25°C) V(BR)DS 200 – – V

Power Switch Circuit and Startup Circuit Off–State Leakage Current

(VDRAIN = 200 V, VUV = 2.0 V)

TJ = 25°C

TJ = 125°C

IDS(off)

–

–TBD

TBD 50

TBD

A

Switching Characteristics (VDS = TBD, RL = TBD)

Rise Time

Fall Time tr

tf–

–50

50 –

–

CURRENT LIMIT AND OVER TEMPERATURE PROTECTION

Current Limit Threshold (TJ = 25°C, di/dt = X) ILIM TBD 0.5 TBD A

Propagation Delay, Current Limit Threshold to Power Switch Circuit Output

RL = TBD (Leading Edge Blanking plus Current Limit Delay) tPLH – 100 TBD ns

Thermal Protection (Note 3)

Shutdown Threshold (TJ Increasing)

Hysteresis TSHDN

THYS 125

–150

25 –

–

°C

TOTAL DEVICE

Power Supply Current After UV Turn–On

Power Switch Enabled

Power Switch Disabled

Non–Fault condition (VFB = 2.7 V)

Fault Condition (VFB = 2.7 V, VUV = 2.0 V)

ICC1

ICC2

ICC3

1.0

–

TBD

1.5

0.7

2.0

1.0

2. Oscillator frequency can be externally synchronized to the maximum frequency of the device.

3. Guaranteed by design only.

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ON/OFF

SYNC GND

COMP

Figure 4. Secondary Side Bias Supply Configuration

VIN

–

VCC

GND FEEDBACK

SECONDARY

SIDE CONTROL

CIRCUITRY

ISOLATED

GATE

DRIVE

VCC

VDRAIN

VFB

VOUT

–

ON/OFF

GND

COMP

Figure 5. Boost Circuit Configuration

VOUT

VCC

VDRAIN

VFB

VIN

–

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OPERATING DESCRIPTION

Introduction

The NCP1030 is a miniature, monolithic Voltage–Mode

switching regulator designed to operate from a 48 V supply,

commonly found in telecommunication systems. It is a fixed

frequency regulator optimized for operation up to 1 MHz.

The NCP1030 incorporates in a single IC all the active

power, control logic and protection circuitry required to

implement, with a minimum of external components,

several switching regulator applications, such as a

secondary side bias, low boost converter or secondary side

regulator. This device is available in the space saving S0–8

and Micro 8 packages, making it a space efficient and cost

saving solution.

The NCP1030 includes a powerful set of features

including over temperature protection, cycle by cycle

current limiting, line under/over voltage lockout with

hysteresis, and regulator output under voltage lockout with

hysteresis, providing full protection during fault conditions.

A description of each of the functional blocks is given below,

and the representative block diagram is shown in Figure 2.

VCC Limiter and Undervoltage Lockout

The NCP1030 contains an internal 200 V start–up

regulator that eliminates the need for external start–up

components. In addition, this regulator increases the

efficiency of the supply as it uses no power when in the

normal mode of operation, but instead uses power supplied

by an auxiliary winding.

The start–up regulator consists of a constant current

source that supplies current from the input line (Vin) to the

capacitor on the VCC pin. The start–up current is typically

5 mA. Once the VCC voltage reaches 10 V during initial

power up, the start–up circuit is disabled and the Power

Switch Circuit is enabled if no faults are present. During this

self–bias mode, power to the NCP1030 is supplied by the

VCC capacitor. The start–up regulator turns ON again once

VCC reaches 7.5 V. This “7.5–10” mode of operation is

known as Dynamic Self Supply (DSS).

If V CC falls below 7.5 V after initial power–up, the device

enters a re–start mode. While in the re–start mode, the Power

Switch Circuit is disabled and VCC is allowed to discharge

to 6.5 V. At that time, the start–up regulator turns ON again

to charge the VCC capacitor.

The V CC pin can be biased above 7.5 V using an auxiliary

winding once switching is allowed. This will keep the

start–up regulator from turning ON, thus reducing power

consumption.

The external VCC capacitor must be sized such that the

self–bias will maintain a VCC voltage greater than 7.5 V

during initial start–up.

The start–up circuit is rated at a maximum of 200 V. If the

device operates in the DSS mode, power dissipation should

be controlled to avoid exceeding the maximum power

dissipation of the controller.

Error Amplifier

The internal error amplifier compares the scaled output

signal to an internal 2.5 V reference connected to its non–

inverting input. The feedback pin (VFB) connects directly to

the error amplifier inverting input. The output of the error

amplifier is available for frequency compensation and

connection to the PWM comparator through the COMP pin.

The error amplifier input bias current is less than 1 µA

over the operating range. The output source and sink

currents are typically 100 µA and 500 µA, respectively.

Line Under/Over Voltage

The NCP1030 incorporates line undervoltage (UV) and

overvoltage (OV) shutdown circuits. The UV and OV

thresholds are 2.5 V. A fault is present if the UV is below

2.5 V or if the OV voltage is above 2.5 V.

The UV/OV circuits can be biased using an external

resistor divider from the input line as shown in Figure 6.

Figure 6. UV/OV resistor divider from the input line

Vin

VUV

–

VOV

–

The resistor divider must be sized to enable the controller

once Vin is within the required operating range. When a UV

or UV fault is present, switching is not allowed and the

COMP voltage is kept low.

Oscillator

The NCP1030 oscillator is designed to operate up to

1 MHz and its frequency is set by the external timing

capacitor (CT) connected on the CT pin. The oscillator has

two modes of operation, free running and synchronized

(sync).

While in free running mode, an internal current source

sequentially charges and discharges CT generating a voltage

ramp between 2.5 V and 3.5 V. Under normal operating

conditions the charge (I1) and discharge (I2) currents are

typically 200 µA and 600 µA, respectively. However, if an

UV fault is present, I1 and I2 are both reduced by a factor of

2.5 to reduce power consumption. The charge:discharge

current ratio of 1:3 discharges CT in 25 % of the charge

period. As the Power Switch is disabled while CT is

discharging, a maximum duty cycle of 75% is assured.

If the operating frequency (f) is known, CT is calculated

using the equation below.

CT(200 A) (0.75)

(1 V) (f)

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Other factors such as operating frequency, comparator

delay and temperature variations affect the calculated CT

value. Figure X shows the measured frequency variation vs

timing capacitor.

The NCP1030 is capable of synchronization to a higher

frequency. The oscillator frequency should be set no more

that 25% below the tar get sync frequency. In sync mode, the

voltage on the CT pin needs to be driven above 3.5 V to

trigger the internal comparator and complete the CT

charging period. This can be done pulsing the CT pin as

shown below.

Figure 7. External Frequency Synchronization

Sync ModeFree

Running

Mode

Sync Pulse

3.5 V

2.5 V

2.5 V/3.5 V

Comparator

Reset

CT Ramp

T1 (f1)T

2 (f2)

T2 (f2)

Once the sync pulse is removed, the CT voltage needs to

closely match the voltage prior to applying the pulse. If not,

the charge:discharge ratio will deviate from the 1:3 ratio,

and the preset maximum duty cycle limit (75%) will change

accordingly.

PWM Comparator and Latch

The Pulse Width Modulator (PWM) Comparator converts

the DC error signal into a duty cycle by comparing the DC

error signal to the CT Ramp. The output of the PWM

Comparator goes high, thus disabling the Power Switch,

when the DC error signal exceeds the CT Ramp as shown in

Figure 2.

The CT Charge Signal out of the 2.5 V/3.5 V Comparator

is filtered through a One Shot Pulse Generator to set the

PWM Latch and enable switching at the beginning of each

period. Switching is allowed while the error signal is above

the C T Ramp and a current limit fault is not present. If the CT

Ramp does not exceed the DC error signal or a current limit

fault is detected, the Power Switch Circuit is disabled once

the CT Charge Signal goes low. Therefore, the maximum

duty cycle is limited by the duration of CT Charge Signal.

Current Limit Comparator and Power Switch Circuit

The NCP1030 monolithically integrates a 200 V Power

Switch Circuit with control logic circuitry. The Power

Switch Circuit is designed to directly drive the converter

transformer. The characteristics of the Power Switch Circuit

are well known. Therefore, the gate drive is tailored to

control switching transitions and help limit electromagnetic

interference (EMI). The Power Switch Circuit is capable of

switching 200 V with a nominal peak drain current of

0.5 Amps.

The Power Switch Circuit incorporates SENSEFET

technology to monitor the drain current. A sense voltage is

generated b y driving a sense element, RSENSE, with a current

proportional to the drain current. The sense voltage is

compared to an internal reference voltage on the

non–inverting input of the Current Limit Comparator. If the

sense voltage exceeds the reference level, the comparator

resets the PWM Latch and switching is terminated until the

next cycle.

Each time the Power Switch Circuit turns ON, a narrow

voltage spike appears across RSENSE . The spike is due to the

Power Switch Circuit gate to source capacitance,

transformer interwinding capacitance, and output rectifier

recovery time. This spike can cause a premature reset of the

PWM Latch. A Leading Edge Blanking (LEB) Circuit

masks the current signal until the Power Switch Circuit

turn–on transition is complete.

The current limit propagation delay time is typically 100

nanoseconds. This time is measured from when an over

current fault appears at the Power Switch Circuit drain, to

the start of the turn–off transition. Propagation delay must

be factor in the transformer design to avoid transformer

saturation.

Thermal Shutdown

Internal Thermal Shutdown circuitry is provided to

protect the integrated circuit in the event the maximum

junction temperature is exceeded. When activated, typically

at 150C, the Power Switch Circuit is disabled. Once the

junction temperature falls below 125C, the NCP1030 is

allowed to resume normal operation. This feature is

provided to prevent catastrophic failures from accidental

device overheating. It is not intended to be used as a

substitute for proper heatsinking.

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PACKAGE DIMENSIONS

S0–8

D SUFFIX

CASE 751–07

ISSUE W

SEATING

PLANE

X 45

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER

SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN

EXCESS OF THE D DIMENSION AT MAXIMUM

MATERIAL CONDITION.

0.10 (0.004)

–X–

–Y–

0.25 (0.010)

–Z–

0.25 (0.010) Z SXS

Micro 8

DM SUFFIX

CASE 846A–02

ISSUE E

0.08 (0.003) A S

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A2.90 3.10 0.114 0.122

B2.90 3.10 0.114 0.122

C--- 1.10 --- 0.043

D0.25 0.40 0.010 0.016

G0.65 BSC 0.026 BSC

H0.05 0.15 0.002 0.006

J0.13 0.23 0.005 0.009

K4.75 5.05 0.187 0.199

L0.40 0.70 0.016 0.028

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH,

PROTRUSIONS OR GATE BURRS. MOLD FLASH,

PROTRUSIONS OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH OR

PROTRUSION SHALL NOT EXCEED 0.25 (0.010)

PER SIDE.

–B–

–A–

PIN 1 ID

8 PL

0.038 (0.0015)

–T– SEATING

PLANE

HJL

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Notes

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ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make

changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any

particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all

liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or

specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be

validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others.

SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death

may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC

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arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that

SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.

PUBLICATION ORDERING INFORMATION

JAPAN: ON Semiconductor, Japan Customer Focus Center

4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan 141–0031

Phone: 81–3–5740–2700

Email: r14525@onsemi.com

ON Semiconductor Website: http://onsemi.com

For additional information, please contact your local

Sales Representative.

NCP1030/D

The product described herein (NCP1030) may be covered by one or more U.S. patents. There may be other patents pending.

SENSEFET is a trademark of Semiconductor Components Industries, LLC.

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