QD48S012015 Data Sheet 36-75 Vdc Input, 15 A, 1.2 Vdc and 15 A, 1.5 Vdc Output The QD48S012015 dual output surface mounted DC/DC converter offers unprecedented performance in a quarter brick package by providing two independently regulated high current outputs. This is accomplished by the use of patent pending circuit and packaging techniques to achieve ultrahigh efficiency, excellent thermal performance and a very low body profile. In telecommunications applications the QD48 converters provide up to 15 A per channel simultaneously - 30 A total - with thermal performance far exceeding existing dual quarter bricks and comparable to dual half-bricks. Low body profile and the preclusion of heatsinks minimize airflow shadowing, thus enhancing cooling for downstream devices. The use of 100% surface-mount technologies for assembly, coupled with di/dt's advanced electric and thermal circuitry and packaging, results in a product with extremely high quality and reliability. Total Output Power [W] 50 40 30 500 LFM (2.5 m/s) 400 LFM (2.0 m/s) 300 LFM (1.5 m/s) 200 LFM (1.0 m/s) 100 LFM (0.5 m/s) 30 LFM (0.15 m/s) 20 10 0 20 30 40 50 60 70 80 90 Ambient Temperature [C] Fig. 1: Available output power vs. ambient air temperature and airflow rates for QD48S012015 converter mounted vertically with air flowing from pin 3 to pin 1, MOSFET temperature 120C, Vin = 48 V and balanced load on both outputs (Iout1 = Iout2). Applications * * * * Telecommunications Datacommunications Wireless Servers QD48S012015 FDS Ver 2 05-01-03 QD48S012015 Converter Features * * * * * * * * * * * * * * * * * * * * * * Delivers up to 15 A simultaneously on 1.2 Vdc and 1.5 Vdc outputs Can replace two single output quarter-bricks Minimal cross-channel interference High efficiency: 83% @ 2x15 A, 84% @ 2x7.5 A Starts-up into pre-biased output No minimum load required No heatsink required Lowest profile in industry: 0.26" [6.6 mm] Lowest weight in industry: 1 oz [28 g] typical Industry-standard footprint: 1.45" x 2.30" Meets Basic Insulation Requirements of EN60950 Withstands 100 V input transient for 100 ms On-board LC input filter Fixed frequency operation Fully protected Output voltage trim range: 10% for both outputs Trim resistor via industry-standard equations High reliability: MTBF 2.6 million hours, calculated per Telcordia TR-332, Method I Case 1 Positive or negative logic ON/OFF option UL 60950 recognized in U.S. & Canada, and DEMKO certified per IEC/EN 60950 (pending) Meets conducted emissions requirements of FCC Class B and EN55022 Class B with external filter All materials meet UL94, V-0 flammability rating USA Toll Free 866 WOW-didt Page 1 of 15 QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Data Sheet Electrical Specifications Conditions: TA=25C, Airflow=300 LFM (1.5 m/s), Vin=48 Vdc, unless otherwise specified. PARAMETER ABSOLUTE MAXIMUM RATINGS NOTES Input Voltage Operating Ambient Temperature Storage Temperature Continuous MIN TYP 0 -40 -55 MAX UNITS 80 85 125 Vdc C C INPUT CHARACTERISTICS Operating Input Voltage Range Input Under Voltage Lockout Turn-on Threshold Turn-off Threshold Input Voltage Transient 36 48 75 Vdc 33 31 34 32 35 33 100 Vdc Vdc V 10,000 10,000 15 15 19.5 19.5 30 30 4 4 F F Adc Adc Adc Adc A A Arms Arms Non-latching 100 ms OUTPUT CHARACTERISTICS External Load Capacitance: Output Current Range: Current Limit Inception: Peak Short-Circuit Current: RMS Short-Circuit Current: 1.2 V 1.5 V 1.2 V 1.5 V 1.2 V 1.5 V 1.2 V 1.5 V 1.2 V 1.5 V Plus full load (resistive) Plus full load (resistive) At nominal output voltage 1.2 V At nominal output voltage 1.5 V Non-latching Non-latching Non-latching. Short = 10 m. Non-latching. Short = 10 m. Non-latching Non-latching 0 0 16.5 16.5 18 18 20 20 ISOLATION CHARACTERISTICS I/O Isolation Isolation Capacitance Isolation Resistance 2000 Vdc nF M 1.3 10 FEATURE CHARACTERISTICS Switching Frequency 1 Output Voltage Trim Range Output Over-Voltage Protection Auto-Restart Period Turn-On Time ON/OFF Control (Positive Logic) Converter Off Converter On ON/OFF Control (Negative Logic) Converter Off Converter On 415 1.2 V See section: Output Voltage Adjust/TRIM 1.5 V Simultaneous with 1.2 V output -10 -10 1.2 V Non-latching 1.5 V Non-latching Applies to all protection features 1.5 V 1.2 V tracks 1.5 V 1.4 1.75 +10 +10 1.48 1.85 100 3 kHz % % 1.56 1.95 V V ms ms -20 2.4 0.8 20 Vdc Vdc 2.4 -20 20 0.8 Vdc Vdc Additional Notes: 1. Vout1 and Vout2 can be simultaneously increased or decreased up to 10% via the Trim function. When trimming up, in order not to exceed the converter`s maximum allowable output power capability equal to the product of the nominal output voltage and the allowable output current for the given conditions, the designer must, if necessary, decrease the maximum current (originally obtained from the derating curves) by the same percentage to ensure the converter's actual output power remains at or below the maximum allowable output power. QD48S012015 FDS Ver 2 05-01-03 USA Toll Free 866 WOW-didt Page 2 of 15 QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Data Sheet Electrical Specifications (continued) Conditions: TA=25C, Airflow=300 LFM (1.5 m/s), Vin=48 Vdc, unless otherwise specified. PARAMETER INPUT CHARACTERISTICS NOTES Maximum Input Current Input Stand-by Current Input No Load Current (0 load on both outputs) Input Reflected-Ripple Current Input Voltage Ripple Rejection MIN 1.2 Vdc @ 15 Adc, 1.5 Vdc @ 15 Adc, Vin = 36 V Vin = 48 V, converter disabled Vin = 48 V, converter enabled See Figure 33 - 25MHz bandwidth 120Hz TYP MAX UNITS 1.36 Adc 3 45 6 TBD mAdc mAdc mAPK-PK dB OUTPUT CHARACTERISTICS 2 Output Voltage Set Point (no load) Output Regulation: Over Line 3 Over Load 4 Cross Regulation Output Voltage Range Output Ripple and Noise - 25MHz BW 1.2 V 1.5 V 1.2 V 1.5 V 1.2 V 1.5 V 1.2 V 1.5 V 1.2 V 1.5 V 1.2 V 1.5 V -40C to 85C -40C to 85C 1.193 1.490 For Iout2 (1.5 V) change from 0 to 15 A For Iout1 (1.2 V) change from 0 to 15 A Over line, load and cross regulation Over line, load and cross regulation Full load + 1 F ceramic Full load + 1 F ceramic 1.176 1.475 1.205 1.505 2 2 -10 -10 -5 -5 20 25 1.217 1.520 1.224 1.535 30 40 Vdc Vdc mV mV mV mV mV mV Vdc Vdc mVPK-PK mVPK-PK DYNAMIC RESPONSE Load Change: 50% to 75% to 50% di/dt = 0.1 A/S 1.2 V 1.5 V Setting Time to 1% 1.2 V 1.5 V di/dt = 5 A/S 1.2 V 1.5 V Setting Time to 1% 1.2 V 1.5 V Iout = 25% of IoutMax Co = 10 F tant. + 1 F ceramic (Fig.20) Co = 10 F tant. + 1 F ceramic (Fig.21) Co = 300 F tant. + 1 F ceramic (Fig.22) Co = 300 F tant. + 1 F ceramic (Fig.23) 75 75 100 100 75 75 60 60 mV mV s s mV mV s s 83 84 % % EFFICIENCY 1.2 V 100% Load, 1.5 V 100% Load 1.2 V 50% Load, 1.5 V 50% Load Additional Notes: 2. No load set point is 5 mV higher than the nominal voltage, to partially compensate voltage drop on the output pins. 3. Load regulation is affected with resistance of the output pins (approximately 0.3 m) since there is no remote sense. 4. Cross regulation is affected with resistance of the RETURN pin (approximately 0.3 m) since there is no remote sense. QD48S012015 FDS Ver 2 05-01-03 USA Toll Free 866 WOW-didt Page 3 of 15 QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Data Sheet Physical Information Pin Connections Pin # 1 2 3 4 5 6 7 7 1 TOP VIEW 2 3 6 5 Function Vin (+) ON/OFF Vin (-) Vout1 (+) RTN [Vout1(-) and Vout2(-)] TRIM Vout2 (+) 4 * * * * * SIDE VIEW All dimensions are in inches [mm] Connector material: Copper Connector Finish: Gold over Nickel Converter Weight: 1 oz. [28 g] typical Recommended Surface-Mount Pads: Min. 0.080" x 0.112" [2.03 x 2.84] Max. 0.092" x 0.124" [2.34 x 3.15] Converter Part Numbering Scheme Product Series Input Voltage Mounting Scheme Output Voltage 1 (VOUT1 ) Output Voltage 2 (VOUT2) QD 48 S 012 015 012 1.2 V 015 1.5 V 36-75 V Surface Mount Dual QuarterBrick Format Note: Always specify VOUT2 as the higher of the two output voltages. - ON/OFF Logic Maximum Height Pin Length Special Features N S 0 0 S 0.273" 0 0.00" N Negative 0 STD P Positive The example above describes P/N QD48S012015-NS00: 36-75 V input, dual output, surface mounting, 1.2 V and 1.5 V outputs @ 15 A each, negative ON/OFF logic. Please consult factory regarding availability of a specific version. QD48S012015 FDS Ver 2 05-01-03 USA Toll Free 866 WOW-didt Page 4 of 15 QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Operation Input and Output Impedance These power converters have been designed to be stable with no external capacitors when used in low inductance input and output circuits. However, in many applications, the inductance associated with the distribution from the power source to the input of the converter can affect the stability of the converter. The addition of a 33 F electrolytic capacitor with an ESR < 1 across the input helps ensure stability of the converter. In many applications, the user has to use decoupling capacitance at the load. The converter will exhibit stable operation with external load capacitance up to 10,000 F on both outputs. age of 0.8 V. An external voltage source of 20 V max. may be connected directly to the ON/OFF input, in which case it should be capable of sourcing or sinking up to 1 mA depending on the signal polarity. See the Start-up Information section for system timing waveforms associated with use of the ON/OFF pin. Output Voltage Adjust /TRIM (Pin 6) The converter's output voltages can be adjusted simultaneously up 10% or down 10% relative to the rated output voltages by the addition of an externally connected resistor. The TRIM pin should be left open if trimming is not being used. To minimize noise pickup, a 0.1 F capacitor is connected internally between the TRIM and RETURN pins. ON/OFF (Pin 2) Q TM Family Converter (Top View) ON/OFF Vin Q Family Converter Vout2 (+) (Top View) TRIM TM Vin (+) The ON/OFF pin is used to turn the power converter on or off remotely via a system signal. There are two remote control options available, positive logic and negative logic and both are referenced to Vin(-). Typical connections are shown in Fig. 2. Vin (+) Data Sheet R T-INCR Rload2 ON/OFF Vin RTN Rload1 Vin (-) Vout1 (+) Fig. 3: Configuration for increasing output voltage. Vout2 (+) TRIM Rload2 RTN To increase the output voltage (refer to Fig. 3), a trim resistor, RT-INCR, should be connected between the TRIM (Pin 6) and RETURN (Pin 5), with a value from the table below. Rload1 Vin (-) Vout1 (+) CONTROL INPUT Fig. 2: Circuit configuration for ON/OFF function. Vout2 (+) (Top View) TRIM ON/OFF Vin The negative logic version turns on when the pin is at logic low and turns off when the pin is at logic high. The ON/OFF pin can be hard wired directly to Vin(-) to enable automatic power up of the converter without the need of an external control signal. ON/OFF pin is internally pulled-up to 5 V through a resistor. A mechanical switch, open collector transistor, or FET can be used to drive the input of the ON/OFF pin. The device must be capable of sinking up to 0.2 mA at a low level volt- Rload2 R T-DECR RTN The positive logic version turns on when the ON/OFF pin is at logic high and turns off when at logic low. The converter is on when the ON/OFF pin is left open. QD48S012015 FDS Ver 2 05-01-03 Q Family Converter TM Vin (+) Rload1 Vin (-) Vout1 (+) Fig. 4: Configuration for decreasing output voltage. To decrease the output voltage, a trim resistor RT-DECR, (Fig. 4) should be connected between the TRIM (Pin 6) and Vout2(+) pin (Pin 7), with a value from the table below, where: = percentage of increase or decrease Vout(NOM). Note 1: Both outputs are trimmed up or down simultaneously. USA Toll Free 866 WOW-didt Page 5 of 15 QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Trim Resistor (Vout Increase) Data Sheet Output Over-Voltage Protection (OVP) Trim Resistor (Vout Decrease) [%] RT-INCR [k] [%] RT-DECR [k] 1 2 3 4 5 6 7 8 9 10 60.4 29.4 19.6 14.3 11.3 9.31 7.87 6.81 5.9 5.23 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 13.7 6.04 3.48 2.26 1.5 1 0.649 0.383 0.174 0 The converter will shut down if the output voltage across either Vout1(+) (Pin 4) or Vout2(+) (Pin 7) and RETURN (Pin 5) exceeds the threshold of the OVP circuitry. The OVP protection is separate for Vout1 and Vout2 with their own reference independent of the output voltage regulation loops. Once the converter has shut down, it will attempt to restart every 100 ms until the OVP condition is removed. Over-Temperature Protection (OTP) Note 2: The above trim resistor values match those typically used in industry-standard dual quarter bricks. Protection Features The converter will shut down under an over-temperature condition to protect itself from overheating caused by operation outside the thermal derating curves, or operation in abnormal conditions such as system fan failure. After the converter has cooled to a safe operating temperature, it will automatically restart. Input Under-Voltage Lockout Safety Requirements Input under-voltage lockout is standard with this converter. The converter will shut down when the input voltage drops below a pre-determined voltage. The converters meet North American and International safety regulatory requirements per UL60950 and EN60950. Basic Insulation is provided between input and output. The input voltage must be at least 35 V for the converter to turn on. Once the converter has been turned on, it will shut off when the input voltage drops below 31 V. This feature is beneficial in preventing deep discharging of batteries used in telecom applications. To comply with safety agencies requirements, an input line fuse must be used external to the converter. A 3-A fuse is recommended for use with this product. Output Over-Current Protection (OCP) EMC requirements must be met at the end-product system level, as no specific standards dedicated to EMC characteristics of board mounted component dc-dc converters exist. However, di/dt tests its converters to several system level standards, primary of which is the more stringent EN55022, Information technology equipment - Radio disturbance characteristics - Limits and methods of measurement. The converter is protected against over-current or short circuit conditions on both outputs. Upon sensing an overcurrent condition, the converter will switch to constant current operation and thereby begin to reduce output voltages. If, due to current limit, the output voltage Vout2 (1.5 V) drops below Vout1 - 0.6 V, converter will shut down. If, due to current limit, the output voltage Vout1 (1.2 V) drops below 60% of its nominal value (0.7 V) the converter will shut down (Figs. 26 and 27). Thus, current limit on one output does not affect regulation on the other output. Once the converter has shut down, it will attempt to restart nominally every 100 ms with a typical 2% duty cycle (Figs. 28 and 29). The attempted restart will continue indefinitely until the overload or short circuit conditions are removed or the output voltage rises above under-voltage threshold. QD48S012015 FDS Ver 2 05-01-03 Electromagnetic Compatibility (EMC) With the addition of a simple external filter (see application notes), all versions of the QD48S converters pass the requirements of Class B conducted emissions per EN55022 and FCC, and meet at a minimum, Class A radiated emissions per EN 55022 and Class B per FCC Title 47CFR, Part 15-J. Please contact di/dt Applications Engineering for details of this testing. USA Toll Free 866 WOW-didt Page 6 of 15 QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Data Sheet temperature was varied between 25C and 85C, with airflow rates from 30 to 500 LFM (0.15 to 2.5 m/s), and vertical and horizontal converter mounting. Characterization General Information The converter has been characterized for many operational aspects, to include thermal derating (maximum load current as a function of ambient temperature and airflow) for vertical and horizontal mounting, efficiency, start-up and shutdown parameters, output ripple and noise, transient response to load step-change, overload and short circuit. The following pages contain specific plots or waveforms associated with the converter. Additional comments for specific data are provided below. Test Conditions All data presented were taken with the converter soldered to a test board, specifically a 0.060" thick printed wiring board (PWB) with four layers. The top and bottom layers were not metalized. The two inner layers, comprising two-ounce copper, were used to provide traces for connectivity to the converter. The lack of metalization on the outer layers as well as the limited thermal connection ensured that heat transfer from the converter to the PWB was minimized. This provides a worst-case but consistent scenario for thermal derating purposes. All measurements requiring airflow were made in di/dt's vertical and horizontal wind tunnel facilities using infrared (IR) thermography and thermocouples for thermometry. Ensuring that the components on the converter do not exceed their ratings is important to maintaining high reliability. If one anticipates operating the converter at or close to the maximum loads specified in the derating curves, it is prudent to check actual operating temperatures in the application. Thermographic imaging is preferable; if this capability is not available, then thermocouples may be used. di/dt recommends the use of AWG #40 gauge thermocouples to ensure measurement accuracy. Careful routing of the thermocouple leads will further minimize measurement error. Refer to Figure 34 for optimum measuring thermocouple location. Thermal Derating For each set of conditions, the maximum load current was defined as the lowest of: (i) The output current at which either any FET junction temperature did not exceed a maximum specified temperature (120C) as indicated by the thermographic image, or (ii) The nominal rating of the converter (15 A on either output). During normal operation, derating curves with maximum FET temperature less or equal to 120C should not be exceeded. Temperature on the PCB at the thermocouple location shown in Fig. 34 should not exceed 118C in order to operate inside the derating curves. Efficiency Efficiency vs. load current plots are shown in Figs. 12-17 for ambient temperature of 25C, airflow rate of 300 LFM (1.5 m/s), both vertical and horizontal orientations, and input voltages of 36 V, 48 V and 72 V, for different combinations of the loads on outputs Vout1 and Vout2. Start-up Output voltage waveforms during the turn-on transient using the ON/OFF pin, are shown without and with full rated load currents (resistive load) in Figs. 18 and 19, respectively. Ripple and Noise Figure 30 shows the output voltage ripple waveform, measured at full rated load current on both outputs with a 1 F ceramic capacitor across both outputs. Note that all output voltage waveforms are measured across a 1 F ceramic capacitor. The input reflected ripple current waveforms are obtained using the test setup shown in Fig. 31. The corresponding waveforms are shown in Figs. 32 and 33. Available output power and load current vs. ambient temperature and airflow rates are given in Figs. 8-11. Ambient QD48S012015 FDS Ver 2 05-01-03 USA Toll Free 866 WOW-didt Page 7 of 15 QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Start-up Information (using negative ON/OFF) Scenario #1: Initial Start-up From Bulk Supply ON/OFF function enabled, converter started via application of VIN. See Figure 5. Time Comments t0 ON/OFF pin is ON; system front end power is toggled on, VIN to converter begins to rise. t1 VIN crosses Under-Voltage Lockout protection circuit threshold; converter enabled. t2 Converter begins to respond to turn-on command (converter turn-on delay). t3 Output voltage VOUT1 reaches 100% of nominal value. t4 Output voltage VOUT2 reaches 100% of nominal value. For this example, the total converter start-up time (t4- t1) is typically 3 ms. Data Sheet VIN ON/OFF STATE OFF ON VOUT2 VOUT2 VOUT1 VOUT1 t0 t1 t2 t3 t4 Fig. 5: Start-up scenario #1. Scenario #2: Initial Start-up Using ON/OFF Pin With VIN previously powered, converter started via ON/OFF pin. See Figure 6. Time Comments t0 VINPUT at nominal value. t1 Arbitrary time when ON/OFF pin is enabled (converter enabled). t2 End of converter turn-on delay. t3 Output voltage VOUT1 reaches 100% of nominal value. t4 Output voltage VOUT2 reaches 100% of nominal value. For this example, the total converter start-up time (t4 - t1) is typically 3 ms. Scenario #3: Turn-off and Restart Using ON/OFF Pin With VIN previously powered, converter is disabled and then enabled via ON/OFF pin. See Figure 7. Time Comments t0 VIN and VOUT are at nominal values; ON/OFF pin ON. t1 ON/OFF pin arbitrarily disabled; converter outputs fall to zero; turn-on inhibit delay period (100 ms typical) is initiated, and ON/OFF pin action is internally inhibited. t2 ON/OFF pin is externally re-enabled. If (t2- t1) 100 ms, external action of ON/OFF pin is locked out by start-up inhibit timer. If (t2- t1) > 100 ms, ON/OFF pin action is internally enabled. t3 Turn-on inhibit delay period ends. If ON/OFF pin is ON, converter begins turn-on; if off, converter awaits ON/OFF pin ON signal; see Figure 6. t4 End of converter turn-on delay. t5 Output voltage VOUT1 reaches 100% of nominal value. t6 Output voltage VOUT2 reaches 100% of nominal value. For the condition, (t2 - t1) 100 ms, the total converter start-up time (t6 - t2) is typically 103 ms. For (t2 - t1) > 100 ms, start-up time will be typically 3 ms after release of ON/OFF pin. QD48S012015 FDS Ver 2 05-01-03 VIN ON/OFF STATE OFF ON VOUT2 VOUT2 VOUT1 VOUT1 t0 t1 t2 t3 t4 Fig. 6: Start-up scenario #2. VIN 100 ms ON/OFF STATE OFF ON VOUT2 VOUT2 VOUT1 VOUT1 t0 USA Toll Free 866 WOW-didt t1 t2 t3 t4 t5 t6 Fig. 7: Start-up scenario #3. Page 8 of 15 50 50 40 40 Total Output Power [W] Total Output Power [W] QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output 30 500 LFM (2.5 m/s) 400 LFM (2.0 m/s) 300 LFM (1.5 m/s) 200 LFM (1.0 m/s) 100 LFM (0.5 m/s) 30 LFM (0.15 m/s) 20 10 0 20 30 40 50 60 70 80 Data Sheet 30 500 LFM (2.5 m/s) 400 LFM (2.0 m/s) 300 LFM (1.5 m/s) 200 LFM (1.0 m/s) 100 LFM (0.5 m/s) 30 LFM (0.15 m/s) 20 10 0 20 90 30 40 Ambient Temperature [C] 20.0 20.0 17.5 17.5 15.0 12.5 10.0 500 LFM (2.5 m/s) 400 LFM (2.0 m/s) 300 LFM (1.5 m/s) 200 LFM (1.0 m/s) 100 LFM (0.5 m/s) 30 LFM (0.15 m/s) 5.0 2.5 0.0 20 30 40 50 60 70 70 80 90 80 90 15.0 12.5 10.0 500 LFM (2.5 m/s) 400 LFM (2.0 m/s) 300 LFM (1.5 m/s) 200 LFM (1.0 m/s) 100 LFM (0.5 m/s) 30 LFM (0.15 m/s) 7.5 5.0 2.5 0.0 20 30 Ambient Temperature [C] 40 50 60 70 80 90 Ambient Temperature [C] Fig. 10: Available balanced load current (Iout1 = Iout2) vs. ambient air temperature and airflow rates for converter mounted vertically with Vin = 48 V, air flowing from pin 3 to pin 1 and maximum FET temperature 120C. QD48S012015 FDS Ver 2 05-01-03 60 Fig. 9: Available output power for balanced load current (Iout1 = Iout2) vs. ambient air temperature and airflow rates for converter mounted horizontally with Vin = 48 V, air flowing from pin 3 to pin 1 and maximum FET temperature 120C. Load Current Iout1, Iout2 [Adc] Load Current Iout1, Iout2 [Adc] Fig. 8: Available output power for balanced load current (Iout1 = Iout2) vs. ambient air temperature and airflow rates for converter mounted vertically with Vin = 48 V, air flowing from pin 3 to pin 1 and maximum FET temperature 120C. 7.5 50 Ambient Temperature [C] Fig. 11: Available balanced load current (Iout1 = Iout2) vs. ambient temperature and airflow rates for converter mounted horizontally with Vin = 48 V, air flowing from pin 3 to pin 1 and maximum FET temperature 120C. USA Toll Free 866 WOW-didt Page 9 of 15 0.95 0.95 0.90 0.90 0.85 0.85 Efficiency Efficiency QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output 0.80 0.75 Data Sheet 0.80 0.75 72 V 48 V 36 V 0.70 72 V 48 V 36 V 0.70 Iout2 = 7.5 Adc Iout2 = 7.5 Adc 0.65 0.65 0 2 4 6 8 10 12 14 16 0 2 4 Load Current Iout1 [Adc] Fig. 12: Efficiency vs. load current Iout1 and input voltage for converter mounted vertically with air flowing from pin 3 to pin 1 at a rate of 300 LFM (1.5 m/s), for Iout2 = 7.5 A and Ta = 25C. 8 10 12 14 16 Fig. 13: Efficiency vs. load current Iout1 and input voltage for converter mounted horizontally with air flowing from pin 3 to pin 1 at a rate of 300 LFM (1.5 m/s), for Iout2 = 7.5 A and Ta = 25C. 0.95 0.95 0.90 0.90 0.85 0.85 Efficiency Efficiency 6 Load Current Iout1 [Adc] 0.80 0.75 0.80 0.75 72 V 48 V 36 V 72 V 48 V 36 V 0.70 0.70 Iout1 = 7.5 Adc Iout1 = 7.5 Adc 0.65 0.65 0 2 4 6 8 10 12 14 16 0 2 6 8 10 12 14 16 Load Current Iout2 [Adc] Load Current Iout2 [Adc] Fig. 14: Efficiency vs. load current Iout2 and input voltage for converter mounted vertically with air flowing from pin 3 to pin 1 at a rate of 300 LFM (1.5 m/s), for Iout1 = 7.5 A and Ta = 25C. QD48S012015 FDS Ver 2 05-01-03 4 Fig. 15: Efficiency vs. load current Iout2 and input voltage for converter mounted horizontally with air flowing from pin 3 to pin 1 at a rate of 300 LFM (1.5 m/s), for Iout1 = 7.5 A and Ta = 25C. USA Toll Free 866 WOW-didt Page 10 of 15 0.95 0.95 0.90 0.90 0.85 0.85 Efficiency Efficiency QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output 0.80 0.75 Data Sheet 0.80 0.75 72 V 48 V 36 V 0.70 72 V 48 V 36 V 0.70 0.65 0.65 0 2 4 6 8 10 12 14 16 0 2 Load Current Iout1 = Iout2 [Adc] 4 6 8 10 12 14 16 Load Current Iout1 = Iout2 [Adc] Fig. 16: Efficiency vs. balanced load current (Iout1 = Iout2) and input voltage for converter mounted vertically with air flowing from pin 3 to pin 1 at a rate of 300 LFM (1.5 m/s) and Ta = 25C. Fig. 17: Efficiency vs. balanced load current (Iout1 = Iout2) and input voltage for converter mounted horizontally with air flowing from pin 3 to pin 1 at a rate of 300 LFM (1.5 m/s) and Ta = 25C. Fig. 18: Turn-on transient waveforms at no load current and Vin = 48 V, triggered via ON/OFF pin. Top trace: ON/OFF signal (5 V/div.). Bottom traces: Vout1 (blue, 0.5 V/div.), Vout2 (red, 0.5 V/div.). Time scale: 1 ms/div. Fig. 19: Turn-on transient waveforms at full rated load current (resistive) and Vin = 48 V, triggered via ON/OFF pin. Top trace: ON/OFF signal (5 V/div.). Bottom traces: Vout1 (blue, 0.5 V/div.), Vout2 (red, 0.5 V/div.). Time scale: 1 ms/div. . QD48S012015 FDS Ver 2 05-01-03 USA Toll Free 866 WOW-didt Page 11 of 15 QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Data Sheet Fig. 20: Output voltage response to Iout1 load current stepchange of 3.75 A (50%-75%-50%) at Iout2 = 7.5 A and Vin = 48 V. Ch1 = Vout1 (50 mV/div), Ch2 = Vout2 (50 mV/div), Ch3 = Iout1 (10 A/div.), Ch4 = Iout2 (10 A/div.). Current slew rate: 0.1 A/s, Co = 10 F tantalum + 1 F ceramic. Time scale: 0.5 ms/div. Fig. 21: Output voltage response to Iout2 load current stepchange of 3.75 A (50%-75%-50%) at Iout1 = 7.5 A and Vin = 48 V. Ch1 = Vout1 (50 mV/div), Ch2 = Vout2 (50 mV/div), Ch3 = Iout1 (10 A/div.), Ch4 = Iout2 (10 A/div.). Current slew rate: 0.1 A/s, Co = 10 F tantalum + 1 F ceramic. Time scale: 0.5 ms/div. Fig. 22: Output voltage response to Iout1 load current stepchange of 3.75 A (50%-75%-50%) at Iout2 = 7.5 A and Vin = 48 V. Ch1 = Vout1 (100 mV/div), Ch2 = Vout2 (100 mV/div), Ch3 = Iout1 (10 A/div.), Ch4 = Iout2 (10 A/div.). Current slew rate: 5 A/s, Co = 300 F tantalum + 1 F ceramic. Time scale: 0.5 ms/div. Fig. 23: Output voltage response to Iout2 load current stepchange of 3.75 A (50%-75%-50%) at Iout1 = 7.5 A and Vin = 48 V. Ch1 = Vout1 (100 mV/div), Ch2 = Vout2 (100 mV/div), Ch3 = Iout1 (10 A/div.), Ch4 = Iout2 (10 A/div.). Current slew rate: 5 A/s, Co = 300 F tantalum + 1 F ceramic. Time scale: 0.5 ms/div. QD48S012015 FDS Ver 2 05-01-03 USA Toll Free 866 WOW-didt Page 12 of 15 QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Fig. 24: Output voltage response to both Iout1 and Iout2 (out of phase) load current step-change of 3.75 A (50%-75%-50%) at Vin = 48 V. Ch1 = Vout1 (50 mV/div), Ch2 = Vout2 (50 mV/div), Ch3 = Iout1 (10 A/div.), Ch4 = Iout2 (10 A/div.). Current slew rate: 0.1 A/s, Co = 10 F tantalum + 1 F ceramic. Time scale: 1 ms/div. Data Sheet Fig. 25: Output voltage response to both Iout1 and Iout2 (out of phase) load current step-change of 3.75 A (50%-75%-50%) at Vin = 48 V. Ch1 = Vout1 (100 mV/div), Ch2 = Vout2 (100 mV/div), Ch3 = Iout1 (10 A/div.), Ch4 = Iout2 (10 A/div.). Current slew rate: 5 A/s, Co = 300 F tantalum + 1 F ceramic. Time scale: 1 ms/div. Note: The only cross-talk during transient is due to the common RETURN pin for both outputs. 2.0 2.0 1.5 1.5 Vout2 Vout [Vdc] Vout [Vdc] Vout1 1.0 0.5 1.0 0.5 0 0 0 5 10 15 20 0 Iout [Adc] 10 15 20 Iout [Adc] Fig. 26: Output voltage Vout1 vs. load current Iout1 showing current limit point and converter shutdown point. When Vout1 is in current limit, Vout2 is not affected until Vout1 reaches the shut-down threshold of 60% of its nominal value. Input voltage has almost no effect on Vout1 current limit characteristic. QD48S012015 FDS Ver 2 05-01-03 5 Fig. 27: Output voltage Vout2 vs. load current Iout2 showing current limit point and converter shutdown point. When Vout2 is in current limit, Vout1 is not affected until Vout2 reaches the shut-down threshold equal to Vout1 - 0.6 V. Input voltage has almost no effect on Vout2 current limit characteristic. USA Toll Free 866 WOW-didt Page 13 of 15 QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Fig. 28: Load current Iout1 into a 10 m short circuit on Vout1 during restart, with Vout2 open (no load), at Vin = 48 V. Ch2 = Iout1 (20 A/div, 20 ms/div). ChB = Iout1 (20 A/div, 1 ms/div) is an expansion of the on-time portion of Iout1. Fig. 29: Load current Iout2 into a 10 m short circuit on Vout2 during restart, with Vout1 open (no load), at Vin = 48 V. Ch2 = Iout2 (20 A/div, 20 ms/div). ChB = Iout2 (20 A/div, 1 ms/div) is an expansion of the on-time portion of Iout2. iS 10 H source inductance Vsource Fig. 30: Output voltage ripple at full rated load current into a resistive load on both outputs with Co = 1uF (ceramic) and Vin = 48 V. Ch2 = Vout2, Ch1 = Vout1 (both 20 mV/div). Time scale: 1 s/div. QD48S012015 FDS Ver 2 05-01-03 Data Sheet iC 33 F ESR <1 electrolytic capacitor Q Family DC/DC Converter TM 1 F ceramic capacitor Vout2 1 F Vout1 ceramic capacitor Fig. 31: Test Set-up for measuring input reflected ripple currents, ic and is. USA Toll Free 866 WOW-didt Page 14 of 15 QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Fig. 32: Input reflected ripple current, ic (100 mA/div), measured at input terminals at full rated load current on both outputs and Vin = 48 V. Refer to Fig. 31 for test setup. Time scale: 1 s/div. Data Sheet Fig. 33: Input reflected ripple current, is (10 mA/div), measured through 10 H at the source at full rated load current on both outputs and Vin = 48 V. Refer to Fig. 31 for test setup. Time scale: 1s/div. Fig. 34: Location of the thermocouple for thermal testing. For more information please contact di/dt, Inc. 1822 Aston Avenue ** Carlsbad, CA ** 92008 ** USA USA Toll Free 866-WOW-didt (969-3438) www.didt.com ** support@didt.com The information and specifications contained in this data sheet are believed to be accurate and reliable at the time of publication. However, di/dt, Inc. assumes no responsibility for its use or for any infringements of patents or other rights of third parties, which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of di/dt, Inc. Specifications are subject to change without notice. (c)Copyright di/dt, Inc. 2003 QD48S012015 FDS Ver 2 05-01-03 USA Toll Free 866 WOW-didt Page 15 of 15