QD48S012015-PS00 - di/dt, Inc.

QD48S012015 Data Sheet

36-75 Vdc Input, 15 A, 1.2 Vdc and 15 A, 1.5 Vdc Output

QD48S012015 FDS Ver 2 05-01-03 USA Toll Free 866 WOW-didt Page 1 of 15

The QD48S012015 dual output surface mounted DC/DC

converter offers unprecedented performance in a quarter

brick package by providing two independently regulated high

current outputs. This is accomplished by the use of patent

pending circuit and packaging techniques to achieve ultra-

high efficiency, excellent thermal performance and a very

low body profile.

In telecommunications applications the QD48 converters

provide up to 15 A per channel simultaneously – 30 A total –

with thermal performance far exceeding existing dual quarter

bricks and comparable to dual half-bricks. Low body profile

and the preclusion of heatsinks minimize airflow shadowing,

thus enhancing cooling for downstream devices. The use of

100% surface-mount technologies for assembly, coupled

with di/dt’s advanced electric and thermal circuitry and pack-

aging, results in a product with extremely high quality and

reliability.

Ambient Temperature [°C]

20 30 40 50 60 70 80 90

Total Output Power [W]

0

10

20

30

40

50

500 LFM (2.5 m/s)

400 LFM (2.0 m/s)

300 LFM (1.5 m/s)

200 LFM (1.0 m/s)

100 LFM (0.5 m/s)

30 LFM (0.15 m/s)

Fig. 1: Available output power vs. ambient air temperature and

airflow rates for QD48S012015 converter mounted vertically with air

flowing from pin 3 to pin 1, MOSFET temperature ≤ 120°C, Vin =

48 V and balanced load on both outputs (Iout1 = Iout2).

Applications

• Telecommunications

• Datacommunications

• Wireless

• Servers

QD48S012015 Converter

Features

• Delivers up to 15 A simultaneously on 1.2 Vdc and

1.5 Vdc outputs

• Can replace two single output quarter-bricks

• Minimal cross-channel interference

• High efficiency: 83% @ 2x15 A, 84% @ 2x7.5 A

• Starts-up into pre-biased output

• No minimum load required

• No heatsink required

• Lowest profile in industry: 0.26” [6.6 mm]

• Lowest weight in industry: 1 oz [28 g] typical

• Industry-standard footprint: 1.45” x 2.30”

• Meets Basic Insulation Requirements of EN60950

• Withstands 100 V input transient for 100 ms

• On-board LC input filter

• Fixed frequency operation

• Fully protected

• Output voltage trim range: ±10% for both outputs

• Trim resistor via industry-standard equations

• High reliability: MTBF 2.6 million hours, calculated per

Telcordia TR-332, Method I Case 1

• Positive or negative logic ON/OFF option

• UL 60950 recognized in U.S. & Canada, and DEMKO

certified per IEC/EN 60950 (pending)

• Meets conducted emissions requirements of FCC

Class B and EN55022 Class B with external filter

• All materials meet UL94, V-0 flammability rating

QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Data Sheet

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Electrical Specifications

Conditions: TA=25ºC, Airflow=300 LFM (1.5 m/s), Vin=48 Vdc, unless otherwise specified.

PARAMETER NOTES MIN TYP MAX UNITS

ABSOLUTE MAXIMUM RATINGS

Input Voltage Continuous 0 80 Vdc

Operating Ambient Temperature -40 85 °C

Storage Temperature -55 125 °C

INPUT CHARACTERISTICS

Operating Input Voltage Range 36 48 75 Vdc

Input Under Voltage Lockout Non-latching

Turn-on Threshold 33 34 35 Vdc

Turn-off Threshold 31 32 33 Vdc

Input Voltage Transient 100 ms 100 V

OUTPUT CHARACTERISTICS

External Load Capacitance: 1.2 V Plus full load (resistive) 10,000 µF

1.5 V Plus full load (resistive) 10,000 µF

Output Current Range: 1.2 V At nominal output voltage 1.2 V 0 15 Adc

1.5 V At nominal output voltage 1.5 V 0 15 Adc

Current Limit Inception: 1.2 V Non-latching 16.5 18 19.5 Adc

1.5 V Non-latching 16.5 18 19.5 Adc

Peak Short-Circuit Current: 1.2 V Non-latching. Short = 10 m. 20 30 A

1.5 V Non-latching. Short = 10 m. 20 30 A

RMS Short-Circuit Current: 1.2 V Non-latching 4 Arms

1.5 V Non-latching 4 Arms

ISOLATION CHARACTERISTICS

I/O Isolation 2000 Vdc

Isolation Capacitance 1.3 nF

Isolation Resistance 10 M

FEATURE CHARACTERISTICS

Switching Frequency 415 kHz

Output Voltage Trim Range1 1.2 V See section: Output Voltage Adjust/TRIM -10 +10 %

1.5 V Simultaneous with 1.2 V output -10 +10 %

Output Over-Voltage Protection 1.2 V Non-latching 1.4 1.48 1.56 V

1.5 V Non-latching 1.75 1.85 1.95 V

Auto-Restart Period Applies to all protection features 100 ms

Turn-On Time 1.5 V 1.2 V tracks 1.5 V 3 ms

ON/OFF Control (Positive Logic)

Converter Off -20 0.8 Vdc

Converter On 2.4 20 Vdc

ON/OFF Control (Negative Logic)

Converter Off 2.4 20 Vdc

Converter On -20 0.8 Vdc

Additional Notes:

1. Vout1 and Vout2 can be simultaneously increased or decreased up to 10% via the Trim function. When trimming up, in order not to exceed

the converter‘s maximum allowable output power capability equal to the product of the nominal output voltage and the allowable output current

for the given conditions, the designer must, if necessary, decrease the maximum current (originally obtained from the derating curves) by the

same percentage to ensure the converter’s actual output power remains at or below the maximum allowable output power.

QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Data Sheet

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Electrical Specifications (continued)

Conditions: TA=25ºC, Airflow=300 LFM (1.5 m/s), Vin=48 Vdc, unless otherwise specified.

PARAMETER NOTES MIN TYP MAX UNITS

INPUT CHARACTERISTICS

Maximum Input Current

1.2 Vdc @ 15 Adc, 1.5 Vdc @ 15 Adc,

Vin = 36 V

1.36

Adc

Input Stand-by Current Vin = 48 V, converter disabled 3 mAdc

Input No Load Current (0 load on both outputs) Vin = 48 V, converter enabled 45 mAdc

Input Reflected-Ripple Current See Figure 33 - 25MHz bandwidth 6 mAPK-PK

Input Voltage Ripple Rejection 120Hz TBD dB

OUTPUT CHARACTERISTICS

Output Voltage Set Point2 (no load) 1.2 V -40ºC to 85ºC 1.193 1.205 1.217 Vdc

1.5 V -40ºC to 85ºC 1.490 1.505 1.520 Vdc

Output Regulation: Over Line 1.2 V ±2 mV

1.5 V ±2 mV

Over Load3 1.2 V -10 mV

1.5 V -10 mV

Cross Regulation4 1.2 V For Iout2 (1.5 V) change from 0 to 15 A -5 mV

1.5 V For Iout1 (1.2 V) change from 0 to 15 A -5 mV

Output Voltage Range 1.2 V Over line, load and cross regulation 1.176 1.224 Vdc

1.5 V Over line, load and cross regulation 1.475 1.535 Vdc

Output Ripple and Noise - 25MHz BW 1.2 V Full load + 1 µF ceramic 20 30 mVPK-PK

1.5 V Full load + 1 µF ceramic 25 40 mVPK-PK

DYNAMIC RESPONSE

Load Change: 50% to 75% to 50% Iout = 25% of IoutMax

di/dt = 0.1 A/µS 1.2 V Co = 10 µF tant. + 1 µF ceramic (Fig.20) 75 mV

1.5 V Co = 10 µF tant. + 1 µF ceramic (Fig.21) 75 mV

Setting Time to 1% 1.2 V 100 µs

1.5 V 100 µs

di/dt = 5 A/µS 1.2 V Co = 300 µF tant. + 1 µF ceramic (Fig.22) 75 mV

1.5 V Co = 300 µF tant. + 1 µF ceramic (Fig.23) 75 mV

Setting Time to 1% 1.2 V 60 µs

1.5 V 60 µs

EFFICIENCY

1.2 V 100% Load, 1.5 V 100% Load 83 %

1.2 V 50% Load, 1.5 V 50% Load 84 %

Additional Notes:

2. No load set point is 5 mV higher than the nominal voltage, to partially compensate voltage drop on the output pins.

3. Load regulation is affected with resistance of the output pins (approximately 0.3 m) since there is no remote sense.

4. Cross regulation is affected with resistance of the RETURN pin (approximately 0.3 m) since there is no remote sense.

QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Data Sheet

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Physical Information

SIDE VIEW

TOP VIEW

2

3

1

4

5

6

7

Converter Part Numbering Scheme

Product

Series

Input

Voltage

Mounting

Scheme

Output

Voltage 1

(VOUT1 )

Output

Voltage 2

(VOUT2)

ON/OFF

Logic

Maximum

Height

Length

Special

Features

QD 48 S 012 015 - N S 0 0

012 ⇒ 1.2 V

015 ⇒ 1.5 V

Dual

Quarter-

Brick

Format

36-75 V

Surface

Mount

Note: Always specify VOUT2 as the

higher of the two output voltages.

N ⇒

Negative

P ⇒

Positive

S ⇒ 0.273” 0 ⇒ 0.00” 0 ⇒ STD

The example above describes P/N QD48S012015-NS00: 36-75 V input, dual output, surface mounting, 1.2 V and 1.5 V outputs @ 15 A each, negative

ON/OFF logic. Please consult factory regarding availability of a specific version.

Pin Connections

Pin # Function

1 Vin (+)

2 ON/OFF

3 Vin (-)

4 Vout1 (+)

5 RTN [Vout1(-) and Vout2(-)]

6 TRIM

7 Vout2 (+)

•

All dimensions are in inches [mm]

• Connector material: Copper

• Connector Finish: Gold over Nickel

• Converter Weight: 1 oz. [28 g] typical

• Recommended Surface-Mount Pads:

Min. 0.080” x 0.112” [2.03 x 2.84]

Max. 0.092” x 0.124” [2.34 x 3.15]

QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Data Sheet

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Operation

Input and Output Impedance

These power converters have been designed to be stable

with no external capacitors when used in low inductance in-

put and output circuits.

However, in many applications, the inductance associated

with the distribution from the power source to the input of the

converter can affect the stability of the converter. The addi-

tion of a 33 µF electrolytic capacitor with an ESR < 1 Ω

across the input helps ensure stability of the converter. In

many applications, the user has to use decoupling capaci-

tance at the load. The converter will exhibit stable operation

with external load capacitance up to 10,000 µF on both out-

puts.

ON/OFF (Pin 2)

The ON/OFF pin is used to turn the power converter on or

off remotely via a system signal. There are two remote con-

trol options available, positive logic and negative logic and

both are referenced to Vin(-). Typical connections are shown

in Fig. 2.

Rload2

Vin

CONTROL

INPUT

Vin (+)

Vin (-)

ON/OFF

Vout2 (+)

Vout1 (+)

TRIM

RTN

(Top View)

Converter

QTM Family

Rload1

Fig. 2: Circuit configuration for ON/OFF function.

The positive logic version turns on when the ON/OFF pin is

at logic high and turns off when at logic low. The converter is

on when the ON/OFF pin is left open.

The negative logic version turns on when the pin is at logic

low and turns off when the pin is at logic high. The ON/OFF

pin can be hard wired directly to Vin(-) to enable automatic

power up of the converter without the need of an external

control signal.

ON/OFF pin is internally pulled-up to 5 V through a resistor.

A mechanical switch, open collector transistor, or FET can

be used to drive the input of the ON/OFF pin. The device

must be capable of sinking up to 0.2 mA at a low level volt-

age of ≤ 0.8 V. An external voltage source of ±20 V max.

may be connected directly to the ON/OFF input, in which

case it should be capable of sourcing or sinking up to 1 mA

depending on the signal polarity. See the Start-up Informa-

tion section for system timing waveforms associated with

use of the ON/OFF pin.

Output Voltage Adjust /TRIM (Pin 6)

The converter’s output voltages can be adjusted simultane-

ously up 10% or down 10% relative to the rated output volt-

ages by the addition of an externally connected resistor.

The TRIM pin should be left open if trimming is not being

used. To minimize noise pickup, a 0.1 µF capacitor is con-

nected internally between the TRIM and RETURN pins.

Rload2

Vin

Vin (+)

Vin (-)

ON/OFF

Vout2 (+)

Vout1 (+)

TRIM

RTN

RT-INCR

(Top View)

Converter

QTM Family

Rload1

Fig. 3: Configuration for increasing output voltage.

To increase the output voltage (refer to Fig. 3), a trim resis-

tor, RT-INCR, should be connected between the TRIM (Pin 6)

and RETURN (Pin 5), with a value from the table below.

Vin

Rload2

Vin (+)

Vin (-)

ON/OFF

Vout2 (+)

Vout1 (+)

TRIM

RTN

RT-DECR

(Top View)

Converter

QTM Family

Rload1

Fig. 4: Configuration for decreasing output voltage.

To decrease the output voltage, a trim resistor RT-DECR, (Fig.

4) should be connected between the TRIM (Pin 6) and

Vout2(+) pin (Pin 7), with a value from the table below,

where:

 = percentage of increase or decrease Vout(NOM).

Note 1: Both outputs are trimmed up or down simultane-

ously.

QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Data Sheet

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Trim Resistor

(Vout Increase)

∆ [%] RT-INCR [kΩ]

1 60.4

2 29.4

3 19.6

4 14.3

5 11.3

6 9.31

7 7.87

8 6.81

9 5.9

10 5.23

Trim Resistor

(Vout Decrease)

∆ [%] RT-DECR [kΩ]

-1 13.7

-2 6.04

-3 3.48

-4 2.26

-5 1.5

-6 1

-7 0.649

-8 0.383

-9 0.174

-10 0

Note 2: The above trim resistor values match those typically

used in industry-standard dual quarter bricks.

Protection Features

Input Under-Voltage Lockout

Input under-voltage lockout is standard with this converter.

The converter will shut down when the input voltage drops

below a pre-determined voltage.

The input voltage must be at least 35 V for the converter to

turn on. Once the converter has been turned on, it will shut

off when the input voltage drops below 31 V. This feature is

beneficial in preventing deep discharging of batteries used in

telecom applications.

Output Over-Current Protection (OCP)

The converter is protected against over-current or short cir-

cuit conditions on both outputs. Upon sensing an over-

current condition, the converter will switch to constant cur-

rent operation and thereby begin to reduce output voltages.

If, due to current limit, the output voltage Vout2 (1.5 V) drops

below Vout1 - 0.6 V, converter will shut down. If, due to cur-

rent limit, the output voltage Vout1 (1.2 V) drops below 60%

of its nominal value (0.7 V) the converter will shut down

(Figs. 26 and 27). Thus, current limit on one output does not

affect regulation on the other output.

Once the converter has shut down, it will attempt to restart

nominally every 100 ms with a typical 2% duty cycle (Figs.

28 and 29). The attempted restart will continue indefinitely

until the overload or short circuit conditions are removed or

the output voltage rises above under-voltage threshold.

Output Over-Voltage Protection (OVP)

The converter will shut down if the output voltage across ei-

ther Vout1(+) (Pin 4) or Vout2(+) (Pin 7) and RETURN (Pin

5) exceeds the threshold of the OVP circuitry. The OVP pro-

tection is separate for Vout1 and Vout2 with their own refer-

ence independent of the output voltage regulation loops.

Once the converter has shut down, it will attempt to restart

every 100 ms until the OVP condition is removed.

Over-Temperature Protection (OTP)

The converter will shut down under an over-temperature

condition to protect itself from overheating caused by opera-

tion outside the thermal derating curves, or operation in ab-

normal conditions such as system fan failure. After the con-

verter has cooled to a safe operating temperature, it will

automatically restart.

Safety Requirements

The converters meet North American and International

safety regulatory requirements per UL60950 and EN60950.

Basic Insulation is provided between input and output.

To comply with safety agencies requirements, an input line

fuse must be used external to the converter. A 3-A fuse is

recommended for use with this product.

Electromagnetic Compatibility (EMC)

EMC requirements must be met at the end-product system

level, as no specific standards dedicated to EMC character-

istics of board mounted component dc-dc converters exist.

However, di/dt tests its converters to several system level

standards, primary of which is the more stringent EN55022,

Information technology equipment - Radio disturbance char-

acteristics - Limits and methods of measurement.

With the addition of a simple external filter (see application

notes), all versions of the QD48S converters pass the re-

quirements of Class B conducted emissions per EN55022

and FCC, and meet at a minimum, Class A radiated emis-

sions per EN 55022 and Class B per FCC Title 47CFR, Part

15-J. Please contact di/dt Applications Engineering for de-

tails of this testing.

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Characterization

General Information

The converter has been characterized for many operational

aspects, to include thermal derating (maximum load current

as a function of ambient temperature and airflow) for vertical

and horizontal mounting, efficiency, start-up and shutdown

parameters, output ripple and noise, transient response to

load step-change, overload and short circuit.

The following pages contain specific plots or waveforms as-

sociated with the converter. Additional comments for specific

data are provided below.

Test Conditions

All data presented were taken with the converter soldered to

a test board, specifically a 0.060” thick printed wiring board

(PWB) with four layers. The top and bottom layers were not

metalized. The two inner layers, comprising two-ounce cop-

per, were used to provide traces for connectivity to the con-

verter.

The lack of metalization on the outer layers as well as the

limited thermal connection ensured that heat transfer from

the converter to the PWB was minimized. This provides a

worst-case but consistent scenario for thermal derating pur-

poses.

All measurements requiring airflow were made in di/dt’s ver-

tical and horizontal wind tunnel facilities using infrared (IR)

thermography and thermocouples for thermometry.

Ensuring that the components on the converter do not ex-

ceed their ratings is important to maintaining high reliability.

If one anticipates operating the converter at or close to the

maximum loads specified in the derating curves, it is prudent

to check actual operating temperatures in the application.

Thermographic imaging is preferable; if this capability is not

available, then thermocouples may be used. di/dt recom-

mends the use of AWG #40 gauge thermocouples to ensure

measurement accuracy. Careful routing of the thermocouple

leads will further minimize measurement error. Refer to Fig-

ure 34 for optimum measuring thermocouple location.

Thermal Derating

Available output power and load current vs. ambient tem-

perature and airflow rates are given in Figs. 8-11. Ambient

temperature was varied between 25°C and 85°C, with airflow

rates from 30 to 500 LFM (0.15 to 2.5 m/s), and vertical and

horizontal converter mounting.

For each set of conditions, the maximum load current was

defined as the lowest of:

(i) The output current at which either any FET junction tem-

perature did not exceed a maximum specified temperature

(120°C) as indicated by the thermographic image, or

(ii) The nominal rating of the converter (15 A on either out-

put).

During normal operation, derating curves with maximum FET

temperature less or equal to 120°C should not be exceeded.

Temperature on the PCB at the thermocouple location

shown in Fig. 34 should not exceed 118C in order to operate

inside the derating curves.

Efficiency

Efficiency vs. load current plots are shown in Figs. 12-17 for

ambient temperature of 25ºC, airflow rate of 300 LFM (1.5

m/s), both vertical and horizontal orientations, and input volt-

ages of 36 V, 48 V and 72 V, for different combinations of

the loads on outputs Vout1 and Vout2.

Start-up

Output voltage waveforms during the turn-on transient using

the ON/OFF pin, are shown without and with full rated load

currents (resistive load) in Figs. 18 and 19, respectively.

Ripple and Noise

Figure 30 shows the output voltage ripple waveform, meas-

ured at full rated load current on both outputs with a 1 µF

ceramic capacitor across both outputs. Note that all output

voltage waveforms are measured across a 1 µF ceramic ca-

pacitor.

The input reflected ripple current waveforms are obtained

using the test setup shown in Fig. 31. The corresponding

waveforms are shown in Figs. 32 and 33.

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Start-up Information (using negative ON/OFF)

Scenario #1: Initial Start-up From Bulk Supply

ON/OFF function enabled, converter started via application of VIN.

See Figure 5.

Time Comments

t0 ON/OFF pin is ON; system front end power is toggled

on, VIN to converter begins to rise.

t1 V

IN crosses Under-Voltage Lockout protection circuit

threshold; converter enabled.

t2 Converter begins to respond to turn-on command

(converter turn-on delay).

t3 Output voltage VOUT1 reaches 100% of nominal value.

t4 Output voltage VOUT2 reaches 100% of nominal value.

For this example, the total converter start-up time (t4- t1) is typically

3 ms.

Scenario #2: Initial Start-up Using ON/OFF Pin

With VIN previously powered, converter started via ON/OFF pin.

See Figure 6.

Time Comments

t0 V

INPUT at nominal value.

t1 Arbitrary time when ON/OFF pin is enabled (converter

enabled).

t2 End of converter turn-on delay.

t3 Output voltage VOUT1 reaches 100% of nominal value.

t4 Output voltage VOUT2 reaches 100% of nominal value.

For this example, the total converter start-up time (t4 - t1) is typi-

cally 3 ms.

Scenario #3: Turn-off and Restart Using ON/OFF Pin

With VIN previously powered, converter is disabled and then en-

abled via ON/OFF pin. See Figure 7.

Time Comments

t0 V

IN and VOUT are at nominal values; ON/OFF pin ON.

t1 ON/OFF pin arbitrarily disabled; converter outputs fall

to zero; turn-on inhibit delay period (100 ms typical) is

initiated, and ON/OFF pin action is internally inhibited.

t2 ON/OFF pin is externally re-enabled.

If (t2- t1) ≤ 100 ms, external action of ON/OFF pin

is locked out by start-up inhibit timer.

If (t2- t1) > 100 ms, ON/OFF pin action is internally

enabled.

t3 Turn-on inhibit delay period ends. If ON/OFF pin is ON,

converter begins turn-on; if off, converter awaits

ON/OFF pin ON signal; see Figure 6.

t4 End of converter turn-on delay.

t5 Output voltage VOUT1 reaches 100% of nominal value.

t6 Output voltage VOUT2 reaches 100% of nominal value.

For the condition, (t2 - t1) ≤ 100 ms, the total converter start-up

time (t6 - t2) is typically 103 ms. For (t2 - t1) > 100 ms, start-up time

will be typically 3 ms after release of ON/OFF pin.

VOUT1

t4

VOUT1

VOUT2

VIN

ON/OFF

STATE

VOUT2

t0t1t2t3

ON

OFF

Fig. 5: Start-up scenario #1.

VOUT1

VOUT2

VOUT1

VOUT2

t4t3

ON/OFF

STATE

t0t1t2

ON

OFF

VIN

Fig. 6: Start-up scenario #2.

t6

VOUT1

VOUT2VOUT2

VOUT1

ON/OFF

STATE OFF

ON

t0t2t1t5

VIN

t4t3

100 ms

Fig. 7: Start-up scenario #3.

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Ambient Temperature [°C]

20 30 40 50 60 70 80 90

Total Output Power [W]

0

10

20

30

40

50

500 LFM (2.5 m/s)

400 LFM (2.0 m/s)

300 LFM (1.5 m/s)

200 LFM (1.0 m/s)

100 LFM (0.5 m/s)

30 LFM (0.15 m/s)

Fig. 8: Available output power for balanced load current (Iout1

= Iout2) vs. ambient air temperature and airflow rates for con-

verter mounted vertically with Vin = 48 V, air flowing from pin 3

to pin 1 and maximum FET temperature ≤ 120°C.

Ambient Temperature [°C]

20 30 40 50 60 70 80 90

Load Current Iout1, Iout2 [Adc]

0.0

2.5

5.0

7.5

10.0

12.5

15.0

17.5

20.0

500 LFM (2.5 m/s)

400 LFM (2.0 m/s)

300 LFM (1.5 m/s)

200 LFM (1.0 m/s)

100 LFM (0.5 m/s)

30 LFM (0.15 m/s)

Fig. 10: Available balanced load current (Iout1 = Iout2) vs.

ambient air temperature and airflow rates for converter

mounted vertically with Vin = 48 V, air flowing from pin 3 to pin

1 and maximum FET temperature ≤ 120°C.

Ambient Temperature [°C]

20 30 40 50 60 70 80 90

Total Output Power [W]

0

10

20

30

40

50

500 LFM (2.5 m/s)

400 LFM (2.0 m/s)

300 LFM (1.5 m/s)

200 LFM (1.0 m/s)

100 LFM (0.5 m/s)

30 LFM (0.15 m/s)

Fig. 9: Available output power for balanced load current (Iout1

= Iout2) vs. ambient air temperature and airflow rates for con-

verter mounted horizontally with Vin = 48 V, air flowing from pin

3 to pin 1 and maximum FET temperature ≤ 120°C.

Ambient Temperature [°C]

20 30 40 50 60 70 80 90

Load Current Iout1, Iout2 [Adc]

0.0

2.5

5.0

7.5

10.0

12.5

15.0

17.5

20.0

500 LFM (2.5 m/s)

400 LFM (2.0 m/s)

300 LFM (1.5 m/s)

200 LFM (1.0 m/s)

100 LFM (0.5 m/s)

30 LFM (0.15 m/s)

Fig. 11: Available balanced load current (Iout1 = Iout2) vs.

ambient temperature and airflow rates for converter mounted

horizontally with Vin = 48 V, air flowing from pin 3 to pin 1 and

maximum FET temperature ≤ 120°C.

QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Data Sheet

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Load Current Iout1 [Adc]

0 2 4 6 8 10 12 14 16

Efficiency

0.65

0.70

0.75

0.80

0.85

0.90

0.95

72 V

48 V

36 V

Iout2 = 7.5 Adc

Fig. 12: Efficiency vs. load current Iout1 and input voltage for

converter mounted vertically with air flowing from pin 3 to pin 1

at a rate of 300 LFM (1.5 m/s), for Iout2 = 7.5 A and Ta = 25°C.

Load Current Iout2 [Adc]

0246810121416

Efficiency

0.65

0.70

0.75

0.80

0.85

0.90

0.95

72 V

48 V

36 V

Iout1 = 7.5 Adc

Fig. 14: Efficiency vs. load current Iout2 and input voltage for

converter mounted vertically with air flowing from pin 3 to pin 1

at a rate of 300 LFM (1.5 m/s), for Iout1 = 7.5 A and Ta = 25°C.

Load Current Iout1 [Adc]

0246810121416

Efficiency

0.65

0.70

0.75

0.80

0.85

0.90

0.95

72 V

48 V

36 V

Iout2 = 7.5 Adc

Fig. 13: Efficiency vs. load current Iout1 and input voltage for

converter mounted horizontally with air flowing from pin 3 to pin

1 at a rate of 300 LFM (1.5 m/s), for Iout2 = 7.5 A and Ta =

25°C.

Load Current Iout2 [Adc]

0246810121416

Efficiency

0.65

0.70

0.75

0.80

0.85

0.90

0.95

72 V

48 V

36 V

Iout1 = 7.5 Adc

Fig. 15: Efficiency vs. load current Iout2 and input voltage for

converter mounted horizontally with air flowing from pin 3 to pin

1 at a rate of 300 LFM (1.5 m/s), for Iout1 = 7.5 A and Ta =

25°C.

QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Data Sheet

QD48S012015 FDS Ver 2 05-01-03 USA Toll Free 866 WOW-didt Page 11 of 15

Load Current Iout1 = Iout2 [Adc]

0246810121416

Efficiency

0.65

0.70

0.75

0.80

0.85

0.90

0.95

72 V

48 V

36 V

Fig. 16: Efficiency vs. balanced load current (Iout1 = Iout2) and

input voltage for converter mounted vertically with air flowing

from pin 3 to pin 1 at a rate of 300 LFM (1.5 m/s) and Ta =

25°C.

Fig. 18: Turn-on transient waveforms at no load current and

Vin = 48 V, triggered via ON/OFF pin. Top trace: ON/OFF sig-

nal (5 V/div.). Bottom traces: Vout1 (blue, 0.5 V/div.), Vout2

(red, 0.5 V/div.). Time scale: 1 ms/div.

Load Current Iout1 = Iout2 [Adc]

0246810121416

Efficiency

0.65

0.70

0.75

0.80

0.85

0.90

0.95

72 V

48 V

36 V

Fig. 17: Efficiency vs. balanced load current (Iout1 = Iout2) and

input voltage for converter mounted horizontally with air flowing

from pin 3 to pin 1 at a rate of 300 LFM (1.5 m/s) and Ta =

25°C.

Fig. 19: Turn-on transient waveforms at full rated load current

(resistive) and Vin = 48 V, triggered via ON/OFF pin. Top trace:

ON/OFF signal (5 V/div.). Bottom traces: Vout1 (blue, 0.5

V/div.), Vout2 (red, 0.5 V/div.). Time scale: 1 ms/div.

.

QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Data Sheet

QD48S012015 FDS Ver 2 05-01-03 USA Toll Free 866 WOW-didt Page 12 of 15

Fig. 20: Output voltage response to Iout1 load current step-

change of 3.75 A (50%-75%-50%) at Iout2 = 7.5 A and Vin =

48 V. Ch1 = Vout1 (50 mV/div), Ch2 = Vout2 (50 mV/div), Ch3

= Iout1 (10 A/div.), Ch4 = Iout2 (10 A/div.). Current slew rate:

0.1 A/µs, Co = 10 µF tantalum + 1 µF ceramic. Time scale: 0.5

ms/div.

Fig. 22: Output voltage response to Iout1 load current step-

change of 3.75 A (50%-75%-50%) at Iout2 = 7.5 A and Vin =

48 V. Ch1 = Vout1 (100 mV/div), Ch2 = Vout2 (100 mV/div),

Ch3 = Iout1 (10 A/div.), Ch4 = Iout2 (10 A/div.). Current slew

rate: 5 A/µs, Co = 300 µF tantalum + 1 µF ceramic. Time scale:

0.5 ms/div.

Fig. 21: Output voltage response to Iout2 load current step-

change of 3.75 A (50%-75%-50%) at Iout1 = 7.5 A and Vin =

48 V. Ch1 = Vout1 (50 mV/div), Ch2 = Vout2 (50 mV/div), Ch3

= Iout1 (10 A/div.), Ch4 = Iout2 (10 A/div.). Current slew rate:

0.1 A/µs, Co = 10 µF tantalum + 1 µF ceramic. Time scale: 0.5

ms/div.

Fig. 23: Output voltage response to Iout2 load current step-

change of 3.75 A (50%-75%-50%) at Iout1 = 7.5 A and Vin =

48 V. Ch1 = Vout1 (100 mV/div), Ch2 = Vout2 (100 mV/div),

Ch3 = Iout1 (10 A/div.), Ch4 = Iout2 (10 A/div.). Current slew

rate: 5 A/µs, Co = 300 µF tantalum + 1 µF ceramic. Time scale:

0.5 ms/div.

QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Data Sheet

QD48S012015 FDS Ver 2 05-01-03 USA Toll Free 866 WOW-didt Page 13 of 15

Fig. 24: Output voltage response to both Iout1 and Iout2 (out

of phase) load current step-change of 3.75 A (50%-75%-50%)

at Vin = 48 V. Ch1 = Vout1 (50 mV/div), Ch2 = Vout2 (50

mV/div), Ch3 = Iout1 (10 A/div.), Ch4 = Iout2 (10 A/div.). Cur-

rent slew rate: 0.1 A/µs, Co = 10 µF tantalum + 1 µF ceramic.

Time scale: 1 ms/div.

5 101520

2.0

Iout [Adc]

Vout [Vdc]

0

1.5

1.0

0.5

Vout1

Fig. 26: Output voltage Vout1 vs. load current Iout1 showing

current limit point and converter shutdown point. When Vout1

is in current limit, Vout2 is not affected until Vout1 reaches the

shut-down threshold of 60% of its nominal value. Input voltage

has almost no effect on Vout1 current limit characteristic.

Fig. 25: Output voltage response to both Iout1 and Iout2 (out

of phase) load current step-change of 3.75 A (50%-75%-50%)

at Vin = 48 V. Ch1 = Vout1 (100 mV/div), Ch2 = Vout2 (100

mV/div), Ch3 = Iout1 (10 A/div.), Ch4 = Iout2 (10 A/div.). Cur-

rent slew rate: 5 A/µs, Co = 300 µF tantalum + 1 µF ceramic.

Time scale: 1 ms/div.

Note: The only cross-talk during transient is due to the com-

mon RETURN pin for both outputs.

5 101520

2.0

Iout [Adc]

Vout [Vdc]

0

1.5

1.0

0.5

Vout2

Fig. 27: Output voltage Vout2 vs. load current Iout2 showing

current limit point and converter shutdown point. When Vout2

is in current limit, Vout1 is not affected until Vout2 reaches the

shut-down threshold equal to Vout1 - 0.6 V. Input voltage has

almost no effect on Vout2 current limit characteristic.

QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Data Sheet

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Fig. 28: Load current Iout1 into a 10 mΩ short circuit on Vout1

during restart, with Vout2 open (no load), at Vin = 48 V. Ch2 =

Iout1 (20 A/div, 20 ms/div). ChB = Iout1 (20 A/div, 1 ms/div) is

an expansion of the on-time portion of Iout1.

Fig. 30: Output voltage ripple at full rated load current into a

resistive load on both outputs with Co = 1uF (ceramic) and Vin

= 48 V. Ch2 = Vout2, Ch1 = Vout1 (both 20 mV/div). Time

scale: 1 µs/div.

Fig. 29: Load current Iout2 into a 10 mΩ short circuit on Vout2

during restart, with Vout1 open (no load), at Vin = 48 V. Ch2 =

Iout2 (20 A/div, 20 ms/div). ChB = Iout2 (20 A/div, 1 ms/div) is

an expansion of the on-time portion of Iout2.

Vout1

Vsource

iSiC

1 µF

ceramic

capacitor

10 µH

source

inductance

DC/DC

Converter

33 µF

ESR <1

electrolytic

capacitor

ΩQTM Family

1 µF

ceramic

capacitor

Vout2

Fig. 31: Test Set-up for measuring input reflected ripple cur-

rents, ic and is.

QD48S012015 36-75 Vdc Input, 1.2 Vdc and 1.5 Vdc Output Data Sheet

QD48S012015 FDS Ver 2 05-01-03 USA Toll Free 866 WOW-didt Page 15 of 15

Fig. 32: Input reflected ripple current, ic (100 mA/div), meas-

ured at input terminals at full rated load current on both outputs

and Vin = 48 V. Refer to Fig. 31 for test setup. Time scale: 1

µs/div.

Fig. 33: Input reflected ripple current, is (10 mA/div), measured

through 10 µH at the source at full rated load current on both

outputs and Vin = 48 V. Refer to Fig. 31 for test setup. Time

scale: 1µs/div.

Fig. 34: Location of the thermocouple for thermal testing.

For more information please contact

di/dt, Inc.

1822 Aston Avenue •• Carlsbad, CA •• 92008 •• USA

USA Toll Free 866-WOW-didt (969-3438)

www.didt.com •• support@didt.com

The information and specifications contained in this data sheet are believed to be accurate and reliable at the time of publication. However, di/dt, Inc. assumes no responsibility for its use or for

any infringements of patents or other rights of third parties, which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of di/dt, Inc. Specifi-

cations are subject to change without notice.