Intel StrataFlash Wireless Memory System (LV18 SCSP) 1024-Mbit LVX Family with LPSDRAM Datasheet Product Features Device Memory Architecture -- Flash density: 128- and 256-Mbit -- LPSDRAM density: 128, 256 Mbit -- Top/Bottom parameter flash configuration Device Voltage -- Core: VCC = 1.8 V (typ) -- I/O: VCCQ = 1.8 V (typ) Device Common Performance -- Buffered EFP: 5s / Byte (Typ) per die -- Buffer Program: 7s / Byte (Typ) per die -- Concurrent Buffered EFP: 6.4 Mbps (4 dies) Device Common Architecture -- Asymmetrical blocking structure -- 16-KWord parameter blocks (Top or Bottom); 64-KWord main blocks -- Zero-latency block locking -- Absolute write protection with block lock down using F-WP# Device Packaging -- 103 active balls; 9 x 12 ball matrix -- Area: 9 x 11 mm -- Height: 1.4 mm SDRAM Architecture and Performance -- Clock rate: 105 MHz -- Four internal banks -- Burst Length: 1, 2, 4, 8 or full page Code Segment Flash Read Performance -- 85 ns initial access -- 25 ns async page -- 14 ns Sync Read (tCHQV) -- 54 MHz (Max) CLK Data Segment Flash Performance -- 170 ns initial access -- 55 ns async page read Code Segment Flash Architecture -- Hardware Read-While-Write/Erase -- Multiple 8-Mbit / 16-Mbit partition sizes -- 2-Kbit One-Time-Programmable (OTP) protection register Data Segment Flash Architecture -- Software Read-While-Write/Erase -- Single Partition Size Die Flash Software -- Intel FDI, Intel PSM, and Intel VFM -- Common Flash Interface (CFI) -- Basic/Extended Command Set Quality and Reliability -- Extended Temp: -25 C to +85 C -- Minimum 100 K flash block erase cycle -- 0.13 m ETOX VIII flash technology The Intel StrataFlash(R) Wireless Memory System (LV18 SCSP) with Low-Power SDRAM (LVX family) offers a variety of high performance code segment, large embedded data segment, and low-power SDRAM combinations in a common package on 0.13 m ETOXTM VIII flash technology. The LVX family integrates up to two code segment flash dies, two data segment flash dies, and two low-power SDRAM dies or one SRAM die in a common x16D Performance ballout. Notice: This document contains information on new products in production. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. 300945-003 April 2004 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel StrataFlash(R) Wireless Memory System (LV18 SCSP); 1024-Mbit LVX Family with Low-Power SDRAM may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright (c) Intel Corporation, 2004 *Other names and brands may be claimed as the property of others. 2 Datasheet Contents Contents 1.0 Introduction ...............................................................................................................................7 1.1 1.2 1.3 Nomenclature .......................................................................................................................7 Acronyms ..............................................................................................................................8 Conventions..........................................................................................................................9 2.0 Functional Overview ............................................................................................................11 2.1 2.2 2.3 2.4 Product Description ............................................................................................................11 Unique Product Features....................................................................................................13 Product Configurations and Memory Partitioning ...............................................................13 Memory Map .......................................................................................................................15 3.0 Package Information ............................................................................................................20 4.0 Ballout and Signal Descriptions......................................................................................21 4.1 4.2 Signal Ballout......................................................................................................................21 Signal Descriptions .............................................................................................................23 5.0 Maximum Ratings and Operating Conditions ...........................................................26 5.1 5.2 Absolute Maximum Ratings ................................................................................................26 Operating Conditions ..........................................................................................................27 6.0 Electrical Specifications .....................................................................................................28 6.1 DC Voltage and Current Characteristics.............................................................................28 7.0 AC Characteristics ................................................................................................................30 7.1 7.2 7.3 7.4 7.5 Device AC Test Conditions .................................................................................................30 Capacitance ........................................................................................................................30 Flash AC Read Operations.................................................................................................31 Flash AC Write Operations .................................................................................................31 LPSDRAM AC Characteristics............................................................................................31 8.0 Power and Reset Specifications .....................................................................................33 9.0 Design Guide: Operation Overview ...............................................................................33 9.1 Bus Operations ...................................................................................................................33 10.0 Flash Read Operations........................................................................................................39 11.0 Flash Program Operations ................................................................................................39 12.0 Flash Erase Operations ......................................................................................................39 13.0 Flash Suspend and Resume Operations .....................................................................39 14.0 Flash Block Locking and Unlocking Operations ......................................................39 15.0 Flash Protection Register Operations ..........................................................................39 16.0 Flash Configuration Operations ......................................................................................39 17.0 Flash Dual Operation Considerations...........................................................................40 Datasheet 3 Contents 18.0 LPSDRAM Operations ......................................................................................................... 40 18.1 18.2 18.3 18.4 LPSDRAM Power-up Sequence and Initialization .............................................................. 40 LPSDRAM Mode Register .................................................................................................. 40 Extended Mode Register .................................................................................................... 41 LPSDRAM Commands and Operations ............................................................................. 42 18.4.1 LPSDRAM No Operation / Device Deselect .......................................................... 42 18.4.1.1 Device Deselect (NOP).......................................................................... 42 18.4.1.2 No Operation (NOP) .............................................................................. 42 18.4.2 LPSDRAM Active................................................................................................... 42 18.4.3 LPSDRAM Read.................................................................................................... 43 18.4.4 LPSDRAM Write .................................................................................................... 43 18.4.5 LPSDRAM Power Down ........................................................................................ 44 18.4.6 LPSDRAM Deep Power Down .............................................................................. 44 18.4.7 LPSDRAM Clock Suspend .................................................................................... 44 18.4.8 LPSDRAM Precharge............................................................................................ 45 18.4.9 LPSDRAM Auto Precharge ................................................................................... 45 18.4.10 LPSDRAM Concurrent Auto Precharge................................................................. 45 18.4.11 LPSDRAM Burst Terminate................................................................................... 53 18.4.12 LPSDRAM Auto Refresh ....................................................................................... 53 18.4.13 LPSDRAM Self Refresh......................................................................................... 53 Appendix A Write State Machine.......................................................................................... 54 Appendix B Common Flash Interface ................................................................................ 54 Appendix C Flash Flowcharts ............................................................................................... 54 Appendix D Additional Information..................................................................................... 55 Appendix E Ordering Information ....................................................................................... 56 4 Datasheet Contents Revision History Datasheet Date Revision Description February, 2004 -001 Initial release. February, 2004 -002 Corrected information in the Memory Map table, code and data segments, bottom parameter. April, 2004 -003 Corrected errors in Tables 2 and 26. The package dimension of part RD48F4444LVYBB0 RD48F4444LVYTB0 now reads 11x11x1.4 instead of 9x11x1.4. 5 Contents 6 Datasheet LVX Family 1.0 Introduction This document provides preliminary information about the Intel StrataFlash(R) Wireless Memory System (LV18 SCSP) with Low-Power SDRAM (LVX family). This document describes the flash dies used in the code and large embedded data segments and the features, operations, and specifications within the subsystem. Also described in this document are the LPSDRAM characteristics and operations. The intent of this document is to provide information where these SCSP products differ from the Intel StrataFlash(R) Wireless Memory System (LV18) datasheet. Refer to the latest revision of the Intel StrataFlash(R) Wireless Memory System Datasheet (order number 253854) for flash product details not included in this document. 1.1 Nomenclature 1.8 V Core Voltage Range of 1.7 V - 1.95 V 1.8 V I/O Voltage Range of 1.7 V - 1.95 V Asserted Signal with logical voltage level VIL, or enabled Deasserted Signal with logical voltage level VIH, or disabled High-Z Tri-stated or High Impedance Low-Z Driven Non-Array Reads Flash reads which return flash Device Identifier, CFI Query, Protection Register and Status Register information Program An operation to Write data to the flash array Write Bus cycle operation at the inputs of the flash die, in which a command or data are sent to the flash array Block Group of cells, bits, bytes or words within the flash memory array that get erased with one erase instruction Parameter block Any 16-Kword flash array block. Main block Any 64-Kword flash array block. Top parameter Previously referred to as a top-boot device, a device with flash parameter partition located at the highest physical address of its memory map for processor system boot up. Bottom parameter Previously referred to as a bottom-boot device, a device with flash parameter partition located at the lowest physical address of its memory map for processor system boot up. Bottom-Top parameter SCSP device configuration of two flash dies in the same segment arranged with the parameter partitions located at the lowest and highest physical address of its memory map. Datasheet 7 LVX Family 1.2 8 Partition A group of flash blocks that shares common status register read state. Parameter partition A flash partition containing parameter and main blocks. Main partition A flash partition containing only main blocks. Die Individual physical flash or RAM die used in a SCSP memory subsystem device Segment A section of the SCSP memory subsystem divided for different operating characteristics. The SCSP memory subsystem has three segments: a code segment, a data segment, and an xRAM segment. Code segment A segment that contains one or two flash memory dies optimized for fast code or data reads. Each die features multi-partitions synchronous read-while-write or burst read-while-erase capability. Data segment A segment contains one or two flash memory dies optimized for large embedded data. Each die feature single-partition asynchronous read, write, and erase operations. xRAM segment A segment contains one or two xRAM memory dies. The xRAM combinations could include SRAM, PSRAM, or LPSDRAM. Subsystem A stacked memory integration concept made up of multiple memory dies arranged in code, data, and xRAM segments. Device A specific stacked flash + xRAM memory density configuration combination within the LVX product family. Acronyms APS Automatic Power Savings Buffered EFP Buffered Enhanced Factory Programming CFI Common Flash Interface CR Configuration Register CUI Command User Interface DU Don't Use ETOX EPROM Tunnel Oxide OTP One-Time Programmable PLR Protection Lock Register PR Protection Register RCR Read Configuration Register RFU Reserved for Future Use (all unused active signals in a package ballout) Datasheet LVX Family 1.3 RWE Read-While-Erase RWW Read-While-Write SCSP Stacked Chip Scale Package SR Status Register SRD Status Register Data WSM Write State Machine Conventions 0x Hexadecimal number prefix 0b Binary number prefix A5 Denotes one element of a signal group membership, in this case address bit 5. ADV# A name without a prefix denotes a global signal of the device; for example, Address Valid is global because there is no die specific reference. bit Binary unit, valid range [0, 1] byte Eight bits, valid range [0x00 - 0xFF] Clear Logical zero (0) DQ[15:0] Denotes a group of similarly named signals, such as data bus. F[3:1]-CE#, F[2:1]-OE# This is the method used to refer to more than one chip-enable or output enable at the same time. When each is referred to individually, the reference will be F1-CE# and F1-OE# (for die #1), F2-CE# and F2-OE# (for die #2), and F3-CE# and F3-OE#(for die #3). "F" denotes the flash specific signal and "CE#" is the root signal name of the flash die. Other notation includes: "S" to denote SRAM, "P" to denote PSRAM, "D" to denote LPSDRAM, and "R" to denote common RAM type signal names. Datasheet k (noun) 1000 (units) Kb 1024 bits KB 1024 bytes Kbit 1024 bits KByte 1024 bytes (8,192 bits) Kword 1024 words (16,384 bits) Mbit 1,048,576 bits MByte 1,048,576 bytes (8,388,608 bits) 9 LVX Family 10 MWord 1,048,576 words (16,777,216 bits) M (noun) 1 million Mb 1,048,576 bits MB 1,048,576 bytes Set Logical one (1) SR[4] Denotes an individual flash status register bit, in this case bit 4 of SR[7:0]. VCC Signal or voltage connection VCC Signal or voltage level Word Two bytes or sixteen bits, valid range [0x0000 - 0xFFFF] Datasheet LVX Family 2.0 Functional Overview This section provides an overview of the features and capabilities of the Intel StrataFlash(R) Wireless Memory System (LV18 family) with Low-Power SDRAM, or LVX family. 2.1 Product Description The Intel StrataFlash(R) Wireless Memory System (LVX) family incorporates flash dies used as code segment flash die and large embedded data segment flash die, along with LPSDRAM for a high performance, cost-effective high density solution. This stacked device utilizes the latest Intel StrataFlash(R) Wireless Memory System on 0.13 m ETOXTM VIII process technology. The code segment is a high performance, multi-partition, synchronous burst-mode Read-WhileWrite (RWW) or Read-While-Erase (RWE), while the large embedded data segment is a cost efficient, single partition, asynchronous memory die. The package for this device is available in a x16D Performance ballout, supporting flash-only or LPSDRAM stacked memory combinations. The Intel(R) SCSP package in a x16D Performance ballout with a 0.8 mm ball pitch, 9 x 12 active ball matrix supports a memory subsystem up to 105 MHz on a x16-bit bus width. See Figure 1, "LVX Device Block Diagram" on page 11 for device block diagram. Figure 1. LVX Device Block Diagram LVX Family Flash (Code/Data) Segment F1-CE# F-WP1# F2-CE# Flash Die #1 (128- or 256-Mbit) Flash Die #2 (128- or 256-Mbit) F-CLK ADV# F-VCC F-WP2# WAIT OE# F3-CE# F-VPP Flash Die #3 (128- or 256-Mbit) Flash Die #4 (128- or 256-Mbit) DQ[15:0] D-DM1 / R-UB# D-DM0 / R-LB# S-CS1# S-CS2 S-VCC Datasheet F4-CE# VCCQ VSS WE# A[MAX:MIN] F-RST# xRAM Segment LPSDRAM Die #1 (128/256-Mbit) SRAM Die #1 (8-Mbit) LPSDRAM Die #2 (128/256-Mbit) R1-CS# R2-CS# D-BA[1:0] D-CAS# D-RAS# R-CLK D-CKE R-VCC 11 LVX Family Table 1. Flash Die CE# (Fx-CE#) Pre-Assignment Definition for LVX Device Family Stacked Combo: Flash Die #1 Flash Die #2 Flash Die #3 Flash Die #4 Code + Data F1-CE# (Code) F2-CE# (Data) N/A N/A Code + Code + Data F1-CE# (Code) F2-CE# (Code) F3-CE# (Data) N/A Code + Data + Data F1-CE# (Code) F2-CE# (Data F3-CE# (Data) N/A Code + Code + Data + Data F1-CE# (Code) F2-CE# (Code) F3-CE# (Data) F4-CE# (Data) The LVX family consists of a 1.8 V flash core device (F-VCC) with 1.8 V and 3.0 V I/O options. The device is available with at least one flash die per code segment and/or one flash die per data segment. However, the device has a maximum of two flash dies per code or data segments. See Table 1, "Flash Die CE# (Fx-CE#) Pre-Assignment Definition for LVX Device Family" on page 12 for possible combinations. Designed for low-voltage systems, the LVX supports read operations with F-VCC at 1.8 V, and erase and program operations with F-VPP at 1.8 V. Buffered Enhanced Factory Programming (Buffered EFP) provides the fastest flash array programming performance, with elevated F-VPP at 9.0 V to increase factory throughput. With F-VPP at 1.8 V, F-VCC and F-VCC can be tied together for a simple, ultra-low-power design. In addition to voltage flexibility, a dedicated F-VPP connection provides complete data protection when F-VPP VPPLK. The Intel StrataFlash(R) Wireless Memory System provides data security through its individual zerolatency block lock capability. Each memory block can be unlocked, locked, or locked-down by hardware or software control. Individualized F-CE# control allows the user to manage which flash die is asserted, furthering the flexibility of power management while controlling data integrity per segment with F-WP#. The F[2:1]-OE# in LVX products with a x16D Performance ballout ballout are common internally. Important: The Intel(R) Ultra-Thin Stacked Chip Scale Package (Intel(R) UT-SCSP) programming socket technology is backward compatible for Intel SCSP packages. This eliminates the need to purchase separate programming hardware for each type of SCSP and simplifies SCSP platform migration across various SCSP technologies. Table 2. LVX Family with Low-Power SDRAM Product Matrix Flash Component RAM Component Package Size (mm) Package Type 256L18 + 256L18 + 256V18 + 256V18 -- 11x11x1.4 SCSP 256L18 + 256L18 + 256V18 12 128-Mbit SDRAM 9x11x1.4 SCSP Device Name (Bottom and/or Top Configuration) RD48F4444LVYBB0 RD48F4444LVYTB0 RD58F0012LVYBB0 RD58F0012LVYTB0 Datasheet LVX Family 2.2 Unique Product Features The code segment of the LVX includes the following enhanced features unless specifically noted otherwise: * 64 unique (Intel pre-programmed) identifier bits and 2,112 user-programmable OTP bits for each code segment flash die. * Traditional write, erase, and burst-mode read capabilities of Intel(R) Wireless Flash Memory (W18). * Simultaneous RWW/RWE operations, enabling a burst read operation in one partition with simultaneous program or erase operations in other partitions. * Burst-read across partition boundaries, but not across segment dies within the subsystem. * User application code responsible for ensuring that burst-mode reads do not cross into a partition that is in program or erase mode. The embedded data segment includes the following features unless specifically noted otherwise: * High density offerings of up to 512 Mbits are designated specifically for large embedded data. * Single partition asynchronous page-mode read operation, allowing for a cost-effective ideal storage format. * Read-while-write or read-while-erase operations can be accomplished with software through program suspend and erase suspend operations. 2.3 Product Configurations and Memory Partitioning The first flash die, by default is the first code segment flash die, which is a fast, execute-in-place (XIP) solution that is ideally suited toward an instruction fetch application. This portion is the user selected parameter configuration option, where the density can be made up of 128-Mbit dies or 256-Mbit dies, each containing one parameter partition and several main partitions.The parameter partition contains four 16-Kword parameter blocks and seven 64-Kword main blocks; all main partitions consist of eight 64-Kword main blocks. The large embedded data die segment is a single partition asynchronous page-mode read device that is available in variations of 128-Mbit dies or 256-Mbit dies. The single partition is made up of four 16-Kword parameter blocks and 64-Kword main blocks. The data segment flash die parameter configuration will always be the opposite of the code segment flash die parameter configuration. See Table 3, "LV Flash Code and Data Die Stacked Configuration" on page 15 for examples of configuration options. Users have the choice of selecting either a top or a bottom parameter configuration for the code die segment. Depending on the choice of configuration, the data die(s) in the LVX device will be parametrically opposed. For instance, if the user selects top parameter configuration for the code die, the data die in the package will be configured as bottom parameter configuration, and viceversa. This ensures the largest number of contiguous main block addresses for software efficiency. The xRAM segment can consist of up to two low-power SDRAM (LPSDRAM) dies. The LPSDRAM can be either a 128-Mbit or a 256-Mbit die. For the code segment, partition configurations are as follows: * 128-Mbit flash die partitions are 8 Mbits. * 256-Mbit flash die partitions are 16 Mbits. * Minimum code + data density combination is 384 Mbits. Datasheet 13 LVX Family Figure 2. Top Parameter Configurations Top Parameter Configuration Stacked Convention Parameter Blocks Code (Top) Code (Top) Code (Top) Code (Top) Data (Bottom) Data (Top) Code (Top) Code (Bottom) 1 Code + 1 Data Data (Bottom) Data (Bottom) Data (Top) 1 Code + 2 Data 2 Code + 1 Data Data (Bottom) Main Blocks Parameter Blocks 2 Code + 2 Data Figure 3. Bottom Parameter Configurations Bottom Parameter Configuration Stacked Convention Data (Top) Data (Top) Data (Top) Data (Bottom) Data (Top) Data (Bottom) Code (Bottom) Code (Top) Code (Bottom) Code (Bottom) Code (Bottom) Code (Bottom) 1 Code + 1 Data 1 Code + 2 Data 2 Code + 1 Data 2 Code + 2 Data Parameter Blocks Main Blocks Parameter Blocks 14 Datasheet LVX Family Table 3. LV Flash Code and Data Die Stacked Configuration Top and Bottom Parameter Stacked Configuration Code Segment Die Stack Configuration Data Segment 1st Flash Code Die (user selected) 2nd Flash Code Die 1st Flash Data Die 2nd Flash Data Die Code + Data Top NA Bottom NA Code + Data + Data Top NA Top Bottom Code + Code + Data Top Top Bottom NA Code + Code + Data + Data Top Bottom Top Bottom Code + Data Bottom NA Top NA Top Code + Data + Data Bottom NA Bottom Top Code + Code + Data Bottom Bottom Top NA Code + Code + Data + Data Bottom Top Bottom Top Bottom 2.4 Memory Map The LVX family is available in several density and parameter configurations. The memory map is based on the stacking of individual 128- and 256-Mbit flash die density options. The memory map shows individual flash die configurations and block/partition allocations. Refer to the following tables for further information: * Table 4, "Two Flash Die (Top Parameter) SCSP Memory Map and Partitioning" on page 16 * Table 5, "Two Flash Die (Bottom Parameter) SCSP Memory Map and Partitioning" on page 17 * Table 6, "Three Flash Die (Top Parameter) SCSP Memory Map and Partitioning" on page 18 * Table 7, "Three Flash Die (Bottom Parameter) SCSP Memory Map and Partitioning" on page 19 Datasheet 15 LVX Family Table 4. Flash Die# Two Flash Die (Top Parameter) SCSP Memory Map and Partitioning Die Stack Config Partitioning Block Size Partition Size (KW) (Mbit) Blk# 16 FFC000-FFFFFF ... ... ... 127 7F0000-7F3FFF 255 FF0000-FF3FFF 7E0000-7EFFFF 254 FE0000-FEFFFF 780000-78FFFF 119 770000-77FFFF 16 ... 120 ... 8 ... ... 64 240 F00000-FFFFFF 239 EF0000-EFFFFF ... ... ... ... 64 64 400000-4FFFFF 128 800000-80FFFF 64 63 3F0000-3FFFFF 127 F70000-F7FFFF ... ... ... ... 64 0 000000-00FFFF 0 000000-00FFFF 64 130 7F0000-7FFFFF 258 FF0000-FFFFFF 67 400000-40FFFF 131 800000-80FFFF 64 66 3F0000-3FFFFF 130 7F0000-7FFFFF ... 010000-01FFFF 4 010000-01FFFF 3 00C000-00FFFF 3 00C000-00FFFF ... ... ... ... 19 100000-10FFFF 18 0F0000-0FFFFF 16 0 000000-003FFF 0 000000-003FFF ... ... 4 16 256 ... 64 ... 255x64 Kword Main Blocks (256 Mb) ... 080000-08FFFF 070000-07FFFF ... 64 128 11 ... ... ... 127x64 Kword Main Blocks (128 Mb) 64 10 ... ... ... ... 64 ... 16 (Bottom Parameter) 258 ... Data 2 4x16 Kword Parameter Blocks Address Range ... Single Partition 7FC000-7FFFFF 256-Mbit Flash Blk# 126 ... Main Partitions (Partition 8 to 15) Partition Size (Mbit) 64 64 (Top Parameter) Main Partitions (Partition 1 to 7) Address Range 16 ... Code 1 ... (Partition 0) ... Parameter Partition 130 128-Mbit Flash Datasheet LVX Family Table 5. Flash Die# Two Flash Die (Bottom Parameter) SCSP Memory Map and Partitioning Die Stack Config Partitioning Partition Block Size Size (KW) (Mbit) 16 256-Mbit Flash Blk# Address Range 258 FFC000-FFFFFF ... 7F0000-7F3FFF 255 FF0000-FF3FFF 7E0000-7EFFFF 254 FE0000-FEFFFF 770000-77FFFF ... ... 780000-78FFFF 119 ... ... 120 ... ... 127 126 127x64 Kword Main Blocks (128 Mb) 64 255x64 Kword Main Blocks (256 Mb) 64 64 400000-4FFFFF 128 800000-80FFFF 64 63 3F0000-3FFFFF 127 F70000-F7FFFF 64 8 16 240 F00000-FFFFFF 239 EF0000-EFFFFF ... ... ... Main Partitions (Partitions 8 to 15) 64 130 7F0000-7FFFFF 258 FF0000-FFFFFF ... ... ... ... 64 67 400000-40FFFF 131 800000-80FFFF Main Partitions (Partitions 1 to 7) 64 66 3F0000-3FFFFF 130 7F0000-7FFFFF 64 11 080000-08FFFF 10 070000-07FFFF 256 19 100000-10FFFF 18 0F0000-0FFFFF 010000-01FFFF 4 010000-01FFFF 3 00C000-00FFFF 3 00C000-00FFFF ... ... ... ... 4 16 ... ... ... 64 ... ... ... Parameter Partition (Partition 0) 128 ... 64 ... ... 000000-00FFFF ... ... 0 ... ... 000000-00FFFF ... ... 0 ... ... 64 (Bottom Parameter) Datasheet 7FC000-7FFFFF Partition Size (Mbit) 64 ... Code 1 130 ... (Top Parameter) Address Range 16 ... Data 2 4x16 Kword Parameter Blocks ... Single Partition 128-Mbit Flash Blk# 16 0 000000-00FFFF 0 000000-00FFFF 17 LVX Family Table 6. Flash Die# Three Flash Die (Top Parameter) SCSP Memory Map and Partitioning Die Stack Config Partitioning Block Partition Size Size (KW) (Mbit) Blk# 16 130 7F0000-7F3FFF 255 FF0000-FF3FFF 7E0000-7EFFFF 254 FE0000-FEFFFF 780000-78FFFF 119 770000-77FFFF 16 ... 120 ... ... 8 240 F00000-FFFFFF 239 EF0000-EFFFFF ... ... ... ... ... Main Partitions (Partition 1 to 7) 64 ... 64 ... ... 127 ... 64 64 400000-4FFFFF 128 800000-80FFFF 64 63 3F0000-3FFFFF 127 F70000-F7FFFF ... ... ... ... ... 64 0 000000-00FFFF 0 000000-00FFFF 16 130 7FC000-7FFFFF 258 FFC000-FFFFFF ... Parameter Partition 16 127 7F0000-7F3FFF 255 FF0000-FF3FFF (Partition 0) 64 126 7E0000-7EFFFF 254 FE0000-FEFFFF 780000-78FFFF 119 770000-77FFFF 16 ... 120 ... ... 8 240 F00000-FFFFFF 239 EF0000-EFFFFF ... ... ... ... ... Main Partitions (Partition 1 to 7) 64 ... ... 64 ... ... ... ... 64 64 400000-4FFFFF 128 800000-80FFFF 64 63 3F0000-3FFFFF 127 F70000-F7FFFF ... ... ... ... ... 64 0 000000-00FFFF 0 000000-00FFFF 64 130 7F0000-7FFFFF 258 FF0000-FFFFFF ... ... ... ... ... 64 67 400000-40FFFF 131 800000-80FFFF 64 66 3F0000-3FFFFF 130 7F0000-7FFFFF 64 255x64 Kword Main Blocks (256 Mb) 64 4 010000-01FFFF 4 010000-01FFFF 16 3 00C000-00FFFF 3 00C000-00FFFF ... ... ... ... ... 16 0 000000-003FFF 0 000000-003FFF 64 128 11 080000-08FFFF 10 070000-07FFFF 256 ... 127x64 Kword Main Blocks (128 Mb) ... (Bottom Parameter) ... 4x16 Kword Parameter Blocks ... Data ... 19 100000-10FFFF 18 0F0000-0FFFFF ... ... ... ... ... 18 FFC000-FFFFFF 126 Single Partition Note: 258 64 Main Partitions (Partition 8 to 15) 3 Address Range 16 Code (Top Parameter) 7FC000-7FFFFF 256-Mbit Flash Blk# (Partition 0) Main Partitions (Partition 8 to 15) 2 Partition Size (Mbit) ... ... ... (Top Parameter) Address Range Parameter Partition Code 1 128-Mbit Flash Only 128-Mbit and 256-Mbit flash densities are used in a three flash die SCSP combination. Datasheet LVX Family Table 7. Flash Die# Three Flash Die (Bottom Parameter) SCSP Memory Map and Partitioning Die Stack Config Partitioning Block Size (KW) Partition Size (Mbit) 16 258 FFC000-FFFFFF ... ... ... ... 127 7F0000-7F3FFF 255 FF0000-FF3FFF 64 126 7E0000-7EFFFF 254 FE0000-FEFFFF ... ... ... ... 64 64 400000-4FFFFF 128 800000-80FFFF 64 63 3F0000-3FFFFF 127 F70000-F7FFFF ... ... ... ... ... 0 000000-00FFFF 0 000000-00FFFF 64 130 7F0000-7FFFFF 258 FF0000-FFFFFF ... ... ... ... 64 67 400000-40FFFF 131 800000-80FFFF 64 66 3F0000-3FFFFF 130 7F0000-7FFFFF 100000-10FFFF 18 0F0000-0FFFFF ... 19 070000-07FFFF ... ... ... 080000-08FFFF 10 ... ... 11 64 ... ... 64 64 4 010000-01FFFF 4 010000-01FFFF 16 3 00C000-00FFFF 3 00C000-00FFFF ... ... ... ... 16 0 000000-003FFF 0 000000-003FFF 64 130 7F0000-7FFFFF 258 FF0000-FFFFFF ... ... ... ... 64 67 400000-40FFFF 131 800000-80FFFF 64 66 3F0000-3FFFFF 130 7F0000-7FFFFF ... 4 010000-01FFFF 4 010000-01FFFF 16 3 00C000-00FFFF 3 00C000-00FFFF ... ... ... 64 ... 0F0000-0FFFFF ... ... 100000-10FFFF 18 ... 19 070000-07FFFF ... ... 080000-08FFFF 10 ... ... 11 64 ... 64 ... ... Parameter Partition (Partition 0) EF0000-EFFFFF ... (Bottom Parameter) F00000-FFFFFF 239 ... Main Partitions (Partition 1 to 7) 240 ... Code 16 64 ... Main Partitions (Partition 8 to 15) 770000-77FFFF ... (Bottom Parameter) 780000-78FFFF 119 ... Main Partitions (Partition 1 to 7) 120 ... 255x64 Kword Main Blocks (256 Mb) 8 ... 64 64 ... 127x64 Kword Main Blocks (128 Mb) ... (Top Parameter) Parameter Partition (Partition 0) Note: Address Range 4x16 Kword Parameter Blocks Code 1 7FC000-7FFFFF 256-Mbit Flash Blk# Data Main Partitions (Partition 8 to 15) 2 130 Partition Size (Mbit) 16 ... 3 Address Range ... Single Partition 128-Mbit Flash Blk# 16 0 000000-003FFF 0 000000-003FFF Only 128-Mbit and 256-Mbit flash densities are used in a three flash die SCSP combination. Datasheet 19 LVX Family 3.0 Package Information The LVX family is available in a standard SCSP x16D Performance ballout package, with its dimensions shown in Figure 4, "Mechanical Specifications for LVX Family. Figure 4. Mechanical Specifications for LVX Family S1 Pin 1 Corner 1 2 3 4 5 6 7 8 9 S2 A B C D E D F G H J K e L M b E SCSP Top View - Ball Side Down A2 A1 A Y Note: Drawing not to scale. Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length Package Body Width Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball Distance Along E Corner to Ball Distance Along D 20 Symbol A A1 A2 b D E e N Y S1 S2 Min Nom Max 1.4 0.200 0.325 10.90 8.90 1.200 1.000 Notes Min Nom Max 0.0551 0.0079 1.070 0.375 11.00 9.00 0.800 103 1.300 1.100 0.425 11.10 9.10 0.0128 0.4291 0.3504 0.100 1.400 1.200 0.0472 0.0394 0.0421 0.0148 0.4331 0.3543 0.0315 103 0.0512 0.0433 0.0167 0.4370 0.3583 0.0039 0.0551 0.0472 Datasheet LVX Family 4.0 Ballout and Signal Descriptions 4.1 Signal Ballout The Intel StrataFlash(R) Wireless Memory System family is available in a x16D Performance ballout, shown in Figure 5, "x16D Performance Signal Ballout for LVX Device Family" The single package ballout is ideal for space-constrained board applications where density upgrades without PCB redesign is preferred. The user is responsible to adapt for density upgrade flexibility in the PCB design. Datasheet 21 LVX Family Figure 5. x16D Performance Signal Ballout for LVX Device Family Pin 1 1 2 3 4 5 6 7 8 9 A DU A5 A7 A8 A20 A24 A25 A26 DU A B A3 A4 A6 A18 A19 RFU A23 A27 A17 B C A2 VSS VSS VSS R-VCC VSS VSS VSS A16 C D A1 S-VCC R-VCC F-VCC ADV# F-VCC R-VCC RFU A15 D E F-WP1# WE# R2-CS# Depop F4-CE# / A28 A22 A11 A14 E F F-WP2# R1-CS# D-CAS# D-RAS# S-CS1# A21 A10 A13 F Depop (RFUs) G RFU F2-CE# F1-CE# D-BA0 D-CKE F-RST# A9 A12 G H RFU S-CS2 F3-CE# D-BA1 RFU OE# D-DM1 / R-UB# D-DM0 / R-LB# H J F-VPP VCCQ VCCQ F-VCC R-CLK F-VCC VCCQ VCCQ WAIT J K DQ2 VSS VSS VSS F-CLK VSS VSS VSS DQ13 K L DQ1 DQ3 DQ5 DQ6 DQ7 DQ9 DQ11 DQ12 DQ14 L M DU DQ0 RFU DQ4 DQ8 DQ10 RFU DQ15 DU M 1 2 3 4 5 6 7 8 9 Top View - Ball Side Down Legend: 22 Active Balls De-Populated Balls Reserved for Future Use Do Not Use Datasheet LVX Family 4.2 Signal Descriptions Table 8 describes the active signals used on the LVX family. Table 8. Symbol Signal Descriptions (Sheet 1 of 3) Type Name and Function Notes ADDRESS: Global device signals. Share inputs for all memory die addresses during read and write operations. LPSDRAM Address inputs also provide the op-code during a Mode Register Set or Special Mode Register Set command. * 256-Mbit die : AMAX = A24 * 128-Mbit die : AMAX = A23 * 64-Mbit die : AMAX = A22 A[MAX:1] Input * 32-Mbit die : AMAX = A21 1,2 * 8-Mbit die : AMAX = A19 * A[13:1] are the row and A[9:1] are the column addresses for 256-Mbit LPSDRAM * A[12:1] are the row and A[9:1] are the column addresses for 128-Mbit LPSDRAM * A11 defines the Auto Precharge. During a LPSDRAM Precharge command, A11 is sampled to determine if all banks are to be precharged (A11 = high). DQ[15:0] Input/ Output DATA INPUT/OUTPUTS: Global device signals. Inputs data and commands during write cycles, outputs data during read cycles. Data signals float when the device or its output are deselected. Data are internally latched during writes on the device. ADDRESS VALID: Low-true input. (For stacked combinations without Synchronous PSRAM, ADV# is a flash-specific input.) ADV# Input During synchronous flash read operations, addresses are latched on the rising edge of ADV#, or on the next valid CLK edge, whichever occurs first. In asynchronous flash read operation, addresses are latched on the rising edge ADV#, or are continuously flow-through when ADV# is kept asserted. FLASH CHIP ENABLE: Low-true input. F[4:1]-CE# low selects the associated flash memory die. F[4:1]-CE# high deselects the associated flash die. When deasserted, the associated flash die is deselected, power is reduced to standby levels, data and WAIT outputs are placed in high-Z state. F[4:1]-CE# Input * F1-CE# is dedicated as flash Code die #1. 3 * F[4:2]-CE# controls any subsequent flash die based on the user ordered SCSP flash type combination. * Any unused F-CE# should be pulled high to F-VCC through a 1K-ohm resistor for future design flexibility. DEVICE CLOCK: Synchronizes the selected memory die to the system's bus clock in synchronous operations. F-CLK, R-CLK Performance ballout: Input * F-CLK is a flash signal. Synchronizes the flash die to the system's flash bus frequency in synchronous operations. * R-CLK is a LPSDRAM input signal. Synchronizes the LPSDRAM die to the system's memory bus clock. LPSDRAM is sampled on the positive edge of R-CLK. OUTPUT ENABLE: Global device signal. Low-true input. OE# Input F-RST# Input OE# low enables the output drivers of the selected die. OE# high places the output drivers of the selected die in high-Z. FLASH RESET: Flash specific signal. Low-true input. Datasheet F-RST# low resets internal operations and inhibits write operations. F-RST# high enables normal operation. Exit from reset places the flash device in asynchronous read array mode. 23 LVX Family Table 8. Symbol Signal Descriptions (Sheet 2 of 3) Type Name and Function Notes DEVICE WAIT: Selectable high-true or low-true output. (For stacked combinations without Synchronous PSRAM, WAIT is a flash specific input.) WAIT Output During synchronous-burst reads (array or non-array), WAIT-asserted indicates invalid read data. During asynchronous-page reads and writes, WAIT is deasserted. Wait is High-Z whenever F-CE# or F-OE# / OE# is deasserted. WRITE ENABLE: Global device signal. Low-true input. WE# Input WE# low selects the associated memory die for write operation. WE# high deselect the associated memory die, data are placed in high-Z state. With LPSDRAM operation, WE# is latched on the positive clock edge in conjunction with the D-RAS# and D-CAS# signals. The WE# input is used to select the Bank Activate or Precharge command and Read or Write command. WRITE PROTECT: Low-true input. F-WP[2:1]# Input F-WP# controls the lock-down protection mechanism of the selected flash die. When low, FWP# enables the lock-down mechanism where locked down blocks cannot be unlocked with software commands. When high, F-WP# disables the lock-down mechanism, allowing locked down blocks to be unlocked with software commands. F-WP1# controls the code segment flash die #1, while F-WP2# controls subsequent code or data segment flash dies. LPSDRAM Clock Enable: High-true input * If D-CKE goes low synchronously with clock, the internal clock is suspended from the next clock cycle. * The state of the outputs and the burst address is halted. D-CKE Input * When all banks are in the idle state, D-CKE is high, the LPDRAM enters into Power Down and Self Refresh modes. * D-CKE is synchronous except after the device enters Power Down and Self Refresh modes, where D-CKE becomes asynchronous until exiting the same mode. The input buffers, including R-CLK, are disabled during Power Down and Self Refresh modes, providing low standby power. D-BA[1:0] Input LPSDRAM Bank Select: D-BA0 and D-BA1 defines to which bank the Bank Activate, Read, Write, or Bank Precharge command is being applied. The bank address D-BA0 and D-BA1 is used latched in mode register set. LPSDRAM Row Address Strobe: Low-true input. * The D-RAS# signal defines the operation commands, with the D-CAS# and WE# signals. D-RAS# Input * The D-RAS# is latched at the rising edges of R-CLK. When D-RAS# and Dx-CS# / RxCS# are asserted and D-CAS# is deasserted, either the Bank Activate command or the Precharge command is selected by the WE# signal. * WE# is deasserted, the Bank Activate command is selected and the bank designated by D-BA[1:0] is turned on to the active state. LPSDRAM Column Address Strobe: Low-true input. D-CAS# Input * D-CAS# signal defines the operation commands in conjunction with the D-RAS# and WE# signals and is latched at the rising edges of R-CLK. * D-RAS# is deasserted and Dx-CS# / Rx-CS# is asserted, the column access is started by asserting D-CAS#. Read or Write command then is selected by asserting WE# low or high. RAM Chip Select: Low-true input. x16D Performance ballout: * R[2:1]-CS# R[2:1]-CS# Input R[2:1]-CS# low selects the associated LPSDRAM memory die. All commands are masked when R[2:1]-CS# high. R[2:1]-CS# provides for external bank selection on systems with multiple banks. It is considered part of the command code. * R1-CS# controls LPSDRAM die #1. * R2-CS# controls LPSDRAM die #2. 24 Datasheet LVX Family Table 8. Symbol Signal Descriptions (Sheet 3 of 3) Type Name and Function Notes LPSDRAM Data Input/Output Mask: Data Input Mask. D-DM[1:0] Input * D-DM[1:0] are byte selects. Input data is masked when D-DM[1:0] are sampled high during a write cycle. D-DM1 masks DQ[15-8], and D-DM0 masks DQ[7-0]. 4 * The D-DM[1:0] latency for Read is 2 Clocks and for Write is 0 Clocks. SRAM CHIP SELECTS: SRAM specific signal. Low-true input. S-CS1# S-CS2 Input When both SRAM chip selects are asserted, SRAM internal control logic, input buffers, decoders, and sense amplifiers are active. When either or both SRAM chip selects are deasserted (S-CS1# = VIH and/or S-CS2 = VIH), the SRAM is deselected and its power is reduced to standby levels. S-CS1# and S-CS2 are available on stacked combinations with SRAM die, and are RFU on stacked combinations without SRAM die. SRAM UPPER/ LOWER BYTE ENABLES: Low - true inputs. R-UB# R-LB# Input * During SRAM read and write cycles, R-UB# low enables the SRAM high-order byte on DQ[15:8], and R-LB# low enables the SRAM low-order byte on DQ[7:0]. 3,4 R-UB# and R-LB# are available on stacked combinations with SRAM die, and are RFUs on stacked combinations without SRAM die. FLASH ERASE/ PROGRAM VOLTAGE LEVEL: Flash specific signal. F-VPP Power F-VCC Power VCCQ Power Valid F-VPP voltage on this ball allows block erase or program functions. Flash memory array contents cannot be altered when F-VPP VPPLK. Block erase and program at invalid FVPP voltage should not be attempted. FLASH CORE VOLTAGE LEVEL: Flash specific signals. Flash core source voltage. Flash operations are inhibited when F-VCC VLKO. Operations at invalid F-VCC voltage should not be attempted. OUTPUT VOLTAGE LEVEL: Global device signals. Device output-driver source voltage. This balls can be tied directly to the respective memory type x-VCC if operating within its xVCC range. RAM POWER SUPPLY: Supplies power to the RAM dies. D-VCC, R-VCC Performance ballout: Power * D-VCC supplies power for LPSDRAM operation. x16D Performance ballout: * R-VCC supplies power for xRAM operation. SRAM POWER SUPPLY: Supplies power to the SRAM die. S-VCC Power S-VCC is available on stacked combinations with SRAM die, and is RFU on stacked combinations without SRAM die. VSS Power GROUND: Connect to system ground. Do not float any VSS connection. DU - DO NOT USE: This ball must be left floating. This ball should not be connected to any power supplies, signals, or other balls. RFU - RESERVED for FUTURE USE: Reserved by Intel for future device functionality and enhancement. NOTE: 1. All unused signals or RFUs should be held either to a static VIL or VIH for future design flexibility and migrations. 2. A1 is the lowest order x16 address. 3. F4-CE# is a shared signal with A28 for the 103-Active Ball High Performance DRAM package. 4. D-DM[1:0] are shared signals with R-UB# and R-LB# respectively. Datasheet 25 LVX Family 5.0 Maximum Ratings and Operating Conditions 5.1 Absolute Maximum Ratings Warning: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. NOTICE: This document contains information available at the time of its release. The specifications are subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Table 9. Absolute Maximum Ratings Parameter Min Max Unit Temperature under Bias Expanded -25 +85 C Storage Temperature -55 +125 C Voltage On Any Signal (except F-VCC, F-VPP, R-VCC and VCCQ) -0.2 +2.1 V 1 F-VCC Voltage -0.2 +2.50 V 1 VCCQ, R-VCC Voltage -0.2 +2.45 V 1 F-VPP Voltage -0.2 +10.0 V 1,2,3 - 50 mA ISH Output Short Circuit Current Notes 4 NOTES: 1. Voltage is referenced to VSS. 2. During power transitions, minimum DC voltage may undershoot to -2.0 V for periods < 20 ns; maximum DC voltage may overshoot to VCC (operating max) + 2.0 V for periods < 20 ns. 3. During power transitions, minimum DC voltage may undershoot to -1.0 V for periods < 20 ns; maximum DC voltage may overshoot to VCCQ (operating max) + 1.0 V for periods < 20 ns. 4. During power transitions, minimum DC voltage may undershoot to -2.0 V for periods < 20 ns; maximum DC voltage may overshoot to VPP2 (operating max) + 2.0 V for periods < 20 ns. 5. F-VPP can be VPP2 for 1000 cycles on main blocks, 2500 cycles on parameter blocks. 6. Output shorted for no more than one second. No more than one output shorted at a time. 26 Datasheet LVX Family 5.2 Warning: Operating Conditions Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. Table 10. Extended Temperature Operation Unit Flash + xRAM Symbol Parameter Min Max Operating Temperature -25 +85 C F-VCC Flash Supply Voltage 1.7 2.0 V VCCQ R-VCC Flash and LPSDRAM I/O Voltage 1.7 1.9 V TC LPSDRAM Supply Voltage VPPL F-VPP Voltage Supply (Logic Level) 0.9 2 V VPPH Factory word programming F-VPP 8.5 9.5 V Block Erase Cycles Main and Parameter Blocks F-VPP = F-VCC 100,000 - Main Blocks F-VPP = VPPH - 1000 Parameter Blocks F-VPP =VPPH - 2500 Cycles NOTE: Operating voltage are for flash + flash only stacked device. Please refer to document numbers 253852 and 253853 for flash + RAM stacked combinations. Datasheet 27 LVX Family 6.0 Electrical Specifications 6.1 DC Voltage and Current Characteristics Refer to the Intel StrataFlash(R) Wireless Memory (L18) Datasheet (order number 251902) for flash DC characteristics. Table 11, "LPSDRAM DC Characteristics" and Table 12, "LPSDRAM Self Refresh Current" on page 29 show DC voltage and current characteristics for LPSDRAM. The DC current characteristics referenced in this document are for individual flash and RAM die in the SCSP device. The total device current is determined by sum of the active and inactive currents of each flash and RAM die in the SCSP device. NOTICE: Individual DC Characteristics of all dies in a SCSP device need to be considered accordingly, depending on the SCSP device stacked combinations and operations. Table 11. LPSDRAM DC Characteristics (Sheet 1 of 2) Parameter D-VCC / R-VCC Description Test Conditions and Density Min Typ Max Unit 1.7 1.8 1.9 V 128-Mbit - - 60 Voltage Range ICC1 (One Bank Active) Operating Current at min cycle time IIO=0mA Burst Length = 1 tCK=min 256-Mbit - - 75 Precharge Standby Current: Power Down Mode (All banks idle) D-CKE=L, 128-Mbit - - 600 ICC2P Dx-CS#/Rx-CS#=H 256-Mbit - - 700 Precharge Standby Current: Non-Power Down Mode (All banks idle) 128-Mbit - - 15 Dx-CS#=H 256-Mbit - - 15 ICC2N D-CKE=H, tCK=min mA Active Standby Current in Power Down Mode (All banks active) D-CKE=L, 128-Mbit - - 5 tCK=min 256-Mbit - - 5 Active Standby Current: Non-Power Down Mode (All banks active) D-CKE=H, 128-Mbit - - 20 ICC3N tCK=min 256-Mbit - - 25 128-Mbit - - 70 256-Mbit - - 80 128-Mbit - - 130 256-Mbit - - 150 Address & Data toggling at min cycle time 128-Mbit - - 500 256-Mbit - - 600 Address & Data toggling at min cycle time 128-Mbit - - 10 256-Mbit - - 10 Operating Current IIO=0mA Page Burst Mode tCK=min ICC5 Auto Refresh Current ICC6 Self Refresh Current ICC7 Deep Power Down Current tRC > tRCmin A mA ICC3P ICC4 (4 Banks active) 28 tCK=min Notes mA mA 3 mA mA 2 A 4 A Datasheet LVX Family Table 11. LPSDRAM DC Characteristics (Sheet 2 of 2) VOH Output High Voltage VOL Output Low Voltage VIH Input High Voltage VIL Input Low Voltage IIL Input Leakage Current -- VCCQ - 0.2 - - V -- -0.1 - 0.2 V - -- VCCQ - 0.3 - VCCQ + 0.2 V - -- -0.2 - 0.3 V -0.2 V < VIN < VCCQ+0.2 V -- -1.5 - +1.5 A IOH = -100 IOL = 100 , VCCQmin 1 NOTES: 1. Input leakage currents include Hi-Z output leakage for bi-directional buffers with tri-state outputs. 2. Input signals are toggled at max frequency to simulate SCSP condition, where another device may be active. 3. No accesses in progress. 4. See Table 12, "LPSDRAM Self Refresh Current" on page 29. Table 12. LPSDRAM Self Refresh Current # of Banks Parameter ICC6 (128-Mbit) ICC6 (256-Mbit) Description Test Condition Set Temperature All Banks Refreshed Banks 0 & 1 Refreshed Bank 0 Refreshed 85 C max 500 400 300 Self Refresh Current D-CKE < 0.2V 70 C max 440 350 280 (All Banks Refreshed) tCK = Infinity 45 C max 390 290 260 15 C max 350 240 240 85 C max 600 450 315 Self Refresh Current D-CKE < 0.2V 70 C max 525 375 295 (All Banks Refreshed) tCK = Infinity 45 C max 450 300 270 15 C max 375 250 250 Unit A A NOTE: Other than ICC6 for all Banks at 85 C, the Self Refresh currents are verified during device characterization and not 100% tested. Datasheet 29 LVX Family 7.0 AC Characteristics 7.1 Device AC Test Conditions Figure 6. AC Input/Output Reference Waveform VCCQ Input VCCQ/2 Test Points VCCQ/2 Output 0V IO_REF.WMF NOTE: AC test inputs are driven at VCCQ for Logic "1" and 0.0 V for Logic "0." Input/output timing begins/ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst case speed occurs at F-VCC = F-VCC MIN. Figure 7. Transient Equivalent Testing Load Circuit1,2 R-Vcc/2 NOTES: 1. Test configuration component value for worst case speed conditions. 2. CL includes jig capacitance. 7.2 Capacitance NOTICE: Refer to the Intel StrataFlash(R) Wireless Memory System datasheet (order number 253854) for flash capacitance details. Table 13. LPSDRAM Capacitance Symbol Parameter MAX Unit Condition CIN Input Capacitance 5 pF VIN = 0 V COUT Output Capacitance 7 pF VOUT = 0 V NOTE: Sampled, not 100% tested. TC = +25 C, f = 1 MHz. 30 Datasheet LVX Family 7.3 Flash AC Read Operations Refer to the Intel StrataFlash(R) Wireless Memory System datasheet (order number 253854) for flash read and write AC Characteristics. 7.4 Flash AC Write Operations Refer to the Intel StrataFlash(R) Wireless Memory System datasheet (order number 253854) for flash read and write AC Characteristics. 7.5 LPSDRAM AC Characteristics Table 14, "LPSDRAM AC Characteristics--Read-Only Operations" on page 31 and Table 15, "LPSDRAM AC Characteristics--Write Operations" on page 32 show the AC Characteristics for the LPSDRAM die. Table 14. LPSDRAM AC Characteristics--Read-Only Operations (Sheet 1 of 2) Symbol Parameter Min Max CL = 3 (125 MHz) 9.5 (105) - CL = 2 (100 MHz) 15 (66) - CL = 1 (50 MHz) Unit tRC Clock Cycle Time - - tCKH Clock High Level Pulse Width 3 - ns tCKL Clock Low Level Pulse Width 3 - ns tT Transition Time 0.5 1.0 ns tCKEH D-CKE Hold Time 1 - ns tCKES D-CKE Setup Time 2 - ns tAH Address Hold Time 1 - ns tAS Address Setup Time 2 - ns ns tIH Data Input Hold Time 1 - ns tIS Data Input Setup Time 2 - ns tCMH Dx-CS#,D-RAS#,D-CAS#,WE#,D-DM Hold time 1 - ns tCMS Dx-CS#,D-RAS#,D-CAS#,WE#,D-DM Setup time 2 - ns CL = 3 - 7 tAC Clock to valid output delay (positive edge of clock) CL = 2 - 9 CL = 1 - - 2.5 - ns ns tOH Data Out Hold Time tLZ Clock to Output in Low-Z tHZ Clock to Output in High-Z 1 - CL = 3 - 7 CL = 2 - 9 CL = 1 - - ns ns tRAS Row Active time (Active to Precharge cmd) 60 100k ns tRC Row Cycle time (Active to Active cmd on same bank) 90 - ns Datasheet 31 LVX Family Table 14. LPSDRAM AC Characteristics--Read-Only Operations (Sheet 2 of 2) Symbol Parameter Min Max Unit tRCD Row to column delay (Active to Read/Write) 30 - ns tRP Row Precharge Time 30 - ns tREF Refresh Period (4096 rows) - 64 ms tRFC Auto Refresh Period 110 - ns tSREX Self Refresh Exit time (Self refresh to Active) 120 - ns NOTES: 1. The minimum number of clock cycles is determined by dividing the minimum time required by clock cycle time. 2. LPSDRAM AC specs are guaranteed only when Normal Output Driver Strength is used. See Table 25. Table 15. LPSDRAM AC Characteristics--Write Operations Symbol Parameter Min Max Unit tWR Write Recovery Time 20 - ns tRRD Active bank a to Active Bank b command 20 - ns tDAL Last data input to Active Delay - tWR + tRP tCDL Last data input to New Read/Write Command - 1 tCK tBDL Last data input to Burst Terminate Command - 1 tCK tCCD Read/Write command to Read/Write command - 1 tCK tDQW D-DM write mask latency - 0 tCK tDQZ D-DM data out mask latency - 2 tCK tMRD Load Mode Register Command to Active/Refresh Command tCK tWR tPHZ tINI Write Recovery Time Data out to High Z from Precharge command Initialization Delay - 2 tWR / tCK < 1 - 1 1 < tWR / tCK < 2 - 2 CL=3 - 3 CL=2 - 2 CL=1 - - 200 - tCK tCK s NOTES: 1. The minimum number of clock cycles is determined by dividing the minimum time required by clock cycle time. 2. LPSDRAM AC specs are guaranteed only when Normal Output Driver Strength is used. See Table 25. 32 Datasheet LVX Family 8.0 Power and Reset Specifications Refer to the latest revision of the Intel StrataFlash(R) Wireless Memory System (LV18/LV30 SCSP; 1024-Mbit LV Family Datasheet (order number 253854) for details not included in this document. 9.0 Design Guide: Operation Overview 9.1 Bus Operations Bus operations for this L18 SCSP LX family (x16) device involve the control of flash, and LPSDRAM inputs. The bus operations and commands are shown in the following tables: * Table 16, "Flash and LPSDRAM Bus Operations" on page 34 * Table 17, "LPSDRAM Functional Mode Description: Current State bank n, Command to Bank n" on page 37 * Table 18, "LPSDRAM Functional Mode: Current State bank n, Command to Bank m" on page 38 Fully synchronous operations are performed by the LPSDRAM to latch the commands at the positive edges of R-CLK. Refer to the Intel StrataFlash(R) Wireless Memory (L18) Datasheet (order number 251902) for complete descriptions of flash modes and commands, command bus-cycle definitions and flowcharts that illustrate operational routines. Table 16, "Flash and LPSDRAM Bus Operations" summarizes the bus operations and voltage levels that must be applied to individual flash die in each mode. Refer to the Intel StrataFlash(R) Wireless Memory System datasheet (order number 253854) for complete descriptions of flash modes and commands, for command bus-cycle definitions, and flowcharts that illustrate operational routines. Each flash die within the LVX system shares basic asynchronous read and write operations unless otherwise specified. Datasheet 33 LVX Family 34 Address D-BA[1:0] D-DM[1:0] D-CAS# D-RAS# Sync Array Read H L L L X Active H Async Read H L L X X Deasserted H Write H L H L VPP1/ VPP2 High-Z L Flash DIN 2,3,5, 6 Output Disable H L H X X High-Z H Flash High-Z 6 Standby H H X X X High-Z X Flash High-Z 6 Reset L X X X X High-Z X Flash High-Z 6 Sync Array Read H L L L X Deasserted H Flash DOUT 1,4,6, 16 Async Read H L L X X Deasserted H Flash DOUT 1,4,5, 6,16 Write H L H L VPP1/ VPP2 Deasserted L Flash DIN 2,3,5, 6 Output Disable H L H X X High-Z H Flash High-Z 6 Standby H H X X X High-Z X Flash High-Z 6 Reset L X X X X High-Z X Flash High-Z 6 A11 F-VPP Dx-CS# ADV# D-CKEn OE# D-CKEn-1 Fx-CE# WAIT Mode WE# F-RST# Flash Die (Data) Flash Die (Code) Device Table 16. Flash and LPSDRAM Bus Operations (Sheet 1 of 3) LPSDRAM outputs must be in High-Z Any LPSDRAM mode allowed LPSDRAM outputs must be in High-Z Any LPSDRAM mode allowed Data Notes Flash DOUT 1,4,6, 16 Flash DOUT 1,4,5, 6,16 Datasheet LVX Family D-RAS# D-CAS# D-DM[1:0] D-BA[1:0] H X L L H X V Read H H X L H L L/H LPSDRAM Die (#1 or #2) 6,7 Col Addr RAM DOUT 6,7,8, 10 X RAM DIN 6,9,10 X RAM High-Z 6 X RAM High-Z 6 L Flash outputs must be in High-Z L H X L H L L/H V H Precharg e One Bank L H H L H H X L H X L L H X All Banks Auto Refresh Datasheet RAM DOUT H Burst Stop Self Refresh Exit Row Address V Write Self Refresh Entry Notes L With Auto Precharg e With Auto Precharg e Address Dx-CS# H Data A11 D-CKEn Active D-CKEn-1 WAIT WE# F-VPP ADV# OE# Fx-CE# Mode F-RST# Device Table 16. Flash and LPSDRAM Bus Operations (Sheet 2 of 3) Flash must be in High-Z X V L X H H H H L L L X X X X RAM High-Z 6,13 H H L L L L X X X X RAM High-Z 6,13 L H H L H X X X X X X RAM High-Z 6 H H Any flash mode allowed X X 35 LVX Family L L L X H X H Address D-CAS# X A11 D-RAS# H D-BA[1:0] Dx-CS# L D-DM[1:0] D-CKEn Load Mode Register D-CKEn-1 WAIT WE# F-VPP ADV# OE# Fx-CE# Mode F-RST# Device Table 16. Flash and LPSDRAM Bus Operations (Sheet 3 of 3) Data Notes X Operand Code RAM High-Z 6,11,1 2 X L X RAM High-Z 6,10 X H X RAM High-Z 6,10 Flash outputs must be in High-Z Input/ Output Enable LPSDRAM Die (#1 or #2) Input Inhibit/ Output High-Z Any flash mode allowed Clock Suspend Entry Clock Suspend Exit Power Down Entry Power Down Exit Deep Power Down Entry X H H X X L V V X X X H X X L H H H X X L H H L V X X X X RAM High-Z 6,14 X X X X RAM High-Z 6 X X X X RAM High-Z 6,15 X X X X RAM High-Z 6 Flash outputs must be in High-Z X Any flash mode allowed L H H L X Flash outputs must be in High-Z H Any flash mode allowed X L H H L H L L H H X X X X RAM High-Z 6 X L H X X X X X X X RAM High-Z 6 Flash outputs must be in High-Z Deep Power Down Exit Device Deselect Any flash mode allowed X H X H X X X X X X RAM High-Z 6 No Operation Flash outputs must be in High-Z H H X L H H X X X X RAM High-Z 6 NOTES: 1. WAIT is only valid during synchronous flash reads. Refer to the discrete datasheet for detailed WAIT functionality. 2. OE# and WE# (Flash and SRAM) should never be asserted simultaneously. 3. X can be VIL or VIH for inputs, VPP1, VPP2 or VPPLK for F-VPP. 4. Flash CFI query and status register accesses use DQ[7:0] only, all other reads use DQ[15:0]. 5. Refer to L18 datasheets for valid DIN during flash writes. 6. All states and sequences not shown are illegal or reserved. 7. A[13:1] provide row address for 256-Mbit LPSDRAM. A[12:1] provide row address for 128-Mbit LPSDRAM. A[9:1] provide column address for 128-Mbit or 256-Mbit LPSDRAM. 8. Select bank and column address, and start Read. A11 High enables auto precharge. 9. Select bank and column address, and start Write. A11 High enables auto precharge. 10.Activate or deactivate the data during Writes with zero-clock delay and during Reads with two-clock delay. D-DM0 corresponds to DQ[7:0], D-DM1 corresponds to DQ[15:8]. 11.A[11:1] define the operand code to the register 12.Extended mode register is programmed by setting D-BA1=H and D-BA0=L. For Mode register programming, set D-BA1=DBA0=L 13.All banks must be precharged before issuing an Auto-refresh command. 14.Clock suspend mode occurs when Column access or burst is in progress 15.Power Down occurs when no accesses are in progress. 16.Data segment flash only operates in asynchronous mode, F-CLK is ignored and WAIT is deasserted. 36 Datasheet LVX Family D-CAS# WE# H X X X No Operation Continue previous Operation L H H H No Operation Continue previous Operation L L H H Active Select and activate row L L L H Auto refresh Auto refresh L L L L Load Mode register Mode register set L L H L Precharge NOP L H L H Read Select Column & start read burst Dx-CS# Current State D-RAS# Table 17. LPSDRAM Functional Mode Description: Current State bank n, Command to Bank n Command Action Notes Any Idle Row Active Read (without Auto precharge) Write (without Auto precharge) L H L L Write Select Column & start write burst L L H L Precharge Deactivate Row in bank (or banks) 3 L H L H READ Truncate READ & start new READ burst 5 L H L L WRITE Truncate READ & start new WRITE burst 5 L L H L PRECHARGE Truncate READ, start PRECHARGE L H H L Burst Terminate Burst terminate L H L H READ Truncate WRITE & start new READ burst 5 L H L L WRITE Truncate WRITE & start new WRITE burst 5 L L H L PRECHARGE Truncate WRITE, start PRECHARGE L H H L Burst Terminate Burst terminate NOTES: 1. The table applies when both D-CKEn-1 and D-CKEn are high. 2. All states and sequences not shown are illegal or reserved. 3. This command may or may not be bank specific. If all banks are being precharged, they must be in a valid state for precharging. 4. A command other than No Operation (NOP), should not be issued to the same bank while a READ or WRITE Burst with auto precharge is enabled. 5. The new Read or Write command could be auto precharge enabled or auto precharge disabled. Datasheet 37 LVX Family H X X X No Operation Continue previous Operation L H H H No Operation Continue previous Operation X X X X Any Any command allowed to bank m L L H H Active Activate Row L H L H Read Start READ burst L H L L WRITE Start WRITE burst L L H L Precharge Precharge L L H H Active Activate Row L H L H Read Start READ burst L H L L WRITE Start WRITE burst L L H L Precharge Precharge L L H H Active Activate Row L H L H Read Start READ burst L H L L WRITE Start WRITE burst L L H L Precharge Precharge L L H H Active Activate Row L H L H Read Start READ burst L H L L WRITE Start WRITE burst L L H L Precharge Precharge L L H H Active Activate Row L H L H Read Start READ burst L H L L WRITE Start WRITE burst L L H L Precharge Precharge WE# D-CAS# D-RAS# Current State Dx-CS# Table 18. LPSDRAM Functional Mode: Current State bank n, Command to Bank m Command Action Notes Any Idle Row Activating, Active, or Precharging Read with Auto Precharge disabled Write with Auto precharge disabled Read with Auto Precharge Write with Auto precharge NOTES: 1. The table applies when both D-CKEn-1 and D-CKEn are high. 2. All states and sequences not shown are illegal or reserved. 38 Datasheet LVX Family 10.0 Flash Read Operations Refer to the Intel StrataFlash(R) Wireless Memory System datasheet (order number 253854) for information regarding flash read modes and operations. 11.0 Flash Program Operations Refer to the Intel StrataFlash(R) Wireless Memory System datasheet (order number 253854) for information regarding flash program operations. 12.0 Flash Erase Operations Refer to the Intel StrataFlash(R) Wireless Memory System datasheet (order number 253854) for information regarding flash erase operations. 13.0 Flash Suspend and Resume Operations Refer to the Intel StrataFlash(R) Wireless Memory System datasheet (order number 253854) for information regarding flash security modes and operations. 14.0 Flash Block Locking and Unlocking Operations Refer to the Intel StrataFlash(R) Wireless Memory System datasheet (order number 253854) for information regarding flash Read Configuration Register (RCR) functions and programming. 15.0 Flash Protection Register Operations Refer to the Intel StrataFlash(R) Wireless Memory System datasheet (order number 253854) for information regarding flash power considerations and consumption. 16.0 Flash Configuration Operations Refer to the Intel StrataFlash(R) Wireless Memory System datasheet (order number 253854) for information regarding flash Read Configuration Register (RCR) functions and programming. Datasheet 39 LVX Family 17.0 Flash Dual Operation Considerations Refer to the Intel StrataFlash(R) Wireless Memory System datasheet (order number 253854) for information regarding flash Read Configuration Register (RCR) functions and programming. 18.0 LPSDRAM Operations 18.1 LPSDRAM Power-up Sequence and Initialization The LPSDRAM must be powered up and initialized in a predefined manner. Once power is applied to D-VCC and VCCQ simultaneously, and the clock is stable, the LPSDRAM requires a tINI delay prior to issuing any command other than the NOP command. The NOP command should be applied at least once during the tINI delay. After the tINI delay, a Precharge command should be applied to precharge all banks. This must be followed by two back to back Auto Refresh cycles. After the Auto Refresh cycles are complete, the Mode registers must be programmed. The Mode Register will power up in an unknown state. The Mode Register and the Extended Mode Register should be loaded prior to issuing any operational commands. 18.2 LPSDRAM Mode Register The Mode Register is used to define specific modes of operation of the LPSDRAM. This definition includes the selection of a burst length, burst type, a CAS latency, and a write burst mode. The Mode Register settings are illustrated in the Table below. The Mode Register is programmed by the Load Mode Register command and will retain the information until it is reprogrammed, the device loses power, or the device goes in Deep Power Down mode. The register should be loaded when all banks are idle, and subsequent operation should only be initiated after tMRD. Addresses A[12:11, 9:8] must be set to 0 for all Mode Register programming. D-BA[1:0] should be set to (0,0) to differentiate from Extended Mode Register Programming. Table 19. LPSDRAM Setting for Burst Length Burst Length A3 A2 A1 1 0 0 0 2 2 0 0 1 4 4 0 1 0 8 8 0 1 1 Full Page Reserved 1 1 1 A4 = 0 A4 = 1 1 NOTES: 1. States not mentioned are undefined. 2. The sequential burst will wrap on reaching the last column of the burst length. 40 Datasheet LVX Family Table 20. LPSDRAM Setting for Burst Type A4 Burst Type 0 Sequential 1 Interleaved Table 21. LPSDRAM Setting for CAS Latency A7 A6 A5 CAS Latency 0 0 1 1 0 1 0 2 0 1 1 3 NOTE: States not mentioned are undefined. Table 22. LPSDRAM Setting for Write Burst Mode 18.3 A10 Write Burst Mode 0 Programmed Burst 1 Single Word Burst Extended Mode Register The Extended Mode Register controls two power saving functions: Temperature-Compensated Self Refresh (TCSR), and Partial Array Self Refresh (PASR). Both these features can only be used when the device is under Self Refresh. In addition the Configurable Output Driver Strength can be programmed through the Extended Mode Register. The Extended Mode Register is programmed by the Load Mode Register command and will retain the information until it is reprogrammed, the device loses power, or the device goes in deep power down mode. The register should be loaded when all banks are idle, and subsequent operation should only be initiated after tMRD. To program the Extended Mode Register, bank addresses D-BA1=1, and D-BA0=0 should be used. Addresses A[12:6] should be set to '0'. Table 23. LPSDRAM Setting for Partial Array Refresh Datasheet A3 A2 A1 Self-Refresh Coverage 0 0 0 Four Banks 0 0 1 Two Banks (Bank 0 & Bank 1) 0 1 0 One Bank (Bank 0) 41 LVX Family Table 24. LPSDRAM Setting for Temperature-Compensated Self Refresh A5 A4 Maximum Ambient Temperature 1 1 85 C 0 0 70 C 0 1 45 C 1 0 15 C Table 25. Configurable Output Driver Strength A7 A6 Strength Output Load (pF) 0 0 Normal 30 0 1 Half TBD 1 0 Reserved NA 1 1 Reserved NA NOTE: LPSDRAM AC specs are guaranteed only when Normal Output Driver Strength is used. 18.4 LPSDRAM Commands and Operations 18.4.1 LPSDRAM No Operation / Device Deselect The LPSDRAM device includes a Device Deselect (NOP) command and a No Operation (NOP) command. 18.4.1.1 Device Deselect (NOP) The Device Deselect (NOP) command is used to deselect the LPSDRAM by preventing new commands from being executed. Operations already in progress are not affected. 18.4.1.2 No Operation (NOP) The No Operation (NOP) command is used on a LPSDRAM device that is selected (Dx-CS# / RxDS# is low). Operations already in progress are not affected. 18.4.2 LPSDRAM Active The Active command is used to activate a row in particular bank for a subsequent read or write access. The value of the bank D-BA[1:0] and the row address needs to be provided. The row remains active until a precharge command is issued to the bank. A Precharge command must be issued before opening a different row in the same bank. More than one bank can be active at any time. A read or write command could be issued to that row, subject to the tRCD specification. tRCD (min) should be divided by the clock period and rounded up to the next whole number to determine the earliest clock edge after the active command on which the read/write can be entered. A subsequent Active command to another row in the same 42 Datasheet LVX Family bank can be issued only after the previous row has been closed. The minimum time interval between two successive active commands on the same bank is defined by tRC. The minimum time interval between two successive active commands on the different banks is defined by tRRD. This is illustrated in Figure 10, "Active Command and Read Access Command issued to 2 Different Banks" on page 46. 18.4.3 LPSDRAM Read Read command is used to initiate a burst read to an active row. The value of D-BA[1:0] selects the bank and address inputs select the starting column location. The value of A11 determines whether or not auto precharge is used. Output data appears on the data bus, subject to the logic level on the D-DM[1:0] inputs two clocks earlier. D-DM[1:0] latency for read command is 2 clock cycles. The burst length is set in the mode register. The starting column and bank address is provided along with the auto precharge option. During read bursts, the starting valid data-out corresponding to the starting column address will be available after CAS latency cycles after the read command. Each subsequent data-out will be valid by the next positive edge of the clock. This is shown in Figure 11, "Example of CAS latency 2" on page 46 with a CAS latency of 2. Data from a read burst may be truncated by a subsequent read command. The first data from the new burst follows either the last element of a completed burst or the last desired element of a longer burst that is being truncated. The new read command can be issued as early as CL-1 cycles before the last desired element. This is shown in Figure 12, "Consecutive Read Bursts with CL=2" on page 47. Figure 13, "Random Read Access with CL=2" on page 47 shows random access reads. These can be issued to the same or different banks. A read burst can be terminated by a subsequent write command, and data from a fixed length read burst can be followed by a write command. The write command may be initiated on the clock edge immediately following the last data element from the read burst, provided the I/O contention could be avoided. D-DM[1:0] can be used to control I/O contention as shown in Figure 14, "Read to Write Command" on page 47. D-DM[1:0] latency is 2 clocks for output buffers masking, so the DDM[1:0] signal must be set high at least 2 clocks prior to the write command. D-DM[1:0] latency for Write is zero clocks, so D-DM[1:0] must be set low before write command to ensure data written is not masked. A read burst may be followed by or truncated with a Precharge command, which could be issued CL-1 cycles before the last desired element. This is shown in Figure 15, "Read Command followed by Precharge" on page 48. Following Precharge command, another command to the same bank cannot be issued until tRP is met. Similarly Burst Terminate command can be used to stop a burst as shown in Figure 16, "Read followed by Burst Terminate" on page 48. 18.4.4 LPSDRAM Write The write command is used to initiate a burst write access to an active row. The value of D-BA[1:0] select the bank and address inputs select the starting column location. The value of A11 determines whether or not auto precharge is used. Input data appearing on the data bus, is written to the memory array subject to the D-DM[1:0] input logic level appearing coincident with the data. DDM[1:0] latency for write command is 0 clock cycles. Datasheet 43 LVX Family The burst length is set in the mode register. The starting column and bank address is provided along with the auto precharge option. The first valid data-in is registered coincident with the Write command. Subsequent data elements will be registered on each successive positive clock edge. Figure 17, "Random Write to 4 Word Bursts" on page 48 shows 2 consecutive 4 word write bursts. A write burst may be followed by or truncated with a Precharge command to the same bank. The Precharge should be issued tWR after the clock edge after the last desired input data is entered. In addition, when truncating a Write burst, the D-DM[1:0] signal must be used to mask input data for the clock edge coincident with the precharge command. This is shown in Figure 18, "Write to Precharge command where Write Recovery takes 1 clock cycle" on page 49 and Figure 19, "Write to Precharge command where Write Recovery takes 2 clock cycles" on page 49, where tWR corresponds to either 1 or 2 clock cycles, respectively. Following the Precharge command, a subsequent command cannot be issued to the same bank until tRP is met. Write Burst can be truncated with a Burst Terminate command. While truncating, the input data being applied coincident to the Burst Terminate will be ignored. Data for any Writes may be truncated by a subsequent Read command as shown in Figure 20, "Write command followed by Read command" on page 49. Once the Read command is registered, the Data inputs will be ignored. 18.4.5 LPSDRAM Power Down Power down occurs if D-CKE is set low coincident with Device Deselect or NOP command and when no accesses are in progress. If power down occurs when all banks are idle, it is Precharge Power Down. If power down occurs when one or more banks are active, it is referred to as Active power down. The device cannot stay in this mode for longer than the refresh period (64ms) without losing data. The power down state is exited by setting D-CKE high while issuing a Device Deselect or NOP command. This is shown in Figure 21, "Precharge Power Down Mode" on page 50. 18.4.6 LPSDRAM Deep Power Down The Deep Power Down (DPD) mode enables very low standby currents. All internal voltage generators inside the LPSDRAM are stopped and all memory data are lost in this mode. To enter the DPD mode, all banks must be precharged, prior to the DPD command. To exit this mode, the DCKE is taken high after the clock is stable. 18.4.7 LPSDRAM Clock Suspend This mode occurs when a column access or burst is in progress, and D-CKE is set low. The internal clock gets suspended freezing the LPSDRAM logic. Any command or data present on the input pins at the time of suspended internal clock is ignored. The output data on the pins stays frozen. This mode is exited by setting D-CKE high, which results in the operation being resumed. Figure 22, "Clock suspend during Write Burst" on page 50 shown Clock suspend during a Write burst and Figure 23, "Clock suspend during Read Burst (CL=2)" on page 51 shows a clock suspend during a Read burst. 44 Datasheet LVX Family 18.4.8 LPSDRAM Precharge The Precharge is used to deactivate an active row in a particular bank or active row in all banks. The banks will be available for row access after a specified time (tRP) after the Precharge command is issued. If one bank is to precharged, the particular bank address needs to be addressed. If all banks are to be precharged, A11 should be set high along with the Precharge command. 18.4.9 LPSDRAM Auto Precharge Auto Precharge is accomplished when A11 is high, to enable auto precharge in conjunction with a specific read or write command. This precharges the row after the read or write burst is complete. Auto precharge ensures that a precharge is initiated at the earliest valid stage within a burst. Another command to the same bank must not be issued until the precharge time (tRP) is completed. Auto precharge does not apply in full-page burst mode. Auto precharge is non- persistent. 18.4.10 LPSDRAM Concurrent Auto Precharge If an access command with Auto Precharge enabled is being executed, it can be interrupted by another access command. Figure 24, "Read with Auto Precharge to bank n interrupted by Read to bank m" on page 51 shows a Read with Auto Precharge to Bank n, interrupted by a Read (with or without Auto precharge) to bank m. The Read to bank m will interrupt the Read to Bank n, CAS latency later. The precharge to bank n will begin when the Read to bank m is registered. Figure 25, "Read with Auto Precharge to bank n interrupted by Write to bank m" on page 52 shows a Read with Auto Precharge to Bank n, interrupted by a Write (with or without Auto precharge) to bank m. The precharge to bank n will begin when the Write to bank m is registered. D-DM[1:0] should be set high 2 clock before the Write command to prevent bus contention. Figure 26, "Write with Auto Precharge to bank n interrupted by Read to bank m" on page 52 shows a Write with Auto Precharge to Bank n, interrupted by a Read (with or without Auto precharge) to bank m. The new command initiates bank n Write recovery (tWR) followed by precharge. The last valid data-in to bank n is 1 clock prior to the Read to bank m. Figure 27, "Write with Auto Precharge to bank n interrupted by Write to bank m" on page 53 shows a Write with Auto Precharge to Bank n, interrupted by a Write (with or without Auto precharge) to bank m. The new command initiates bank n Write recovery (tWR) followed by precharge. The last valid data-in to bank n is 1 clock prior to the Write to bank m. Figure 8. Auto Refresh Cycles with D-CKE High T0 T1 T2 Tn Tm R-CLK tRFC tRP Command Datasheet Precharge NOP Auto Refresh tRFC Auto Refresh Active 45 LVX Family Figure 9. Self Refresh Entry and Exit Mode T0 T1 T2 Tn Tm R-CLK tRP Command Precharge NOP NOP Auto Refresh Auto Refresh tSREX D-CKE > tRAS Figure 10. Active Command and Read Access Command issued to 2 Different Banks T0 T1 T2 Active NOP T3 T4 T5 NOP Active NOP T6 T7 R-CLK Command Read-AP Read-AP NOP tRCD, Bank 0 Address Bk 0/Row Bk 0/Col a Bk 1/Row Bk1/ Col b tRRD Data I/O Dout - a Dout-a+1 Dout-a+2 tRAS, Bank 0 Figure 11. Example of CAS latency 2 T0 R-CLK Command tAS Read T1 T2 NOP NOP T3 tAH NOP tOH tLZ Dout tAC tHZ CL=2 46 Datasheet LVX Family Figure 12. Consecutive Read Bursts with CL=2 T0 T1 T2 T3 T4 T5 T6 NOP NOP NOP Read NOP NOP Dout - a+3 Dout - b R-CLK Command Read Address Bk n /Col a Bk any/Col b CL - 1 Data I/O Dout - a Dout-a+1 Dout-a+2 NOTE: New command should be issued CL-1 clock cycles before the last desired data. New command can be used to truncate previous Read Burst. Figure 13. Random Read Access with CL=2 T0 T1 T2 T3 T4 T5 T6 Read Read Read NOP NOP NOP Bk any/Col b Bk any/Col c Bk any/Col d Dout - a Dout - b Dout - c Dout - d R-CLK Command Read Address Bk any/Col a Data I/O Figure 14. Read to Write Command T0 T1 T2 T3 T4 NOP NOP NOP Write R-CLK D-DM Command Read Address Bk n /Col a Data I/O Bk any/Col b Dout - a Dout-a+1 Din - b NOTE: Data masking used to prevent I/O contention. Datasheet 47 LVX Family Figure 15. Read Command followed by Precharge T0 T1 T2 T3 T4 NOP NOP NOP T5 T6 NOP NOP T7 R-CLK Command Read Address Bk n /Col a Precharge Active Bk n/all Bk/Row CL - 1 Data I/O Dout - a Dout-a+1 Dout-a+2 Dout - a+3 CL=2 NOTE: Command issued CL-1 clocks before last desired data-out element. Figure 16. Read followed by Burst Terminate T0 T1 T2 T3 NOP NOP NOP Dout - a Dout-a+1 T4 T5 T6 NOP NOP R-CLK Command Read Address Bk n /Col a Brst Term CL - 1 Data I/O Dout-a+2 Dout - a+3 CL=2 Figure 17. Random Write to 4 Word Bursts T0 T1 T2 T3 T4 T5 T6 Write NOP NOP NOP Write NOP NOP Din - b+1 Din - b+2 CLK R-CLK Command Address Bk n /Col a Data I/O Din - a Bk any/Col b Din-a+1 Din-a+2 Din - a+3 Din - b NOTE: The commands can be to any active bank. 48 Datasheet LVX Family Figure 18. Write to Precharge command where Write Recovery takes 1 clock cycle T0 T1 T2 Write NOP T3 T4 T5 T6 NOP Active NOP CLK R-CLK DQM D-DM Command Precharge NOP tRP Address Bk n /Col a Bk a/all Bk any/Col b tWR Data I/O Din - a Din-a+1 Figure 19. Write to Precharge command where Write Recovery takes 2 clock cycles T0 T1 T2 Write NOP NOP T3 T4 T5 T6 NOP Active R-CLK D-DM Command Precharge NOP tRP Address Bk n /Col a Bk a/all Bk any/Col b tWR Data I/O Din - a Din-a+1 Figure 20. Write command followed by Read command T0 T1 T2 T3 T4 T5 Write NOP Read NOP NOP NOP CLK R-CLK Command Address Bk n /Col a Data I/O Din - a Bk any /Col b Din - a+1 Dout - b Dout - b+1 CL=2 NOTE: The Read and Write commands can be done to any bank (CL=2). Datasheet 49 LVX Family Figure 21. Precharge Power Down Mode T0 T1 T2 Tn Tn+1 R-CLK CLK CKE D-CKE Two CLK cycles Command Precharge NOP NOP NOP Active All Banks A11 A10 Row Single Bank Ba0, Ba1 D-BA[1:0] Bank Row High-Z Data I/O NOTE: All banks are idle with D-CKE low. Figure 22. Clock suspend during Write Burst T0 T1 NOP T2 T3 T4 T5 Write NOP NOP Address Bk n /Col a Bk any/Col b Data I/O Din - a Din - a+1 R-CLK CLK CKE D-CKE Internal Clock Command Din - a+2 NOTE: Input data is ignored when internal clock is suspended. 50 Datasheet LVX Family Figure 23. Clock suspend during Read Burst (CL=2) T0 T1 T2 NOP NOP T3 T4 T5 T6 NOP NOP NOP Dout - a+2 Dout - a+3 R-CLK CLK CKE D-CKE Internal Clock Command Read Address Bk n /Col a Data I/O Dout - a Dout-a+1 NOTE: Output data gets frozen while internal clock is suspended. Figure 24. Read with Auto Precharge to bank n interrupted by Read to bank m T0 T1 T2 T3 T4 T5 T6 NOP NOP NOP R-CLK Command NOP Bank n Page Active Bank n Read-AP NOP Bank m Read-AP tRP, Bank n Read Burst Bank m Page Active Address Bk n /Col a Interrupt Burst, Precharge Idle Read Burst Bk m/Col b CL=2 Data I/O Datasheet Dout - a Dout - a+1 Dout - b Dout - b+1 51 LVX Family Figure 25. Read with Auto Precharge to bank n interrupted by Write to bank m T0 T1 T2 T3 NOP NOP T4 T5 T6 NOP NOP R-CLK Bank n Read-AP Command NOP Bank n Page Active Bank m Write-AP tRP, Bank n Read Burst Bank m Page Active Address Bk n /Col a Interrupt Burst, Precharge Write Burst Bk m/Col b D-DM CL=2 Data I/O Dout - a Din - b Din - b+1 Din - b+2 Figure 26. Write with Auto Precharge to bank n interrupted by Read to bank m T0 T1 T2 T3 T4 T5 T6 NOP NOP NOP CLK R-CLK Command Bank n Write-AP NOP Bank m Read-AP tWR, Bank n Bank n Active Bank m 52 Write Burst Interrupt Burst, Write Recovery Page Active Address Bk n /Col a Data I/O Din -a NOP tRP, Bank n Precharge Read Burst (4 Word) Precharge Bk m/Col b Din -a+1 Dout - b Dout - b+1 Dout - b+2 Datasheet LVX Family Figure 27. Write with Auto Precharge to bank n interrupted by Write to bank m T0 T1 T2 T3 T4 T5 T6 NOP NOP NOP NOP CLK R-CLK Command Bank n Write-AP NOP Bank m Write-AP tWR, Bank n Bank n Active Write Burst (4 Word) tRP, Bank n Interrupt Burst, Write Recovery Precharge tWR , Bank m Bank m Page Active Address Bk n /Col a Data I/O Din -a 18.4.11 Write Burst (4 Word) Wrtie Recovery Bk m/Col b Din -a+1 Din - b Din - b+1 Din - b+2 Din - b+3 LPSDRAM Burst Terminate This command is used to truncate bursts. The most recent command prior to the burst terminate command will be truncated. 18.4.12 LPSDRAM Auto Refresh This command is used during normal operation of the LPSDRAM. This command is nonpersistent. All banks must be idle before issuing Auto Refresh command. This command can be issued after a minimum of tRP after the precharge command. The address bits are "Do Not Care" during the Auto Refresh command. As an example, the 128-Mbit LPSDRAM requires 4096 auto refresh cycles (4096 rows/bank) every 64 ms (tREF). Providing a distributed Auto Refresh command every 15.625 s will meet the refresh requirement and ensure that each row is refreshed. Alternatively, 4096 refresh command cycles can be issued in a burst at a minimum cycle rate (tRFC), once every 64 ms. Figure 8, "Auto Refresh Cycles with D-CKE High" on page 45 shows auto refresh cycles. 18.4.13 LPSDRAM Self Refresh This state retains data in the LPSDRAM, even as the rest of the system is powered down. The Self Refresh command is initiated like the auto refresh command, except the D-CKE is disabled (low). All banks must be idle before this command is issued. Once the Self Refresh command is registered, all inputs become "Do Not Care" except D-CKE, which must remain low. The procedure for exiting Self Refresh mode requires a series of commands. First clock must be stable before D-CKE going high. NOP commands should be issued (minimum of 2 clocks) to meet the refresh exit time (tSREX) limitation. Figure 9, "Self Refresh Entry and Exit Mode" on page 46 shows self refresh entry and exit mode. Datasheet 53 LVX Family Appendix A Write State Machine Refer to the Intel StrataFlash(R) Wireless Memory System datasheet (order number 253854) for the Write State Machine (WSM) details. Appendix B Common Flash Interface Refer to the Intel StrataFlash(R) Wireless Memory System datasheet (order number 253854) for the Common Flash Interface (CFI) details. Appendix C Flash Flowcharts Refer to the Intel StrataFlash(R) Wireless Memory System datasheet (order number 253854) for the flash flowchart details. 54 Datasheet LVX Family Appendix D Additional Information : Order Number 253854 Datasheets Intel StrataFlash Wireless Memory System (LV18/LV30 SCSP) Datasheet (R) Application Notes 253856 Concurrent Program and Erase Using the Intel StrataFlash(R) Wireless Memory System (L18/L30 SCSP) 292221 AP-663 Using the Intel StrataFlash(R) memory write buffer(R) 292286 AP-738 Reduce Manufacturing Costs with Intel(R) Flash Memory Enhanced Factory Programming 251237 AP-759 Intel(R) Flash Memory Programming Algorithm Optimizations 297769 AP-678 Improving Programming Throughput of Automated Flash Memories 292186 AP-630 Designing for On-Board Programming Using IEEE1149.1 (JTAG) Access Port 292185 AP-629 Simplifying Manufacturing by Using Automatic Test Equipment for On-Board Programming Software Manuals (R) 297833 Intel Flash Data Integrator (FDI) User's Guide 298136 Intel(R) Persistent Storage Manager (PSM) 298132 Intel(R) Virtual Small Block File Manager (VFM) SCSP User Guide 298161 (R) Intel Flash Memory Chip Scale Package User's Guide NOTES: 1. Please call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers should contact their local Intel or distribution sales office. 2. For the most current information on Intel(R) Flash memory products, software and tools, visit our website at http://developer.intel.com/design/flash. Datasheet 55 LVX Family Appendix E Ordering Information Table 26, "Ordering Information: LVX Family with LPSDRAM Product Matrix" shows the ordering information for the Flash + RAM combinations in the LVX family. The figures and tables listed here show the decoder information for the Flash + RAM combinations in the LVX family. * Figure 28, "Decoder for Flash + LPSDRAM Combinations" * Table 27, "38F and 48F Product Density Decoder" on page 57 * Table 28, "58F Product Density Decoder" on page 57 Table 26. Ordering Information: LVX Family with LPSDRAM Product Matrix Flash Component RAM Component Package Size (mm) Package Type 256L18 + 256L18 + 256V18 + 256V18 -- 11x11x1.4 SCSP 256L18 + 256L18 + 256V18 128-Mbit SDRAM 9x11x1.4 SCSP Device Name (Bottom and/or Top Configuration) RD48F4444LVYBB0 RD48F4444LVYTB0 RD58F0012LVYBB0 RD58F0012LVYTB0 Figure 28. Decoder for Flash + LPSDRAM Combinations RD 58F 0012 LV Z B Package Designator B x Device Details RD = SCSP, leaded x = Variable that can be 0- 9 or A - Z (excluding characters I and O) PF = SCSP, Pb-free 0 = Initial version of a product as defined by the first 14 characters. NZ = Intel(R) UT-SCSP, BT, leaded LZ = Intel(R) UT-SCSP, Tape, leaded JZ = Intel(R) UT-SCSP, BT, Pb-free RZ = Intel(R) UT-SCSP, Tape, Pb-free Ballout Identifier B = x16D Performance Product Line Designator 38F = Stacked Flash + RAM Parameter Configuration 48F = Stacked Flash Only B = Bottom 58F = Stacked Flash / RAM T = Top Product Die / Density Configuration Voltage Options See the 38F/48F and 58F Product Density Decoder Tables. Z = 3.0 V I/O Flash Product Family Y = 1.8 V I/O (R) L = Intel StrataFlash Wireless Memory LV = Intel(R) StrataFlash Wireless Memory System 0 = No die 56 Datasheet LVX Family Table 27. 38F and 48F Product Density Decoder Code Flash Die Density RAM Die Density 0 No Die No Die 1 32-Mbit 4-Mbit 2 64-Mbit 8-Mbit 3 128-Mbit 16-Mbit 4 256-Mbit 32-Mbit 5 512-Mbit 64-Mbit 6 1-Gbit 128-Mbit 7 2-Gbit 256-Mbit 8 4-Gbit 512-Mbit 9 8-Gbit 1-Gbit A 16-Gbit 2-Gbit Table 28. 58F Product Density Decoder Sequence Code Number Flash + RAM Dies Explanation 256L (Bottom) + 256L (Bottom) + 256V (Top) +128SD Bottom parameter configuration 256L (Top) + 256L (Top) + 256V (Bottom) +128SD To parameter configuration 0012 ... ... ... 9999 TBD TBD Datasheet 57 LVX Family 58 Datasheet