LVX Family
24 Datasheet
WAIT Output
DEVICE WAIT: Selectable high-true or low-true output. (For stacked combinations without
Synchronous PSRAM, WAIT is a flash specific input.)
During synchronous-burst reads (array or non-array), WAIT-asserted indicates invalid read
data. During asynchronous-page reads and writes, WAIT is deasserted. Wait is High-Z
whenever F-CE# or F-OE# / OE# is deasserted.
WE# Input
WRITE ENABLE: Global device signal. Low-true input.
WE# low selects the associated memory die for write operation. WE# high deselect the
associated memory die, data are placed in high-Z state.
With LPSDRAM operation, WE# is latched on the positive clock edge in conjunction with the
D-RAS# and D-CAS# signals. The WE# input is used to select the Bank Activate or
Precharge command and Read or Write command.
F-WP[2:1]# Input
WRITE PROTECT: Low-true input.
F-WP# controls the lock-down protection mechanism of the selected flash die. When low, F-
WP# enables the lock-down mechanism where locked down blocks cannot be unlocked with
software commands. When high, F-WP# disables the lock-down mechanism, allowing
locked down blocks to be unlocked with software commands.
F-WP1# controls the code segment flash die #1, while F-WP2# controls subsequent code or
data segment flash dies.
D-CKE Input
LPSDRAM Clock Enable: High-true input
• If D-CKE goes low synchronously with clock, the internal clock is suspended from the
next clock cycle.
• The state of the outputs and the burst address is halted.
• When all banks are in the idle state, D-CKE is high, the LPDRAM enters into Power
Down and Self Refresh modes.
• D-CKE is synchronous except after the device enters Power Down and Self Refresh
modes, where D-CKE becomes asynchronous until exiting the same mode. The input
buffers, including R-CLK, are disabled during Power Down and Self Refresh modes,
providing low standby power.
D-BA[1:0] Input
LPSDRAM Bank Select: D-BA0 and D-BA1 defines to which bank the Bank Activate, Read,
Write, or Bank Precharge command is being applied. The bank address D-BA0 and D-BA1
isusedlatchedinmoderegisterset.
D-RAS# Input
LPSDRAM Row Address Strobe: Low-true input.
• The D-RAS# signal defines the operation commands, with the D-CAS# and WE#
signals.
• The D-RAS# is latched at the rising edges of R-CLK. When D-RAS# and Dx-CS# / Rx-
CS# are asserted and D-CAS# is deasserted, either the Bank Activate command or the
Precharge command is selected by the WE# signal.
• WE# is deasserted, the Bank Activate command is selected and the bank designated by
D-BA[1:0] is turned on to the active state.
D-CAS# Input
LPSDRAM Column Address Strobe: Low-true input.
• D-CAS# signal defines the operation commands in conjunction with the D-RAS# and
WE# signals and is latched at the rising edges of R-CLK.
• D-RAS# is deasserted and Dx-CS# / Rx-CS# is asserted, the column access is started
by asserting D-CAS#. Read or Write command then is selected by asserting WE# low or
high.
R[2:1]-CS# Input
RAM Chip Select: Low-true input.
x16D Performance ballout:
• R[2:1]-CS#
R[2:1]-CS# low selects the associated LPSDRAM memory die. All commands are masked
when R[2:1]-CS# high. R[2:1]-CS# provides for external bank selection on systems with
multiple banks. It is considered part of the command code.
• R1-CS# controls LPSDRAM die #1.
• R2-CS# controls LPSDRAM die #2.
Table 8. Signal Descriptions (Sheet 2 of 3)
Symbol Type Name and Function Notes