M30263F6AFP#U9A - Renesas Technology / Hitachi Semiconductor

RENE

-BIT

LE-

HIP MI

OCO

M16

FAMILY / M16

/Tin

ERIE

M16C/26A Group

(M16C/26A, M16C/26B, M16C/26T)

Rev. 2.00

Revision Date: Feb.15, 2007

Hardware Manual

www.renesas.com

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Technology Corp. without notice. Please review the latest information published

by Renesas Technology Corp. through various means, including the Renesas Technology

Corp. website (http://www.renesas.com).

REJ09B0202-0200

1. This document is provided for reference purposes only so that Renesas customers may select the appropriate

Renesas products for their use. Renesas neither makes warranties or representations with respect to the

accuracy or completeness of the information contained in this document nor grants any license to any

intellectual property rights or any other rights of Renesas or any third party with respect to the information in

this document.

2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising

out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,

programs, algorithms, and application circuit examples.

3. You should not use the products or the technology described in this document for the purpose of military

applications such as the development of weapons of mass destruction or for the purpose of any other military

use. When exporting the products or technology described herein, you should follow the applicable export

control laws and regulations, and procedures required by such laws and regulations.

4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and

application circuit examples, is current as of the date this document is issued. Such information, however, is

subject to change without any prior notice. Before purchasing or using any Renesas products listed in this

document, please confirm the latest product information with a Renesas sales office. Also, please pay regular

and careful attention to additional and different information to be disclosed by Renesas such as that disclosed

through our website. (http://www.renesas.com )

5. Renesas has used reasonable care in compiling the information included in this document, but Renesas

assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information

included in this document.

6. When using or otherwise relying on the information in this document, you should evaluate the information in

light of the total system before deciding about the applicability of such information to the intended application.

Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any

particular application and specifically disclaims any liability arising out of the application and use of the

information in this document or Renesas products.

7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas

products are not designed, manufactured or tested for applications or otherwise in systems the failure or

malfunction of which may cause a direct threat to human life or create a risk of human injury or which require

especially high quality and reliability such as safety systems, or equipment or systems for transportation and

traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication

transmission. If you are considering the use of our products for such purposes, please contact a Renesas

sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.

8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:

(1) artificial life support devices or systems

(2) surgical implantations

(3) healthcare intervention (e.g., excision, administration of medication, etc.)

(4) any other purposes that pose a direct threat to human life

Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who

elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas

Technology Corp., its affiliated companies and their officers, directors, and employees against any and all

damages arising out of such applications.

9. You should use the products described herein within the range specified by Renesas, especially with respect

to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation

characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or

damages arising out of the use of Renesas products beyond such specified ranges.

10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific

characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use

conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and

injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for

hardware and software including but not limited to redundancy, fire control and malfunction prevention,

appropriate treatment for aging degradation or any other applicable measures. Among others, since the

evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or

system manufactured by you.

11. In case Renesas products listed in this document are detached from the products to which the Renesas

products are attached or affixed, the risk of accident such as swallowing by infants and small children is very

high. You should implement safety measures so that Renesas products may not be easily detached from your

products. Renesas shall have no liability for damages arising out of such detachment.

12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written

approval from Renesas.

13. Please contact a Renesas sales office if you have any questions regarding the information contained in this

document, Renesas semiconductor products, or if you have any other inquiries.

Notes regarding these materials

General Precautions in the Handling of MPU/MCU Products

The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes

on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under

General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each

other, the description in the body of the manual takes precedence.

1. Handling of Unused Pins

Handle unused pins in accord with the directions given under Handling of Unused Pins in the

manual.

 The input pins of CMOS products are generally in the high-impedance state. In operation

with an unused pin in the open-circuit state, extra electromagnetic noise is induced in the

vicinity of LSI, an associated shoot-through current flows internally, and malfunctions occur

due to the false recognition of the pin state as an input signal become possible. Unused

pins should be handled as described under Handling of Unused Pins in the manual.

2. Processing at Power-on

The state of the product is undefined at the moment when power is supplied.

 The states of internal circuits in the LSI are indeterminate and the states of register

settings and pins are undefined at the moment when power is supplied.

In a finished product where the reset signal is applied to the external reset pin, the states

of pins are not guaranteed from the moment when power is supplied until the reset

process is completed.

In a similar way, the states of pins in a product that is reset by an on-chip power-on reset

function are not guaranteed from the moment when power is supplied until the power

reaches the level at which resetting has been specified.

3. Prohibition of Access to Reserved Addresses

Access to reserved addresses is prohibited.

 The reserved addresses are provided for the possible future expansion of functions. Do

not access these addresses; the correct operation of LSI is not guaranteed if they are

accessed.

4. Clock Signals

After applying a reset, only release the reset line after the operating clock signal has become

stable. When switching the clock signal during program execution, wait until the target clock

signal has stabilized.

 When the clock signal is generated with an external resonator (or from an external

oscillator) during a reset, ensure that the reset line is only released after full stabilization of

the clock signal. Moreover, when switching to a clock signal produced with an external

resonator (or by an external oscillator) while program execution is in progress, wait until

the target clock signal is stable.

5. Differences between Products

Before changing from one product to another, i.e. to one with a different part number, confirm

that the change will not lead to problems.

 The characteristics of MPU/MCU in the same group but having different part numbers may

differ because of the differences in internal memory capacity and layout pattern. When

changing to products of different part numbers, implement a system-evaluation test for

each of the products.

How to Use This Manual

1. Purpose and Target Readers

This manual is designed to provide the user with an understanding of the hardware functions and electrical

characteristics of the MCU. It is intended for users designing application systems incorporating the MCU. A basic

knowledge of electric circuits, logical circuits, and MCUs is necessary in order to use this manual.

The manual comprises an overview of the product; descriptions of the CPU, system control functions, peripheral

functions, and electrical characteristics; and usage notes.

Particular attention should be paid to the precautionary notes when using the manual. These notes occur

within the body of the text, at the end of each section, and in the Usage Notes section.

The revision history summarizes the locations of revisions and additions. It does not list all revisions. Refer

to the text of the manual for details.

The following documents apply to the M16 C/26A Group (M16C/26A, M16C/26B, and M16C/26T). Make sure to

refer to the latest versions of these documents. The newest versions of the documents listed may be obtained from the

Renesas Technology Web site.

Document Type Description Document Title Document No.

Hardware manual Hardware specifications (pin assignments,

memory maps, peripheral function

specifications, electrical characteristics, timing

charts) and operation description

Note: Refer to the application notes for details on

using peripheral functions.

M16C/26A Group

(M16C/26A,

M16C/26B,

M16C/26T)

Hardware Manual

This hardware

manual

Software manual Description of CPU instruction set M16C/60,

M16C/20,

M16C/Tiny Series

Software Manual

REJ09B0137

Application note Information on using peripheral functions and

application examples

Sample programs

Information on writing programs in assembly

language and C

Available from Renesas

Technology Web site.

Renesas

technical update Product specifications, updates on documents,

etc.

2. Notation of Numbers and Symbols

The notation conventions for register names, bit names, numbers, and symbols used in this manual are described

below.

(1) Register Names, Bit Names, and Pin Names

Registers, bits, and pins are referred to in the text by symbols. The symbol is accompanied by the word

“register,” “bit,” or “pin” to distinguish the three categories.

Examples the PM03 bit in the PM0 register

P3_5 pin, VCC pin

(2) Notation of Numbers

The indication “2” is appended to numeric values given in binary format. However, nothing is appended to the

values of single bits. The indication “16” is appended to numeric values given in hexadecim al format. Nothing

is appended to numeric values given in decimal format.

Examples Binary: 112

Hexadecimal: EFA016

Decimal: 123 4

3. Register Notation

The symbols and terms used in register diagrams are described below.

*1 Blank: Set to 0 or 1 according to the application.

0: Set to 0.

1: Set to 1.

X: Nothing is assigned.

*2 RW: Read and write.

RO: Read only.

WO: Write only.

−: Nothing is assigned.

*3• Reserved bit

Reserved bit. Set to specified value.

*4• Nothing is assigned

Nothing is assigned to the bit. As the bit may be used fo r future functions, if necessary, set to 0.

• Do not set to a value

Operation is not guaranteed when a value is set.

• Function varies according to the operating mode.

The function of the bit varies with the peripheral function mode. Refer to the register diagram for information

on the individual mode s.

XXX Register

Symbol Address After Reset

XXX XXX 0016

Bit NameBit Symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

XXX bits 1 0: XXX

0 1: XXX

1 0: Do not set.

1 1: XXX

b1 b0

XXX1

XXX0

XXX4

Reserved bits

XXX5

XXX7

XXX6

Function

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined.

XXX bit

Function varies according to the operating

mode.

Set to 0.

(b3)

(b2)

XXX bits

0: XXX

1: XXX

4. List of Abbreviations and Acronyms

Abbreviation Full Form

ACIA Asynchronous Communication Interface Adapter

bps bits per second

CRC Cyclic Redundancy Check

DMA Direct Memory Access

DMAC Direct Memory Access Controller

GSM Global System for Mobile Communications

Hi-Z High Impedance

IEBus Inter Equipment bus

I/O Input/Output

IrDA Infrared Data Association

LSB Least Significant Bit

MSB Most Significant Bit

NC Non-Connection

PLL Phase Locked Loop

PWM Pulse Width Modulation

SFR Special Function Registers

SIM Subscriber Identity Module

UART Universal Asynchronous Receiver/Transmitter

VCO Voltage Controlled Oscillator

All trademarks and registered trademarks are the property of their respective owners.

IEBus is a registered trademark of NEC Electronics Corporation.

A-1

Table of Contents

Quick Reference by Address_______________________ B-1

1. Overview ______________________________________ 1

1.1 Applications ...................................................................................................................1

1.2 Performance Outline .....................................................................................................2

1.3 Block Diagram...............................................................................................................4

1.4 Product List ...................................................................................................................6

1.5 Pin Assignments.......................................................................................................... 11

1.6 Pin Description ............................................................................................................15

2. Central Processing Unit (CPU) ____________________ 17

2.1 Data Registers (R0, R1, R2 and R3)...........................................................................17

2.2 Address Registers (A0 and A1) ...................................................................................17

2.3 Frame Base Register (FB) ..........................................................................................18

2.4 Interrupt Table Register (INTB) ...................................................................................18

2.5 Program Counter (PC) ................................................................................................18

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP) ......................................18

2.7 Static Base Register (SB) ...........................................................................................18

2.8 Flag Register (FLG) ....................................................................................................18

2.8.1 Carry Flag (C Flag) ..............................................................................................18

2.8.2 Debug Flag (D Flag) ............................................................................................18

2.8.3 Zero Flag (Z Flag) ...............................................................................................18

2.8.4 Sign Flag (S Flag) ................................................................................................18

2.8.5 Register Bank Select Flag (B Flag)......................................................................18

2.8.6 Overflow Flag (O Flag).........................................................................................18

2.8.7 Interrupt Enable Flag (I Flag) ...............................................................................18

2.8.8 Stack Pointer Select Flag (U Flag).......................................................................18

2.8.9 Processor Interrupt Priority Level (IPL)................................................................18

2.8.10 Reserved Area ...................................................................................................18

3. Memory ______________________________________ 19

4. Special Function Registers (SFRs) _________________ 20

A-2

5. Reset________________________________________ 26

5.1 Hardware Reset ..........................................................................................................26

5.1.1 Hardware Reset 1 ................................................................................................26

5.1.2 Hardware Reset 2 ................................................................................................26

5.2 Software Reset............................................................................................................27

5.3 Watchdog Timer Reset................................................................................................27

5.4 Oscillation Stop Detection Reset.................................................................................27

5.5 Voltage Detection Circuit.............................................................................................29

5.5.1 Voltage Down Detection Interrupt .......................................................................32

5.5.2 Limitations on Exiting Stop Mode........................................................................34

5.5.3 Limitations on Exiting Wait Mode ........................................................................34

6. Processor Mode _______________________________ 35

7. Clock Generation Circuit _________________________ 38

7.1 Main Clock ..................................................................................................................45

7.2 Sub Clock....................................................................................................................46

7.3 On-chip Oscillator Clock..............................................................................................47

7.4 PLL Clock ....................................................................................................................47

7.5 CPU Clock and Peripheral Function Clock .................................................................49

7.5.1 CPU Clock ...........................................................................................................49

7.5.2 Peripheral Function Clock (f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32) .......49

7.5.3 ClockOutput Function ..........................................................................................49

7.6 Power Control .............................................................................................................50

7.6.1 Normal Operation Mode.......................................................................................50

7.6.2 Wait Mode ............................................................................................................51

7.6.3 Stop Mode...........................................................................................................53

7.7 System Clock Protective Function ..............................................................................57

7.8 Oscillation Stop and Re-oscillation Detect Function ...................................................57

7.8.1 Operation When the CM27 bit is set to "0" (Oscillation Stop Detection Reset) ...58

7.8.2 Operation When the CM27 bit is set to "1"

(Oscillation Stop and Re-oscillation Detect Interrupt) ..................58

7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function.........................59

8. Protection ____________________________________ 60

9. Interrupt______________________________________ 61

9.1 Type of Interrupts ........................................................................................................61

9.1.1 Software Interrupts...............................................................................................62

9.1.2 Hardware Interrupts .............................................................................................63

A-3

9.2 Interrupts and Interrupt Vector ....................................................................................64

9.2.1 Fixed Vector Tables..............................................................................................64

9.2.2 Relocatable Vector Tables ...................................................................................65

9.3 Interrupt Control ..........................................................................................................66

9.3.1 I Flag ....................................................................................................................69

9.3.2 IR Bit ....................................................................................................................69

9.3.3 ILVL2 to ILVL0 Bits and IPL .................................................................................69

9.4 Interrupt Sequence......................................................................................................70

9.4.1 Interrupt Response Time......................................................................................71

9.4.2 Variation of IPL when Interrupt Request is Accepted...........................................71

9.4.3 Saving Registers..................................................................................................72

9.4.4 Returning from an Interrupt Routine ....................................................................74

9.5 Interrupt Priority...........................................................................................................74

9.5.1 Interrupt Priority Resolution Circuit ......................................................................74

______

9.6 INT Interrupt ................................................................................................................76

______

9.7 NMI Interrupt ...............................................................................................................77

9.8 Key Input Interrupt.......................................................................................................77

9.9 Address Match Interrupt ..............................................................................................78

10. Watchdog Timer ______________________________ 80

10.1 Count Source Protective Mode .................................................................................81

11. DMAC ______________________________________ 82

11.1 Transfer Cycles.........................................................................................................87

11.2. DMA Transfer Cycles................................................................................................89

11.3 DMA Enable...............................................................................................................90

11.4 DMA Request ............................................................................................................90

11.5 Channel Priority and DMA Transfer Timing ..............................................................91

12. Timer _______________________________________ 92

12.1 Timer A .....................................................................................................................94

12.1.1. T imer Mode .......................................................................................................97

12.1.2. Event Counter Mode.........................................................................................98

12.1.3. One-shot Timer Mode .....................................................................................103

12.1.4. Pulse Width Modulation (PWM) Mode............................................................105

12.2 Timer B...................................................................................................................108

12.2.1 Timer Mode..................................................................................................... 111

12.2.2 Event Counter Mode........................................................................................ 112

12.2.3 Pulse Period and Pulse Width Measurement Mode ....................................... 113

12.2.4 A/D Trigger Mode ............................................................................................ 115

A-4

12.3 Three-phase Motor Control Timer Function ............................................................ 117

12.3.1 Position-data-retain Function ...........................................................................128

12.3.2 Three-phase/Port Output Switch Function.......................................................130

13. Serial I/O ___________________________________ 132

13.1. UARTi (i=0 to 2)......................................................................................................132

13.1.1. Clock Synchronous serial I/O Mode................................................................142

13.1.2. Clock Asynchronous Serial I/O (UART) Mode ................................................150

13.1.3 Special Mode 1 (I2C bus mode)(UART2).........................................................158

13.1.4 Special Mode 2 (UART2) .................................................................................168

13.1.5 Special Mode 3 (IE Bus mode )(UART2) ........................................................173

13.1.6 Special Mode 4 (SIM Mode) (UART2) ............................................................175

14. A/D Converter _______________________________ 180

14.1 Operation Modes.....................................................................................................186

14.1.1 One-Shot Mode................................................................................................186

14.1.2 Repeat mode ...................................................................................................188

14.1.3 Single Sweep Mode ........................................................................................190

14.1.4 Repeat Sweep Mode 0 ....................................................................................192

14.1.5 Repeat Sweep Mode 1 ....................................................................................194

14.1.6 Simultaneous Sample Sweep Mode ................................................................196

14.1.7 Delayed Trigger Mode 0...................................................................................199

14.1.8 Delayed Trigger Mode 1...................................................................................205

14.2 Resolution Select Function ..................................................................................... 211

14.3 Sample and Hold..................................................................................................... 211

14.4 Power Consumption Reducing Function................................................................. 211

14.5 Output Impedance of Sensor under A/D Conversion ..............................................212

15. CRC Calculation Circuit _______________________ 213

15.1. CRC Snoop ............................................................................................................213

16. Programmable I/O Ports _______________________ 216

16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)...........................................216

16.2 Port Pi Register (Pi Register, i = 1, 6 to 10) ............................................................216

16.3 Pull-up Control Register 0 to Pull-up Control Register 2

(PUR0 to PUR2 Registers)...

216

16.4 Port Control Register...............................................................................................217

16.5 Pin Assignment Control register (PACR).................................................................217

16.6 Digital Debounce function .......................................................................................217

17. Flash Memory Version_________________________ 230

17.1 Flash Memory Performance....................................................................................230

17.1.1 Boot Mode.......................................................................................................231

A-5

17.2 Memory Map ...........................................................................................................232

17.3 Functions To Prevent Flash Memory from Rewriting...............................................235

17.3.1 ROM Code Protect Function............................................................................235

17.3.2 ID Code Check Function..................................................................................235

17.4 CPU Rewrite Mode .................................................................................................237

17.4.1 EW0 Mode .......................................................................................................238

17.4.2 EW1 Mode .......................................................................................................238

17.5 Register Description................................................................................................239

17.5.1 Flash memory control register 0 (FMR0) .........................................................239

17.5.2 Flash memory control register 1 (FMR1) .........................................................240

17.5.3 Flash memory control register 4 (FMR4) .........................................................240

17.6 Precautions in CPU Rewrite Mode..........................................................................245

17.6.1 Operation Speed..............................................................................................245

17.6.2 Prohibited Instructions .....................................................................................245

17.6.3 Interrupts..........................................................................................................245

17.6.4 How to Access .................................................................................................245

17.6.5 Writing in the User ROM Space.......................................................................245

17.6.6 DMA Transfer ...................................................................................................246

17.6.7 Writing Command and Data.............................................................................246

17.6.8 Wait Mode........................................................................................................246

17.6.9 Stop Mode........................................................................................................246

17.6.10

Low Power Consumption Mode and On-chip Oscillator-Low Power Consumption Mode ...

246

17.7 Software Commands...............................................................................................247

17.7.1 Read Array Command (FF16) ..........................................................................247

17.7.2 Read Status Register Command (7016)...........................................................247

17.7.3 Clear Status Register Command (5016)...........................................................248

17.7.4 Program Command (4016) ...............................................................................248

17.7.5 Block Erase......................................................................................................249

17.8 Status Register........................................................................................................251

17.8.1 Sequence Status (SR7 and FMR00 Bits ) .......................................................251

17.8.2 Erase Status (SR5 and FMR07 Bits) ...............................................................251

17.8.3 Program Status (SR4 and FMR06 Bits)...........................................................251

17.8.4 Full Status Check.............................................................................................252

17.9 Standard Serial I/O Mode........................................................................................254

17.9.1 ID Code Check Function..................................................................................254

17.9.2 Example of Circuit Application in Standard Serial I/O Mode ............................258

17.10 Parallel I/O Mode ..................................................................................................260

17.10.1 ROM Code Protect Function..........................................................................260

A-6

18. Electrical Characteristics_______________________ 261

18.1. M16C/26A, M16C/26B (Normal version)................................................................261

18.2. M16C/26T (T version) ............................................................................................280

19. Usage Notes ________________________________ 299

19.1 SFR .........................................................................................................................299

19.1.1 Precaution for 48-pin package .........................................................................299

19.1.2 Precaution for 42-pin package .........................................................................299

19.1.3 Register Setting ...............................................................................................299

19.2 PLL Frequency Synthesizer ....................................................................................300

19.3 Power Control .........................................................................................................301

19.4 Protect.....................................................................................................................303

19.5 Interrupts .................................................................................................................304

19.5.1 Reading address 0000016....................................................................................................304

19.5.2 Setting the SP ..................................................................................................304

_______

19.5.3 The NMI Interrupt.............................................................................................304

19.5.4 Changing the Interrupt Generation Factor .......................................................304

______

19.5.5 INT Interrupt.....................................................................................................305

19.5.6 Rewrite the Interrupt Control Register .............................................................306

19.5.7 Watchdog Timer Interrupt.................................................................................306

19.6 DMAC......................................................................................................................307

19.6.1 Write to DMAE Bit in DMiCON Register ..........................................................307

19.7 Timer .......................................................................................................................308

19.7.1 Timer A.............................................................................................................308

19.7.2 Timer B............................................................................................................. 311

19.7.3 Three-phase Motor Control Timer Function .....................................................312

19.8 Serial I/O .................................................................................................................313

19.8.1 Clock-Synchronous Serial I/O..........................................................................313

19.8.2 Serial I/O (UART Mode)...................................................................................314

19.9 A/D Converter..........................................................................................................315

19.10 Programmable I/O Ports .......................................................................................317

19.11 Electric Characteristic Differences Between Mask ROM

and Flash Memory Version Microcomputers..................318

19.12 Mask ROM Version ...............................................................................................319

19.12.1 Internal ROM area .........................................................................................319

19.12.2 Reserve bit.....................................................................................................319

A-7

19.13 Flash Memory Version ..........................................................................................320

19.13.1 Functions to Inhibit Rewriting Flash Memory .................................................320

19.13.2 Stop mode......................................................................................................320

19.13.3 Wait mode ......................................................................................................320

19.13.4

Low power dissipation mode, on-chip oscillator low power dissipation mode...

320

19.13.5 Writing command and data ............................................................................320

19.13.6 Program Command........................................................................................320

19.13.7 Operation speed ............................................................................................320

19.13.8 Instructions prohibited in EW0 Mode .............................................................320

19.13.9 Interrupts........................................................................................................321

19.13.10 How to access..............................................................................................321

19.13.11 Writing in the user ROM area.......................................................................321

19.13.12 DMA transfer ................................................................................................321

19.13.13 Regarding Programming/Erasure Times and Execution Time .....................321

19.13.14 Definition of Programming/Erasure Times ...................................................322

19.13.15

Flash Memory Version Electrical Characteristics 10,000 E/W cycle product..

322

19.13.16 Boot Mode....................................................................................................322

19.14 Noise .....................................................................................................................323

19.15 Instruction for a Device Use ..................................................................................324

Appendix 1. Package Dimensions___________________ 325

Appendix 2. Functional Difference __________________ 326

Appendix 2.1 Differences between M16C/26A, M16C/26B, and M16C/26T...................326

Appendix 2.2 Differences between M16C/26A Group and M16C/26 Group ...................327

B-1

Quick Reference by Address

000016

000116

000216

000316

000416

000516

000616

000716

000816

000916

000A16

000B16

000C16

000D16

000E16

000F16

001016

001116

001216

001316

001416

001516

001616

001716

001816

001916

001A16

001B16

001C16

001D16

001E16

001F16

002016

002116

002216

002316

002416

002516

002616

002716

002816

002916

002A16

002B16

002C16

002D16

002E16

002F16

003016

003116

003216

003316

003416

003516

003616

003716

003816

003916

003A16

003B16

003C16

003D16

003E16

003F16

Address

NOTE:

1. The blank areas are reserved and cannot be accessed by users.

004016

004116

004216

004316

004416

004516

004616

004716

004816

004916

004A16

004B16

004C16

004D16

004E16

004F16

005016

005116

005216

005316

005416

005516

005616

005716

005816

005916

005A16

005B16

005C16

005D16

005E16

005F16

006016

006116

006216

006316

006416

006516

006616

006716

006816

006916

006A16

006B16

006C16

006D16

006E16

006F16

007016

007116

007216

007316

007416

007516

007616

007716

007816

007916

007A16

007B16

007C16

007D16

007E16

007F16

Watchdog timer start register WDTS

Watchdog timer control register WDC

Processor mode register 0 PM0

System clock control register 0 CM0

System clock control register 1 CM1

Address match interrupt enable register AIER

Protect register PRCR

Processor mode register 1 PM1

Oscillation stop detection register CM2

PLL control register 0 PLC0

Processor mode register 2 PM2

Address match interrupt register 0 RMAD0

Address match interrupt register 1 RMAD1

DMA0 control register DM0CON

DMA0 transfer counter TCR0

DMA1 control register DM1CON

DMA1 source pointer SAR1

DMA1 destination pointer DAR1

DMA0 destination pointer DAR0

DMA0 source pointer SAR0

Voltage detection register 1 VCR1

Voltage detection register 2 VCR2

Voltage down detection interrupt register D4INT

UART0 transmit interrupt control register

S0TIC

UART0 receive interrupt control register

S0RIC

UART1 transmit interrupt control register

S1TIC

UART1 receive interrupt control register

S1RIC

DMA1 transfer counter TCR1

INT3 interrupt control register INT3IC

INT5 interrupt control register INT5IC

INT4 interrupt control register INT4IC

UART2 Bus collision detection interrupt control register

BCNIC

DMA0 interrupt control register DM0IC

DMA1 interrupt control register DM1IC

Key input interrupt control register KUPIC

A/D conversion interrupt control register ADIC

UART2 transmit interrupt control register

S2TIC

UART2 receive interrupt control register

S2RIC

Timer A0 interrupt control register TA0IC

Timer A1 interrupt control register TA1IC

Timer A2 interrupt control register TA2IC

Timer A3 interrupt control register TA3IC

Timer A4 interrupt control register TA4IC

Timer B0 interrupt control register TB0IC

Timer B2 interrupt control register TB2IC

INT0 interrupt control register INT0IC

INT1 interrupt control register INT1IC

INT2 interrupt control register INT2IC

Timer B1 interrupt control register TB1IC

36, 43

Address

B-2

Quick Reference by Address

Flash memory control register 0 FMR0

Flash memory control register 1 FMR1

Flash memory control register 4 FMR4

NOTES:

1. The blank areas are reserved and cannot be accessed by users.

2. This register is included in the flash memory version.

0080

0081

0082

0083

0084

0085

0086

01B0

01B1

01B2

01B3

01B4

01B5

01B6

01B7

01B8

01B9

01BA

01BB

01BC

01BD

01BE

01BF

0250

0251

0252

0253

0254

0255

0256

0257

0258

0259

025A

025B

025C

025D

025E

025F

02E0

02E1

02E2

02E3

02E4

02E5

02E6

02E7

02E8

02E9

033D

033E

033F

Peripheral clock select register PCLKR

241

(2)

Address

(2)

242

Pin assignment control register PACR

On-chip oscillator control register ROCR 139, 226

digital debounce register P17DDR

NMI digital debounce register NDDR 227

227

Three phase protect control register TPRC

0340

0341

0342

0343

0344

0345

0346

0347

0348

0349

034A

034B

034C

034D

034E

034F

0350

0351

0352

0353

0354

0355

0356

0357

0358

0359

035A

035B

035C

035D

035E

035F

0360

0361

0362

0363

0364

0365

0366

0367

0368

0369

036A

036B

036C

036D

036E

036F

0370

0371

0372

0373

0374

0375

0376

0377

0378

0379

037A

037B

037C

037D

037E

037F

Timer A1-1 register TA11

Timer A2-1 register TA21

Dead time timer DTT

Timer B2 interrupt occurrence frequency set counter

ICTB2

Three-phase PWM control register 0 INVC0

Three-phase PWM control register 1 INVC1

Three-phase output buffer register 0 IDB0

Three-phase output buffer register 1 IDB1

Interrupt request cause select register

IFSR

UART2 special mode register U2SMR

UART2 receive buffer register

U2RB

UART2 transmit buffer register

U2TB

UART2 transmit/receive control register 0

U2C0

UART2 transmit/receive mode register

U2MR

UART2 transmit/receive control register 1

U2C1

UART2 bit rate generator

U2BRG

Timer A4-1 register TA41

UART2 special mode register 2 U2SMR2

UART2 special mode register 3 U2SMR3

UART2 special mode register 4 U2SMR4

122

119

120

121

122

141

140

137

136

138

139

136

68, 76

Address

Position-data-retain function contol register

PDRF 129

Port function contol register PFCR

Interrupt request cause select register 2

IFSR2A 68

131

B-3

Quick Reference by Address

NOTE:

1. The blank areas are reserved and cannot be accessed by users.

038016

038116

038216

038316

038416

038516

038616

038716

038816

038916

038A16

038B16

038C16

038D16

038E16

038F16

039016

039116

039216

039316

039416

039516

039616

039716

039816

039916

039A16

039B16

039C16

039D16

039E16

039F16

03A016

03A116

03A216

03A316

03A416

03A516

03A616

03A716

03A816

03A916

03AA16

03AB16

03AC16

03AD16

03AE16

03AF16

03B016

03B116

03B216

03B316

03B416

03B516

03B616

03B716

03B816

03B916

03BA16

03BB16

03BC16

03BD16

03BE16

03BF16

Count start flag TABSR

Trigger select register TRGSR

Timer A0 register TA0

Timer A1 register TA1

Timer A2 register TA2

Timer B0 register TB0

Timer B1 register TB1

Timer B2 register TB2

One-shot start flag ONSF

Timer A0 mode register TA0MR

Timer A1 mode register TA1MR

Timer A2 mode register TA2MR

Timer B0 mode register TB0MR

Timer B1 mode register TB1MR

Timer B2 mode register TB2MR

Up-down flag UDF

Timer A3 register TA3

Timer A4 register TA4

Timer A3 mode register TA3MR

Timer A4 mode register TA4MR

Clock prescaler reset flag CPSRF

UART0 transmit/receive mode register

U0MR

UART0 transmit buffer register U0TB

UART0 receive buffer register U0RB

UART1 transmit/receive mode register

U1MR

UART1 transmit buffer register U1TB

UART1 receive buffer register U1RB

UART0 bit rate generator U0BRG

UART0 transmit/receive control register 0

U0C0

UART0 transmit/receive control register 1

U0C1

UART1 bit rate generator U1BRG

UART1 transmit/receive control register 0

U1C0

UART1 transmit/receive control register 1

U1C1

DMA1 request cause select register DM1SL

DMA0 request cause select register DM0SL

UART transmit/receive control register 2

UCON

Timer B2 special mode register TB2SC

95, 110,

124

r0)

96, 124

110

110, 124

94, 125

109

123, 185

137

136

138

139

136

137

136

138

139

136

138

95, 122

94, 125

109, 125

Address

CRC snoop address register CRCSAR

CRC mode register CRCMR

CRC data register CRCD

CRC input register CRCIN

03C016

03C116

03C216

03C316

03C416

03C516

03C616

03C716

03C816

03C916

03CA16

03CB16

03CC16

03CD16

03CE16

03CF16

03D016

03D116

03D216

03D316

03D416

03D516

03D616

03D716

03D816

03D916

03DA16

03DB16

03DC16

03DD16

03DE16

03DF16

03E016

03E116

03E216

03E316

03E416

03E516

03E616

03E716

03E816

03E916

03EA16

03EB16

03EC16

03ED16

03EE16

03EF16

03F016

03F116

03F216

03F316

03F416

03F516

03F616

03F716

03F816

03F916

03FA16

03FB16

03FC16

03FD16

03FE16

03FF16

A/D control register 1 ADCON1

Port P9 register P9

Pull-up control register 0 PUR0

Port control register PCR

A/D register 7 AD7

A/D register 0 AD0

A/D register 1 AD1

A/D register 2 AD2

A/D register 3 AD3

A/D register 4 AD4

A/D register 5 AD5

A/D register 6 AD6

A/D control register 0 ADCON0

A/D control register 2 ADCON2

Port P1 register P1

Port P1 direction register PD1

Port P6 register P6

Port P6 direction register PD6

Port P7 register P7

Port P7 direction register PD7

Port P8 register P8

Port P8 direction register PD8

Port P9 direction register PD9

Port P10 register P10

Port P10 direction register PD10

Pull-up control register 1 PUR1

Pull-up control register 2 PUR2

184

182

224

223

224

223

224

223

224

223

225

226

Address

A/D convert status register 0 ADSTAT0 184

A/D trigger control register ADTRGCON 183

214

SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER

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1. Overview

The M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) is a single-chip control MCU, fabricated using

high-performance silicon gate CMOS technology, embedding the M16C/60 Series CPU core. The M16C/

26A Group (M16C/26A, M16C/26B, M16C/26T) is housed in 42-pin and 48-pin plastic molded packages.

This MCU combines advanced instruction manipulation capabilities to process complex instructions by less

bytes and execute instructions at higher speed. The M16C/26A Group (M16C/26A, M16C/26B, M16C/

26T) has a multiplier and DMAC adequate for office automation, communication devices and industrial

equipment, and other high-speed processing applications. The M16C/26A and M16C/26B have normal

version. The M16C/26T has T version and V version.

1.1 Applications

Audio, cameras, office/communications/portable/ equipment, air-conditioning equipment, home appli-

ances, etc.

1. Overview

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Item Specification

CPU Basic instructions 91 instructions

Minimun instruction

41.7 ns (f(BCLK) = 24MHZ(3), VCC = 4.2 to 5.5 V) (M16C/26B)

execution time

50 ns (f(BCLK) = 20MHZ, VCC = 3.0 to 5.5 V)

(M16C/26A, M16C/26B, M16C/26T(T-ver.))

100 ns (f(BCLK) = 10MHZ, VCC = 2.7 to 5.5 V)

(M16C/26A , M16C/26B)

50 ns (f(BCLK) = 20MHZ, VCC = 4.2 to 5.5 V -40 to 105°C)

(M16C/26T(V-ver.))

62.5 ns (f(BCLK) = 16MHZ, VCC = 4.2 to 5.5 V -40 to 125°C)

(M16C/26T(V-ver.))

Operating mode Single-chip mode

Address space 1 Mbyte

Memory capacity ROM/RAM: See 1.4 Product Information

Peripheral I/O ports 39 I/O pins

Function Multifunction timers TimerA:16 bits x 5 channels, TimerB:16 bits x 3 channels

Three-phase motor control timer

Serial I/O 2 channels (UART, clock synchronous serial I/O)

1 channel

(UART, clock synchronous, I

C bus, or IEBus

(1)

)

A/D converter 10 bit A/D Converter : 1 circuit, 12 channels

DMAC 2 channels

CRC calcuration circuit

1 circuit (CRC-CCITT and CRC-16) with MSB/LSB selectable

Watchdog timer 15 bits x 1 channel (with prescaler)

Interrupts 20 internal and 8 external sources, 4 software sources,

Interrupt priority level: 7

Clock generation circuit 4 circuits

Main clock oscillation circuit(*), Sub-clock oscillation circuit(*)

On-chip oscillator, PLL frequency synthesizer

(*)Equipped with a built-in feedback resister.

Oscillation stop detection Main clock oscillation stop, re-oscillation detection function

Voltage detection circuit On-chip (M16C/26A, M16C/26B), not on-chip (M16C/26T)

Electrical Power supply voltage VCC = 4.2 to 5.5 V (f(BCLK) = 24 MHZ)(3) (M16C/26B)

Characteristics VCC = 3.0 to 5.5 V (f(BCLK) = 20 MHZ) (M16C/26A, M16C/26B)

VCC = 2.7 to 5.5 V (f(BCLK) = 10 MHZ)

VCC = 3.0 to 5.5 V (M16C/26T(T-ver.))

VCC = 4.2 to 5.5 V (M16C/26T(V-ver.))

Power consumption 20 mA (Vcc = 5 V, f(BCLK) = 24 MHz) (M16C/26B)

16 mA (Vcc = 5 V, f(BCLK) = 20 MHz)

25 µA (f(XCIN) = 32 KHz on RAM)

3 µA (Vcc = 3 V, f(XCIN) = 32 KHz, in wait mode)

0.7 µA (Vcc = 3 V, in stop mode)

Flash Memory Programming /erasure 2.7 to 5.5 V (M16C/26A, M16C/26B)

Version voltage 3.0 to 5.5 V (M16C/26T(T-ver.)) 4.2 to 5.5 V (M16C/26T(V-ver.))

Programming /erasure

100 times (all area) or 1,000 times (block 0 to 3)

endurance

/ 10,000 times

(block A, block B)(2)

Operating Ambient Temperature -20 to 85°C / -40 to 85°C (2) (M16C/26A , M16C/26B)

-40 to 85°C (M16C/26T(T-ver.))

-40 to 105°C / -40 to 125°C (M16C/26T(V-ver.))

Package 48-pin plastic molded QFP

NOTES:

1. IEBus is a trademark of NEC Electronics Corporation.

2. See Tables 1.7 to 1.10 Product Code for the program and erase endurance, and operating ambient temperature.

3. The PLL frequency synthesizer is used to run the M16C/26B at f(BCLK) = 24 MHz.

Table 1.1. M16C/26A Group(M16C/26A, M16C/26B, M16C/26T) Performance (48-Pin Package)

1.2 Performance Outline

Table 1.1 and 1.2 outline performance overview of the M16C/26A Group (M16C/26A, M16C/26B, M16C/

26T).

1. Overview

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Table 1.2. Performance outline of M16C/26A group (M16C/26A, M16C/26B) (42-pin package)

Item Performance

CPU Basic instructions 91 instructions

Minimun instruction

41.7 ns (f(BCLK) = 24 MHz

(3)

, VCC = 4.2 to 5.5 V (M16C/26B)

execution time

50 ns (f(BCLK) = 20 MH

, V

= 3.0 to 5.5 V) (M16C/26A, M16C/26B)

100 ns (f(BCLK) = 10 MH

, V

= 2.7 to 5.5 V) (M16C/26A, M16C/26B)

Operation mode Single-chip mode

Address space 1M byte

Memory capacity ROM/RAM: See 1.4 Product Information

Peripheral Port 33 I/O pins

function Multifunction timer Timer A: 16 bits x 5 channels, Timer B: 16 bits x 3 channels

Three-phase motor control timer

Serial I/O 1 channel (UART, clock synchronous serial I/O)

1 channel (UART, clock synchronous, I2C bus, or IEBus(1))

A/D converter 10 bit A/D converter: 1 circuit, 10 channels

DMAC 2 channels

CRC calcuration circuit 1 circuits (CRC-CCITT and CRC-16) with MSB/LSB selectable

Watchdog timer 15 bits x 1 channel (with prescaler)

Interrupt 18 internal and 8 external sources, 4 software sources,

Interrupt priority level: 7

Clock generation circuit 4 circuits

Main clock(*), Sub-clock(*)

On-chip oscillator, PLL frequency synthesizer

(*)Equipped with a built-in feedback resister.

Oscillation stop detection Main clock oscillation stop, re-oscillation detection function

Voltage detection circuit On-chip

Electrical Supply voltage VCC = 4.2 to 5.5 V (f(BCLK) = 24 MHZ)(3) (M16C/26B)

Characteristics VCC = 3.0 to 5.5 V (f(BCLK) = 20 MHZ) (M16C/26A, M16C/26B)

VCC = 2.7 to 5.5 V (f(BCLK) = 10 MHZ)

Power Consumption 20 mA (Vcc = 5 V, f(BCLK) = 24 MHz) (M16C/26B)

16 mA (Vcc = 5 V, f(BCLK) = 20 MHz)

25 µA (f(XCIN) = 32 KHz on RAM)

3 µA (Vcc = 3 V, f(XCIN) = 32 KHz, in wait mode)

0.7 µA (Vcc = 3 V, in stop mode)

Flash memory Programming/erasure 2.7 to 5.5 V

voltage

Programming/erasure 100 times (all area) or 1,000 times (block 0 to 3)

endurance / 10,000 times (block A, block B)(2)

Operating Ambient Temperature -20 to 85°C / -40 to 85°C (2)

Package 42-pin plastic molded SSOP

NOTES:

1. IEBus is a trademark of NEC Electronics Corporation.

2. See Tables 1.7 and 1.8 Product Code for the program and erase endurance, and operating ambient tempera-

ture.

3. The PLL frequency synthesizer is used to run the M16C/26B at f(BCLK) = 24 MHz.

1. Overview

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1.3 Block Diagram

Figure 1.1 and 1.2 show block diagrams of the M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) 48-

pin package and 42-pin package.

Figure 1.1 Block Diagram(48-pin Package)

Timer (16-bit)

Output (timer A): 5channels

Input (timer B): 3 channels

Peripheral functions

Watchdog timer

(15 bits)

DMAC

(2 channels)

UART or

clock synchronous serial I/O

(8 bits X 3 channels)

Clock generation circuit

XIN-XOUT

XCIN-XCOUT

On-Chip Oscillator

PLL frequency synthesizer

M16C/60 series CPU core

Port P1

Port P10

Memory

ROM

(1)

RAM

(2)

NOTES:

1: ROM size depends on the MCU type.

2: RAM size depends on the MCU type.

R0LR0H

R1H R1L

FLG

USP

ISP

INTB

PC Multiplier

Three-phase motor

control circuit

Port P6

Port P7

Port P8

Port P9

CRC calculation circuit

(CCITT, CRC-16 )

10-bit A/D converter

12 channels

1. Overview

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Figure 1.2 Block Diagram( 42-pin Package)

Timer (16-bit)

Output (timer A): 5channels

Input (timer B): 3 channels

Peripheral functions

Watchdog timer

(15 bits)

DMAC

(2 channels)

UART or

clock synchronous serial I/O

(8 bits X 2 channels)

Clock generation circuit

XIN-XOUT

XCIN-XCOUT

On-Chip Oscillator

PLL frequency synthesizer

M16C/60 series CPU core

Port P1

Port P10

Memory

ROM

(1)

RAM

(2)

NOTES:

1: ROM size depends on the MCU type.

2: RAM size depends on the MCU type.

R0LR0H

R1H R1L

FLG

USP

ISP

INTB

PC Multiplier

Three-phase motor

control circuit

Port P6

Port P7

Port P8

Port P9

CRC calculation circuit

(CCITT, CRC-16 )

10-bit A/D converter

10 channels

1. Overview

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1.4 Product List

Tables 1.3 to 1.6 lists product information, Figure 1.3 shows a product numbering system, Table 1.7 lists

the product code, and Figure 1.4 shows the marking.

Table 1.3 M16C/26A Current as of Feb., 2007

rebmuNepyT MOR yticapaC MAR yticapaC epyTegakcaPskrameRedoCtcudorP

PGA3F06203M)N(K4+K42K1)A-Q6P84(A-BK8400PQLP

hsalF yromem

9U,7U,5U,3U

PGA6F06203M)N(K4+K84K2

PGA8F06203M)N(K4+K46K2

PFA3F36203M)N(K4+K42K1)R2P24(B-AG2400PSRP9U,5U

PFA6F36203M)N(K4+K84K2

PFA8F36203M)N(K4+K46K2

PGXXX-A3M06203M)N(K42K1)A-Q6P84(A-BK8400PQLP

MORksaM

5U,3U

PGXXX-A6M06203M)N(K84K2

PGXXX-A8M06203M)N(K46K2

PFXXX-A3M36203M)N(K42K1)R2P24(B-AG2400PSRP5U

PFXXX-A6M36203M)N(K84K2

PFXXX-A8M36203M)N(K46K2

weN:)N(

rebmuNepyT MOR yticapaC MAR yticapaC epyTegakcaPskrameRedoCtcudorP

PGB8F06203M)N(K4+K46K2)A-Q6P84(A-BK8400PQLP hsalF yromem 7U

PFB8F36203M)N(K4+K46K2)R2P24(B-AG2400PSRP9U

weN:)N(

rebmuNepyT MOR yticapaC MAR yticapaC epyTegakcaPskrameRedoCtcudorP

PGT3F06203MK4+K42K1)A-Q6P84(A-BK8400PQLP hsalF yromem 7U,3U

PGT6F06203MK4+K84K2

PGT8F06203MK4+K46K2

:ETON .ylnonoisrevyromemhsalfnielbaliavA.1

Table 1.4 M16C/26B Current as of Feb., 2007

Table 1.5 M16C/26T T-ver. Current as of Feb., 2007

Table 1.6 M16C/26T V-ver. Current as of Feb., 2007

rebmuNepyT MOR yticapaC MAR yticapaC egakcaPskrameRedoCtcudorP

PGV8F06203MK4+K46K2)A-Q6P84(A-BK8400PQLP hsalF yromem 7U,3U

:ETON .ylnonoisrevyromemhsalfnielbaliavA.1

1. Overview

page 7

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Figure 1.3 Product Numbering System

Package type:

GP: PLQP0048KB-A (48P6Q) (M16C/26A, M16C/26B, M16C/26T)

FP: PRSP0042GA-B (42P2R) (M16C/26A, M16C/26B)

Version:

A : M16C/26A

B : M16C/26B

T : M16C/26T T-ver.

V : M16C/26T V-ver.

ROM / RAM capacity:

3: (24K+4K) bytes (1) / 1K bytes

6: (48K+4K) bytes (1) / 2K bytes

8: (64K+4K) bytes (1) / 2K bytes

NOTE:

1. Only flash memory version exists in "+4K bytes"

Memory type:

M: Mask ROM version

F: Flash memory version

Type No. M 3 0 2 6 0 M 8 A - XXX G P - U3

M16C/26A Group

M16C Family

Pin count (The value itself has no specific meaning)

Product code:

See Tables 1.7 to 1.10

ROM number:

ROM number is omitted in flash memory version

1. Overview

page 8

923fo7002,51.beF00.2.veR 0020-2020B90JER

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tcudorP edoC egakcaP

MORlanretnI )3ot0skcolB:ecapSmargorP( MORlanretnI )BdnaAskcolB:ecapSataD( tneibmAgnitarepO erutarepmeT

dnamargorP esarE ecnarudnE

erutarepmeT egnaR

dnamargorP esarE ecnarudnE

erutarepmeT egnaR

eerfdaeL

001

Cº06ot0

001Cº06ot0 Cº58ot04-

5U Cº58ot02-

7U 000,1000,01 Cº58ot04-Cº58ot04-

9U Cº58ot02-Cº58ot02-

Table 1.7 Product Code (Flash Memory Version) - M16C/26A, M16C/26B

Table 1.8 Product Code (Mask ROM Version - M16C/26A)

tcudorP edoC egakcaP tneibmAgnitarepO erutarepmeT

3U eerfdaeL Cº04-otCº58

5UCº02-otCº58

tcudorP edoC egakcaP

MORlanretnI )3ot0skcolB:ecapSmargorP( MORlanretnI )BdnaAskcolB:ecapSataD( tneibmAgnitarepO erutaremeT

gnimmargorP erusaredna ecnarudne

erutarepmeT egnar

gnimmargorP erusaredna ecnarudne

erutarepmeT egnar

3U eerfdaeL 001 Cº06otCº0001 Cº58otCº04-Cº58otCº04-

7U000,1000,01

NOTE:

1. The lead contained products, D3, D5, D7, and D9 are put together with U3, U5, U7, and U9 respectively.

Lead-free products can be mounted by both conventional Sn-Pb paste and Lead-free paste (Sn-Ag-Cu

plating).

tcudorP edoC egakcaP

MORlanretnI )3ot0skcolB:ecapSmargorP( MORlanretnI )BdnaAskcolB:ecapSataD( tneibmAgnitarepO erutaremeT

gnimmargorP erusaredna ecnarudne

erutarepmeT egnar

gnimmargorP erusaredna ecnarudne

erutarepmeT egnar

3U eerfdaeL 001 Cº06otCº0001 Cº521otCº04-Cº521otCº04-

7U000,1000,01

Table 1.9 Product Code (Flash Memory Version) - M16C/26T T-ver.

Table 1.10 Product Code (Flash Memory Version) - M16C/26T V-ver.

1. Overview

page 9

923fo7002,51.beF00.2.veR 0020-2020B90JER

)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

Figure 1.4 Marking Diagram (M16C/26A , M16C/26B)

0260F8A

A U3

XXXXX

(1) Flash memory version, PLQP0048KB-A (48P6Q), M16C/26A, M16C/26B

M30263F8AFP

A U3

XXXXXXX

(2) Flash memory version, PRSP0042GA-B (42P2R), M16C/26A, M16C/26B

0260M8A

001A U3

XXXXX

(3) MASK ROM version, PLQP0048KB-A (48P6Q), M16C/26A

M30263M8A-001FP

A U3

XXXXXXX

(4) MASK ROM version, PRSP0042GA-B (42P2R), M16C/26A

Product Name : indicates M30260F8AGP

Chip Version and Product Code:

A : Indicates chip version

The first edition is shown to be blank and continues

with A and B.

U3 : Indicates Product code (see Table 1.7 Product Code)

Date Code (5 digits) ﬁ indicates manufacturing management code

Product Name : indicates M30260M8AGP

ROM number, Chip Version and Product Code:

001: Indicates ROM Number

A : Indicates chip version

The first edition is shown to be blank and continues

with A and B.

U3 : Indicates Product code (see Table 1.8 Product Code)

Date Code (5 digits) ﬁ indicates manufacturing management code

Product Name : indicates M30263F8AFP

Chip Version and Product Code:

A : Indicates chip version

The first edition is shown to be blank and continues

with A and B.

U3 : Indicates Product code (see Table 1.7 Product Code)

Date Code (7 digits) ﬁ indicates manufacturing management code

Product Name and ROM number

M30263M8A and FP are indicated of Produnct name

001 is indicated of ROM number

Chip Version and Product Code:

A : Indicates chip version

The first edition is shown to be blank and continues

with A and B.

U3 : Indicates Product code (see Table 1.8 Product Code)

Date Code (7 digits) ﬁ indicates manufacturing management code

1. Overview

page 10

923fo7002,51.beF00.2.veR 0020-2020B90JER

)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

0260F8T

A U3

XXXXX

0260F8V

A U3

XXXXX

(1) Flash memory version, PLQP0048KB-A (48P6Q), M16C/26T T-ver.

(2) Flash memory version, PLQP0048KB-A (48P6Q), M16C/26T V-ver.

Product Name : indicates M30260F8VGP

Chip Version and Product Code:

A : Indicates chip version

The first edition is shown to be blank and continues

with A and B.

U3 : Indicates product code (see Table 1.10 Product Code)

Date Code (5 digits) ﬁ indicates manufacturing management code

Product Name : indicates M30260F8TGP

Chip Version and Product Code:

A : Indicates chip version

The first edition is shown to be blank and continues

with A and B.

U3 : Indicates product code (see Table 1.9 Product Code)

Date Code (5 digits) ﬁ indicates manufacturing management code

Figure 1.5 Marking Diagram (M16C/26T)

1. Overview

page 11

923fo7002,51.beF00.2.veR 0020-2020B90JER

)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

/TB2

/AN

/TB1

/AN

CNV

/INT

/IDU

/INT

/IDW

/INT

/AD

TRG

/IDV

P10

/AN

/KI

/TxD

/TA

0OUT

/SDA

/CTS

/RTS

/CTS

/CLKS

OUT

/NMI/SD

/TxD

/RxD

/CLK

RESET

/RxD

/TA0

/SCL

/CLK

/TA1

OUT

/V/RxD

/CTS

/RTS

/TA1

/V/TxD

/TA2

OUT

/TA2

/TA3

OUT

/TA3

/TA4

OUT

/TA4

/INT

/CTS

/RTS

/CTS

/CLKS

/TxD

/RxD

/CLK

/CTS

/RTS

/TB0

/AN

/CLK

OUT

CIN

COUT

P10

/AN

/KI

P10

/AN

/KI

P10

/AN

/KI

P10

/AN

P10

/AN

P10

/AN

P10

/AN

REF

/AN

/INT

/ZP

NOTE:

1. Set PACR2 to PACR0 bit in the PACR register

to "100

" before you input and output it after

resetting to each pin. When the PACR register

isn't set up, the input and output function of

some of the

ins are disabled.

Package: PLQP0048KB-A (48P6Q)

1.5 Pin Assignments

Figures 1.6 and 1.7 show the Pin Assignments (top view).

Figure 1.6 Pin Assignment for 48-Pin Package (Top View)

1. Overview

page 12

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)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

Table 1.11 Pin Characteristics for 48-Pin Package

niP .oN lortnoC niP troP tpurretnI niP niPremiTniPTRAUniPgolanA

19P

NI2

3NA

29P

NI1

3NA

39P

NI0

KLC

TUO

3NA

4ssVNC

NIC

TUOC

7TESER

TUO

9ssV

01X

11ccV

218P

IMNDS

318P

TNI

418P

TNI

518P

TNI

618P

NI4

718P

TUO4

817P

NI3

917P

TUO3

027P

NI2

127P

TUO2

227P

NI1

V/STC

STR/

327P

TUO1

V/KLC

427P

NI0

LCS/

KLC/

527P

TUO0

ADS/

STR/

STC/

SKLC/

626P

726P

826P

KLC

926P

STR

STC/

SKLC/

036P

136P

236P

KLC

336P

STR

STC/

431P

TNI

UDI

531P

TNI

WDI

631P

TNI

VDIDA

GRT

7301P

8301P

9301P

0401P

1401P

2401P

3401P

44ssVA

5401P

64V

FER

74ccVA

849P

2NA

1. Overview

page 13

923fo7002,51.beF00.2.veR 0020-2020B90JER

)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

RESET

AVSS

P100/AN0

VREF

XIN

XOUT

VSS

VCC

P86/XCOUT

P65/CLK1

P83/INT1

P82/INT0

P81/TA4IN/U

P80/TA4OUT/U

P77/TA3IN P76/TA3OUT

P75/TA2IN/W

P74/TA2OUT/W

P64/CTS1/RTS1/CTS0/CLKS1

P70/TxD2/SDA2/TA0OUT/CTS1/RTS1/CTS0/CLKS1

P71/RxD2/SCL2/TA0IN/CLK1

P72/CLK2/TA1OUT/V/RxD1

P73/CTS2/RTS2/TA1IN/V/TxD1

AVCC

P91/TB1IN/AN31

P90/TB0IN/AN30/CLKout

CNVSS

P87/XCIN

P66/RxD1

P67/TxD1

P85/NMI/SD

P84/INT2/ZP

P17/INT5/IDU

P16/INT4/IDW

P15/INT3/ADTRG/IDV

P107/AN7/KI3

P106/AN6/KI2

P105/AN5/KI1

P104/AN4/KI0

P103/AN3

P102/AN2

P101/AN1

NOTE:

1. Set PACR2 to PACR0 bit in the PACR register

to "001

" before you input and output it after

resetting to each pin. When the PACR register

isn't set up, the input and output function of

some of the

ins are disabled.

Package: PRSP0042GA-B (42P2R)

Figure 1.7 Pin Assignment for 42-Pin Package (Top View)

1. Overview

page 14

923fo7002,51.beF00.2.veR 0020-2020B90JER

)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

Table 1.12 Pin Characteristics for 42-Pin Package

niP .oN lortnoC niP troP tpurretnI niP niPremiTniPTRAUniPgolanA

1ssVA

201P

FER

4VA

59P

NI1

3NA

69P

NI0

KLC

TUO

3NA

7ssVNC

NIC

TUOC

01TESER

11X

TUO

21ssV

31X

41V

518P

IMNDS

618P

TNI

718P

TNI

818P

TNI

918P

NI4

028P

TUO4

127P

NI3

227P

TUO3

327P

NI2

427P

TUO2

527P

NI1

V/STC

STR/

627P

TUO1

V/KLC

727P

NI0

LCS/

KLC/

827P

TUO0

ADS/

STR/

STC/

SKLC/

926P

036P

136P

KLC

236P

STR

STC/

SKLC/

331P

TNI

UDI

431P

TNI

WDI

531P

TNI

VDIDA

GRT

6301P

7301P

8301P

9301P

0401P

1401P

2401P

1. Overview

page 15

923fo7002,51.beF00.2.veR 0020-2020B90JER

)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

1.6 Pin Description

Apply 0V to the Vss pin. Apply following voltage to the Vcc pin.

2.7 to 5.5 V (M16C/26A, M16C/26B), 3.0 to 5.5 V (M16C/26T T-ver.), 4.2

to 5.5 V (M16C/26T V-ver.)

Supplies power to the A/D converter. Connect the AVCC pin to VCC and

the AVSS pin to VSS ___________

The MCU is in a reset state when "L" is applied to the RESET pin

Connect the CNVSS pin to VSS

I/O pins for the main clock oscillation circuit. Connect a ceramic resonator

or crystal oscillator between XIN and XOUT. To apply external clock, apply

it to XIN and leave XOUT open. If XIN is not used (for external oscillator or

external clock), connect XIN pin to VCC and leave XOUT open

I/O pins for the sub clock oscillation circuit. Connect a crystal oscillator

between XCIN and XCOUT

Outputs the clock having the same frequency as f1, f8, f32, or fC

______ ________

Input pins for the INT interrupt. INT2 can be used for Timer A Z-phase

function

_______ _______

NMI

interrupt input pin.

NMI

cannot be used as I/O port while the three-phase

_______

motor control is enabled. Apply a stable "H" to NMI after setting it's direction

Input pins for the key input interrupt

I/O pins for the timer A0 to A4

Input pins for the timer A0 to A4

Input pin for Z-phase

Timer B0 to B1 input pins

Output pins for the three-phase motor control timer

I/O pins for the three-phase motor control timer

Input pins to control data transmission

Output pins to control data reception

Inputs and outputs the transfer clock

Inputs serial data

Outputs serial data

Output pin for transfer clock

Applies reference voltage to the A/D converter

Analog input pins for the A/D converter

Input pin for an external A/D trigger

I/O ports for CMOS. Each port can be programmed for input or output

under the control of the direction register. An input port can be set, by

program, for a pull-up resistor available or for no pull-up resister available

in 3-bit units

CMOS I/O ports which have a direction register determines an individual

pin used as an input port or an output port. A pull-up resistor is selectable

for every 4 input ports

VCC, VSS

AVCC

AVSS

____________

RESET

CNVSS

XIN

XOUT

XCIN

XCOUT

CLKOUT

________ ________

INT0 to INT5

_______

NMI

_____ _____

KI0 to KI3

TA0OUT to

TA4OUT

TA0IN to

TA4IN

TB0IN to

TB1IN

___ ___

U, U, V, V,

___

W, W

IDU, IDW,

_____

IDV, SD

_________ _________

CTS1 to CTS2

_________ _________

RTS1 to RTS2

CLK1 to CLK2

RxD1 to RxD2

TxD1 to TxD2

CLKS1

VREF

AN0 to AN7

AN3

to AN3

___________

ADTRG

P15 to P17

P64 to P67

P70 to P77

P80 to P87

P10

to P10

P90 to P91

Power Supply

Analog Power

Supply

Reset Input

CNVSS

Main Clock

Input

Main Clock

Output

Sub Clock Input

Sub Clock Output

Clock Output

______

INT Interrupt

Input

_______

NMI Interrupt

Input

Key Input Interrupt

Timer A

Timer B

Three-Phase

Motor Control

Timer Output

Serial I/O

Reference

Voltage Input

A/D Converter

I/O Ports

I/O

I : Input O : Output I/O : Input and output

Classification Pin Name I/O Type Description

Table 1.13 Pin Description (48-Pin and 42-Pin Packages)

1. Overview

page 16

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)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

Inputs pin to control data transmission

Output pin to control data reception

Inputs and outputs the transfer clock

Inputs serial data

Outputs serial data

Timer B2 input pin

Analog input pins for the A/D converter

CMOS I/O ports which have a direction register determines an individual

pin used as an input port or an output port. A pull-up resistor is selectable

for every 4 input ports

_________

CTS0

_________

RTS0

CLK0

RxD0

TxD0

TB2IN

AN24

AN32

P60 to P63

P92 to P93

Serial I/O

Timer B

A/D Converter

I/O Ports

I/O

Classification Pin Name I/O Type Description

Table 1.13 Pin Description ( 48-pin packages only) (Continued)

I : Input O : Output I/O : Input and output

2. CPU

page 17

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923fo7002,51.beF00.2.veR 0020-2020B90JER

2. Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. The register bank is comprised of seven registers (R0, R1, R2, R3,

A0, A1 and FB) out of 13 registers. There are two sets of register bank.

Figure 2.1. CPU Register

2.1 Data Registers (R0, R1, R2 and R3)

The R0 register consists of 16 bits, and is used mainly for transfers and arithmetic/logic operations. R1 to

R3 are the same as R0.

The R0 register can be separated between high (R0H) and low (R0L) for use as two 8-bit data registers.

R1H and R1L are the same as R0H and R0L. Conversely, R2 and R0 can be combined for use as a 32-bit

data register (R2R0). R3R1 is the same as R2R0.

2.2 Address Registers (A0 and A1)

The register A0 consists of 16 bits, and is used for address register indirect addressing and address regis-

ter relative addressing. They also are used for transfers and arithmetic/logic operations. A1 is the same as

A0.

In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).

Data registers (1)

Address registers (1)

Frame base registers (1)

Program counter

Interrupt table register

User stack pointer

Interrupt stack pointer

Static base register

Flag register

NOTE:

1. These registers comprise a register bank. There are two register banks.

R0H(R0's high bits)

b15 b8 b7 b0

INTBH

USP

ISP

R0L(R0's low bits)

R1H(R1's high bits)R1L(R1's low bits)

b31

b19

INTBL

b15 b0

b19 b0

b15 b0

FLG

b15 b0

b15

Reserved area

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved area

Processor interrupt priority level

The upper 4 bits of INTB are INTBH and

the lower 16 bits of INTB are INTBL.

2. CPU

page 18

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923fo7002,51.beF00.2.veR 0020-2020B90JER

2.3 Frame Base Register (FB)

FB is configured with 16 bits, and is used for FB relative addressing.

2.4 Interrupt Table Register (INTB)

INTB is configured with 20 bits, indicating the start address of an interrupt vector table.

2.5 Program Counter (PC)

PC is configured with 20 bits, indicating the address of an instruction to be executed.

2.6 User Stack Pointer (USP) and Interrupt Stack Pointer (ISP)

Stack pointer (SP) comes in two types: USP and ISP, each configured with 16 bits.

Your desired type of stack pointer (USP or ISP) can be selected by the U flag of FLG.

2.7 Static Base Register (SB)

SB is configured with 16 bits, and is used for SB relative addressing.

2.8 Flag Register (FLG)

FLG consists of 11 bits, indicating the CPU status.

2.8.1 Carry Flag (C Flag)

This flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit.

2.8.2 Debug Flag (D Flag)

The D flag is used exclusively for debugging purpose. During normal use, it must be set to 0.

2.8.3 Zero Flag (Z Flag)

This flag is set to 1 when an arithmetic operation resulted in 0; otherwise, it is 0.

2.8.4 Sign Flag (S Flag)

This flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, it is 0.

2.8.5 Register Bank Select Flag (B Flag)

2.8.6 Overflow Flag (O Flag)

This flag is set to 1 when the operation resulted in an overflow; otherwise, it is 0.

2.8.7 Interrupt Enable Flag (I Flag)

This flag enables a maskable interrupt.

Maskable interrupts are disabled when the I flag is 0, and are enabled when the I flag is 1.

The I flag is cleared to 0 when the interrupt request is accepted.

2.8.8 Stack Pointer Select Flag (U Flag)

ISP is selected when the U flag is 0; USP is selected when the U flag is 1.

The U flag is cleared to 0 when a hardware interrupt request is accepted or an INT instruction for software

interrupt Nos. 0 to 31 is executed.

2.8.9 Processor Interrupt Priority Level (IPL)

IPL is configured with three bits, for specification of up to eight processor interrupt priority levels from level

0 to level 7.

If a requested interrupt has priority greater than IPL, the interrupt is enabled.

2.8.10 Reserved Area

When write to this bit, write 0. When read, its content is undefined.

3. Memory

page 19

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923fo7002,51.beF00.2.veR 0020-2020B90JER

3. Memory

Figure 3.1 is a memory map of the M16C/26A Group (M16C/26A, M16C/26B, M16C/26T). The M16C/26A

Group provides 1-Mbyte address space addresses 0000016 to FFFFF16.

The internal ROM is allocated lower address, beginning with address FFFFF16. For example, a 64-Kbyte

internal ROM area is allocated in addresses F000016 to FFFFF16. The flash memory version has two sets

of 2-Kbyte internal ROM area, block A and block B, for data space. These blocks are allocated addresses

F00016 to FFFF16.

The fixed interrupt vectors are allocated addresses FFFDC16 to FFFFF16 and they store the start address

of each interrupt routine.

The internal RAM is allocated higher addresses, beginning with address 0040016. For example, a 1-Kbyte

internal RAM area is allocated in addresses 0040016 to 007FF16. The internal RAM is used for temporarily

storing data. The area is also used as stacks when subroutines are called or interrupt requests are ac-

knowledged.

The SFR is allocated addresses 0000016 to 003FF16. The peripheral function control registers are allo-

cated here. All blank spaces within SFR location are reserved and cannot be accessed by users.

The special page vectors are allocated addresses FFE0016 to FFFDB16. They are used for the JMPS

instruction and JSRS instruction. Refer to the Renesas publication M16C/60 and M16C/20 Series Soft-

ware Manual for details.

Figure 3.1 Memory Map

0000016

XXXXX16

Internal ROM

(Data space)

Internal ROM

(Program space)

SFR

Internal RAM

Reserved

FFE0016

FFFDC16

FFFFF16

NOTE:

1. Block A (2 Kbytes) and block B (2 Kbytes).

2. Do not write to the internal ROM in Mask ROM version.

Undefined instruction

Overflow

BRK instruction

Address match

Single step

Watchdog timer

Reset

Special page

vector table

DBC

NMI

1K bytes 007FF16

00BFF16

Address XXXXX16

2K bytes

Size Address YYYYY16Size

F400016

FA00016

48K bytes

24K bytes

Reserved

0040016

0F00016

0FFFF16

YYYYY16

FFFFF16

(1)

F000016

64K bytes

Internal RAM Internal ROM

(2)

4. SFRs

page 20

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923fo7002,51.beF00.2.veR 0020-2020B90JER

4. Special Function Registers (SFRs)

Table 4.1 SFR Information(1)(1)

Processor mode register 0 PM0 00

Processor mode register 1 PM1 00001000

System clock control register 0 CM0 01001000

(5)

01101000

2(M16C/26T)

System clock control register 1 CM1 00100000

Address match interrupt enable register AIER XXXXXX00

Protect register PRCR XX000000

Oscillation stop detection register(2) CM2 0X000000

Watchdog timer start register WDTS XX

Watchdog timer control register WDC 00XXXXXX

Address match interrupt register 0 RMAD0 00

Address match interrupt register 1 RMAD1 00

Voltage detection register 1 (3, 4) VCR1 00001000

Voltage detection register 2 (3, 4) VCR2 00

PLL control register 0 PLC0 0001X010

Processor mode register 2 PM2 XXX00000

Low voltage detection interrupt register(4) D4INT 00

DMA0 source pointer SAR0 XX

DMA0 destination pointer DAR0 XX

DMA0 transfer counter TCR0 XX

DMA0 control register DM0CON 00000X00

DMA1 source pointer SAR1 XX

DMA1 destination pointer DAR1 XX

DMA1 transfer counter TCR1 XX

DMA1 control register DM1CON 00000X00

NOTES:

1. The blank spaces are reserved. No access is allowed.

2. Bits CM27, CM21, and CM20 do not change at oscillation stop detection reset.

3. The VCR1 and VCR2 registers do not change at software reset, watchdog timer reset, and oscillation stop detection reset.

4. Registers VCR1, VCR2, and D4INT cannot be used in M16C/26T.

5. M16C/26A, M16C/26B

X : Undefined

0000

0001

0002

0003

0004

0005

0006

0007

0008

0009

000A

000B

000C

000D

000E

000F

0010

0011

0012

0013

0014

0015

0016

0017

0018

0019

001A

001B

001C

001D

001E

001F

0020

0021

0022

0023

0024

0025

0026

0027

0028

0029

002A

002B

002C

002D

002E

002F

0030

0031

0032

0033

0034

0035

0036

0037

0038

0039

003A

003B

003C

003D

003E

003F

Address

4. SFRs

page 21

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923fo7002,51.beF00.2.veR 0020-2020B90JER

NOTE:

1. Blank spaces are reserved. No access is allowed.

X: Undefined

004016

004116

004216

004316

004416

004516

004616

004716

004816

004916

004A16

004B16

004C16

004D16

004E16

004F16

005016

005116

005216

005316

005416

005516

005616

005716

005816

005916

005A16

005B16

005C16

005D16

005E16

005F16

006016

006116

006216

006316

006416

006516

006616

006716

006816

006916

006A16

006B16

006C16

006D16

006E16

006F16

007016

007116

007216

007316

007416

007516

007616

007716

007816

007916

007A16

007B16

007C16

007D16

007E16

007F16

Address Register Symbol After reset

INT3 interrupt control register INT3IC XX00X000

INT5 interrupt control register INT5IC XX00X000

INT4 interrupt control register INT4IC XX00X000

UART2 Bus collision detection interrupt control register BCNIC XXXXX000

DMA0 interrupt control register DM0IC XXXXX000

DMA1 interrupt control register DM1IC XXXXX000

Key input interrupt control register KUPIC XXXXX000

A/D conversion interrupt control register ADIC XXXXX000

UART2 transmit interrupt control register S2TIC XXXXX000

UART2 receive interrupt control register S2RIC XXXXX000

UART0 transmit interrupt control register S0TIC XXXXX000

UART0 receive interrupt control register S0RIC XXXXX000

UART1 transmit interrupt control register S1TIC XXXXX000

UART1 receive interrupt control register S1RIC XXXXX000

TimerA0 interrupt control register TA0IC XXXXX000

TimerA1 interrupt control register TA1IC XXXXX000

TimerA2 interrupt control register TA2IC XXXXX000

TimerA3 interrupt control register TA3IC XXXXX000

TimerA4 interrupt control register TA4IC XXXXX000

TimerB0 interrupt control register TB0IC XXXXX000

TimerB1 interrupt control register TB1IC XXXXX000

TimerB2 interrupt control register TB2IC XXXXX000

INT0 interrupt control register INT0IC XX00X000

INT1 interrupt control register INT1IC XX00X000

INT2 interrupt control register INT2IC XX00X000

Table 4.2 SFR Information(2)(1)

4. SFRs

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008016

008116

008216

008316

008416

008516

008616

01B016

01B116

01B216

01B316

01B416

01B516

01B616

01B716

01B816

01B916

01BA16

01BB16

01BC16

01BD16

01BE16

01BF16

025016

025116

025216

025316

025416

025516

025616

025716

025816

025916

025A16

025B16

025C16

025D16

025E16

025F16

033016

033116

033216

033316

033416

033516

033616

033716

033816

033916

033A16

033B16

033C16

033D16

033E16

033F16

NOTES:

1. Blank spaces are reserved. No access is allowed.

2. This register is included in the flash memory version.

X: Undefined

Address Register Symbol After reset

Flash memory control register 4 (2) FMR4 010000002

Flash memory control register 1 (2) FMR1 000XXX0X2

Flash memory control register 0 (2) FMR0 0116

Three phase protect control register TPRC 0016

On-chip oscillator control register ROCR X00001012

Pin assignment control register PACR 0016

Peripheral clock select register PCLKR 000000112

NMI digital debounce register NDDR FF16

Port17 digital debounce register P17DDR FF16

Table 4.3 SFR Information(3)(1)

4. SFRs

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Address Register Symbol After reset

034016

034116

034216

034316

034416

034516

034616

034716

034816

034916

034A16

034B16

034C16

034D16

034E16

034F16

035016

035116

035216

035316

035416

035516

035616

035716

035816

035916

035A16

035B16

035C16

035D16

035E16

035F16

036016

036116

036216

036316

036416

036516

036616

036716

036816

036916

036A16

036B16

036C16

036D16

036E16

036F16

037016

037116

037216

037316

037416

037516

037616

037716

037816

037916

037A16

037B16

037C16

037D16

037E16

037F16

NOTE:

1. Blank spaces are reserved. No access is allowed.

2. Write "1" to bit 0 after reset.

X : Undefined

Timer A1-1 register TA11 XX16

XX16

Timer A2-1 register TA21 XX16

XX16

Timer A4-1 register TA41 XX16

XX16

Three phase PWM control register 0 INVC0 0016

Three phase PWM control register 1 INVC1 0016

Three phase output buffer register 0 IDB0 001111112

Three phase output buffer register 1 IDB1 001111112

Dead time timer DTT XX16

Timer B2 Interrupt occurrence frequency set counter ICTB2 XX16

Position-data-retain function control register PDRF XXXX00002

Port function control register PFCR 001111112

Interrupt request cause select register 2 IFSR2A XXXXXXX02

(2)

Interrupt request cause select register IFSR 0016

UART2 special mode register 4 U2SMR4 0016

UART2 special mode register 3 U2SMR3 000X0X0X2

UART2 special mode register 2 U2SMR2 X00000002

UART2 special mode register U2SMR X00000002

UART2 transmit/receive mode register U2MR 0016

UART2 bit rate register U2BRG XX16

UART2 transmit buffer register U2TB XXXXXXXX2

XXXXXXXX2

UART2 transmit/receive control register 0 U2C0 000010002

UART2 transmit/receive control register 1 U2C1 000000102

UART2 receive buffer register U2RB XXXXXXXX2

XXXXXXXX2

Table 4.4 SFR Information(4)(1)

4. SFRs

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Table 4.5 SFR Information(5)(1)

038016

038116

038216

038316

038416

038516

038616

038716

038816

038916

038A16

038B16

038C16

038D16

038E16

038F16

039016

039116

039216

039316

039416

039516

039616

039716

039816

039916

039A16

039B16

039C16

039D16

039E16

039F16

03A016

03A116

03A216

03A316

03A416

03A516

03A616

03A716

03A816

03A916

03AA16

03AB16

03AC16

03AD16

03AE16

03AF16

03B016

03B116

03B216

03B316

03B416

03B516

03B616

03B716

03B816

03B916

03BA16

03BB16

03BC16

03BD16

03BE16

03BF16

NOTE:

1. Blank spaces are reserved. No access is allowed.

X : Undefined

Address Register Symbol After reset

Count start flag TABSR 00

Clock prescaler reset flag CPSRF 0XXXXXXX

One-shot start flag ONSF 00

Trigger select register TRGSR 00

Up-dowm flag UDF 00

Timer A0 register TA0 XX

Timer A1 register TA1 XX

Timer A2 register TA2 XX

Timer A3 register TA3 XX

Timer A4 register TA4 XX

Timer B0 register TB0 XX

Timer B1 register TB1 XX

Timer B2 register TB2 XX

Timer A0 mode register TA0MR 00

Timer A1 mode register TA1MR 00

Timer A2 mode register TA2MR 00

Timer A3 mode register TA3MR 00

Timer A4 mode register TA4MR 00

Timer B0 mode register TB0MR 00XX0000

Timer B1 mode register TB1MR 00XX0000

Timer B2 mode register TB2MR 00XX0000

Timer B2 special mode register TB2SC X0000000

UART0 transmit/receive mode register U0MR 00

UART0 bit rate register U0BRG XX

UART0 transmit buffer register U0TB XXXXXXXX

XXXXXXXX

UART0 transmit/receive control register 0 U0C0 00001000

UART0 transmit/receive control register 1 U0C1 00000010

UART0 receive buffer register U0RB XXXXXXXX

XXXXXXXX

UART1 transmit/receive mode register U1MR 00

UART1 bit rate register U1BRG XX

UART1 transmit buffer register U1TB XXXXXXXX

XXXXXXXX

UART1 transmit/receive control register 0 U1C0 00001000

UART1 transmit/receive control register 1 U1C1 00000010

UART1 receive buffer register U1RB XXXXXXXX

XXXXXXXX

UART transmit/receive control register 2 UCON X0000000

CRC snoop address register CRCSAR XX

00XXXXXX

CRC mode register CRCMR 0XXXXXX0

DMA0 request cause select register DM0SL 00

DMA1 request cause select register DM1SL 00

CRC data register CRCD XX

CRC input register CRCIN XX

4. SFRs

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Table 4.6 SFR Information(6)(1)

03C0

03C1

03C2

03C3

03C4

03C5

03C6

03C7

03C8

03C9

03CA

03CB

03CC

03CD

03CE

03CF

03D0

03D1

03D2

03D3

03D4

03D5

03D6

03D7

03D8

03D9

03DA

03DB

03DC

03DD

03DE

03DF

03E0

03E1

03E2

03E3

03E4

03E5

03E6

03E7

03E8

03E9

03EA

03EB

03EC

03ED

03EE

03EF

03F0

03F1

03F2

03F3

03F4

03F5

03F6

03F7

03F8

03F9

03FA

03FB

03FC

03FD

03FE

03FF

NOTE:

1. Blank spaces are reserved. No access is allowed.

X: Undefined

A/D register 0 AD0 XXXXXXXX

XXXXXXXX

A/D register 1 AD1 XXXXXXXX2

XXXXXXXX

A/D register 2 AD2 XXXXXXXX

XXXXXXXX

A/D register 3 AD3 XXXXXXXX

XXXXXXXX

A/D register 4 AD4 XXXXXXXX

XXXXXXXX

A/D register 5 AD5 XXXXXXXX

XXXXXXXX

A/D register 6 AD6 XXXXXXXX

XXXXXXXX

A/D register 7 AD7 XXXXXXXX

XXXXXXXX

A/D trigger control register ADTRGCON 00

A/D status register 0 ADSTAT0 00000X00

A/D control register 2 ADCON2 00

A/D control register 0 ADCON0 00000XXX

A/D control register 1 ADCON1 00

Port P1 register P1 XX

Port P1 direction register PD1 00

Port P6 register P6 XX

Port P7 register P7 XX

Port P6 direction register PD6 00

Port P7 direction register PD7 00

Port P8 register P8 XX

Port P9 register P9 XXXXXXXX

Port P8 direction register PD8 00

Port P9 direction register PD9 XXXX0000

Port P10 register P10 XX

Port P10 direction register PD10 00

Pull-up control register 0 PUR0 00

Pull-up control register 1 PUR1 00

Pull-up control register 2 PUR2 00

Port control register PCR 00

Address

5. Reset

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5. Reset

There are four types of resets: a hardware reset, a software reset, an watchdog timer reset, and an oscilla-

tion stop detection reset.

5.1 Hardware Reset

There are two types of hardware resets: a hardware reset 1 and a hardware reset 2.

5.1.1 Hardware Reset 1 ____________ ____________

A reset is applied using the RESET pin. When an “L” signal is applied to the RESET pin while the

power supply voltage is within the recommended operating condition, the pins are initialized (see

____________

Table 5.1.1.1 Pin Status When RESET Pin Level is “L”). The internal on-chip oscillator is initialized

and used as CPU clock. ____________

When the input level at the RESET pin is released from “L” to “H”, the CPU and SFR are initialized,

and the program is executed starting from the address indicated by the reset vector. The internal RAM

____________

is not initialized. If the RESET pin is pulled “L” while writing to the internal RAM, the internal RAM

becomes indeterminate.

Figure 5.1.1.1 shows the example reset circuit. Figure 5.1.1.2 shows the reset sequence. Table

____________

5.1.1.1 shows the status of the other pins while the RESET pin is “L”. Figure 5.1.1.3 shows the CPU

1. When the power supply is stable

____________

(1) Apply an “L” signal to the RESET pin.

(2) Wait td(ROC) or more. ____________

(3) Apply an “H” signal to the RESET pin.

2. Power on ____________

(1) Apply an “L” signal to the RESET pin.

(2) Let the power supply voltage increase until it meets the recommended operating condition.

(3) Wait td(P-R) or more until the internal power supply stabilizes.

(4) Wait td(ROC) or more. ____________

(5) Apply an “H” signal to the RESET pin.

5.1.2 Hardware Reset 2

Note

M16C/26T does not use this function.

This reset is generated by the microcomputer’s internal voltage detection circuit. The voltage detec-

tion circuit monitors the voltage supplied to the VCC pin.

If the VC26 bit in the VCR2 register is set to “1” (reset level detection circuit enabled), the microcom-

puter is reset when the voltage at the VCC input pin drops below Vdet3.

Conversely, when the input voltage at the VCC pin rises to Vdet3r or more, the pins and the CPU and

SFR are initialized, and the program is executed starting from the address indicated by the reset

vector. It takes about td(S-R) before the program starts running after Vdet3r is detected. The initialized

pins and registers and the status thereof are the same as in hardware reset 1.

The microcomputer cannot exit stop mode by voltage down detection reset (hardware reset 2).

5. Reset

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5.2 Software Reset

When the PM03 bit in the PM0 register is set to “1” (microcomputer reset), the microcomputer has its pins,

CPU, and SFR initialized. Then the program is executed starting from the address indicated by the reset

vector.

The device will reset using on-chip oscillator as the CPU clock.

At software reset, some SFR’s are not initialized. Refer to “SFR”.

5.3 Watchdog Timer Reset

When the PM12 bit in the PM1 register is “1” (reset when watchdog timer underflows), the microcomputer

initializes its pins, CPU and SFR if the watchdog timer underflows.

The device will reset using on-chip oscillator as the system clock. Then the program is executed starting

from the address indicated by the reset vector.

At watchdog timer reset, some SFR’s are not initialized. Refer to “SFR”.

5.4 Oscillation Stop Detection Reset

When the CM20 bit in the CM2 register is set to “1”(oscillation stop, re-oscillation detection function

enabled) and the CM27 bit is set to “0” (reset at oscillation stop detection), the microcomputer initializes

its pins, CPU and SFR, coming to a halt if it detects main clock oscillation circuit stop. Refer to the section

“oscillation stop, re-oscillation detection function”.

At oscillation stop detection reset, some SFR’s are not initialized. Refer to the section “SFR”.

Figure 5.1.1.1. Example Reset Circuit

RESET V

RESET

More than td(ROC) + td(P-R)

Equal to or less

than 0.2V

Equal to or less

than 0.2V

Recommended

operating

voltage

5. Reset

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____________

Table 5.1.1.1. Pin Status When RESET Pin Level is “L”

Status

Pin name

P1, P6 to P10 Input port (high impedance)

Figure 5.1.1.3. CPU Register Status After Reset

b15 b0

Data register(R0)

Address register(A0)

Frame base register(FB)

Program counter(PC)

Interrupt table register(INTB)

User stack pointer(USP)

Interrupt stack pointer(ISP)

Static base register(SB)

Flag register(FLG)

0000

AAAAAA

CDZSBOIU

IPL

0000

b19 b0

Content of addresses FFFFE

to FFFFC

b15 b0

b7 b8

00000

Data register(R1)

Data register(R2)

Data register(R3)

Address register(A1)

0000

Figure 5.1.1.2. Reset Sequence

td(P-R) More than

td(ROC)

CPU clock

Address

ROC

RESET

Content of reset vector

CPU clock

28 cycles

FFFFE

FFFFC

5. Reset

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Figure 5.5.1. Voltage Detection Circuit Block

b7 b6

VCR2 Register

RESET

CM10 Bit=1

(Stop Mode)

>Vdet3

>Vdet4

ENoise Rejection Low Voltage

Detect Signal

VCR1 Register

VC13 Bit

1 shot

Internal Reset Signal

(“L” active)

VCC

td(S-R)

Brown-out Detect Reset

(Hardware Reset 2

Release Wait Time)

Reset level

detection circuit

Low voltage

detection circuit

5.5 Voltage Detection Circuit

Note

VCC=5 V is assumed. Voltage Detection Circuit is not available in M16C/26T.

The voltage detection circuit has circuits to monitor the input voltage at the VCC pin, each checking the input

voltage with respect to Vdet3, and Vdet4, respectively. Use the VC26 to VC27 bits in the VCR2 register to

select whether or not to enable these circuits.

Use the reset level detection circuit for hardware reset 2.

The voltage down detection circuit can be set to detect whether the input voltage is equal to or greater than

Vdet4 or less than Vdet4 by monitoring the VC13 bit in the VCR1 register. Furthermore, a voltage down

detection interrupt can be generated.

5. Reset

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Figure 5.5.2. VCR1 Register, VCR2 Register, and D4INT Register

VC13

(

(1)

Bit name F unction

lRW

b7 b6 b

0:V

< Vdet4

1:V

≥ Vdet4 RO

0000 000

“

”

“

”

(1)

(5)

b7 b6 b

VC27

00000

Reserved bit Must set to “0”

Reset level monitor bit

(2, 3, 6) 0

Voltage down monitor

bit (4, 6) 0: Disable voltage down

detection circuit

1: Enable voltage down

detection circuit

(

)

(

)

(

)

NOTES:

1. The VC13 bit is useful when the VC27 bit in the VCR2 register is set to "1" (voltage down detection circuit

enable). The VC13 bit is always "1" (VCC ≥ Vdet4) when the VC27 bit in the VCR2 register is set to "0"

(voltage down detection circuit disable).

2. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.

NOTES:

1. Write to this register after setting the PRC3 bit in the PRCR register to “1” (write enable).

2. When not in stop mode, to use hardware reset 2, set the VC26 bit to “1” (reset level detection circuit enable).

3. VC26 bit is disabled in stop mode. (The microcomputer is not reset even if the voltage input to Vcc pin

becomes lower than Vdet3.)

4. When the VC13 bit in the VCR1 register and D42 bit in the D4INT register are used or the D40 bit is set to

“1” (voltage down detection interrupt enable), set the VC27 bit to “1” (voltage down detection circuit enable).

5. This register does not change at software reset, watchdog timer reset and oscillation stop detection reset.

6. The detection circuit does not start operation until td(E-A) elapses after the VC26 bit, or VC27 bit are set to

“1”.

(1)

interrupt enable bit (5)

Bit name

0 :

Disable

1 :

Enable

STOP mode deactivation

control bit

(4)

(

)

(

)

Voltage change detection flag

(2) 0: Not detected

1: Vdet4 passing detection

D43

WDT overflow detect flag 0

DF0

Sampling clock select bit

(b7-b6)

Function

Nothing is assigned. When write, set to “0”. When read, its

content is “0”.

NOTES:

1. Write to this register after setting the PRC3 bit in the PRCR register to “1” (write enable).

2. Useful when the VC27 bit in the VCR2 register is set to “1” (voltage down detection circuit enabled). If the

VC27 bit is set to “0” (voltage down detection circuit disable), the D42 bit is set to “0” (Not detect).

3. This bit is set to “0” by writing a “0” in a program. (Writing a “1” has no effect.)

4. If the voltage down detection interrupt needs to be used to get out of stop mode again after once used for

that purpose, reset the D41 bit by writing a “0” and then a “1”.

5. The D40 bit is effective when the VC27 bit in the VCR2 register is set to “1”. To set the D40 bit to “1”, follow

the procedure described below.

(1) Set the VC27 bit to “1”.

(2) Wait for td(E-A) until the detection circuit is actuated.

(3) Wait for the sampling time (refer to “Table 5.5.1.2 Sampling Clock Periods”).

(4) Set the D40 bit to “1”.

(3)

5. Reset

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Figure 5.5.3. Typical Operation of Hardware Reset 2

Vdet4

Vdet3

5.0V 5.0V

VCC

Internal Reset Signal

VC13 bit in

VCR1 register

VC26 bit in

VCR2 register

(1)

VC27 bit in

VCR2 register

Set to “1” by program (reset level detect circuit enable)

Set to “1” by program

(voltage down detect circuit enable)

VSS

Indefinite

RESET

Vdet3s

Vdet3r

NOTES :

1. VC26 bit is invalid (the microcomputer is not reset even if input voltage of VCC pin

becomes lower than Vdet3).

5. Reset

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5.5.1 Voltage Down Detection Interrupt

If the D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled), the voltage

down detection interrupt request is generated when the voltage applied to the VCC pin crosses the

Vdet4 voltage level. The voltage down detection interrupt shares the same interrupt vector with the

watchdog timer interrupt and oscillation stop, re-oscillation detection interrupt.

Set the D41 bit in the D4INT register to “1” (enabled) to use the voltage down detection interrupt to exit

stop mode.

The D42 bit in the D4INT register is set to “1” as soon as the voltage applied to the VCC pin reaches

Vdet4 due to the voltage rise and voltage drop. When the D42 bit changes “0” to “1”, the voltage down

detection interrupt request is generated. Set the D42 bit to “0” by program. However, when the D41

bit is set to “1” and the microcomputer is in stop mode, the voltage down detection interrupt request is

generated regardless of the D42 bit state if the voltage applied to the VCC pin is detected to be above

Vdet4. The microcomputer then exits stop mode.

Table 5.5.1.1 shows how the voltage down detection interrupt request is generated.

The DF1 to DF0 bits in the D4INT register determine the sampling period that detects the voltage

applied to the VCC pin reaches Vdet4. Table 5.5.1.2 shows the sampling periods.

CPU

Clock

(MHz) DF1 to DF0=00

(CPU clock divided by 8)

Sampling Period (µs)

16 3.0 6.0 12.0 24.0

DF1 to DF0=01

(CPU clock divided by 16) DF1 to DF0=10

(CPU clock divided by 32) DF1 to DF0=11

(CPU clock divided by 64)

Table 5.5.1.1 Voltage Down Detection Interrupt Request Generation Conditions

D41 BitVC27 BitOperation Mode D40 Bit D42 Bit CM02 Bit VC13 Bit

Normal

Operation

Mode(1)

Wait Mode(2)

Stop Mode(2)

NOTES:

1. The status except the wait mode and stop mode is handled as the normal mode.(Refer to 7. Clock generating circuit)

2. Refer to 5.5.2 Limitations on stop mode, 5.5.3 Limitations on wait mode.

3. An interrupt request for voltage reduction is generated a sampling time after the value of the VC13 bit has changed.

See the Figure 5.5.1.2 Voltage Down Detection Interrupt Generation Circuit Operation Example for details.

0 to 1(3)

1 to 0(3)

0 to 1(3)

1 to 0(3)

0 to 1

– : “0”or “1”

Table 5.5.1.2 Sampling Periods

5. Reset

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Figure 5.5.1.1 Power Supply Down Detection Interrupt Generation Block

Figure 5.5.1.2 Power Supply Down Detection Interrupt Generation Circuit Operation Example

Output of the digital filter

(2)

D42 bit in D4INT register

NOTES :

1. D40 bit in the D4INT register is set to “1” (voltage down

detection interrupt enabled).

2. Output of the digital filter is shown in Figure 5.5.1.1.

Voltage down

detection

interrupt signal

No voltage down detection interrupt signals are

generated when the D42 bit is “1”.

sampling

VC13 bit in VCR1 register

VCC

sampling sampling sampling

Set to “0” by program (not detected)

Voltage down detection interrupt generation circuit

Watchdog

timer interrupt

signal

VC27

VC13

Voltage Down Detection Circuit

D4INT clock(the

clock with which it

operates also in

wait mode)

D42

DF1, DF0

1/2

00b

01b

10b

11b

1/2

1/21/8

Non-maskable

interrupt signal

Oscillation stop,

re-oscillation

detection

interrupt signal

Voltage down

detection

interrupt signal

Watchdog Timer Block

This bit is set to “0”(not detected) by program.

Watchdog timer

underflow signal

D43

D41

CM02

WAIT instruction(wait mode)

D40

VCC

VREF

Noise

Rejection

(Rejection Range:200 ns)

Voltage down

detection signal

The Voltage down detection

signal becomes “H” when the

VC27 bit is set to “0” (disabled)

Noise Rejection

Circuit Digital

Filter

CM10

The D42 bit is set to “0” (not detected)

by program. the VC27 bit is set to “0”

(voltage down detect circuit disabled),

the D42 bit is set to “0”.

5. Reset

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5.5.2 Limitations on Exiting Stop Mode

The voltage down detection interrupt is immediately generated and the microcomputer exits stop

mode if the CM10 bit in the CM1 register is set to “1” under the conditions below.

• the VC27 bit in the VCR2 register is set to “1” (voltage down detection circuit enabled),

• the D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled),

• the D41 bit in the D4INT register is set to “1” (voltage down detection interrupt is used to exit stop

mode), and

• the voltage applied to the VCC pin is higher than Vdet4 (the VC13 bit in the VCR1 register is “1”)

If the microcomputer is set to enter stop mode when the voltage applied to the VCC pin drops below

Vdet4 and to exit stop mode when the voltage applied rises to Vdet4 or above, set the CM10 bit to “1”

when VC13 bit is “0” (VCC < Vdet4).

5.5.3 Limitations on Exiting Wait Mode

The voltage down detection interrupt is immediately generated and the microcomputer exits wait

mode If WAIT instruction is executed under the conditions below.

• the CM02 bit in the CM0 register is set to “1” (stop peripheral function clock),

• the VC27 bit in the VCR2 register is set to “1” (voltage down detection circuit enabled),

• the D40 bit in the D4INT register is set to “1” (voltage down detection interrupt enabled),

• the D41 bit in the D4INT register is set to “1” (voltage down detection interrupt is used to exit wait

mode), and

• the voltage applied to the VCC pin is higher than Vdet4 (the VC13 bit in the VCR1 register is “1”)

If the microcomputer is set to enter wait mode when the voltage applied to the VCC pin drops below

Vdet4 and to exit wait mode when the voltage applied rises to Vdet4 or above, perform WAIT instruc-

tion when VC13 bit is “0” (VCC < Vdet4).

6. Processor Mode

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6. Processor Mode

The microcomputer supports single-chip mode only. Figures 6.1 and 6.2 show the associated registers.

Figure 6.1 PM0 Register, PM1 Register

Processor Mode Register 0 (1)

Symbol Address After Reset

PM0 000416 0016

Bit Name FunctionBit Symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

The microcomputer is reset when

this bit is set to "1". When read,

its content is "0".

Software reset bitPM03

NOTES:

1. Rewrite the PM0 register after the PRC1 bit in the PRCR register is set to "1" (write enable).

Set to "0"

(b2-b0) Reserved bit

Set to "0"

(b7-b4) Reserved bit

0000000

Processor Mode Register 1 (1)

Symbol Address After Reset

PM1 000516 000010002

Bit Name FunctionBit Symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

Flash data block access

bit

(2)

0: Disabled

1: Enabled

(3)

PM10

PM17 Wait bit

(5)

0 : No wait state

1 : Wait state (1 wait)

0 : Watchdog timer interrupt

1 : Watchdog timer reset

(4)

Watchdog timer function

select bit

PM12

NOTES:

1. Rewrite the PM1 register after the PRC1 bit in the PRCR register is set to "1" (write enable).

2. To access the two 2K-byte data spaces in data block A and data block B, set the PM10 bit to "1". The PM10

bit is not available in mask version.

3. When the FMR01 bit in the FMR0 register is set to "1" (enables CPU rewrite mode), the PM10 bit is

automatically set to "1".

4. Set the PM12 bit to "1" by program. (Writing "0" by program has no effect)

5. When the PM17 bit is set to "1" (wait state), one wait is inserted when accessing the internal RAM or the

internal ROM.

Set to "0"

(b1) Reserved bit

Set to "1"Reserved bit

Set to "0"

(b6-b4) Reserved bit

(b3)

010

6. Processor Mode

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Figure 6.2 PM2 Register

Function

Bit Symbol Bit Name

Processeor Mode Register 2

(1)

Symbol Address After Reset

PM2 001E16 XXX000002

b7 b6 b5 b4 b3 b2 b1 b0

PM20

PM21 System clock protective bit

(3,4)

(b7-b5)

PM22

PM24

(b3) Reserved bit Set to “0”RW

NOTES:

1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable).

2. The PM20 bit become effective when PLC07 bit in the PLC0 register is set to "1" (PLL on). Change the PM20 bit

when the PLC07 bit is set to "0" (PLL off). Set the PM20 bit to "0" (2 waits) when PLL clock > 16 MHz.

3. Once this bit is set to “1”, it cannot be set to “0” by program.

4. Writing to the following bits has no effect when the PM21 bit is set to “1”:

CM02 bit in the CM0 register

CM05 bit in the CM0 register (main clock is not halted)

CM07 bit in the CM0 register (CPU clock source does not change)

CM10 bit in the CM1 register (stop mode is not entered)

CM11 bit in the CM1 register (CPU clock source does not change)

CM20 bit in the CM2 register (oscillation stop, re-oscillation detection function settings do not change)

All bits in the PLC0 register (PLL frequency synthesizer setting do not change)

When the PM21 bit is set to "1", do not execute the WAIT instruction.

5. Setting the PM22 bit to “1” results in the following conditions:

- The on-chip oscillator continues oscillating even if the CM21 bit in the CM2 register is set to "0" (main clock or

PLL clock) (system clock of count source selected by the CM21 bit is valid)

- The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer count

source.

- The CM10 bit in the CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode

entered)

- The watchdog timer does not stop in wait mode.

6. For NMI function, the PM24 bit must be set to “1”(NMI function). Once this bit is set to “1”, it cannot be cleared to

“0” by program.

7. SD input is valid regardless of the PM24 setting.

Specifying wait when

accessing SFR during PLL

operation

(2)

0: 2 wait

1: 1 wait

WDT count source

protective bit

(3,5)

P85/NMI configuration bit

(6,7)

0: P8

function (NMI disable)

1: NMI function

0: CPU clock is used for the

watchdog timer count source

1: On-chip oscillator clock is used

for the watchdog timer count

source

0: Clock is protected by PRCR

1: Clock modification disabled

Nothing is assigned. When write, set to“0”.

When read,its content is indeterminate

6. Processor Mode

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The internal bus consists of CPU bus, memory bus, and peripheral bus. Bus Interface Unit (BIU) is used to

interfere with CPU, ROM/RAM, and perpheral functions by controling CPU bus, memory bus, and periph-

eral bus. Figure 6.3 shows the block diagram of the internal bus.

Figure 6.3 Bus Block Diagram

The number of bus cycle varies by the internal bus. Table 6.1 lists the accessible area and bus cycle.

Table 6.1 Accessible Area and Bus Cycle

Accessible Area Bus Cycle

SFR PM20 bit = 0 (2 waits) 3 CPU clock cycles

PM20 bit = 1 (1 wait) 2 CPU clock cycles

ROM/RAM PM17 bit = 0 (no wait) 1 CPU clock cycle

PM17 bit = 1 (1 wait) 2 CPU clock cycles

CPU

ROM

BIU

I/O

U address bus

Memory data bus

Periphral data bus

DMAC

Memory address bus

Peripheral address bus

Timer

WDT

Serial I/O

ADC

Peripheral function

CPU clock

RAM

CPU data bus

Peripheral function

Clock

generation

circuit

S F R

7. Clock Generation Circuit

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7. Clock Generation Circuit

The clock generation circuit contains four oscillator circuits as follows:

(1) Main clock oscillation circuit

(2) Sub clock oscillation circuit

(3) On-chip oscillator (available at reset, oscillation stop detect function)

(4) PLL frequency synthesizer

Table 7.1 lists the clock generation circuit specifications. Figure 7.1 shows the clock generation circuit.

Figures 7.2 to 7.6 show the clock-related registers.

Table 7.1. Clock Generation Circuit Specifications

• CPU clock source

• Peripheral function

clock source

Use of clock

Main clock

oscillation circuit Sub clock

oscillation circuit

Item

• CPU clock source

• Timer A, B's clock

source

Clock frequency 0 to 20 MHz 32.768 kHz

• Ceramic oscillator

• Crystal oscillator

Usable oscillator • Crystal oscillator

XIN, XOUT

Pins to connect

oscillator XCIN, XCOUT

Available

Oscillation stop,

restart function Available

Oscillating

( )

Oscillator status

after reset Stopped

Externally derived clock can be inputOther

PLL frequency

synthesizer

Available

Stopped

On-chip oscillator

• CPU clock source

• Peripheral function clock source

• CPU and peripheral function

clock sources when the main

clock stops oscillating

• Selectable source frequency:

f1(ROC), f2(ROC), f3(ROC)

• Selectable divider:

by 2, by 4, by 8

Available

Oscillating

• CPU clock source

• Peripheral function clock

source

(CPU clock source)

M16C/26A

M16C/26B

Stopped(M16C/26T)

10 to 20 MHz

( )

10 to 24 MHz (M16C/26B)

M16C/26A

M16C/26T

7. Clock Generation Circuit

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CM00, CM01, CM02, CM04, CM05, CM06, CM07: CM0 register bits

CM10, CM11, CM16, CM17: CM1 register bits

PCLK0, PCLK1, PCLK5: PCLKR register bits

CM21, CM27 : CM2 register bits

1/32

Main clock

generating circuit

CM02

CM04

CM10=1(stop mode) Q

WAIT instruction

CM05

NMI

Interrupt request level judgment output

RESET

Software reset

CPU clock

CM07

1/2 1/2 1/2 1/2

CM06=0

CM17-CM16=00

CM06=0

CM17-CM16=01

CM06=0

CM17-CM16=10

CM06=1

CM06=0

CM17-CM16=11

Details of divider

Sub-clock

generating circuit

CIN

COUT

OUT

1/2

32SIO

1/2 1/4 1/8 1/16 1/32

PLL

frequency

M21=

M11

M21=

cloc

Sub-clock

n-chi

oscillato

cloc

LK1=1

LK1=

Main

clock

Oscillation

stop, re-

oscillation

detection

circuit

D4INT clock

CLK

OUT

I/O ports PCLK5=0,CM01-CM00=00

PCLK5=0,CM01-CM00=01

PCLK5=1,

CM01-CM00=00

PCLK5=0,

CM01-CM00=10

PCLK5=0,

CM01-CM00=11

CM21

BCLK

Figure 7.1. Clock Generation Circuit

Phase

comparator Charge

pump

Voltage

control

oscillator

(VCO)

PLL clock

Main clock

1/2

Programmable

counter

Internal low-

pass filter

PLL frequency synthesizer

Pulse generation

circuit for clock

edge detection

and charge,

discharge control

Charge,

discharge

circuit

Reset

generating

circuit

Oscillation stop,

re-oscillation

detection interrupt

generating circuit

Main

clock

Oscillation stop

detection reset

CM27=0

CM21 switch signal

Oscillation stop,

re-oscillation

detection signal

Oscillation stop, re-oscillation detection circuit

CM27=1

1/2 1/2 1/2

ROCR3-ROCR2=11

On-chip

oscillator

clock

1/8

1/4

1/2

ROCR3-ROCR2=10

ROCR3-ROCR2=01

ROCR1-ROCR0=00

1(ROC)

2(ROC)

3(ROC)

ROCR1-ROCR0=01

ROCR1-ROCR0=11

On-chip Oscillator

7. Clock Generation Circuit

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Figure 7.2. CM0 Register

System clock control register 0 (1)

Symbol Address After reset

CM0 0006

01001000

(M16C/26A, M16C/26B)

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

CM07

CM05

CM04

CM03

CM02

CM06

WAIT peripheral function

clock stop bit (10) 1 : Stop peripheral function clock in wait mode (8)

CIN

-X

COUT

drive capacity

select bit (2) 1 : HIGH

Main clock stop bit

(3, 10, 12, 13) 0 : On

1 : Off (4, 5)

Main clock division select

bit 0 (7, 13, 14) 0 : CM16 and CM17 valid

1 : Division by 8 mode

System clock select bit

(6, 10, 11, 12)

0 : Main clock, PLL clock, or on-chip oscillator clock

1 : Sub-clock

Port X

select bit

(2)

Refer to Table 7.5.3.1 Function of the CLKout pin

01101000

(M16C/26T)

CM00

CM01

Clock output function

select bit

0 : Do not stop peripheral function clock in wait mode

0 : LOW

0 : I/O port P8

, P8

1 : X

CIN

-X

COUT

generation function (9)

NOTES:

1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).

2. The CM03 bit is set to "1" (high) when the CM04 bit is set to "0" (I/O port) or the microcomputer goes to a stop mode.

3. This bit is provided to stop the main clock when the low power dissipation mode or on-chip oscillator low power dissipation

mode is selected. This bit cannot be used for detection as to whether the main clock stopped or not. To stop the main clock, the

following setting is required:

(1) Set the CM07 bit to "1" (Sub-clock select) or the CM21 bit in the CM2 register to "1" (on-chip oscillator select) with the sub-

clock stably oscillating.

(2) Set the CM20 bit in CM2 register to "0" (Oscillation stop, re-oscillation detection function disabled).

(3) Set the CM05 bit to "1" (Stop).

4. During external clock input, only the clock oscillation buffer is turned off and clock input is accepted.

5. When CM05 bit is set to "1", the X

OUT

pin goes "H". Furthermore, because the internal feedback resistor remains connected, the

pin is pulled "H" to the same level as X

OUT

via the feedback resistor.

6. After setting the CM04 bit to "1" (X

CIN

-X

COUT

oscillator function), wait until the sub-clock oscillates stably before switching the

CM07 bit from "0" to "1" (sub-clock).

7. When entering stop mode from high or middle speed mode, on-chip oscillator mode or on-chip oscillator low power mode, the

CM06 bit is set to "1" (divide-by-8 mode).

8. The f

C32

clock does not stop. During low speed or low power dissipation mode, do not set this bit to "1" (peripheral clock turned

off when in wait mode).

9. To use a sub-clock, set this bit to "1". Also make sure ports P8

and P8

are directed for input, with no pull-ups.

10. When the PM21 bit of PM2 register is set to "1" (clock modification disable), writing to the CM02, CM05, and CM07 bits has no

effect.

11. If the PM21 bit needs to be set to "1", set the CM07 bit to "0"(main clock) before setting it.

12. To use the main clock as the clock source for the CPU clock, follow the procedure below.

(1) Set the CM05 bit to "0" (oscillate).

(2) Wait until td(M-L) elapses or the main clock oscillation stabilizes, whichever is longer.

(3) Set the CM11, CM21 and CM07 bits all to "0".

13. When the CM21 bit is set to "0" (on-chip oscillaor turned off) and the CM05 bit is set to "1" (main clock turned off), the CM06 bit is

fixed to "1" (divide-by-8 mode) and the CM15 bit is fixed to "1" (drive capability High).

14. To return from on-chip oscillator mode to high-speed or middle-speed mode set the CM06 and CM15 bits both to "1".

7. Clock Generation Circuit

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System clock control register 1 (1)

Symbol Address After reset

CM1 0007

00100000

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

CM10 All clock stop control bit

(4, 6) 0 : Clock on

1 : All clocks off (stop mode)

CM15 X

-X

OUT

drive capacity

select bit (2) 0 : LOW

1 : HIGH

CM16

CM17

Reserved bit Must set to “0”

Main clock division

select bits (3) 0 0 : No division mode

0 1 : Division by 2 mode

1 0 : Division by 4 mode

1 1 : Division by 16 mode

b7 b6

000

CM11 System clock select bit 1

(6, 7) 0 : Main clock

1 : PLL clock (5)

(b4-b2)

NOTES:

1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (write enable).

2. When entering stop mode from high or middle speed mode, or when the CM05 bit is set to “1” (main clock turned off) in low

speed mode, the CM15 bit is set to “1” (drive capability high).

3. Effective when the CM06 bit is “0” (CM16 and CM17 bits enable).

4. If the CM10 bit is “1” (stop mode), X

OUT

goes “H” and the internal feedback resistor is disconnected. The X

CIN

and X

COUT

pins

are placed in the high-impedance state. When the CM11 bit is set to “1” (PLL clock), or the CM20 bit in the CM2 register is set

to “1” (oscillation stop, re-oscillation detection function enabled), do not set the CM10 bit to “1”.

5. After setting the PLC07 bit in the PLC0 register to “1” (PLL operation), wait until Tsu (PLL) elapses before setting the CM11 bit

to “1” (PLL clock).

6. When the PM21 bit in the PM2 register is set to “1” (clock modification disable), writing to the CM10, CM011 bits has no effect.

When the PM22 bit in the PM2 register is set to “1” (watchdog timer count source is on-chip oscillator clock), writing to the CM10

bit has no effect.

7. Effective when CM07 bit is “0” and CM21 bit is “0” .

Figure 7.3. CM1 Register

Figure 7.4. ROCR Register

b7 b6 b5 b4 b3 b2 b1 b0

ROCR0

ROCR1

On-chip Oscillator Control Register (1)

Symbol Address After Reset

ROCR 025C

X0000101

Bit Name Function

Bit Symbol

Frequency select bits

Reserved bit

000

0 0: f

(ROC)

0 1: f

(ROC)

1 0: Do not set to this value

1 1: f

(ROC)

b1 b0

ROCR2

ROCR3

Divider select bits

0 0: Do not set to this value

0 1: divide by 2

1 0: divide by 4

1 1: divide by 8

b3 b2

NOTE:

1. Write to this register after setting the PRC0 bit in the PRCR register to 1 (write enable).

(b6-b4) Set to 0

Nothing is assigned. When write, set to 0. When read, its

content is undefined

(b7)

7. Clock Generation Circuit

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b7 b6 b5 b4 b3 b2 b1 b0

CM20

CM21

Oscillation stop detection register (1)

Symbol Address After reset

CM2 000C16 0X0000102(11)

Bit name Function

Bit symbol

System clock select bit 2

(2, 3, 6, 8, 11, 12 )

0: Oscillation stop, re-oscillation

detection function disabled

1: Oscillation stop, re-oscillation

detection function enabled

0: Main clock or PLL clock

1: On-chip oscillator clock

(On-chip oscillator oscillating)

Oscillation stop, re-

oscillation detection bit

(7, 9, 10, 11)

CM22

CM23

Oscillation stop, re-

oscillation detection flag 0: Main clock stop or re-oscillation

not detected

1: Main clock stop or re-oscillation

detected

0: Main clock oscillating

1: Main clock not oscillating

monitor flag

(4)

CM27 0: Oscillation stop detection reset

1: Oscillation stop, re-oscillation

detection interrupt

Nothing is assigned. When write, set to “0”. When read, its

content is indeterminate.

Operation select bit

(when an oscillation stop,

re-oscillation is detected)

(11)

(b6)

(5)

Reserved bit

(b5-b4) Must set to “0”

NOTES:

1. Write to this register after setting the PRC0 bit in the PRCR register to “1” (write enable).

2. When the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is set to

“1”(oscillation stop, re-oscillation detection interrupt), and the CPU clock source is the main clock, the CM21 bit

isautomatically set to “1” (on-chip oscillator clock) if the main clock stop is detected.

3. If the CM20 bit is set to “1” and the CM23 bit is set to “1” (main clock not oscillating), do not set the CM21 bit to “0”.

4. This flag is set to “1” when the main clock is detected to have stopped or when the main clock is detected to

haverestarted oscillating. When this flag changes state from “0” to “1”, an oscillation stop, reoscillation detection interrupt

isgenerated. Use this flag in an interrupt routine to discriminate the causes of interrupts between theoscillation

stop,reoscillation detection interrupts and the watchdog timer interrupt. The flag is cleared to “0” by writing a “0” in

aprogram. (Writing a “1” has no effect. Nor is it cleared to “0” by an oscillation stop or an oscillation restart

detectiointerrupt request acknowledged.) If when the CM22 bit is set to "1" an oscillation stop or an oscillation restart is

detected, no oscillation stop, reoscillation detection interrupts are generated.

5. Read the CM23 bit in an oscillation stop, re-oscillation detection interrupt handling routine to determine the main

clockstatus.

6. Effective when the CM07 bit in the CM0 register is set to “0”.

7. When the PM21 bit in the PM2 register is “1” (clock modification disabled), writing to the CM20 bit has no effect.

8. When the CM20 bit is set to “1” (oscillation stop, re-oscillation detection function enabled), the CM27 bit is set to “1”

(oscillation stop, re-oscillation detection interrupt), and the CM11 bit is set to “1” (the CPU clock source is PLL clock), the

CM21 bit remains unchanged even when main clock stop is detected. If the CM22 bit is set to “0” under these conditions,

oscillation stop, re-oscillation detection interrupt occur at main clock stop detection; it is, therefore, necessary to set the

CM21 bit to “1” (on-chip oscillator clock) inside the interrupt routine.

9. Set the CM20 bit to “0” (disable) before entering stop mode. After exiting stop mode, set the CM20 bit back to "1”

(enable).

10. Set the CM20 bit to “0” (disable) before setting the CM05 bit in the CM0 register.

11. The CM20, CM21 and CM27 bits do not change at oscillation stop detection reset.

12. When the CM21 bit is set to "0" (on-chip oscillator turned off) and the CM05 bit is set to "1" (main clock turned off), the

CM06 bit is fixed to “1” (divide-by-8 mode) and the CM15 bit is fixed to “1” (drive capability High).

Figure 7.5. CM2 Register

7. Clock Generation Circuit

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Figure 7.6. PCLKR Register and PM2 Register

Function

Bit Symbol Bit Name

Peripheral Clock Select Register (1)

Symbol Address After Reset

PCLKR 025E16 000000112

b7 b6 b5 b4 b3 b2 b1 b0

PCLK0 0: f

1: f

000

Reserved bit Set to 0

NOTE:

1. Write to this register after setting the PRC0 bit in PRCR register to 1 (write enable).

PCLK1

0: f

SIO

1: f

SIO

(b4-b2)

Reserved bit Set to 0 RW

(b7-b6)

PCLK5

Refer to Table 7.5.3.1

Clock output function

expansion select bit

Timers A, B clock select bit

(Clock source for the timers A,

B, the timer S, the dead timer,

SI/O3, SI/O4 and multi-master

C bus)

SI/O clock select bit

(Clock source for UART0 to

UART2)

NOTES:

1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enable).

2. The PM20 bit becomes effective when PLC07 bit in the PLC0 register is set to 1 (PLL on). Change the PM20

bit when the PLC07 bit is set to 0 (PLL off). Set the PM20 bit to 0 (2 waits) when PLL clock > 16MHz.

3. Once this bit is set to 1, it cannot be cleared to 0 by program.

4. Writting to the following bits has no effect when the PM21 bit is set to 1:

CM02 bit in the CM0 register

CM05 bit in the CM0 register (main clock is not halted)

CM07 bit in the CM0 register (CPU clock source does not change)

CM10 bit in the CM1 register (stop mode is not entered)

CM11 bit in the CM1 register (CPU clock source does not change)

CM20 bit in the CM2 register (oscillation stop, re-oscillation detection function settings do not change)

All bits in the PLC0 register (PLL frequency synthesizer setting do not change)

Do not execute WAIT instruction when the PM21 bit is set to 1.

5. Setting the PM22 bit to 1 results in the following conditions:

• The on-chip oscillator continues oscillating even if the CM21 bit in the CM2 register is set to "0" (main clock or

PLL clock) (system clock of count source selected by the CM21 bit is valid)

• The on-chip oscillator starts oscillating, and the on-chip oscillator clock becomes the watchdog timer

count source.

• The CM10 bit in the CM1 register cannnot be written. (Writing 1 has no effect, stop mode is not entered.)

• The watchdog timer does not stop in wait mode.

6. For NMI function, the PM24 bit must be set to 1(NMI function). Once this bit is set to 1, it cannot be set to 0 by

program.

7. SD input is valid regardless of the PM24 setting.

Function

Bit Symbol Bit Name

Processeor Mode Register 2

(1)

Symbol Address After Reset

PM2 001E

XXX00000

b7 b6 b5 b4 b3 b2 b1 b0

PM20

PM21

(b7-b5)

PM22

PM24

(b3) Reserved bit Set to 0 RW

Nothing is assigned. When write, set to 0.

When read, thecontent is undefined

0: CPU clock is used for the

watchdog timer count source

1: On-chip oscillator clock is used

for the watchdog timer count

source

0: 2 waits

1: 1 wait

Specifying wait when

accessing SFR(2)

System clock protective

bit(3,4)

WDT count source

protective bit

(3,5)

0: Clock is protected by PRCR

1: Clock modification disabled

/NMI configuration bit(6,7) 0: P8

function (NMI disabled)

1: NMI function

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Figure 7.7. PLC0 Register

PLC00

PLC01

PLC02

PLC07

(3)

(4)

Function

PLL control register 0 (1, 2)

PLL multiplying factor

select bit

Nothing is assigned. When write, set to "0".

When read, its content is indeterminate.

Reserved bit

Operation enable bit

0 0 0:

0 0 1: Multiply by 2

0 1 0: Multiply by 4

0 1 1:

1 0 0:

1 0 1:

1 1 0:

1 1 1:

0: PLL Off

1: PLL On

Must set to "1"

Bit name

Bit

symbol

Symbol Address After reset

PLC0 001C

0001 X010

b1b0b2

Reserved bit Must set to "0"

Do not set

(b4)

(b6-b5)

(b3)

b7 b6 b5 b4 b3 b2 b1 b0

0 10

NOTES:

1. Write to this register after setting the PRC0 bit in the PRCR register to "1" (write enable).

2. When the PM21 bit in the PM2 register is "1" (clock modification disable), writing to this register has

no effect.

These three bits can only be modified when the PLC07 bit is set to "0" (PLL turned off). The value once

written to this bit cannot be modified.

4. Before setting this bit to "1" , set the CM07 bit to "0" (main clock), set the CM17 and CM16 bits to

"00

" (main clock undivided mode), and set the CM06 bit to "0" (CM16 and CM17 bits enable).

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Figure 7.1.1. Examples of Main Clock Connection Circuit

The following describes the clocks generated by the clock generation circuit.

7.1 Main Clock

The main clock is generated by the main clock oscillation circuit. This clock is used as the clock source for

the CPU and peripheral function clocks. The main clock oscillator circuit is configured by connecting a

resonator between the XIN and XOUT pins. The main clock oscillator circuit contains a feedback resistor,

which is disconnected from the oscillator circuit during stop mode in order to reduce the amount of power

consumed in the chip. The main clock oscillator circuit may also be configured by feeding an externally

generated clock to the XIN pin. Figure 7.1.1 shows the examples of main clock connection circuit.

The main clock after reset oscillates in the M16C/26A and M16C/26B, but stop in the M16C/26T.

The power consumption in the chip can be reduced by setting the CM05 bit in the CM0 register to “1” (main

clock oscillator circuit turned off) after switching the clock source for the CPU clock to a sub clock or on-chip

oscillator clock. In this case, XOUT goes “H”. Furthermore, because the internal feedback resistor remains

on, XIN is pulled “H” to XOUT via the feedback resistor.

During stop mode, all clocks including the main clock are turned off. Refer to 7.6 power control.

If the main clock is not used, it is recommended to connect the XIN pin to VCC to reduce power consump-

tion during reset.

External Clock

XIN

XOUT Open

NOTE:

1. Insert a damping resistor if required. Resistance value varies depending on the oscillator setting.

Use resistance value recommended by the oscillator manufacturer. If the oscillator manufacturer

recommends that a feedback resistor be added to the chip externally, insert a feedback resistor

between X

and X

OUT

2. The external clock should not be stopped when it is connected to the X

pin and the main clock is

selected as the CPU clock.

Oscillator

(1)

OUT

MCU

(Built-in Feedback Resistor) MCU

(Built-in Feedback Resistor)

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Figure 7.2.1. Examples of Sub Clock Connection Circuit

7.2 Sub Clock

The sub clock is generated by the sub clock oscillation circuit. This clock is used as the clock source for the

CPU clock, as well as the timer A and timer B count sources.

The sub clock oscillator circuit is configured by connecting a crystal resonator between the XCIN and XCOUT

pins. The sub clock oscillator circuit contains a feedback resistor, which is disconnected from the oscillator

circuit during stop mode in order to reduce the amount of power consumed in the chip. The sub clock

oscillator circuit may also be configured by feeding an externally generated clock to the XCIN pin. Figure

7.2.1 shows the examples of sub clock connection circuit.

After reset, the sub clock is turned off. At this time, the feedback resistor is disconnected from the oscillator

circuit.

To use the sub clock for the CPU clock, set the CM07 bit in the CM0 register to “1 ” (sub clock) after the sub

clock becomes oscillating stably.

During stop mode, all clocks including the sub clock are turned off. Refer to 7.6 Power Control.

External Clock

XCIN

XCOUT

Open

NOTE:

1. Place a damping resistor if required. Resistance values vary depending on the oscillator setting.

Use values recommended by each oscillator manufacturer.

Place a feedback resistor between X

CIN

and X

COUT

if the oscillator manufacturer recommends

placing the resistor externally.

Oscillator

(1)

CIN

COUT

CIN

COUT

MCU

(Built-in Feedback Resistor) MCU

(Built-in Feedback Resistor)

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7.3 On-chip Oscillator Clock

This clock is supplied by a on-chip oscillator. This clock is used as the clock source for the CPU and

peripheral function clocks. In addition, if the PM22 bit in the PM2 register is “1” (on-chip oscillator clock for

the watchdog timer count source), this clock is used as the count source for the watchdog timer (Refer to

10.1 Count source protective mode).

The on-chip oscillator clock after reset oscillates. The on-chip oscillator clock f2(ROC) divided by 16 is used

for the CPU clock. It can also be turned off by setting the CM21 bit in the CM2 register to “0” (main clock or

PLL clock). If the main clock stops oscillating when the CM20 bit in the CM2 register is “1” (oscillation stop,

re-oscillation detection function enabled) and the CM27 bit is “1” (oscillation stop, re-oscillation detection

interrupt), the on-chip oscillator automatically starts operating, supplying the necessary clock for the micro-

computer.

7.4 PLL Clock

The PLL clock is generated from the main clock by a PLL frequency synthesizer. This clock is used as the

clock source for the CPU and peripheral function clocks. After reset, the PLL clock is turned off. The PLL

frequency synthesizer is activated by setting the PLC07 bit to “1” (PLL operation). When the PLL clock is

used as the clock source for the CPU clock, wait tsu(PLL) for the PLL clock to be stable, and then set the

CM11 bit in the CM1 register to “1”.

Before entering wait mode or stop mode, be sure to set the CM11 bit to “0” (CPU clock source is the main

clock). Furthermore, before entering stop mode, be sure to set the PLC07 bit in the PLC0 register to “0”

(PLL stops). Figure 7.4.1 shows the procedure for using the PLL clock as the clock source for the CPU.

The PLL clock frequency is determined by the equation below.

PLL clock frequency=f(XIN) X (multiplying factor set by the PLC02 to PLC00 bits in the PLC0 register)

(However, 10 MHz ≤ PLL clock frequency ≤ 20 MHz in M16C/26A and M16C/26T, 10 MHz ≤ PLL clock

frequency ≤ 24 MHz in M16C/26B)

The PLC02 to PLC00 bits can be set only once after reset. Table 7.4.1 shows the example for setting PLL

clock frequencies.

XIN

(MHz) PLC02 PLC01 PLC00 Multiplying factor PLL clock

(MHz)

(1)

10 0 0 1 2 20

50 1 0 4

Table 7.4.1. Example for Setting PLL Clock Frequencies

NOTE:

1. 10 MHz ≤ PLL clock frequency ≤ 20 MHz in M16C/26A and M16C/26T, 10 MHz ≤ PLL clock

frequency ≤ 24 MHz in M16C/26B)

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Figure 7.4.1. Procedure to Use PLL Clock as CPU Clock Source

START

Set the CM07 bit to “0” (main clock), the CM17 to CM16

bits to “00

”(main clock undivided), and the CM06 bit to “0”

(CM16 and CM17 bits enabled).

(1)

Set the PLC02 to PLC00 bits (multiplying factor).

(To select a 16 MHz < PLL clock)

Set the PM20 bit to “0” (2-wait states).

Set the PLC07 bit to “1” (PLL operation).

Wait until the PLL clock becomes stable (t

(PLL)).

Set the CM11 bit to “1” (PLL clock for the CPU clock source).

END

NOTE:

1. PLL operation mode can be entered from high speed mode.

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7.5 CPU Clock and Peripheral Function Clock

The CPU clock is used to operate the CPU and peripheral function clocks are used to operate the periph-

eral functions.

7.5.1 CPU Clock

This is the operating clock for the CPU and watchdog timer.

The clock source for the CPU clock can be chosen to be the main clock, sub clock, on-chip oscillator clock

or the PLL clock.

If the main clock or on-chip oscillator clock is selected as the clock source for the CPU clock, the selected

clock source can be divided by 1 (undivided), 2, 4, 8 or 16 to produce the CPU clock. Use the CM06 bit in

CM0 register and the CM17 to CM16 bits in CM1 register to select the divide-by-n value.

When the PLL clock is selected as the clock source for the CPU clock, the CM06 bit should be set to “0”

and the CM17 and CM16 bits to “002” (undivided).

After reset, the on-chip oscillator clock divided by 16 provides the CPU clock.

Note that when entering stop mode from high or middle speed mode, on-chip oscillator mode or on-chip

oscillator low power dissipation mode, or when the CM05 bit in the CM0 register is set to “1” (main clock

turned off) in low-speed mode, the CM06 bit in the CM0 register is set to “1” (divide-by-8 mode).

7.5.2 Peripheral Function Clock (f1, f2, f8, f32, f1SIO, f2SIO, f8SIO, f32SIO, fAD, fC32)

These are operating clocks for the peripheral functions.

Of these, fi (i = 1, 2, 8, 32) and fiSIO are derived from the main clock, PLL clock or on-chip oscillator clock

divided by i. The clock fi is used for Timer A and Timer B while fiSIO is used for UART0 to UART2.

Additionally, the f1 and f2 clocks are also used for dead time timer.

The fAD clock is produced from the main clock, PLL clock or on-chip oscillator clock, and is used for the A/

D converter.

When the WAIT instruction is executed after setting the CM02 bit in the CM0 register to “1” (peripheral

function clock turned off during wait mode), or when the microcomputer is in low power dissipation mode,

the fi, fiSIO and fAD clocks are turned off.

The fC32 clock is produced from the sub clock, and is used for timers A and B. This clock can only be used

when the sub clock is on.

7.5.3 ClockOutput Function

The f1, f8, f32 or fC clock can be output from the CLKOUT pin. Use the PCLK5 bit in the PCLKR register and

CM01 to CM00 bits in the CM0 register to select. Table 7.5.3.1 shows the function of the CLKOUT pin.

Table 7.5.3.1 The function of the CLKOUT pin

PCLK5 CM01 CM00 The function of the CLKOUT pin

0 0 0 I/O port P90

001fC

010f8

011f32

100f1

1 0 1 Do not set

1 1 0 Do not set

1 1 1 Do not set

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7.6 Power Control

There are three power control modes. For convenience’ sake, all modes other than wait and stop modes

are referred to as normal operation mode here.

7.6.1 Normal Operation Mode

Normal operation mode is further classified into seven modes.

In normal operation mode, because the CPU clock and the peripheral function clocks both are on, the

CPU and the peripheral functions are operating. Power control is exercised by controlling the CPU clock

frequency. The higher the CPU clock frequency, the greater the processing capability. The lower the CPU

clock frequency, the smaller the power consumption in the chip. If the unnecessary oscillator circuits are

turned off, the power consumption is further reduced.

Before the clock sources for the CPU clock can be switched over, the new clock source to which switched

must be oscillating stably. If the new clock source is the main clock, sub clock or PLL clock, allow a

sufficient wait time in a program until it becomes oscillating stably.

Note that operation modes cannot be changed directly from low power dissipation mode to on-chip oscil-

lator mode or on-chip oscillator low power dissipation mode. Nor can operation modes be changed

directly from on-chip oscillator mode or on-chip oscillator low power dissipation mode to low power dissi-

pation mode.

When the CPU clock source is changed from the on-chip oscillator to the main clock, change the opera-

tion mode to the medium speed mode (divided by 8 mode) after the clock was divided by 8 (the CM06 bit

in the CM0 register was set to “1”) in the on-chip oscillator mode.

7.6.1.1 High-speed Mode

The main clock divided by 1 provides the CPU clock. If the sub clock is on, fC32 can be used as the

count source for timers A and B.

7.6.1.2 PLL Operation Mode

The main clock multiplied by 2 or 4 provides the PLL clock, and this PLL clock serves as the CPU

clock. If the sub clock is on, fC32 can be used as the count source for timers A and B. PLL operation

mode can be entered from high speed mode. If PLL operation mode is to be changed to wait or stop

mode, first go to high speed mode before changing.

7.6.1.3 Medium-speed Mode

The main clock divided by 2, 4, 8 or 16 provides the CPU clock. If the sub clock is on, fC32 can be used

as the count source for timers A and B.

7.6.1.4 Low-speed Mode

The sub clock provides the CPU clock. The main clock is used as the clock source for the peripheral

function clock when the CM21 bit is set to “0” (on-chip oscillator turned off), and the on-chip oscillator

clock is used when the CM21 bit is set to “1” (on-chip oscillator oscillating).

The fC32 clock can be used as the count source for timers A and B.

7.6.1.5 Low Power Dissipation Mode

In this mode, the main clock is turned off after being placed in low speed mode. The sub clock provides

the CPU clock. The fC32 clock can be used as the count source for timers A and B. Peripheral function

clock can use only fC32.

Simultaneously when this mode is selected, the CM06 bit in the CM0 register becomes “1” (divided by

8 mode). In the low power dissipation mode, do not change the CM06 bit. Consequently, the medium

speed (divided by 8) mode is to be selected when the main clock is operated next.

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7.6.1.6 On-chip Oscillator Mode

The selected on-chip oscillator clock divided by 1 (undivided), 2, 4, 8 or 16 provides the CPU clock.

The on-chip oscillator clock is also the clock source for the peripheral function clocks. If the sub clock

is on, fC32 can be used as the count source for timers A and B. The on-chip oscillator frequency can be

selected ROCR3 to ROCR0 bits in ROCR register. When the operation mode is returned to the high

and medium speed modes, set the CM06 bit to “1” (divided by 8 mode).

7.6.1.7 On-chip Oscillator Low Power Dissipation Mode

The main clock is turned off after being placed in on-chip oscillator mode. The CPU clock can be

selected as in the on-chip oscillator mode. The on-chip oscillator clock is the clock source for the

peripheral function clocks. If the sub clock is on, fC32 can be used as the count source for timers A and

1(1)

Modes CM2 register

CM21 CM1 register

CM11 CM17, CM16 CM0 register

CM07 CM06 CM05 CM04

PLL operation mode 01002 00

High-speed mode 0 0 002 000

Medium-

speed

mode

0001

2 000

0010

2 000

divided by 2

00 01

0011

2 000

Low-speed mode 1 0 1

Low power dissipation mode 11

On-chip

oscillator

mode

(3)

divided by 4

divided by 8

divided by 16

On-chip oscillator low power

dissipation mode

101

2 000

110

2 000

110

111

2 000

100

2 000

(2)

divided by 2

divided by 4

divided by 8

divided by 16

divided by 1 1(1)

(2) 1

NOTES:

1. When the CM05 bit is set to “1” (main clock turned off) in low-speed mode, the mode goes to low power

dissipation mode and CM06 bit is set to “1” (divided by 8 mode) simultaneously.

2. The divide-by-n value can be selected the same way as in on-chip oscillator mode.

3. On-chip oscillator frequency can be any of those described in the section 7.6.1.6 On-chip Oscillator Mode.

7.6.2 Wait Mode

In wait mode, the CPU clock is turned off, so are the CPU (because operated by the CPU clock) and the

watchdog timer. However, if the PM22 bit in the PM2 register is “1” (on-chip oscillator clock for the watch-

dog timer count source), the watchdog timer remains active. Because the main clock, sub clock, on-chip

oscillator clock and PLL clock all are on, the peripheral functions using these clocks keep operating.

7.6.2.1 Peripheral Function Clock Stop Function

If the CM02 bit is “1” (peripheral function clocks turned off during wait mode), the f1, f2, f8, f32, f1SIO,

f8SIO, f32SIO and fAD clocks are turned off when in wait mode, with the power consumption reduced

that much. However, fC32 remains on.

7.6.2.2 Entering Wait Mode

The microcomputer is placed into wait mode by executing the WAIT instruction.

When the CM11 bit is set to “1” (CPU clock source is the PLL clock), be sure to clear the CM11 bit to

“0” (CPU clock source is the main clock) before going to wait mode. The power consumption of the

chip can be reduced by clearing the PLC07 bit to “0” (PLL stops).

Table 7.6.1.1. Setting Clock Related Bit and Modes

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Interrupt CM02=0 CM02=1

NMI interrupt Can be used

Serial I/O interrupt Can be used when operating

with internal or external clock Can be used when operating

with external clock

key input interrupt Can be used Can be used

A/D conversion

interrupt Can be used in one-shot mode

or single sweep mode

Timer A interrupt Can be used in all modes Can be used in event counter

mode or when the count

source is fC32

Timer B interrupt

INT interrupt

Can be used

(Do not use)

Can be used

Table 7.6.2.4.1. Interrupts to Exit Wait Mode

7.6.2.3 Pin Status During Wait Mode

Table 7.6.2.3.1 lists pin status during wait mode.

Table 7.6.2.3.1 Pin Status in Wait Mode

Pin Status

I/O ports Retains status before wait mode

When fC selected Does not stop

CLKOUT When f1, f8, f32 selected Does not stop when the CM02 bit is set to “0”.

Retains status before wait mode when the CM02 bit is set to “1”

7.6.2.4 Exiting Wait Mode ______

The microcomputer is moved out of wait mode by a hardware reset, NMI interrupt or peripheral func-

tion interrupt. ______

If the microcomputer is to be moved out of exit wait mode by a hardware reset or NMI interrupt, set the

peripheral function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disabled) before execut-

ing the WAIT instruction.

The peripheral function interrupts are affected by the CM02 bit. If the CM02 bit is set to “0” (peripheral

function clocks not turned off during wait mode), all peripheral function interrupts can be used to exit

wait mode. If the CM02 bit is set to “1” (peripheral function clocks turned off during wait mode), the

peripheral functions using the peripheral function clocks stop operating, so that only the peripheral

functions clocked by external signals can be used to exit wait mode.

Table 7.6.2.4.1 lists the interrupts to exit wait mode.

If the microcomputer is to be moved out of wait mode by a peripheral function interrupt, set up the

following before executing the WAIT instruction.

1. In the ILVL2 to ILVL0 bits in the interrupt control register, set the interrupt priority level of the periph

eral function interrupt to be used to exit wait mode.

Also, for all of the peripheral function interrupts not used to exit wait mode, set the ILVL2 to ILVL0

bits to “0002” (interrupt disable).

2. Set the I flag to “1”.

3. Enable the peripheral function whose interrupt is to be used to exit wait mode.

In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an

interrupt routine is executed.

The CPU clock turned on when exiting wait mode by a peripheral function interrupt is the same CPU

clock that was on when the WAIT instruction was executed.

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7.6.3 Stop Mode

In stop mode, all oscillator circuits are turned off, so are the CPU clock and the peripheral function clocks.

Therefore, the CPU and the peripheral functions clocked by these clocks stop operating. The least

amount of power is consumed in this mode. If the voltage applied to Vcc pin is VRAM or more, the internal

RAM is retained. When applying 2.7 or less voltage to Vcc pin, make sure Vcc≥VRAM.

However, the peripheral functions clocked by external signals keep operating. The following interrupts

can be used to exit stop mode.

______

• NMI interrupt

• Key interrupt

______

• INT interrupt

• Timer A, Timer B interrupt (when counting external pulses in event counter mode)

• Serial I/O interrupt (when external clock is selected)

• Voltage down detection interrupt

(refer to 5.5.1 Voltage Down Detection Interrupt for an operating condition)

7.6.3.1 Entering Stop Mode

The microcomputer is placed into stop mode by setting the CM10 bit in the CM1 register to “1” (all

clocks turned off). At the same time, the CM06 bit in the CM0 register is set to “1” (divide-by-8 mode)

and the CM15 bit in the CM10 register is set to “1” (main clock oscillator circuit drive capability high).

Before entering stop mode, set the CM20 bit to “0” (oscillation stop, re-oscillation detection function

disable).

Also, if the CM11 bit is “1” (PLL clock for the CPU clock source), set the CM11 bit to “0” (main clock for

the CPU clock source) and the PLC07 bit to “0” (PLL turned off) before entering stop mode.

7.6.3.2 Pin Status during Stop Mode

The I/O pins retain their status held just prior to entering stop mode.

7.6.3.3 Exiting Stop Mode ______

The microcomputer is moved out of stop mode by a hardware reset, NMI interrupt or peripheral func-

tion interrupt. ______

If the microcomputer is to be moved out of stop mode by a hardware reset or NMI interrupt, set the

peripheral function interrupt priority ILVL2 to ILVL0 bits to “0002” (interrupts disable) before setting the

CM10 bit to “1”.

If the microcomputer is to be moved out of stop mode by a peripheral function interrupt, set up the

following before setting the CM10 bit to “1”.

1. In the ILVL2 to ILVL0 bits in the interrupt control register, set the interrupt priority level of the

peripheral function interrupt to be used to exit stop mode.

Also, for all of the peripheral function interrupts not used to exit stop mode, set the ILVL2 to ILVL0

bits to “0002”.

2. Set the I flag to “1”.

3. Enable the peripheral function whose interrupt is to be used to exit stop mode.

In this case, when an interrupt request is generated and the CPU clock is thereby turned on, an

interrupt service routine is executed.

______

Which CPU clock will be used after exiting stop mode by a peripheral function or NMI interrupt is

determined by the CPU clock that was on when the microcomputer was placed into stop mode as

follows:

If the CPU clock before entering stop mode was derived from the sub clock :

sub clock

If the CPU clock before entering stop mode was derived from the main clock :

main clock divide-by-8

If the CPU clock before entering stop mode was derived from the on-chip oscillator clock: on-chip oscillator clock

divide-by-8

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Figure 7.6.1. State Transition to Stop Mode and Wait Mode

Figure 7.6.1 shows the state transition from normal operation mode to stop mode and wait mode. Figure

7.6.1.1 shows the state transition in normal operation mode.

Table 7.6.1 shows a state transition matrix describing allowed transition and setting. The vertical line

shows current state and horizontal line shows state after transition.

Reset

Medium-speed mode

(divided-by-8 mode)

High-speed, medium-

speed mode

Stop mode Wait mode

Interrupt

Low-speed mode

Stop mode

Interrupt

Wait mode

Interrupt

Stop mode

All oscillators stopped

Interrupt

Wait mode

WAIT

instruction

Interrupt

CPU operation stopped

PLL operation

mode

(1, 2)

Wait mode

Interrupt

CM10=1

(6)

Interrupt

(4)

Stop mode

WAIT

instruction

WAIT

instruction

WAIT

instruction

On-chip oscillator mode

(selectable frequency)

On-chip oscillator

mode (f

2(ROC)

/16)

Normal operation mode

CM07=0

CM06=1

CM05=0

CM11=0

CM10=1

(5)

On-chip oscillator low power

dissipation mode

Stop mode

Interrupt

(4)

Wait mode

Interrupt

WAIT

instruction

CM05, CM06, CM07: Bits in the CM0 register

CM10, CM11: Bits in the CM1 register

CM10=1

(6)

CM10=1

(6)

CM10=1

(6)

CM10=1

(6)

Low power dissipation modeStop mode

Interrupt

Wait mode

Interrupt

WAIT

instruction

CM21=1

CM21=0

CM10=1

(6)

(7)

: Arrow shows mode can be changed. Do not change mode to another mode when no arrow is shown.

NOTES:

1. Do not go directly from PLL operation mode to wait or stop mode.

2. PLL operation mode can be entered from high speed mode. Similarly, PLL operation mode can be changed back to high speed mode.

3. When the PM21 bit is set to 0 (system clock protective function unused).

4. The on-chip oscillator clock divided by 8 provides the CPU clock.

5. Write to the CM0 register and CM1 register simultaneously by accessing in word units while CM21 bit is set to 0 (on-chip oscillator

turned off). When the clock generated externally is input to the XCIN pin, transit to stop mode with this process.

6. Before entering stop mode, be sure to clear the CM20 bit in the CM2 register to 0 (oscillation stop and oscillation restart detection

function disabled).

7. The CM06 bit is set to 1 (divide-by-8).

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Figure 7.6.1.1. State Transition in Normal Mode

CM04=0

CPU clock: f(PLL)

CM07=0

CM06=0

CM17=0

CM16=0

PLL operation mode

CM07=0

CM06=0

CM17=0

CM16=0

CM07=0

CM17=0

CM06=0

CM16=0

CM07=0

CM17=0

CM06=0

CM16=1

CM07=0

CM17=1

CM06=0

CM16=0

CM07=0

CM06=1

CM07=0

CM17=1

CM06=0

CM16=1

High-speed mode

CM07=0

CM17=0

CM06=0

CM16=0

CM07=0

CM17=0

CM06=0

CM16=1

CM07=0

CM17=1

CM06=0

CM16=0

CM07=0

CM06=1

CM07=0

CM17=1

CM06=0

CM16=1

CM07=0

Low-speed mode

CM07=0

Low power dissipation mode

CM06=1

CM15=1

On-chip oscillator mode

CPU clock

On-chip oscillator

mode

CPU clock

On-chip oscillator

low power

dissipation mode

CPU clock

CM07=0

Low-speed

mode

PLC07=1

CM11=1

(5)

PLC07=0

CM11=0

(5)

CM04=0

PLC07=1

CM11=1

PLC07=0

CM11=0

CM04=0CM04=1CM04=1 CM04=1 CM04=0CM04=1

CM07=0

(2, 4)

CM07=1

(3)

CM05=1

(1, 7) CM05=0

CM21=0

(2, 6)

CM21=1

CM21=0

(2, 6)

CM21=1

CM21=0

CM21=1

Main clock oscillation On-chip oscillator clock

oscillation

Sub clock oscillation

f(ROC)

f(ROC)/2

f(ROC)/4

f(ROC)/8

f(ROC)/16

f(ROC)

f(ROC)/2

f(ROC)/4

f(ROC)/8

f(ROC)/16

f(ROC)

f(ROC)/2

f(ROC)/4

f(ROC)/8

f(ROC)/16

f(ROC)

f(ROC)/2

f(ROC)/4

f(ROC)/8

f(ROC)/16

PLL operation

mode

CPU clock: f(PLL) CPU clock: f(XIN)

High-speed mode Middle-speed mode

(divide by 2)

CPU clock: f(X

)/2 CPU clock: f(X

)/4 CPU clock: f(X

)/8 CPU clock: f(X

)/16

CPU clock: f(XCIN)

CM05=0

CM05=1

(1)

CM05=1

(1)

CM05=0

(5)

Middle-speed mode

(divide by 4) Middle-speed mode

(divide by 8) Middle-speed mode

(divide by 16)

Middle-speed mode

(divide by 2) Middle-speed mode

(divide by 4) Middle-speed mode

(divide by 8) Middle-speed mode

(divide by 16)

CPU clock: f(XIN)

CPU clock: f(X

)/2 CPU clock: f(X

)/4 CPU clock: f(X

)/8 CPU clock: f(X

)/16

On-chip oscillator low power

dissipation mode

: Arrow shows mode can be changed. Do not change mode to another mode when no arrow is shown.

NOTES:

1. Avoid making a transition when the CM20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled).

Set the CM20 bit to 0 (oscillation stop, re-oscillation detection function disabled) before transiting.

2. Wait for the main clock oscillation stabilization time before switching over. Set the CM15 bit in the CM1 register to 1 (drive capacity High) until main clock oscillation is stabilized.

3. Switch clock after oscillation of sub-clock is sufficiently stable.

4. Change bits CM17 and CM16 before changing the CM06 bit.

5. The PM20 bit in the PM2 register becomes effective when the PLC07 bit in the PLC0 register is set to 1 (PLL on). Change the PM20 bit when the PLC07 bit is set to 0 (PLL off).

Set the PM20 bit to 0 (2 waits) when PLL clock > 16MHz.

6. Set the CM06 bit to 1 (division by 8 mode) before changing back the operation mode from on-chip oscillator mode to high- or middle-speed mode.

7. When the CM21 bit is set to 0 (on-chip oscillator turned off) and the CM05 bit is set to 1 (main clock turned off), the CM06 bit is fixed to 1 (divide-by-8 mode) and the

CM15 bit is fixed to 1 (drive capability High).

CM07=1

(3) CM07=0

(4)

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Table 7.6.1. Allowed Transition and Setting

High-speed mode,

middle-speed mode

On-chip oscillator mode

Stop mode

Wait mode

On-chip oscillator

low power dissipation

mode

PLL operation mode2

Low power dissipation

mode

Low-speed mode2

Current state

State after transition

(8)

(18)5

(9)7--

(10)

(11)1, 6

(12)3

(14)4

-- --

(13)3(15) --

(10)

-- -- --

(18)(18) --

(16)1(17)

-- --

(18)5(18)5

(18)(18)(18)(18)(18)

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)

(9)

(10)

(11)

(12)

(13)

(14)

(15)

(16)

(17)

(18)

Setting Operation

CM04 = 0 Sub clock turned off

CM04 = 1 Sub clock oscillating

CM06 = 0, CPU clock no division mode

CM17 = 0 , CM16 = 0

CM06 = 0, CPU clock division by 2 mode

CM17 = 0 , CM16 = 1

CM06 = 0, CPU clock division by 4 mode

CM17 = 1 , CM16 = 0

CM06 = 1 CPU clock division by 8 mode

CM06 = 0, CPU clock division by 16 mode

CM17 = 1 , CM16 = 1

CM07 = 0 Main clock, PLL clock,

or on-chip oscillator clock selected

CM07 = 1 Sub clock selected

CM05 = 0 Main clock oscillating

CM05 = 1 Main clock turned off

PLC07 = 0,

CM11 = 0 Main clock selected

PLC07 = 1,

CM11 = 1 PLL clock selected

CM21 = 0

Main clock or PLL clock selected

CM21 = 1 On-chip oscillator clock selected

CM10 = 1 Transition to stop mode

wait instruction Transition to wait mode

Hardware interrupt

Exit stop mode or wait mode

NOTES:

1. Avoid making a transition when the CM20 bit is set to 1 (oscillation stop, re-oscillation detection function enabled).

Set the CM20 bit to 0 (oscillation stop, re-oscillation detection function disabled) before transiting.

2. On-chip oscillator clock oscillates and stops in low-speed mode. In this mode, the on-chip oscillator can be used as peripheral function clock.

Sub clock oscillates and stops in PLL operation mode. In this mode, sub clock can be used as a clock for the timers A and B.

3. PLL operation mode can only be entered from and changed to high-speed mode.

4. Set the CM06 bit to 1 (division by 8 mode) before transiting from on-chip oscillator mode to high- or middle-speed mode.

5. When exiting stop mode, the CM06 bit is set to 1 (division by 8 mode).

6. If the CM05 bit is set to 1 (main clock stop), then the CM06 bit is set to 1 (division by 8 mode).

7. A transition can be made only when sub clock is oscillating.

8. State transitions within the same mode (divide-by-n values changed or subclock oscillation turned on or off) are shown in the table below.

--: Cannot transit

(11)1

High-speed mode,

middle-speed mode On-chip oscillator

mode Stop mode Wait mode

On-chip oscillator

low power

dissipation mode

PLL operation

mode2

Low power

dissipation mode

Low-speed mode2

(3)

(4)

(5) (7)

(7)

(5)

(7)

(6)

division Divided

by 2

(3)

(4)

(5)

(5) (7)

(7)

(6)

(1) (1) (1) (1) (1)

(2) (2) (2) (2) (2)

-- --

----

-- --

-- -- --

-- --

Sub clock oscillating Sub clock turned off

--: Cannot transit

Divided

by 4 Divided

by 8 Divided

by 16 No

division Divided

by 2 Divided

by 4 Divided

by 8 Divided

by 16

No division

Divided by 4

Sub clock

oscillating

Sub clock

turned off

Divided by 8

Divided by 16

Divided by 2

No division

Divided by 4

Divided by 8

Divided by 16

Divided by 2

9. ( ) : setting method. Refer to following table.

CM04, CM05, CM06, CM07 : Bits in the CM0 register

CM10, CM11, CM16, CM17 : Bits in the CM1 register

CM20, CM21 : Bits in the CM2 register

PLC07 : Bit in the PLC0 register

(9)7

(8)

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7.7 System Clock Protective Function

When the main clock is selected for the CPU clock source, this function protects the clock from modifica-

tions in order to prevent the CPU clock from becoming halted by run-away.

If the PM21 bit in the PM2 register is set to “1” (clock modification disabled), the following bits are protected

against writes:

• CM02, CM05, and CM07 bits in CM0 register

• CM10, CM11 bits in CM1 register

• CM20 bit in CM2 register

• All bits in PLC0 register

Before the system clock protective function can be used, the following register settings must be made while

the CM05 bit in the CM0 register is “0” (main clock oscillating) and CM07 bit is “0” (main clock selected for

the CPU clock source):

(1) Set the PRC1 bit in the PRCR register to “1” (enable writes to PM2 register).

(2) Set the PM21 bit in the PM2 register to “1” (disable clock modification).

(3) Set the PRC1 bit in the PRCR register to “0” (disable writes to PM2 register).

Do not execute the WAIT instruction when the PM21 bit is set to “1”.

7.8 Oscillation Stop and Re-oscillation Detect Function

The oscillation stop and re-oscillation detect function allows the detection of main clock oscillation stop and

reoscillation. At oscillation stop or re-oscillation detection, reset or oscillation stop, re-oscillation detection

interrupt are generated. Depending on the CM27 bit in the CM2 register. The oscillation stop detection

function can be enabled and disabled by the CM20 bit in the CM2 register. Table 7.8.1 lists a specification

overview of the oscillation stop and re-oscillation detect function.

Table 7.8.1. Specification Overview of Oscillation Stop and Re-oscillation Detect Function

Item Specification

Oscillation stop detectable clock and f(XIN) ≥ 2 MHz

frequency bandwidth

Enabling condition for oscillation stop, Set the CM20 bit to “1”(enable)

re-oscillation detection function

Operation at oscillation stop, •Reset occurs (when the CM27 bit is set to "0")

re-oscillation detection •

Oscillation stop, re-oscillation detection interrupt occurs(when the CM27 bit is

set to "1")

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7.8.1 Operation When the CM27 bit is set to "0" (Oscillation Stop Detection Reset)

When main clock stop is detected when the CM20 bit is “1” (oscillation stop, re-oscillation detection

function enabled), the microcomputer is initialized, coming to a halt (oscillation stop reset; refer to 4. SFR,

5. Reset).

This status is reset with hardware reset 1 or hardware reset 2. Also, even when re-oscillation is detected,

the microcomputer can be initialized and stopped; it is, however, necessary to avoid such usage. (During

main clock stop, do not set the CM20 bit to “1” and the CM27 bit to “0”.)

7.8.2 Operation When the CM27 bit is set to "1" (Oscillation Stop and Re-oscillation

Detect Interrupt)

When the main clock corresponds to the CPU clock source and the CM20 bit is “1” (oscillation stop and

re-oscillation detect function enabled), the system is placed in the following state if the main clock comes

to a halt:

• Oscillation stop and re-oscillation detect interrupt request occurs.

• The on-chip oscillator starts oscillation, and the on-chip oscillator clock becomes the CPU clock and

clock source for peripheral functions in place of the main clock.

• CM21 bit is set to "1" (on-chip oscillator clock for CPU clock source)

• CM22 bit is set to "1" (main clock stop detected)

• CM23 bit is set to "1" (main clock stopped)

When the PLL clock corresponds to the CPU clock source and the CM20 bit is “1”, the system is placed

in the following state if the main clock comes to a halt: Since the CM21 bit remains unchanged, set it to “1”

(on-chip oscillator clock) inside the interrupt routine.

• Oscillation stop and re-oscillation detect interrupt request occurs.

• CM22 bit is set to "1" (main clock stop detected)

• CM23 bit is set to "1" (main clock stopped)

• CM21 bit remains unchanged

When the CM20 bit is “1”, the system is placed in the following state if the main clock re-oscillates from the

stop condition:

• Oscillation stop and re-oscillation detect interrupt request occurs.

• CM22 bit is set to "1" (main clock re-oscillation detected)

• CM23 bit is set to "0" (main clock oscillation)

• CM21 bit remains unchanged

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7.8.3 How to Use Oscillation Stop and Re-oscillation Detect Function

• The oscillation stop and re-oscillation detect interrupt shares the vector with the watchdog timer inter-

rupt. If the oscillation stop, re-oscillation detection and watchdog timer interrupts both are used, read

the CM22 bit in an interrupt routine to determine which interrupt source is requesting the interrupt.

• Where the main clock re-oscillated after oscillation stop, return the main clock to the CPU clock and

peripheral function clock source in the program. Figure 7.8.3.1 shows the procedure for switching the

clock source from the on-chip oscillator to the main clock.

• Simultaneously with oscillation stop, re-oscillation detection interrupt occurrence, the CM22 bit be-

comes “1”. When the CM22 bit is set at “1”, oscillation stop, re-oscillation detection interrupt are dis-

abled. By setting the CM22 bit to “0” in the program, oscillation stop, re-oscillation detection interrupt

are enabled.

• If the main clock stops during low speed mode where the CM20 bit is “1”, an oscillation stop, re-oscilla-

tion detection interrupt request is generated. At the same time, the on-chip oscillator starts oscillating.

In this case, although the CPU clock is derived from the sub clock as it was before the interrupt oc-

curred, the peripheral function clocks now are derived from the on-chip oscillator clock.

• To enter wait mode while using the oscillation stop, re-oscillation detection function, set the CM02 bit to

“0” (peripheral function clocks not turned off during wait mode).

• Since the oscillation stop, re-oscillation detection function is provided in preparation for main clock stop

due to external factors, set the CM20 bit to “0” (Oscillation stop, re-oscillation detection function dis-

abled) where the main clock is stopped or oscillated in the program, that is where the stop mode is

selected or the CM05 bit is altered.

• This function cannot be used if the main clock frequency is 2 MHz or less. In that case, set the CM20 bit

to “0”.

Figure 7.8.3.1.

Procedure to Switch Clock Source From On-chip Oscillator to Main Clock

Switch to the main clock

Determine several times whether

the CM23 bit is set to 0

(main clock oscillates)

Set the CM22 bit to 0

("oscillatin stop, re-oscillation" not detected)

Set the CM06 bit to 1

(divide-by-8 mode)

Set the CM21 bit to 0

(main clock or PLL clock)

CM06: Bit in the CM0 register

CM23 to CM21: Bits in the CM2 register

Yes

End

NOTE:

1. If the clock source for CPU clock is to be changed to PLL clock, set to PLL operation

mode after set to high-speed mode.

8. Protection

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8. Protection

Note The PRC3 bit in the PRCR register is not available in M16C/26T.

In the event that a program runs out of control, this function protects the important registers so that they will

not be rewritten easily. Figure 8.1 shows the PRCR register. The following lists the registers protected by

the PRCR register.

• Registers protected by PRC0 bit: CM0, CM1, CM2, PLC0, ROCR and PCLKR registers

• Registers protected by PRC1 bit: PM0, PM1, PM2, TB2SC, INVC0 and INVC1 registers

• Registers protected by PRC2 bit: PD9, PACR and NDDR registers

• Registers protected by PRC3 bit: VCR2 and D4INT registers

Set the PRC2 bit to “1” (write enabled) and then write to SFR area, and the PRC2 bit will be cleared to “0”

(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after

setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in

which the PRC2 bit is set to “1” and the next instruction. The PRC0, PRC1 and PRC3 bits are not automati-

cally cleared to “0” by writing to any address. They can only be cleared in a program.

Protect register

Symbol Address After reset

PRCR 000A16 XX0000002

Bit nameBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

0 : Write protected

1 : Write enabled

PRC1

PRC0

PRC2

Function RW

Nothing is assigned. When write, set to "0". When read, its

content is indeterminate.

Reserved bit Must set to "0"

Protect bit 0

Protect bit 1

Protect bit 2

Enable write to CM0, CM1, CM2,

ROCR, PLC0 and PCLKR registers

0 : Write protected

1 : Write enabled

Enable write to PM0, PM1, PM2,

TB2SC, INVC0 and INVC1

registers

0 : Write protected

1 : Write enabled

Enable write to PD9, PACR and

NDDR registers

PRC3

Protect bit 3

0 : Write protected

1 : Write enabled

Enable write to VCR2 and D4INT

registers

(b5-b4)

(b7-b6)

NOTE:

1. The PRC2 bit is set to "0" if data is written to the SFR area after the PRC2 bit is set to "1". The

PRC0, PRC1 and PRC3 bits are not automatically set to "0". Set them to "0" by program.

Figure 8.1. PRCR Register

9. Interrupt

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• Maskable Interrupt: An interrupt which can be enabled (disabled) by the interrupt enable flag (I flag) or

whose interrupt priority can be changed by priority level.

• Non-maskable Interrupt: An interrupt which cannot be enabled (disabled) by the interrupt enable flag

(I flag) or whose interrupt priority cannot be changed by priority level.

Figure 9.1.1. Interrupts

Interrupt











Software

(Non-maskable interrupt)

Hardware











Special

(Non-maskable interrupt)

Peripheral function (1)

(Maskable interrupt)











Undefined instruction (UND instruction)

Overflow (INTO instruction)

BRK instruction

INT instruction











_______

NMI

________

DBC (2)

Watchdog timer

Oscillation stop and re-oscillation

detection

Low voltage detection

Single step (2)

Address match

NOTES:

1. Peripheral function interrupts are generated by the microcomputer's internal functions.

Do not normally use this interrupt because it is provided exclusively for use by development tools.

9. Interrupt

Note

The 42-pin package does not use UART0 transmission interrupt and UART0 reception interrupt of

peripheral function.

M16C/26T does not use voltage down detection interrupt.

9.1 Type of Interrupts

Figure 9.1.1 shows types of interrupts.

9. Interrupt

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9.1.1 Software Interrupts

A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable

interrupts.

9.1.1.1 Undefined Instruction Interrupt

An undefined instruction interrupt occurs when executing the UND instruction.

9.1.1.2 Overflow Interrupt

An overflow interrupt occurs when executing the INTO instruction with the O flag set to “1” (the opera-

tion resulted in an overflow). The following are instructions whose O flag changes by arithmetic: ABS,

ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB

9.1.1.3 BRK Interrupt

A BRK interrupt occurs when executing the BRK instruction.

9.1.1.4 INT Instruction Interrupt

An INT instruction interrupt occurs when executing the INT instruction. Software interrupt Nos. 0 to 63

can be specified for the INT instruction. Because software interrupt Nos. 4, 8 to 31 are assigned to

peripheral function interrupts, the same interrupt routine as for peripheral function interrupts can be

executed by executing the INT instruction.

In software interrupt Nos. 0 to 31, the U flag is saved to the stack during instruction execution and is

cleared to “0” (ISP selected) before executing an interrupt sequence. The U flag is restored from the

stack when returning from the interrupt routine. In software interrupt Nos. 32 to 63, the U flag does not

change state during instruction execution, and the SP then selected is used.

9. Interrupt

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9.1.2 Hardware Interrupts

Hardware interrupts are classified into two types — special interrupts and peripheral function interrupts.

9.1.2.1 Special Interrupts

Special interrupts are non-maskable interrupts.

_______

9.1.2.1.1 NMI Interrupt

_______ _______

An NMI interrupt is generated when input on the NMI pin changes state from high to low. For details

_______ _______

about the NMI interrupt, refer to the section 9.7 NMI Interrupt.

________

9.1.2.1.2 DBC Interrupt

This interrupt is exclusively for debugger, do not use in any other circumstances.

9.1.2.1.3 Watchdog Timer Interrupt

Generated by the watchdog timer. Once a watchdog timer interrupt is generated, be sure to initialize

the watchdog timer. For details about the watchdog timer, refer to the section 10. Watchdog Timer.

9.1.2.1.4 Oscillation Stop and Re-oscillation Detection Interrupt

Generated by the oscillation stop and re-oscillation detection function. For details about the oscilla-

tion stop and re-oscillation detection function, refer to the section 7. Clock Generating Circuit.

9.1.2.1.5 Voltage Down Detection Interrupt

Generated by the voltage detection circuit. For details about the voltage detection circuit, refer to the

section 5.5 Voltage Detection Circuit.

9.1.2.1.6 Single-step Interrupt

Do not normally use this interrupt because it is provided exclusively for use by development tools.

9.1.2.1.7 Address Match Interrupt

An address match interrupt is generated immediately before executing the instruction at the address

indicated by the RMAD0 or RMAD1 register, if the corresponding enable bit (the AIER0 or AIER1 bit

in the AIER register) is set to “1”. For details about the address match interrupt, refer to the section

9.9 Address Match Interrupt.

9.1.2.2 Peripheral Function Interrupts

Peripheral function interrupts are maskable interrupts and generated by the microcomputer's internal

functions. The interrupt sources for peripheral function interrupts are listed in Table 9.2.2.1

Relocatable Vector Tables. For details about the peripheral functions, refer to the description of

each peripheral function in this manual.

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Interrupt source Vector table addresses Remarks Reference

Address (L) to address (H)

Undefined instruction FFFDC16 to FFFDF16 Interrupt on UND instruction M16C/60, M16C/20

Overflow FFFE016 to FFFE316 Interrupt on INTO instruction serise software

BRK instruction FFFE4 16 to FFFE716 maual

Address match FFFE816 to FFFEB16

Address match interrupt

Single step (1) FFFEC16 to FFFEF16

Watchdog timer FFFF016 to FFFF316 Watchdog timer

Oscillation stop and

re-oscillation detection Clock generating circuit

Voltage down

detection

Voltage detection circuit

________

DBC (1) FFFF416 to FFFF716

_______

NMI FFFF816 to FFFFB16 _______

NMI interrupt

Reset (2) FFFFC16 to FFFFF16 Reset

Figure 9.2.1. Interrupt Vector

AAAAAAAAA

Mid address

AAAAAAAAA

Low address

AAAAAAAAA

0 0 0 0 High address

AAAAAAAAA

0 0 0 0 0 0 0 0

Vector address (L)

LSB

MSB

Vector address (H)

9.2 Interrupts and Interrupt Vector

One interrupt vector consists of 4 bytes. Set the start address of each interrupt routine in the respective

interrupt vectors. When an interrupt request is accepted, the CPU branches to the address set in the

corresponding interrupt vector. Figure 9.2.1 shows the interrupt vector.

Table 9.2.1.1. Fixed Vector Tables

If the contents of address

FFFE716 is FF16, program ex-

ecution starts from the address

shown by the vector in the

relocatable vector table.

9.2.1 Fixed Vector Tables

The fixed vector tables are allocated to the addresses from FFFDC16 to FFFFF16. Table 9.2.1.1 lists the

fixed vector tables. In the flash memory version of microcomputer, the vector addresses (H) of fixed

vectors are used by the ID code check function. For details, refer to the section 17.3 Flash Memory

Rewrite Disabling Function.

NOTES:

Do not normally use this interrupt because it is provided exclusively for use by development tools.

2. The b3 to b0 in address 0FFFFF16 are reserve bits. Set these bits to “11112”.

9. Interrupt

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Table 9.2.2.1. Relocatable Vector Tables

Software interrupt

number Reference

Vector address

(1)

Address (L) to address (H)

5 to 7

1 to 3

Interrupt source

BRK instruction

INT3

INT4

INT5 (2)

(2)

DMA0

DMA1

Key input interrupt

A/D

UART0 transmit

UART0 receive

UART1 transmit

UART1 receive

Timer A0

Timer A1

Timer A2

Timer A3

Timer A4

Timer B0

Timer B1

Timer B2

INT0

INT1

INT2

Software interrupt

UART 2 bus collision detection

UART2 transmit, NACK2 (3)

UART2 receive, ACK2 (3)

M16C/60, M16C/20

series software

manual

INT interrupt

Serial I/O

DMAC

Key input interrupt

A/D convertor

Serial I/O

Timer

INT interrupt

M16C/60, M16C/20

series software

manual

(4)

(Reserved)

+0 to +3 (0000

to 0003

)

+44 to +47 (002C

to 002F

)

+48 to +51 (0030

to 0033

)

+52 to +55 (0034

to 0037

)

+56 to +59 (0038

to 003B

)

+68 to +71 (0044

to 0047

)

+72 to +75 (0048

to 004B

)

+76 to +79 (004C

to 004F

)

+80 to +83 (0050

to 0053

)

+84 to +87 (0054

to 0057

)

+88 to +91 (0058

to 005B

)

+92 to +95 (005C

to 005F

)

+96 to +99 (0060

to 0063

)

+100 to +103 (0064

to 0067

)

+104 to +107 (0068

to 006B

)

+108 to +111 (006C

to 006F

)

+112 to +115 (0070

to 0073

)

+116 to +119 (0074

to 0077

)

+120 to +123 (0078

to 007B

)

+124 to +127 (007C

to 007F

)

+128 to +131 (0080

to 0083

)

+252 to +255 (00FC

to 00FF

)

+40 to +43 (0028

to 002B

)

+60 to +63 (003C

to 003F

)

+64 to +67 (0040

to 0043

)

+32 to +35 (0020

to 0023

)

+16 to +19 (0010

to 0013

)

+36 to +39 (0024

to 0027

)

(4)

(5)

(Reserved)

NOTES:

1. Address relative to address in INTB.

2. Set the IFSR6 and IFSR7 bits in the IFSR register.

3. During I

C bus mode, NACK and ACK interrupts comprise the interrupt source.

4. These interrupts cannot be disabled using the I flag.

5. Bus collision detection:

During IEBus mode, this bus collision detection constitutes the cause of an interrupt.

During I

C bus mode, however, a start condition or a stop condition detection constitutes the cause of an interrupt.

9.2.2 Relocatable Vector Tables

The 256 bytes beginning with the start address set in the INTB register comprise a reloacatable vector

table area. Table 9.2.2.1 lists the relocatable vector tables. Setting an even address in the INTB register

results in the interrupt sequence being executed faster than in the case of odd addresses.

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9.3 Interrupt Control

The following describes how to enable/disable the maskable interrupts, and how to set the priority in which

order they are accepted. What is explained here does not apply to nonmaskable interrupts.

Use the I flag in the FLG register, IPL, and the ILVL2 to ILVL0 bits in the each interrupt control register to

enable/disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in each

interrupt control register.

Figure 9.3.1 shows the interrupt control registers.

Figure 9.3.2 shows the IFSR, IFSR2A registers.

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Figure 9.3.1. Interrupt Control Registers

Symbol Address After reset

INT3IC 004416 XX00X000 2

INT5IC 004816 XX00X0002

INT4IC 004916 XX00X0002

INT0IC to INT2IC 005D16 to 005F16 XX00X0002

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

ILVL0

POL

No functions are assigned.

When writing to these bits, write “0”. The values in these bits

when read are indeterminate.

Interrupt priority level

select bit

Interrupt request bit

Polarity select bit

Reserved bit

0: Interrupt not requested

1: Interrupt requested

0 : Selects falling edge (3)

1 : Selects rising edge

Must always be set to “0”

ILVL1

ILVL2

(1)

Interrupt control register (2)

b7 b6 b5 b4 b3 b2 b1 b0

Bit name FunctionBit symbol RW

Symbol Address After reset

BCNIC 004A16 XXXXX0002

DM0IC, DM1IC 004B16, 004C16 XXXXX0002

KUPIC 004D16 XXXXX0002

ADIC 004E16 XXXXX0002

S0TIC to S2TIC 005116, 005316, 004F16 XXXXX0002

S0RIC to S2RIC 005216, 005416, 005016 XXXXX0002

TA0IC to TA4IC 005516 to 005916 XXXXX0002

TB0IC to TB2IC 005A16 to 005C16 XXXXX0002

ILVL0

Interrupt priority level

select bit

Interrupt request bit 0 : Interrupt not requested

1 : Interrupt requested

ILVL1

ILVL2

No functions are assigned.

When writing to these bits, write “0”. The values in these bits

when read are indeterminate.

(1)

0 0 0 : Level 0 (interrupt disabled)

0 0 1 : Level 1

0 1 0 : Level 2

0 1 1 : Level 3

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

b2 b1 b0

0 0 0 : Level 0 (interrupt disabled)

0 0 1 : Level 1

0 1 0 : Level 2

0 1 1 : Level 3

1 0 0 : Level 4

1 0 1 : Level 5

1 1 0 : Level 6

1 1 1 : Level 7

b2 b1 b0

(b7-b4)

(b7-b6)

(b5)

NOTES:

1.This bit can only be reset by writing “0” (Do not write “1”).

2. To rewrite the interrupt control registers, do so at a point that does not generate the interrupt request for that

NOTES:

1. This bit can only be reset by writing “0” (Do not write “1”).

2. To rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register.

For details, see 19.5 Interrupts.

3. If the IFSRi bit (i = 0 to 5) in the IFSR register is “1” (both edges), set the POL bit in the INTiIC register to “0” (falling

edge).

BCNIC, DM0IC, DM1IC, KUPIC, ADIC, S0TIC to S2TIC, S0RIC to S2RIC, TA0IC to TA4IC, TB0IC TO

TB2IC, INT3IC, INT4IC, INT5IC, INT0IC to INT2IC

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Figure 9.3.2. IFSR Register and IFSR2A Register

Interrupt request cause select register

Bit name Function

Bit symbol RW

Symbol Address After reset

IFSR 035F16 00

IFSR0

b7 b6 b5 b4 b3 b2 b1 b0

INT0 interrupt polarity

switching bit

0 : Reserved

1 : INT4

0 : Reserved

1 : INT5

0 : One edge

1 : Both edges

0 : One edge

1 : Both edges

0 : One edge

1 : Both edges

0 : One edge

1 : Both edges

0 : One edge

1 : Both edges

INT1 interrupt polarity

switching bit

INT2 interrupt polarity

switching bit

INT3 interrupt polarity

switching bit

INT4 interrupt polarity

switching bit

INT5 interrupt polarity

switching bit 0 : One edge

1 : Both edges

Interrupt request cause

select bit

Interrupt request cause

select bit

IFSR1

IFSR2

IFSR3

IFSR4

IFSR5

IFSR6

IFSR7

(1)

NOTE:

1. When setting this bit to “1” (= both edges), make sure the POL bit in the INT0IC to INT5IC register is set to

“0” (= falling edge).

Interrupt request cause select register 2

Bit name Function

Bit symbol RW

Symbol Address After reset

IFSR2A 035E

XXXXXXX0

b7 b6 b5 b4 b3 b2 b1 b0

Must be set to “1”.

(b7-b1) Nothing is assigned. When write, set to “0”.

When read, their contents are indeterminate.

IFSR20

Reserved bit RW

(1)

NOTE:

1. Set this bit to "1" before you enable interrupt after resetting.

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9.3.1 I Flag

The I flag enables or disables the maskable interrupt. Setting the I flag to “1” (= enabled) enables the

maskable interrupt. Setting the I flag to “0” (= disabled) disables all maskable interrupts.

9.3.2 IR Bit

The IR bit is set to “1” (= interrupt requested) when an interrupt request is generated. Then, when the

interrupt request is accepted and the CPU branches to the corresponding interrupt vector, the IR bit is

cleared to “0” (= interrupt not requested).

The IR bit can be cleared to “0” in a program. Note that do not write “1” to this bit.

9.3.3 ILVL2 to ILVL0 Bits and IPL

Interrupt priority levels can be set using the ILVL2 to ILVL0 bits.

Table 9.3.3.1 shows the settings of interrupt priority levels and Table 9.3.3.2 shows the interrupt priority

levels enabled by the IPL.

The following are conditions under which an interrupt is accepted:

· I flag is set to “1”

· IR bit is set to “1”

· interrupt priority level > IPL

The I flag, IR bit, ILVL2 to ILVL0 bits and IPL are independent of each other. In no case do they affect one

another.

Table 9.3.3.2. Interrupt Priority Levels

Enabled by IPL

Table 9.3.3.1. Settings of Interrupt Priority

Levels

ILVL2 to ILVL0 bits Interrupt priority

level Priority

order

000

001

010

011

100

101

110

111

Level 0 (interrupt disabled)

Level 1

Level 2

Level 3

Level 4

Level 5

Level 6

Level 7

Low

High

Enabled interrupt priority levels

Interrupt levels 1 and above are enabled

Interrupt levels 2 and above are enabled

Interrupt levels 3 and above are enabled

Interrupt levels 4 and above are enabled

Interrupt levels 5 and above are enabled

Interrupt levels 6 and above are enabled

Interrupt levels 7 and above are enabled

All maskable interrupts are disabled

IPL

000

001

010

011

100

101

110

111

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9.4 Interrupt Sequence

An interrupt sequence (the devicebehavior from the instant an interrupt is accepted to the instant the inter-

rupt routine is executed) is described here.

If an interrupt occurs during execution of an instruction, the processor determines its priority when the

execution of the instruction is completed, and transfers control to the interrupt sequence from the next

cycle. If an interrupt occurs during execution of either the SMOVB, SMOVF, SSTR or RMPA instruction,

the processor temporarily suspends the instruction being executed, and transfers control to the interrupt

sequence.

The CPU behavior during the interrupt sequence is described below. Figure 9.4.1 shows time required for

executing the interrupt sequence.

(1) The CPU gets interrupt information (interrupt number and interrupt request priority level) by reading

the address 0000016. Then it clears the IR bit for the corresponding interrupt to “0” (interrupt not

requested).

(2) The FLG register immediately before entering the interrupt sequence is saved to the CPU’s internal

temporary register(1).

(3) The I, D and U flags in the FLG register become as follows:

The I flag is cleared to “0” (interrupts disabled).

The D flag is cleared to “0” (single-step interrupt disabled).

The U flag is cleared to “0” (ISP selected).

However, the U flag does not change state if an INT instruction for software interrupt Nos. 32 to 63 is

executed.

(4) The CPU’s internal temporary register (1) is saved to the stack.

(5) The PC is saved to the stack.

(6) The interrupt priority level of the accepted interrupt is set in the IPL.

(7) The start address of the relevant interrupt routine set in the interrupt vector is stored in the PC.

After the interrupt sequence is completed, the processor resumes executing instructions from the start

address of the interrupt routine.

NOTE:

1. This register cannot be used by user.

Indeterminate

(1)

123456789 101112 13 14 15 16 17 18

Indeterminate

(1)

SP-2

contents SP-4

contents vec

contents vec+2

contents

Interrupt

information

Address

000016 Indeterminate

(1)

SP-2 SP-4 vec vec+2 PC

CPU clock

Address bus

Data bus

(2)

NOTES:

1. The indeterminate state depends on the instruction queue buffer. A read cycle occurs when the

instruction queue buffer is ready to accept instructions.

2. RD is the internal signal which is set to “L” when the internal memory is read out and WR is the

internal signal which is set to “L” when the internal memory is written.

Figure 9.4.1. Time Required for Executing Interrupt Sequence

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Interrupt sources

Level that is set to IPL

_______

Watchdog timer, NMI, Oscillation stop and re-oscillation detection,

voltage down detection _________

Software, address match, DBC, single-step Not changed

9.4.2 Variation of IPL when Interrupt Request is Accepted

When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is set

in the IPL.

When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels listed

in Table 9.4.2.1 is set in the IPL. Shown in Table 9.4.2.1 are the IPL values of software and special

interrupts when they are accepted.

Table 9.4.2.1. IPL Level That is Set to IPL When A Software or Special Interrupt Is Accepted

Instruction Interrupt sequence Instruction in

interrupt routine

Time

Interrupt response time

(a) (b)

Interrupt request acknowledgedInterrupt request generated

(a) The time from when an interrupt request is generated till when the instruction then

executing is completed. The length of this time varies with the instruction being

executed. The DIVX instruction requires the longest time, which is equal to 30 cycles

(without wait state, the divisor being a register).

(b) The time during which the interrupt sequence is executed. For details, see the table

below. Note, however, that the values in this table must be increased 2 cycles for the

DBC interrupt and 1 cycle for the address match and single-step interrupts.

Interrupt vector address

Even

Odd

SP value

Even

Odd

Even

Odd

Without wait

18 cycles

19 cycles

20 cycles

Figure 9.4.1.1. Interrupt response time

9.4.1 Interrupt Response Time

Figure 9.4.1.1 shows the interrupt response time. The interrupt response or interrupt acknowledge time

denotes the time from when an interrupt request is generated till when the first instruction in the interrupt

routine is executed. Specifically, it consists of the time from when an interrupt request is generated till

when the instruction then executing is completed ((a) in Figure 9.4.1.1) and the time during which the

interrupt sequence is executed ((b) in Figure 9.4.1.1).

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9.4.3 Saving Registers

In the interrupt sequence, the FLG register and PC are saved to the stack.

At this time, the 4 high-order bits of the PC and the 4 high-order (IPL) and 8 low-order bits in the FLG

9.4.3.1 shows the stack status before and after an interrupt request is accepted.

The other necessary registers must be saved in a program at the beginning of the interrupt routine. Use

the PUSHM instruction, and all registers except SP can be saved with a single instruction.

Address

Content of previous stack

Stack

[SP]

SP value before

interrupt request is

accepted.

m – 1

m – 2

m – 3

m – 4

Stack status before interrupt request

is acknowledged Stack status after interrupt request

is acknowledged

Content of previous stack

m + 1

MSB LSB

m – 1

m – 2

m – 3

m – 4

Address

FLG

Content of previous stack

Stack

FLG

[SP]

New SP value

Content of previous stack

m + 1

MSB LSB

Figure 9.4.3.1. Stack Status Before and After Acceptance of Interrupt Request

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Figure 9.4.3.2. Operation of Saving Register

(2) SP contains odd number

[SP] (Odd)

[SP] – 1 (Even)

[SP] – 2 (Odd)

[SP] – 3 (Even)

[SP] – 4 (Odd)

[SP] – 5 (Even)

Address Sequence in which order

registers are saved

(2)

(1)

Finished saving registers

in four operations.

(3)

(4)

(1) SP contains even number

[SP] (Even)

[SP] – 1 (Odd)

[SP] – 2 (Even)

[SP] – 3 (Odd)

[SP] – 4 (Even)

[SP] – 5 (Odd)

NOTE:

1. [SP] denotes the initial value of the SP when interrupt request is acknowledged.

After registers are saved, the SP content is [SP] minus 4.

Address

Stack

FLG

Sequence in which order

registers are saved

(2) Saved simultaneously,

all 16 bits

(1) Saved simultaneously,

all 16 bits

Finished saving registers

in two operations.

Stack

FLG

Saved, 8 bits at a time

FLG

The operation of saving registers carried out in the interrupt sequence is dependent on whether the SP(1),

at the time of acceptance of an interrupt request, is even or odd. If the stack pointer (1) is even, the FLG

Figure 9.4.3.2 shows the operation of the saving registers.

NOTE:

1. When any INT instruction in software numbers 32 to 63 has been executed, this is the SP indicated

by the U flag. Otherwise, it is the ISP.

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9.5 Interrupt Priority

If two or more interrupt requests are generated while executing one instruction, the interrupt request that

has the highest priority is accepted.

For maskable interrupts (peripheral functions), any desired priority level can be selected using the ILVL2 to

ILVL0 bits. However, if two or more maskable interrupts have the same priority level, their interrupt priority

is resolved by hardware, with the highest priority interrupt accepted.

The watchdog timer and other special interrupts have their priority levels set in hardware. Figure 9.5.1

shows the priorities of hardware interrupts.

Software interrupts are not affected by the interrupt priority. If an instruction is executed, control branches

invariably to the interrupt routine.

9.4.4 Returning from an Interrupt Routine

The FLG register and PC in the state in which they were immediately before entering the interrupt se-

quence are restored from the stack by executing the REIT instruction at the end of the interrupt routine.

Thereafter the CPU returns to the program which was being executed before accepting the interrupt

request.

Return the other registers saved by a program within the interrupt routine using the POPM or similar

instruction before executing the REIT instruction.

9.5.1 Interrupt Priority Resolution Circuit

The interrupt priority resolution circuit is used to select the interrupt with the highest priority among those

requested.

Figure 9.5.1.1 shows the circuit that judges the interrupt priority level.

Figure 9.5.1. Hardware Interrupt Priority

Reset

W atchdog Timer ,

Oscillation stop and re-oscillation

detection,

voltage down detection

Peripheral function

Single step

Address match

High

Low

NMI

DBC

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Figure 9.5.1.1. Interrupts Priority Select Circuit

Timer B2

Timer B0

Timer A3

Timer A1

Timer B1

Timer A4

Timer A2

UART1 reception

UART0 reception

UART2 reception, ACK2

A/D conversion

DMA1

UART 2 bus collision

Timer A0

UART1 transmission

UART0 transmission

UART2 transmission, NACK2

Key input interrupt

DMA0

IPL

I flag

INT1

INT2

INT0

Watchdog timer

DBC

NMI

Interrupt

request

accepted

Level 0 (initial value)

Priority level of each interrupt

Highest

Lowest

Priority of peripheral function interrupts

(if priority levels are same)

INT3

INT5

INT4

Address match

Interrupt request level resolution output to clock

generating circuit (Fig.7.1.)

Oscillation stop and

re-oscillation detection

Voltage down detection

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______

9.6 INT Interrupt

_______

INTi interrupt (i=0 to 5) is triggered by the edges of external inputs. The edge polarity is selected using the

IFSRi bit in the IFSR register.

________ ________ ________

To use the INT4 interrupt, set the IFSR6 bit in the IFSR register to "1" (=INT4). To use the INT5 interrupt, set

________

the IFSR7 bit in the IFSR register to "1" (=INT5).

After modifiying the IFSR6 or IFSR7 bit, clear the corresponding IR bit to "0" (=interrupt not requested)

before enabling the interrupt.

________

The INT5 input has an effective digital debounce function for a noize rejection. Refer to 16.6 Digital

________

Debounce function for this detail. When using INT5 interrupt to exit stop mode, set the P17DDR register

to "FF16" before entering stop mode.

Figure 9.6.1 shows the IFSR register.

Figure 9.6.1. IFSR Register

Interrupt request cause select register

Bit name Function

Bit symbol RW

Symbol Address After reset

IFSR 035F

0016

IFSR0

b7 b6 b5 b4 b3 b2 b1 b0

INT0 interrupt polarity

switching bit

0 : Reserved

1 : INT4

0 : Reserved

1 : INT5

0 : One edge

1 : Both edges

0 : One edge

1 : Both edges

0 : One edge

1 : Both edges

0 : One edge

1 : Both edges

0 : One edge

1 : Both edges

INT1 interrupt polarity

switching bit

INT2 interrupt polarity

switching bit

INT3 interrupt polarity

switching bit

INT4 interrupt polarity

switching bit

INT5 interrupt polarity

switching bit 0 : One edge

1 : Both edges

Interrupt request cause

select bit

Interrupt request cause

select bit

IFSR1

IFSR2

IFSR3

IFSR4

IFSR5

IFSR6

IFSR7

(1)

NOTE:

1. When setting this bit to “1” (= both edges), make sure the POL bit in the INT0IC to INT5IC register is set to

“0” (= falling edge).

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Figure 9.8.1. Key Input Interrupt

______

9.7 NMI Interrupt

_______ _______

An NMI interrupt request is generated when input on the NMI pin changes state from high to low, after the

_______ ______

NMI interrupt was enabled by writing a “1” to PM24 bit in the PM2 register. The NMI interrupt is a non-

maskable interrupt, once it is enabled.

_______

The input level of this NMI interrupt input pin can be read by accessing the P8_5 bit in the P8 register.

_______

NMI is disabled by default after reset (the pin is a GPIO pin, P85) and can be enabled using PM24 bit in the

PM2 register. Once enabled, it can only be disabled by a reset signal.

_______

The NMI input has an effective digital debounce function for a noise rejection. Refer to 16.6 Digital

_______

Debounce Function for this detail. When using NMI interrupt to exit stop mode, set the NDDR register to

"FF16" before entering stop mode.

9.8 Key Input Interrupt

Of P104 to P107, a key input interrupt is generated when input on any of the P104 to P107 pins which has

had the PD10_4 to PD10_7 bits in the PD10 register set to “0” (= input) goes low. Key input interrupts can

be used as a key-on wakeup function, the function which gets the microcomputer out of wait or stop mode.

However, if you intend to use the key input interrupt, do not use P104 to P107 as analog input ports. Figure

9.8.1 shows the block diagram of the key input interrupt. Note, however, that while input on any pin which

has had the PD10_4 to PD10_7 bits set to “0” (= input mode) is pulled low, inputs on all other pins of the port

are not detected as interrupts.

Interrupt control circuit

KUPIC register

Key input interrupt

request

KI3

KI2

KI1

KI0

PU25 bit in the

PD10 register

PD10_7 bit in the

PD10 register

Pull-up

transistor

PD10_7 bit in the PD10 register

PD10_6 bit in the

PD10 register

PD10_5 bit in the

PD10 register

PD10_4 bit in the

PD10 register

Pull-up

transistor

Pull-up

transistor

Pull-up

transistor

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Table 9.9.2. Relationship Between Address Match Interrupt Sources and Associated Registers

Address match interrupt sources Address match interrupt enable bit Address match interrupt register

Address match interrupt 0 AIER0 RMAD0

Address match interrupt 1 AIER1 RMAD1

9.9 Address Match Interrupt

An address match interrupt request is generated immediately before executing the instruction at the ad-

dress indicated by the RMADi register (i=0 to 1). Set the start address of any instruction in the RMADi

address match interrupt is unaffected by the I flag and IPL. For address match interrupts, the value of the

PC that is saved to the stack area varies depending on the instruction being executed (refer to “Saving

Registers”).

(The value of the PC that is saved to the stack area is not the correct return address.) Therefore, follow one

of the methods described below to return from the address match interrupt.

• Rewrite the content of the stack and then use the REIT instruction to return.

• Restore the stack to its previous state before the interrupt request was accepted by using the POP or

similar other instruction and then use a jump instruction to return.

Table 9.9.1 shows the value of the PC that is saved to the stack area when an address match interrupt

request is accepted.

Figure 9.9.1 shows the AIER, RMAD0 and RMAD1 registers.

Table 9.9.1. Value of the PC that is saved to the stack area when an address match interrupt

request is accepted.

• 2-byte op-code instruction

• 1-byte op-code instructions which are followed:

ADD.B:S #IMM8,dest SUB.B:S #IMM8,dest AND.B:S #IMM8,dest

OR.B:S #IMM8,dest MOV.B:S #IMM8,dest STZ.B #IMM8,dest

STNZ.B #IMM8,dest STZX.B #IMM81,#IMM82,dest

CMP.B:S #IMM8,dest PUSHM src POPM dest

JMPS #IMM8 JSRS #IMM8

MOV.B:S #IMM,dest (However, dest=A0 or A1)

Instructions other than the above

Instruction at the address indicated by the RMADi register

Value of the PC that is

saved to the stack area

The address

indicated by the

RMADi register +2

The address

indicated by the

RMADi register +1

Value of the PC that is saved to the stack area : Refer to “Saving Registers”.

Op-code is an abbreviation of Operation Code. It is a portion of instruction code.

Refer to Chapter 4 Instruction Code/Number of Cycles in M16C/60, M16C/20 Series Software Manual. Op-code is shown

as a bold-framed figure directly below the Syntax.

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Figure 9.9.1. AIER Register, RMAD0 and RMAD1 Registers

Bit nameBit symbol

Symbol Address After reset

AIER 0009

XXXXXX00

Address match interrupt enable register

Function

Address match interrupt 0

enable bit 0 : Interrupt disabled

1 : Interrupt enabled

AIER0

Address match interrupt 1

enable bit

AIER1

Symbol Address After reset

RMAD0 0012

to 0010

X00000

RMAD1 0016

to 0014

X00000

b7 b6 b5 b4 b3 b2 b1 b0

Address setting register for address match interrupt

Function Setting range

Address match interrupt register i (i = 0 to 1)

00000

to FFFFF

0 : Interrupt disabled

1 : Interrupt enabled

b0 b7 b0b3

(b19) (b16) b7 b0

(b15) (b8)

(b23)

(b7-b2)

Nothing is assigned.

When write, set to “0”.

When read, their contents are indeterminate.

Nothing is assigned.

When write, set to “0”.

When read, their contents are indeterminate.

10. Watchdog Timer

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For example, when CPU clock = 16 MHz and the divide-by-N value for the prescaler= 16, the watchdog timer

period is approx. 32.8 ms.

The watchdog timer is initialized by writing to the WDTS register. The prescaler is initialized after reset. Note that

the watchdog timer and the prescaler both are inactive after reset, so that the watchdog timer is activated to start

counting by writing to the WDTS register.

Write the WDTS register with shorter cycle than the watchdog timer cycle. Set the WDTS register also in the

beginning of the watchdog timer interrupt routine.

In stop mode, wait mode and when erase/program opration is excuting in EW1 mode without erase suspend

requeired, the watchdog timer and prescaler are stopped. Counting is resumed from the held value when the

modes or state are released.

Figure 10.1 shows the block diagram of the watchdog timer. Figure 10.2 shows the watchdog timer-related registers.

With main clock source chosen for CPU clock, on-chip oscillator clock, PLL clock

Watchdog timer period =

With sub-clock chosen for CPU clock

Watchdog timer period = Prescaler dividing (16 or 128) X Watchdog timer count (32768)

CPU clock

Prescaler dividing (2) X Watchdog timer count (32768)

CPU clock

Figure 10.1. Watchdog Timer Block Diagram

10. Watchdog Timer

The watchdog timer is the function that detects when a program is out of control. Use the watchdog timer is

recommended to improve reliability of the system. The watchdog timer contains a 15-bit counter which is

decremented by the CPU clock that the prescaler divides. The PM12 bit in the PM1 register determines whether

to generate a watchdog timer interrupt request or reset the watchdog timer when the watchdog timer underflows.

The PM12 bit can only be set to “1” (reset). Once the PM12 bit is set to “1”, it cannot be changed to “0” (watchdog

timer interrupt) by program. Refer to “5.3 Watchdog Timer Reset” for watchdog timer reset.

When the main clock, on-chip oscillator clock, or PLL clock runs as CPU clock, the WDC7 bit in the WDC register

determines whether the prescaler divides the clock by 16 or 128. When the sub clock runs as CPU clock, the

prescaler divides the clock by 2 regardless of the WDC7 bit setting. Watchdog timer cycle is calculated as

follows. Marginal errors, due to the prescaler, may occur in watchdog timer cycle.

CPU clock

Write to WDTS register

PM12 = 0

Watchdog timer

Set to 7FFF

1/128

1/16

CM07 = 0

WDC7 = 1

CM07 = 0

WDC7 = 0

CM07 = 1

1/2

Prescaler

PM12 = 1

Reset

PM22 = 0

PM22 = 1

On-chip oscillator clock

Internal reset signal

(low active)

Watchdog timer

interrupt request

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10.1 Count Source Protective Mode

In this mode, a on-chip oscillator clock is used for the watchdog timer count source. The watchdog timer

can be kept being clocked even when CPU clock stops as a result of run-away.

Before this mode can be used, the following register settings are required:

(1) Set the PRC1 bit in the PRCR register to “1” (enable writes to PM1 and PM2 registers).

(2) Set the PM12 bit in the PM1 register to “1” (reset when the watchdog timer underflows).

(3) Set the PM22 bit in the PM2 register to “1” (on-chip oscillator clock used for the watchdog timer count

source).

(4) Set the PRC1 bit in the PRCR register to “0” (disable writes to PM1 and PM2 registers).

(5) Write to the WDTS register (watchdog timer starts counting).

Setting the PM22 bit to “1” results in the following conditions

• The on-chip oscillator continues oscillating even if the CM21 bit in the CM2 register is set to "0" (main

clock or PLL clock) (system clock of count source selected by the CM21 bit is valid)

• The on-chip oscillator starts oscillating, and the in-chip oscillator clock becomes the watchdog timer count

source.

• The CM10 bit in the CM1 register is disabled against write. (Writing a “1” has no effect, nor is stop mode

entered.)

• The watchdog timer does not stop when in wait mode.

Figure 10.2 WDC Register and WDTS Register

Watchdog timer period = Watchdog timer count (32768)

on-chip oscillator clock

Watchdog Timer Control Register

Symbol Address After Reset

WDC 000F16 00XXXXXX2

FunctionBit Symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

High-order bit of watchdog timer

WDC7

Bit Name

Prescaler select bit 0: Divided by 16

1: Divided by 128

(b4-b0)

(b6-b5) Reserved bit Set to “0”

Watchdog Timer Start Register

Symbol Address After Reset

WDTS 000E16 Indeterminate

b7 b0

Function

The watchdog timer is initialized and starts counting after a write instruction to

this register. The watchdog timer value is always initialized to “7FFF 16”

regardless of whatever value is written.

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11. DMAC

Note

Do not use UART0 transfer and UART0 reception interrupt request as a DMA request in the 42-pin

package.

The DMAC (Direct Memory Access Controller) allows data to be transferred without the CPU intervention.

Two DMAC channels are included. Each time a DMA request occurs, the DMAC transfers one (8 or 16-bit)

data from the source address to the destination address. The DMAC uses the same data bus as used by

the CPU. Because the DMAC has higher priority of bus control than the CPU and because it makes use of

a cycle steal method, it can transfer one word (16 bits) or one byte (8 bits) of data within a very short time

after a DMA request is generated. Figure 11.1 shows the block diagram of the DMAC. Table 11.1 shows the

DMAC specifications. Figures 11.2 to 11.4 show the DMAC-related registers.

A DMA request is generated by a write to the DSR bit in the DMiSL register (i = 0,1), as well as by an

interrupt request which is generated by any function specified by the DMS and DSEL3 to DSEL0 bits in the

DMiSL register. However, unlike in the case of interrupt requests, DMA requests are not affected by the I

flag and the interrupt control register, so that even when interrupt requests are disabled and no interrupt

request can be accepted, DMA requests are always accepted. Furthermore, because the DMAC does not

affect interrupts, the IR bit in the interrupt control register does not change state due to a DMA transfer.

A data transfer is initiated each time a DMA request is generated when the DMAE bit in the DMiCON

than the DMA transfer cycle, the number of transfer requests generated and the number of times data is

transferred may not match. For details, refer to 11.4 DMA Requests.

Figure 11.1 DMAC Block Diagram

Data bus low-order bits

DMA latch high-order bits DMA latch low-order bits

DMA0 source pointer SAR0(20)

DMA0 destination pointer DAR0 (20)

DMA0 forward address pointer (20)

(1)

Data bus high-order bits

Address bus

DMA1 destination pointer DAR1 (20)

DMA1 source pointer SAR1 (20)

DMA1 forward address pointer (20)

(1)

DMA0 transfer counter reload register TCR0 (16)

DMA0 transfer counter TCR0 (16)

DMA1 transfer counter reload register TCR1 (16)

DMA1 transfer counter TCR1 (16)

(addresses 0029

, 0028

)

(addresses 0039

, 0038

)

(addresses 0022

to 0020

)

(addresses 0026

to 0024

)

(addresses 0032

to 0030

)

(addresses 0036

to 0034

)

NOTE:

1. Pointer is incremented by a DMA request.

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Table 11.1 DMAC Specifications

Item Specification

No. of channels 2 (cycle steal method)

Transfer memory space •From any address in the 1M bytes space to a fixed address

•From a fixed address to any address in the 1M bytes space

•From a fixed address to a fixed address

Maximum No. of bytes transferred

128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)

DMA request factors (1, 2) ________ ________

Falling edge of INT0 or INT1

________ ________

Both edge of INT0 or INT1

Timer A0 to timer A4 interrupt requests

Timer B0 to timer B2 interrupt requests

UART0 transfer, UART0 reception interrupt requests

UART1 transfer, UART1 reception interrupt requests

UART2 transfer, UART2 reception interrupt requests

A/D conversion interrupt requests

Software triggers

Channel priority DMA0 > DMA1 (DMA0 takes precedence)

Transfer unit 8 bits or 16 bits

Transfer address direction forward or fixed (The source and destination addresses cannot both be

in the forward direction.)

Transfer mode Single transfer Transfer is completed when the DMAi transfer counter (i = 0,1)

underflows after reaching the terminal count.

Repeat transfer When the DMAi transfer counter underflows, it is reloaded with the value

of the DMAi transfer counter reload register and a DMA transfer is con

tinued with it.

DMA interrupt request generation timing

When the DMAi transfer counter underflowed

DMA startup Data transfer is initiated each time a DMA request is generated when the

DMAE bit in the DMAiCON register is set to “1” (enabled).

DMA shutdown

Single transfer •When the DMAE bit is set to “0” (disabled)

•After the DMAi transfer counter underflows

Repeat transfer When the DMAE bit is set to “0” (disabled)

When a data transfer is started after setting the DMAE bit to “1” (en

abled), the forward address pointer is reloaded with the value of the

SARi or the DARi pointer whichever is specified to be in the forward

direction and the DMAi transfer counter is reloaded with the value of the

DMAi transfer counter reload register.

N OTES:

1. DMA transfer is not effective to any interrupt. DMA transfer is affected neither by the I flag nor by the

interrupt control register.

2. The selectable causes of DMA requests differ with each channel.

3. Make sure that no DMAC-related registers (addresses 002016 to 003F16) are accessed by the DMAC.

11. DMAC

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Figure 11.2 DM0SL Register

DMA0 request cause select register

Symbol Address After reset

DM0SL 03B816 0016

Function

Bit symbol

b7 b6 b5 b4 b3 b2 b1 b0

DMA request cause

select bit

DSEL0

DSEL1

DSEL2

DSEL3

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

Software DMA

request bit A DMA request is generated by

setting this bit to “1” when the DMS

bit is “0” (basic cause) and the

DSEL3 to DSEL0 bits are “00012”

(software trigger).

The value of this bit when read is “0” .

DSR

DSEL3 to DSEL0 DMS=0(basic cause of request) DMS=1(extended cause of request)

0 0 0 0

Falling edge of INT0 pin –

0 0 0 1

Software trigger –

0 0 1 0

Timer A0 –

0 0 1 1

Timer A1 –

0 1 0 0

Timer A2 –

0 1 0 1

Timer A3 –

0 1 1 0

Timer A4 Two edges of INT0 pin

0 1 1 1

Timer B0 –

1 0 0 0

Timer B1 –

1 0 0 1

Timer B2 –

1 0 1 0

UART0 transmit –

1 0 1 1

UART0 receive –

1 1 0 0

UART2 transmit –

1 1 0 1

UART2 receive –

1 1 1 0

A/D conversion –

1 1 1 1

UART1 transmit –

Bit name

DMA request cause

expansion select bit

DMS 0: Basic cause of request

1: Extended cause of request

(b5-b4)

Refer to note

NOTE:

1. The causes of DMA0 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the

manner described below.

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Figure 11.3 DM1SL Register, DM0CON Register, and DM1CON Register

DMAi control register

(i=0,1)

Symbol Address After reset

DM0CON 002C16 00000X002

DM1CON 003C16 00000X002

Bit name FunctionBit symbol

Transfer unit bit select bit

b7 b6 b5 b4 b3 b2 b1 b0

0 : 16 bits

1 : 8 bits

DMBIT

DMASL

DMAS

DMAE

Repeat transfer mode

select bit 0 : Single transfer

1 : Repeat transfer

DMA request bit 0 : DMA not requested

1 : DMA requested

0 : Disabled

1 : Enabled

0 : Fixed

1 : Forward

DMA enable bit

Source address direction

select bit (2)

Destination address

direction select bit (2) 0 : Fixed

1 : Forward

DSD

DAD

Nothing is assigned. When write, set to “0”. When

read, its content is “0”.

(1)

DMA1 request cause select register

Symbol Address After reset

DM1SL 03BA16 0016

Function

Bit symbol

b7 b6 b5 b4 b3 b2 b1 b0

DMA request cause

select bit

DSEL0

DSEL1

DSEL2

DSEL3

Software DMA

request bit

DSR

DSEL3 to DSEL0 DMS=0(basic cause of request) DMS=1(extended cause of request)

0 0 0 0

Falling edge of INT1 pin –

0 0 0 1

Software trigger –

0 0 1 0

Timer A0 –

0 0 1 1

Timer A1 –

0 1 0 0

Timer A2 –

0 1 0 1

Timer A3 –

0 1 1 0

Timer A4 –

0 1 1 1

Timer B0 Two edges of INT1

1 0 0 0

Timer B1 –

1 0 0 1

Timer B2 –

1 0 1 0

UART0 transmit –

1 0 1 1

UART0 receive –

1 1 0 0

UART2 transmit –

1 1 0 1

UART2 receive/ACK2 –

1 1 1 0

A/D conversion –

1 1 1 1

UART1 receive –

Bit name

DMA request cause

expansion select bit

DMS

(b5-b4)

(b7-b6)

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

A DMA request is generated by

setting this bit to “1” when the DMS

bit is “0” (basic cause) and the

DSEL3 to DSEL0 bits are “00012”

(software trigger).

The value of this bit when read is “0” .

0: Basic cause of request

1: Extended cause of request

Refer to note

NOTE:

1. The causes of DMA1 requests can be selected by a combination of DMS bit and DSEL3 to DSEL0 bits in the

manner described below.

NOTES:

1.The DMAS bit can be set to “0” by writing “0” in a program (This bit remains unchanged even if “1” is written).

2. At least one of the DAD and DSD bits must be “0” (address direction fixed).

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Figure 11.4 SAR0 and SAR1, DAR0 and DAR1, TCR0 and TCR1 Registers

b7 b0 b7 b0

(b8)(b15)

Function

Set the transfer count minus 1. The written value is

stored in the DMAi transfer counter reload register, and

when the DMAE bit in the DMiCON register is set to “1”

(DMA enabled) or the DMAi transfer counter

underflows when the DMASL bit in the DMiCON

transfer counter reload register is transferred to the

DMAi transfer counter. When read, the DMAi transfer

counter is read.

Symbol Address After reset

TCR0 0029

, 0028

Indeterminate

TCR1 0039

, 0038

Indeterminate

DMAi transfer counter (i = 0, 1)

Setting range

0000

to FFFF

(b23) b3 b0 b7 b0 b7 b0

(b8)(b16)(b15)(b19)

Function

Set the source address of transfer

Symbol Address After reset

SAR0 0022

to 0020

Indeterminate

SAR1 0032

to 0030

Indeterminate

DMAi source pointer (i = 0, 1)

(1)

Setting range

00000

to FFFFF

Nothing is assigned. When write, set “0”. When read, these contents

are “0”.

Symbol Address After reset

DAR0 0026

to 0024

Indeterminate

DAR1 0036

to 0034

Indeterminate

b3 b0 b7 b0 b7 b0

(b8)(b15)(b16)(b19)

Function

Set the destination address of transfer

DMAi destination pointer (i = 0, 1)

(1)

Setting range

00000

to FFFFF

(b23)

Nothing is assigned. When write, set “0”. When read, these contents

are “0”.

NOTE:

1. If the DSD bit in the DMiCON register is “0” (fixed), this register can only be written to when the DMAE bit in the

DMiCON register is “0” (DMA disabled). If the DSD bit is set to “1” (forward direction), this register can be written to

at any time. If the DSD bit is set to “1” and the DMAE bit is “1” (DMA enabled), the DMAi forward address pointer

can be read from this register. Otherwise, the value written to it can be read.

NOTE:

1. If the DAD bit in the DMiCON register is “0” (fixed), this register can only be written to when the DMAE bit in the

DMiCON register is “0”(DMA disabled). If the DAD bit is set to “1” (forward direction), this register can be written to at

any time. If the DAD bit is set to “1” and the DMAE bit is “1” (DMA enabled), the DMAi forward address pointer can

be read from this register. Otherwise, the value written to it can be read.

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11.1 Transfer Cycles

The transfer cycle consists of a memory or SFR read (source read) bus cycle and a write (destination write)

bus cycle. The number of read and write bus cycles is affected by the source and destination addresses of

transfer. Furthermore, the bus cycle itself is extended by a software wait.

11.1.1 Effect of Source and Destination Addresses

If the transfer unit is 16 bits and the source address of transfer begins with an odd address, the source

read cycle consists of one more bus cycle than when the source address of transfer begins with an even

address.

Similarly, if the transfer unit is 16 bits and the destination address of transfer begins with an odd address,

the destination write cycle consists of one more bus cycle than when the destination address of transfer

begins with an even address.

11.1.2 Effect of Software Wait

For memory or SFR accesses in which one or more software wait states are inserted, the number of bus

cycles required for that access increases by an amount equal to software wait states.

Figure 11.1.1 shows the example of the cycles for a source read. For convenience, the destination write

cycle is shown as one cycle and the source read cycles for the different conditions are shown. In reality, the

destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle

changing accordingly. When calculating transfer cycles, take into consideration each condition for the

source read and the destination write cycle, respectively. For example, when data is transferred in 16 bit

units and when both the source address and destination address are an odd address ((2) in Figure 11.1.1),

two source read bus cycles and two destination write bus cycles are required.

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Figure 11.1.1 Transfer Cycles for Source Read

CPU clock

Address

bus

RD signal

WR signal

Data

bus

CPU use

CPU use CPU use

CPU useSource

Source

Destination

Dummy

cycle

Dummy

cycle

(1) When the transfer unit is 8 or 16 bits and the source of transfer is an even address

Address

bus

RD signal

WR signal

Data

bus

CPU use

CPU use CPU use

CPU use

Source

Destination

Dummy

cycle

Dummy

cycle

(3) When the source read cycle under condition (1) has one wait state inserted

Address

bus

RD signal

WR signal

Data

bus

CPU use

CPU use CPU use

CPU useSource

Source

Destination

Dummy

cycle

Dummy

cycle

Source + 1

(2) When the transfer unit is 16 bits and the source address of transfer is an odd address

Address

bus

RD signal

WR signal

Data

bus

CPU use

CPU use CPU use

CPU useSource

Source

Destination

Dummy

cycle

Dummy

cycle

Source + 1

(4) When the source read cycle under condition (2) has one wait state inserted

CPU clock

NOTE:

1. The same timing changes occur with the respective conditions at the destination as at the source.

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11.2. DMA Transfer Cycles

Any combination of even or odd transfer read and write adresses is possible. Table 11.2.1 shows the

number of DMA transfer cycles. Table 11.2.2 shows the Coefficient j, k.

The number of DMAC transfer cycles can be calculated as follows:

No. of transfer cycles per transfer unit = No. of read cycles x j + No. of write cycles x k

Table 11.2.1 DMA Transfer Cycles

Table 11.2.2 Coefficient j, k

Transfer unit Access address No. of read cycles No. of write cycles

8-bit transfers Even 1 1

(DMBIT= “1”) Odd 1 1

16-bit transfers Even 1 1

(DMBIT= “0”) Odd 2 2

Internal area

Internal ROM, RAM SFR

No wait With wait

1 wait 2 wait

(1) (1)

NOTE:

1. Depends on the set value of PM20 bit in PM2 register.

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11.3 DMA Enable

When a data transfer starts after setting the DMAE bit in DMiCON register (i = 0, 1) to “1” (enabled), the

DMAC operates as follows:

(1) Reload the forward address pointer with the SARi register value when the DSD bit in the DMiCON

(2) Reload the DMAi transfer counter with the DMAi transfer counter reload register value.

If the DMAE bit is set to “1” again while it remains set, the DMAC performs the above operation. However,

if a DMA request may occur simultaneously when the DMAE bit is being written, follow the steps below.

Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously.

Step 2: Make sure that the DMAi is in an initial state as described above (1) and (2) in a program.

If the DMAi is not in an initial state, the above steps should be repeated.

11.4 DMA Request

The DMAC can generate a DMA request as triggered by the cause of request that is selected with the DMS

and DSEL3 to DSEL0 bits in the DMiSL register (i = 0, 1) on either channel. Table 11.4.1 shows the timing

at which the DMAS bit changes state.

Whenever a DMA request is generated, the DMAS bit is set to “1” (DMA requested) regardless of whether

or not the DMAE bit is set. If the DMAE bit was set to “1” (enabled) when this occurred, the DMAS bit is set

to “0” (DMA not requested) immediately before a data transfer starts. This bit cannot be set to “1” in a

program (it can only be set to “0”).

The DMAS bit may be set to “1” when the DMS or the DSEL3 to DSEL0 bits change state. Therefore,

always be sure to set the DMAS bit to “0” after changing the DMS or the DSEL3 to DSEL0 bits.

Because if the DMAE bit is “1”, a data transfer starts immediately after a DMA request is generated, the

DMAS bit in almost all cases is “0” when read in a program. Read the DMAE bit to determine whether the

DMAC is enabled.

Table 11.4.1 Timing at Which the DMAS Bit Changes State

DMA factor

Software trigger

Peripheral function

Timing at which the bit is set to “1” Timing at which the bit is set to “0”

DMAS bit in the DMiCON register

When the DSR bit in the DMiSL

When the interrupt control register

for the peripheral function that is

selected by the DSEL3 to DSEL0

and DMS bits in the DMiSL register

has its IR bit set to “1”

• Immediately before a data transfer starts

• When set by writing “0” in a program

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11.5 Channel Priority and DMA Transfer Timing

If both DMA0 and DMA1 are enabled and DMA transfer request signals from DMA0 and DMA1 are de-

tected active in the same sampling period (one period from a falling edge to the next falling edge of CPU

clock), the DMAS bit on each channel is set to “1” (DMA requested) at the same time. In this case, the DMA

requests are arbitrated according to the channel priority, DMA0 > DMA1. The following describes DMAC

operation when DMA0 and DMA1 requests are detected active in the same sampling period. Figure 11.5.1

shows an example of DMA transfer effected by external factors.

DMA0 request having priority is received first to start a transfer when a DMA0 request and DMA1 request

are generated simultanelously. After one DMA0 transfer is completed, a bus arbitration is returned to the

CPU. When the CPU has completed one bus access, a DMA1 transfer starts. After one DMA1 transfer is

completed, the bus arbitration is again returned to the CPU.

In addition, DMA requsts cannot be counted up since each channel has one DMAS bit. Therefore, when

DMA requests, as DMA1 in Figure 11.5.1, occurs more than one time, the DAMS bit is set to "0" as soon

as getting the bus arbitration. The bus arbitration is returned to the CPU when one transfer is completed.

Figure 11.5.1 DMA Transfer by External Factors

AAAA

DMA0

AAAA

DMA1

DMA0

request bit

DMA1

request bit

AAA

AAAAA

CPU

INT0

INT1

Obtainment

of the bus

right

An example where DMA requests for external causes are detected active at the same

CPU clock

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Figure 12.1. Timer A Configuration

12. Timer

Note

The TB2IN pin is not available in the 42-pin package. Do not use functions associated with the TB2IN

pin.

Eight 16-bit timers, each capable of operating independently of the others, can be classified by function as

either timer A (five) and timer B (three). The count source for each timer acts as a clock, to control such

timer operations as counting, reloading, etc. Figures 12.1 and 12.2 show block diagrams of timer A and

timer B configuration, respectively.

• Timer mode

• One-shot timer mode

• Pulse Width Measuring (PWM) mode

• Timer mode

• One-shot timer mode

• PWM mode

• Timer mode

• One-shot timer mode

• PWM mode

• Timer mode

• One-shot timer mode

• PWM mode

• Timer mode

• One-shot timer mode

• PWM mode

• Event counter mode

TA0

TA1

TA2

TA3

TA4

Timer A0

Timer A1

Timer A2

Timer A3

Timer A4

C32

Timer A0 interrupt

Timer A1 interrupt

Timer A2 interrupt

Timer A3 interrupt

Timer A4 interrupt

Noise

filter

Noise

filter

Noise

filter

Noise

filter

Noise

filter

1/32 f

C32

1/8

1/4

1 or

• Main clock

• PLL clock

• On-chip

oscillator clock

CIN

Reset

Clock prescaler

Timer B2 overflow or underflow

1/2

PCLK0 bit = "0"

PCLK0 bit = "1"

1 or

Set the CPSR bit in the

CPSRF register to “1”

(= prescaler reset)

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Figure 12.2. Timer B Configuration

• Event counter mode

• Timer mode

• Pulse width measuring mode,

pulse period measuring mode

• Timer mode

• Pulse width measuring mode,

pulse period measuring mode

• Timer mode

• Pulse width measuring mode,

pulse period measuring mode

TB0IN

TB1IN

TB2IN

Timer B0

Timer B1

Timer B2

f8 f32 fC32

Timer B0 interrupt

Noise

filter

Noise

filter

Noise

filter

1/32 fC32

XCIN Reset

Clock prescaler

Timer B2 overflow or underflow ( to Timer A count source)

Timer B1 interrupt

Timer B2 interrupt

1/8

1/4

f32

1/2f1 or f2

• Main clock

• PLL clock

• On-chip

oscillator clock

f2PCLK0 bit = "0"

PCLK0 bit = "1"

f1 or f2

Set the CPSR bit in the

CPSRF register to “1”

(= prescaler reset)

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12.1 Timer A

Figure 12.1.1 shows a block diagram of the timer A. Figures 12.1.2 to 12.1.4 show registers related to the

timer A.

The timer A supports the following four modes. Except in event counter mode, timers A0 to A4 all have the

same function. Use the TMOD1 to TMOD0 bits in the TAiMR register (i = 0 to 4) to select the desired mode.

• Timer mode: The timer counts an internal count source.

• Event counter mode: The timer counts pulses from an external device or overflows and underflows of

other timers.

• One-shot timer mode: The timer outputs a pulse only once before it reaches the minimum count

“000016.”

• Pulse width modulation (PWM) mode: The timer outputs pulses in a given width successively.

Figure 12.1.2. TA0MR to TA4MR Registers

TABSR register

Up-count/down-count

TAi Addresses TAj TAk

Timer A0 0387

- 0386

Timer A4 Timer A1

Timer A1 0389

- 0388

Timer A0 Timer A2

Timer A2 038B

- 038A

Timer A1 Timer A3

Timer A3 038D

- 038C

Timer A2 Timer A4

Timer A4 038F

- 038E

Timer A3 Timer A0

Always counts down except

in event counter mode

Reload register

Counter

Low-order

8 bits High-order

8 bits

Clock source

selection

• Timer

(gate function)

• Timer

• One shot

• PWM

or f

TAi

(i = 0 to 4)

TB2 overflow

• Event counter

C32

Clock selection

TAj overflow

(j = i – 1. Note, however, that j = 4 when i = 0)

Pulse output

Toggle flip-flop

TAi

OUT

(i = 0 to 4)

Data bus low-order bits

Data bus high-order bits

UDF register

Down count

TAk overflow

(k = i + 1. Note, however, that k = 0 when i = 4)

Polarity

selection

To external

trigger circuit

(1)

NOTE:

1. Overflow or underflow

Clock selection

Figure 12.1.1. Timer A Block Diagram

Timer Ai mode register (i=0 to 4)

Symbol Address After reset

TA0MR to TA4MR 039616 to 039A16 0016

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

0 0 : Timer mode

0 1 : Event counter mode

1 0 : One-shot timer mode

1 1 : Pulse width modulation

(PWM) mode

b1 b0

TCK1

MR3

MR2

MR1

TMOD1

MR0

TMOD0

TCK0

Function varies with each

operation mode

Count source select bit

Operation mode select bitRW

Function varies with each

operation mode

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Figure 12.1.3. TA0 to TA4 Registers, TABSR Register, and UDF Register

Symbol Address After reset

TA0 038716, 038616 Indeterminate

TA1 038916, 038816 Indeterminate

TA2 038B16, 038A16 Indeterminate

TA3 038D16, 038C16 Indeterminate

TA4 038F16, 038E16 Indeterminate

b7 b0 b7 b0

(b15) (b8)

Timer Ai register (i= 0 to 4) (1)

Divide the count source by n + 1 where n =

set value

Function Setting range

Divide the count source by FFFF16 – n + 1

where n = set value when counting up or

by n + 1 when counting down

Divide the count source by n where n = set

value and cause the timer to stop

Modify the pulse width as follows:

PWM period: (216 – 1) / fj

High level PWM pulse width: n / fj

where n = set value, fj = count source

frequency

000016 to FFFE16

(3, 4)

0016 to FE16

(High-order address)

0016 to FF16

(Low-order address)

Timer A4 up/down flag

Timer A3 up/down flag

Timer A2 up/down flag

Timer A1 up/down flag

Timer A0 up/down flag

Timer A2 two-phase pulse

signal processing select bit

Timer A3 two-phase pulse

signal processing select bit

Timer A4 two-phase pulse

signal processing select bit

Symbol Address After reset

UDF 038416 0016

TA4P

TA3P

TA2P

Up/down flag (1)

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

TA4UD

TA3UD

TA2UD

TA1UD

TA0UD 0 : Down count

1 : Up count

Enabled by setting the TAiMR

(= switching source in UDF

mode.

0 : two-phase pulse signal

processing disabled

1 : two-phase pulse signal

processing enabled

Symbol Address After reset

TABSR 038016 0016

Count start flag

Bit name FunctionBit symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

Timer B2 count start flag

Timer B1 count start flag

Timer B0 count start flag

Timer A4 count start flag

Timer A3 count start flag

Timer A2 count start flag

Timer A1 count start flag

Timer A0 count start flag 0 : Stops counting

1 : Starts counting

TB2S

TB1S

TB0S

TA4S

TA3S

TA2S

TA1S

TA0S

Timer

mode

Event

counter

mode

One-shot

timer mode

Pulse width

modulation

mode

(16-bit PWM)

Pulse width

modulation

mode

(8-bit PWM)

000016 to FFFF16

(2, 4)

Mode

Modify the pulse width as follows:

PWM period: (28 – 1) x (m + 1)/ fj

High level PWM pulse width: (m + 1)n / fj

where n = high-order address set value,

m = low-order address set value, fj =

count source frequency (3, 4)

(2, 3)

(5)

NOTES:

1. The register must be accessed in 16 bit units.

2.: If the TAi register is set to ‘000016,’ the counter does not work and timer Ai interrupt requests are

not generated either. Furthermore, if “pulse output” is selected, no pulses are output from the

TAiOUT pin.

3. If the TAi register is set to ‘000016,’ the pulse width modulator does not work, the output level on

the TAiOUT pin remains low, and timer Ai interrupt requests are not generated either. The same

applies when the 8 high-order bits of the timer TAi register are set to ‘0016’ while operating as an

8-bit pulse width modulator.

4. Use the MOV instruction to write to the TAi register.

5. The timer counts pulses from an external device or overflows or underflows in other timers.

NOTES:

1. Use MOV instruction to write to this register.

2. Make sure the port direction bits for the TA2IN to TA4IN and TA2OUT to TA4OUT pins are set to “0”

(

ut mode

)

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Figure 12.1.4. ONSF Register, TRGSR Register, and CPSRF Register

Symbol Address After reset

CPSRF 0381

0XXXXXXX

Clock prescaler reset flag

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

Clock prescaler reset flag Setting this bit to “1” initializes the

prescaler for the timekeeping clock.

(When read, its content is “0”.)

CPSR

Nothing is assigned.

When write, set to “0”. When read, their contents are

indeterminate.

TA1TGL

Symbol Address After reset

TRGSR 0383

Timer A1 event/trigger

select bit 0 0 :

Input on TA1

is selected (1)

0 1 : TB2 overflow is selected

1 0 : TA0 overflow is selected

1 1 : TA2 overflow is selected

Trigger select register

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

0 0 :

Input on TA2

is selected (1)

0 1 : TB2 overflow is selected

1 0 : TA1 overflow is selected

1 1 : TA3 overflow is selected

0 0 :

Input on TA3

is selected (1)

0 1 : TB2 overflow is selected

1 0 : TA2 overflow is selected

1 1 : TA4 overflow is selected

0 0 :

Input on TA4

is selected (1)

0 1 : TB2 overflow is selected

1 0 : TA3 overflow is selected

1 1 : TA0 overflow is selected

Timer A2 event/trigger

select bit

Timer A3 event/trigger

select bit

Timer A4 event/trigger

select bit

TA1TGH

TA2TGL

TA2TGH

TA3TGL

TA3TGH

TA4TGL

TA4TGH

b1 b0

b3 b2

b5 b4

b7 b6

TA1OS

TA2OS

TA0OS

One-shot start flag

Symbol Address After reset

ONSF 0382

Timer A0 one-shot start flag

Timer A1 one-shot start flag

Timer A2 one-shot start flag

Timer A3 one-shot start flag

Timer A4 one-shot start flag

TA3OS

TA4OS

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

TA0TGL

TA0TGH

0 0 : Input on TA0

is selected

0 1 : TB2 overflow is selected

1 0 : TA4 overflow is selected

1 1 : TA1 overflow is selected

Timer A0 event/trigger

select bit

b7 b6

The timer starts counting by setting

this bit to “1” while the TMOD1 to

TMOD0 bits in the TAiMR register

(i = 0 to 4) is set to ‘10

’ (= one-

shot timer mode) and the MR2 bit

in the TAiMR register is set to “0”

(=TAiOS bit enabled). When read,

its content is “0”.

Z-phase input enable bit

TAZIE

0 : Z-phase input disabled

1 : Z-phase input enabled

(b6-b0)

(2)

(1)

(2)

NOTES:

1. Make sure the port direction bits for the TA1

to TA4

pins are set to “0” (= input mode).

2. Overflow or underflow.

NOTES:

1. Make sure the PD7_1 bit in the PD7 register is set to “0” (= input mode).

2. Overflow or underflow.

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Item Specification

Count source f1, f2, f8, f32, fC32

Count operation • Down-count

•

When the timer underflows, it reloads the reload register contents and continues counting

Divide ratio 1/(n+1) n: set value of TAi register (i= 0 to 4) 000016 to FFFF16

Count start condition Set TAiS bit in the TABSR register to “1” (= start counting)

Count stop condition Set TAiS bit to “0” (= stop counting)

Interrupt request generation timing

Timer underflow

TAiIN pin function I/O port or gate input

TAiOUT pin function I/O port or pulse output

Read from timer Count value can be read by reading TAi register

Write to timer

• When not counting and until the 1st count source is input after counting start

Value written to TAi register is written to both reload register and counter

• When counting (after 1st count source input)

Value written to TAi register is written to only reload register

(Transferred to counter when reloaded next)

Select function • Gate function

Counting can be started and stopped by an input signal to TAiIN pin

• Pulse output function

Whenever the timer underflows, the output polarity of TAiOUT pin is inverted.

When not counting, the pin outputs a low.

12.1.1. Timer Mode

In timer mode, the timer counts a count source generated internally (see Table 12.1.1.1). Figure 1.2.1.1.1

shows TAiMR register in timer mode.

Table 12.1.1.1. Specifications in Timer Mode

Timer Ai mode register (i=0 to 4)

Symbol Address After reset

TA0MR to TA4MR 039616 to 039A16 0016

Bit name FunctionBit symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

Operation mode

select bit 0 0 : Timer mode

b1 b0

TMOD1

TMOD0

MR0 Pulse output function

select bit 0 : Pulse is not output

(TA

iOUT pin is a normal port pin)

1 : Pulse is output

(TAiOUT pin is a pulse output pin)

Gate function select bit 0 0 : Gate function not available

0 1 : (TAiIN pin functions as I/O port)

1 0 : Counts while input on the TAiIN pin

is low (1)

1 1 : Counts while input on the TAiIN pin

is high (1)

b4 b3

MR2

MR1

MR3 Must be set to “0” in timer mode

0 0 : f

1 or f2

0 1 : f8

1 0 : f32

1 1 : fC32

b7 b6

TCK1

TCK0 Count source select bit

000

}

NOTE:

1.The port direction bit for the TAiIN pin must be set to “0” (= input mode).

Figure 12.1.1.1. Timer Ai Mode Register in Timer Mode

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Item Specification

Count source • External signals input to TAiIN pin (i=0 to 4) (effective edge can be selected

in program)

• Timer B2 overflows or underflows,

timer Aj (j=i-1, except j=4 if i=0) overflows or underflows,

timer Ak (k=i+1, except k=0 if i=4) overflows or underflows

Count operation •Up-count or down-count can be selected by external signal or program

•When the timer overflows or underflows, it reloads the reload register con-

tents and continues counting. When operating in free-running mode, the

timer continues counting without reloading.

Divided ratio 1/ (FFFF16 - n + 1) for up-count

1/ (n + 1) for down-count n : set value of TAi register 000016 to FFFF16

Count start condition Set TAiS bit in the TABSR register to “1” (= start counting)

Count stop condition Set TAiS bit to “0” (= stop counting)

Interrupt request generation timing

Timer overflow or underflow

TAiIN pin function I/O port or count source input

TAiOUT pin function I/O port, pulse output, or up/down-count select input

Read from timer Count value can be read by reading TAi register

Write to timer

• When not counting and until the 1st count source is input after counting start

Value written to TAi register is written to both reload register and counter

• When counting (after 1st count source input)

Value written to TAi register is written to only reload register

(Transferred to counter when reloaded next)

Select function •Free-run count function

Even when the timer overflows or underflows, the reload register content is

not reloaded to it

•Pulse output function

Whenever the timer underflows or underflows, the output polarity of TAiOUT

pin is inverted . When not counting, the pin outputs a low.

12.1.2. Event Counter Mode

In event counter mode, the timer counts pulses from an external device or overflows and underflows of

other timers. Timers A2, A3 and A4 can count two-phase external signals. Table 12.1.2.1 lists specifica-

tions in event counter mode (when not processing two-phase pulse signal). Table 12.1.2.2 lists specifica-

tions in event counter mode (when processing two-phase pulse signal with the timers A2, A3 and A4).

Figure 12.1.2.1 shows TAiMR register in event counter mode (when not processing two-phase pulse

signal). Figure 12.1.2.2 shows TA2MR to TA4MR registers in event counter mode (when processing two-

phase pulse signal with the timers A2, A3 and A4).

Table 12.1.2.1. Specifications in Event Counter Mode (when not processing two-phase pulse signal)

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Figure 12.1.2.1. TAiMR Register in Event Counter Mode (when not using two-phase pulse signal

processing)

Symbol Address After reset

TA0MR to TA4MR 0396

to 039A

b7 b6 b5 b4 b3 b2 b1 b0

Operation mode select bit 0 1 : Event counter mode

(1)

b1 b0

TMOD0

MR0 Pulse output function

select bit 0 : Pulse is not output

(TA

iOUT

pin functions as I/O port)

1 : Pulse is output

(TAi

OUT

pin functions as pulse output pin)

Count polarity

select bit (2)

MR2

MR1

MR3 Must be set to “0” in event counter mode

TCK0 Count operation type

select bit

010

0 : Counts external signal's falling edge

1 : Counts external signal's rising edge

Up/down switching

cause select bit 0 : UDF register

1 : Input signal to TA

iOUT

pin (3)

0 : Reload type

1 : Free-run type

Bit symbol Bit name Function RW

TCK1 Can be “0” or “1” when not using two-phase pulse signal

processing

TMOD1

Timer Ai mode register (i=0 to 4)

(When not using two-phase pulse signal processing)

NOTES:

1. During event counter mode, the count source can be selected using the ONSF and TRGSR registers.

2. Effective when the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are ‘00

’ (TAi

pin input).

3. Count down when input on TAi

OUT

pin is low or count up when input on that pin is high. The port

direction bit for TAi

OUT

pin must be set to “0” (= input mode).

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Item Specification

Count source •Two-phase pulse signals input to TAiIN or TAiOUT pins (i = 2 to 4)

Count operation •Up-count or down-count can be selected by two-phase pulse signal

•When the timer overflows or underflows, it reloads the reload register con-

tents and continues counting. When operating in free-running mode, the

timer continues counting without reloading.

Divide ratio 1/ (FFFF16 - n + 1) for up-count

1/ (n + 1) for down-count n : set value of TAi register 000016 to FFFF16

Count start condition Set TAiS bit in the TABSR register to “1” (= start counting)

Count stop condition Set TAiS bit to “0” (= stop counting)

Interrupt request generation timing

Timer overflow or underflow

TAiIN pin function Two-phase pulse input

TAiOUT pin function Two-phase pulse input

Read from timer Count value can be read by reading timer A2, A3 or A4 register

Write to timer •

When not counting and until the 1st count source is input after counting start

Value written to TAi register is written to both reload register and counter

• When counting (after 1st count source input)

Value written to TAi register is written to reload register

(Transferred to counter when reloaded next)

Select function (1) •Normal processing operation (timer A2 and timer A3)

The timer counts up rising edges or counts down falling edges on TAjIN

(j=2, 3) pin when input signals on TAjOUT pin is “H”.

•Multiply-by-4 processing operation (timer A3 and timer A4)

If the phase relationship is such that TAkIN(k=3, 4) pin goes “H” when the

input signal on TAkOUT pin is “H”, the timer counts up rising and falling

edges on TAkOUT and TAkIN pins. If the phase relationship is such that

TAkIN pin goes “L” when the input signal on TAkOUT pin is “H”, the timer

counts down rising and falling edges on TAkOUT and TAkIN pins.

Table 12.1.2.2. Specifications in Event Counter Mode (when processing two-phase pulse signal with timers A2, A3 and A4)

TAjOUT

Up-

count Up-

count Down-

count

TAjIN

(j=2,3)

TAkOUT

TAkIN

(k=3,4)

Count up all edges

Count down all edges

• Counter initialization by Z-phase input (timer A3)

The timer count value is initialized to 0 by Z-phase input.

NOTE:

1. Only timer A3 is selectable. Timer A2 is fixed to normal processing operation, and timer A4 is fixed to

multiply-by-4 processing operation.

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Figure 12.1.2.2. TA2MR to TA4MR Registers in Event Counter Mode (when using two-phase

pulse signal processing with timer A2, A3 or A4)

Timer Ai mode register (i=2 to 4)

(When using two-phase pulse signal processing)

Symbol Address After reset

TA2MR to TA4MR 0398

to 039A

b6 b5 b4 b3 b2 b1 b0

Operation mode select bit 0 1 : Event counter mode

b1 b0

TMOD1

TMOD0

MR0 To use two-phase pulse signal processing, set this bit to “0”.

MR2

MR1

MR3

TCK1

TCK0

010

Bit name FunctionRW

Count operation type

select bit

Two-phase pulse signal

processing operation

select bit (1, 2)

0 : Reload type

1 : Free-run type

0 : Normal processing operation

1 : Multiply-by-4 processing operation

001

To use two-phase pulse signal processing, set this bit to “0”.

To use two-phase pulse signal processing, set this bit to “1”.

To use two-phase pulse signal processing, set this bit to “0”.

Bit symbol

NOTES:

1. TCK1 bit is valid for timer A3 mode register. No matter how this bit is set, Timers A2 and A4 always operate in

normal processing mode and x4 processing mode, respectively.

2. If two-phase pulse signal processing is desired, following register settings are required:

• Set the TAiP bit in the UDF register to “1” (two-phase pulse signal processing function enabled).

• Set the TAiTGH and TAiTGL bits in the TRGSR register to ‘00

’ (TAiIN pin input).

• Set the port direction bits for TAi

and TAi

OUT

to “0” (input mode).

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m m+1 1 2 3 4 5

TA3OUT

(A phase)

Count source

TA3IN

(B phase)

Timer A3

INT2

(Z phase)

(1)

Input equal to or greater than one clock cycle

of count source

NOTE:

1. This timing diagram is for the case where the POL bit in the INT2IC register is set to “1” (= rising edge).

12.1.2.1 Counter Initialization by Two-Phase Pulse Signal Processing

This function initializes the timer count value to “0” by Z-phase (counter initialization) input during two-

phase pulse signal processing.

This function can only be used in timer A3 event counter mode during two-phase pulse signal process-

_______

ing, free-running type, x4 processing, with Z-phase entered from the INT2 pin.

Counter initialization by Z-phase input is enabled by writing “000016” to the TA3 register and setting

the TAZIE bit in ONSF register to “1” (= Z-phase input enabled).

Counter initialization is accomplished by detecting Z-phase input edge. The active edge can be cho-

sen to be the rising or falling edge by using the POL bit in the INT2IC register. The Z-phase pulse width

_______

applied to the INT2 pin must be equal to or greater than one clock cycle of the timer A3 count source.

The counter is initialized at the next count timing after recognizing Z-phase input. Figure 12.1.2.1.1

shows the relationship between the two-phase pulse (A phase and B phase) and the Z phase.

If timer A3 overflow or underflow coincides with the counter initialization by Z-phase input, a timer A3

interrupt request is generated twice in succession. Do not use the timer A3 interrupt when using this

function.

Figure 12.1.2.1.1. Two-phase Pulse (A phase and B phase) and the Z Phase

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Item Specification

Count source f1, f2, f8, f32, fC32

Count operation •Down-count

•

When the counter reaches 0000

, it stops counting after reloading a new value

•If a trigger occurs when counting, the timer reloads a new count and restarts counting

Divide ratio 1/n n : set value of TAi register 000016 to FFFF16

However, the counter does not work if the divide-by-n value is set to 000016.

Count start condition T AiS bit in t he TABSR register is set to “1” (start counting) and one of the

following triggers occurs.

• External trigger input from the TAiIN pin

• Timer B2 overflow or underflow,

timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,

timer Ak (k=i+1, except k=0 if i=4) overflow or underflow

• The TAiOS bit in the ONSF register is set to “1” (= timer starts)

Count stop condition • When the counter is reloaded after reaching “000016”

• TAiS bit is set to “0” (= stop counting)

Interrupt request generation timing

When the counter reaches “000016”

TAiIN pin function I/O port or trigger input

TAiOUT pin function I/O port or pulse output

Read from timer An indeterminate value is read by reading TAi register

Write to timer

•

When not counting and until the 1st count source is input after counting start

Value written to TAi register is written to both reload register and counter

• When counting (after 1st count source input)

Value written to TAi register is written to only reload register

(Transferred to counter when reloaded next)

Select function • Pulse output function

The timer outputs a low when not counting and a high when counting.

Table 12.1.3.1. Specifications in One-shot Timer Mode

12.1.3. One-shot Timer Mode

In one-shot timer mode, the timer is activated only once by one trigger. (See Table 12.1.3.1.) When the

trigger occurs, the timer starts up and continues operating for a given period. Figure 12.1.3.1 shows the

TAiMR register in one-shot timer mode.

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Figure 12.1.3.1. TAiMR Register in One-shot Timer Mode

Bit name

Timer Ai mode register (i=0 to 4)

Symbol Address After reset

TA0MR to TA4MR 39616 to 039A16 0016

Function

Bit symbol

b7 b6 b5 b4 b3 b2 b1 b0

Operation mode select bit 1 0 : One-shot timer mode

b1 b0

TMOD1

TMOD0

MR0 Pulse output function

select bit 0 : Pulse is not output

(TAiOUT pin functions as I/O port)

1 : Pulse is output

(TAiOUT pin functions as a pulse output pin)

MR2

MR1

MR3 Must be set to “0” in one-shot timer mode

0 0 : f1 or f2

0 1 : f8

1 0 : f32

1 1 : fC32

b7 b6

TCK1

TCK0 Count source select bit

100

0 : TAiOS bit is enabled

1 : Selected by TAiTGH to TAiTGL bits

Trigger select bit

External trigger select

bit (1) 0 : Falling edge of input signal to TAiIN pin (2)

1 : Rising edge of input signal to TAiIN pin (2)

NOTES:

1. Effective when the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are ‘002’ (TAiIN pin input).

2. The port direction bit for the TAiIN pin must be set to “0” (= input mode).

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12.1.4. Pulse Width Modulation (PWM) Mode

In PWM mode, the timer outputs pulses of a given width in succession (see Table 12.1.4.1). The counter

functions as either 16-bit pulse width modulator or 8-bit pulse width modulator. Figure 12.1.4.1 shows

TAiMR register in pulse width modulation mode. Figures 12.1.4.2 and 12.1.4.3 show examples of how a

16-bit pulse width modulator operates and how an 8-bit pulse width modulator operates.

Table 12.1.4.1. Specifications in Pulse Width Modulation Mode

Item Specification

Count source f1, f2, f8, f32, fC32

Count operation •D

own-count (operating as an 8-bit or a 16-bit pulse width modulator)

•

The timer reloads a new value at a rising edge of PWM pulse and continues counting

•The timer is not affected by a trigger that occurs during counting

16-bit PWM •High level width n / fj n : set value of TAi register (i=o to 4)

•Cycle time (216-1) / fj fixed fj: count source frequency (f1, f2, f8, f32, fC32)

8-bit PWM

•

High level width n x (m+1) / fj n : set value of TAi register high-order address

•

Cycle time (2

-1) x (m+1) / fj m : set value of TAi register low-order address

Count start condition • TAiS bit in theTABSR register is set to “1” (= start counting)

• The TAiS bit is set to "1" and external trigger input from the TAiIN pin

• The TAiS bit is set to "1" and one of the following external triggers occurs

Timer B2 overflow or underflow,

timer Aj (j=i-1, except j=4 if i=0) overflow or underflow,

timer Ak (k=i+1, except k=0 if i=4) overflow or underflow

Count stop condition TAiS bit is set to “0” (= stop counting)

Interrupt request generation timing

PWM pulse goes “L”

TAiIN pin function I/O port or trigger input

TAiOUT pin function Pulse output

Read from timer An indeterminate value is read by reading TAi register

Write to timer

•

When not counting and until the 1st count source is input after counting start

Value written to TAi register is written to both reload register and counter

• When counting (after 1st count source input)

Value written to TAi register is written to only reload register

(Transferred to counter when reloaded next)

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Figure 12.1.4.1. TAiMR Register in Pulse Width Modulation Mode

Bit name

Timer Ai mode register (i= 0 to 4)

Symbol Address After reset

TA0MR to TA4MR 039616 to 039A16 0016

FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

Operation mode

select bit 1 1 : PWM mode

b1 b0

TMOD1

TMOD0

MR0

MR2

MR1

MR3

0 0 : f1 or f2

0 1 : f8

1 0 : f32

1 1 : fC32

b7 b6

TCK1

TCK0 Count source select bit

111

16/8-bit PWM mode

select bit 0: Functions as a 16-bit pulse width modulator

1: Functions as an 8-bit pulse width modulator

Trigger select bit

External trigger select

bit (1) 0: Falling edge of input signal to TAiIN pin(2)

1: Rising edge of input signal to TAiIN pin(2)

0 : Write “1” to TAiS bit in the TASF register

1 : Selected by TAiTGH to TAiTGL bits

0: Pulse is not output (TAiOUT pin functions as I/O port)

1: Pulse is output (TAiOUT pin functions as a pulse output

pin)

Pulse output funcion

select bit

NOTES:

1. Effective when the TAiTGH and TAiTGL bits in the ONSF or TRGSR register are ‘002’ (TAiIN pin input).

2. The port direction bit for the TAiIN pin must be set to “0” (= input mode).

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Figure 12.1.4.2. Example of 16-bit Pulse Width Modulator Operation

Figure 12.1.4.3. Example of 8-bit Pulse Width Modulator Operation

1 / f

X (2 – 1)

Count source

Input signal to

iIN

PWM pulse output

from TA

iOUT

Trigger is not generated by this signal

“H”

“L”

IR bit in the

TAiIC register “1”

“0”

: Frequency of count source

, f

C32

)

i = 0 to 4

1 / f

Set to “0” upon accepting an interrupt request or by writing in program

NOTES:

1. n = 0000

to FFFE

2. This timing diagram is for the case where the TAi register is set to "0003

", the TAiTGH and TAiTGL bits in

the ONSF or TRGSR register is set to "00

" (TAi

pin input), the MR1 bit in the TAiMR register is set to "1"

(rising edge), and the MR2 bit in the TAiMR register is set to "1" (trigger selected by TAiTGH and TAiTGL bits).

Count source

(1)

Input signal to

iIN

Underflow signal of

8-bit prescaler

(2)

PWM pulse output

from TA

iOUT

“H”

“L”

“1”

“0”

Set to “0” upon accepting an interrupt request or by writing in program

1 / fj X (m + 1) X (2 – 1)

1 / fj X (m + 1) X n

1 / fj X (m + 1)

IR bit in the

TAiIC register

: Frequency of count source

, f

C32

)

i = 0 to 4

NOTES:

1. The 8-bit prescaler counts the count source.

2. The 8-bit pulse width modulator counts the 8-bit prescaler's underflow signal.

3. m = 00

to FF

; n = 00

to FE

4. This timing diagram is for the case where the TAi register is set to "0202

", the TAiTGH and TAiTGL bits in the

ONSF or TRGSR register is set to "00

" (TAi

pin input), the MR1 bit in the TAiMR register is set to "0"(falling

edge), and the MR2 bit in the TAiMR register is set to "1" (trigger selected by TAiTGH and TAiTGL bits).

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Figure 12.2.1. Timer B Block Diagram

12.2 Timer B

Note

The TB2IN pin for Timer B2 is not available in 42-pin package.

[Precautions when using Timer B2]

• Event Counter Mode The external input signals cannot be counted. Set the TCK1 bit in the

TB2MR register to “1” when using the Event Count Mode.

• Pulse Period/Pulse Width Measurement Mode

This mode connot be used.

Figure 12.2.1 shows a block diagram of the timer B. Figures 12.2.2 and 12.2.3 show registers related to the

timer B.

Timer B supports the following four modes. Use the TMOD1 and TMOD0 bits in the TBiMR register (i = 0 to

2) to select the desired mode.

• Timer mode: The timer counts an internal count source.

• Event counter mode: The timer counts pulses from an external device or overflows or underflows of

other timers.

• Pulse period/pulse width measuring mode: The timer measures an external signal's pulse period or

pulse width.

• A/D trigger mode: The timer starts counting by one trigger until the count value becomes 000016.

This mode is used together with simultaneous sample sweep mode or delayed trigger mode 0 of A/D

converter to start A/D conversion.

Clock source selection

• Event counter

Reload register

Low-order 8 bits High-order 8 bits

Data bus low-order bits

Data bus high-order bits

TABSR register

Polarity switching,

edge pulse

Counter reset circuit

Counter

Clock selection

• Timer mode

• Pulse period/, pulse width measuring mode

• A/D trigger mode

or f

C32

TBj overflow

(1)

(j = i – 1, except j = 2 if i = 0)

Can be selected in

onlyevent counter mode

TBi

(i = 0 to 2)

NOTE:

1. Overflow or underflow.

TBi Address TBj

Timer B0 0391

0390

Timer B2

Timer B1 0393

16 -

0392

Timer B0

Timer B2 0395

16 -

0394

Timer B1

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Timer Bi mode register (i=0 to 2)

Symbol Address After reset

TB0MR to TB2MR 039B16 to 039D16 00XX00002

Bit name FunctionBit symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

0 0 : Timer mode or A/D trigger mode

0 1 : Event counter mode

1 0 : Pulse period measurement mode,

pulse width measurement mode

1 1 : Must not be set

b1 b0

TCK1

MR3

MR2

MR1

TMOD1

MR0

TMOD0

TCK0

Function varies with each operation

mode

Count source select bit

Operation mode select bit

(1)

(2)

Function varies with each operation

mode

Figure 12.2.2. TB0MR to TB2MR Registers

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Symbol Address After reset

TABSR 038016 0016

Count start flag

Bit name

Bit symbol

b7 b6 b5 b4 b3 b2 b1 b0

Timer B2 count start flag

Timer B1 count start flag

Timer B0 count start flag

Timer A4 count start flag

Timer A3 count start flag

Timer A2 count start flag

Timer A1 count start flag

Timer A0 count start flag 0 : Stops counting

1 : Starts counting

TB2S

TB1S

TB0S

TA4S

TA3S

TA2S

TA1S

TA0S

Function

Symbol Address After reset

TB0 039116, 039016 Indeterminate

TB1 039316, 039216 Indeterminate

TB2 039516, 039416 Indeterminate

b7 b0 b7 b0

(b15) (b8)

Timer Bi register (i=0 to 2)(1)

Measures a pulse period or width

Function

Divide the count source by n + 1

where n = set value

Timer mode

Event counter

mode

000016 to FFFF16

Divide the count source by n + 1

where n = set value (2) 000016 to FFFF16

Pulse period

modulation mode,

Pulse width

modulation mode

Symbol Address After reset

CPSRF 038116 0XXXXXXX2

Clock prescaler reset flag

Bit name Function

Bit symbol

b7 b6 b5 b4 b3 b2 b1 b0

Clock prescaler reset flag

CPSR

Nothing is assigned. When write, set to “0”. When read, their

contents are indeterminate.

(b6-b0)

Setting this bit to “1” initializes the

prescaler for the timekeeping clock.

(When read, the value of this bit is “0”.)

Mode Setting range

A/D trigger

mode (3) Divide the count source by n + 1 where

n = set value and cause the timer stop

000016 to FFFF16

NOTES:

1. The register must be accessed in 16 bit units.

2. The timer counts pulses from an external device or overflows or underflows of other timers.

3. When this mode is used combining delayed trigger mode 0, set the larger value than the value of the timer

B0 register to the timer B1 register.

Figure 12.2.3. TB0 to TB2 Registers, TABSR Register, CPSRF Register

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Item Specification

Count source f1, f2, f8, f32, fC32

Count operation •Down-count

•When the timer underflows, it reloads the reload register contents and

continues counting

Divide ratio 1/(n+1) n: set value of TBi register (i= 0 to 2) 000016 to FFFF16

Count start condition Set TBiS bit(1) to “1” (= start counting)

Count stop condition Set TBiS bit to “0” (= stop counting)

Interrupt request generation timing

Timer underflow

TBiIN pin function I/O port

Read from timer Count value can be read by reading TBi register

Write to timer

•

When not counting and until the 1st count source is input after counting start

Value written to TBi register is written to both reload register and counter

• When counting (after 1st count source input)

Value written to TBi register is written to only reload register

(Transferred to counter when reloaded next)

NOTE:

1. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.

12.2.1 Timer Mode

In timer mode, the timer counts a count source generated internally (see Table 12.2.1.1). Figure 12.2.1.1

shows TBiMR register in timer mode.

Table 12.2.1.1 Specifications in Timer Mode

Figure 12.2.1.1 TBiMR Register in Timer Mode

Timer Bi mode register (i= 0 to 2)

Symbol Address After reset

TB0MR to TB2MR 039B16 to 039D16 00XX00002

Bit name Function

Bit symbol

b7 b6 b5 b4 b3 b2 b1 b0

Operation mode select bit 0 0 : Timer mode or A/D trigger mode

b1 b0

TMOD1

TMOD0

MR0 Has no effect in timer mode

Can be set to “0” or “1”

MR2

MR1

MR3

0 0 : f1 or f2

0 1 : f8

1 0 : f32

1 1 : fC32

TCK1

TCK0 Count source select bit

TB0MR register

Must be set to “0” in timer mode

b7 b6

TB1MR, TB2MR registers

Nothing is assigned. When write, set to “0”. When read, its

content is indeterminate

When write in timer mode, set to “0”. When read in timer mode, its

content is indeterminate.

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Item Specification

Count source • External signals input to TBiIN pin (i=0 to 2) (effective edge can be selected

in program)

• Timer Bj overflow or underflow (j=i-1, except j=2 if i=0)

Count operation •Down-count

•When the timer underflows, it reloads the reload register contents and

continues counting

Divide ratio 1/(n+1) n: set value of TBi register 000016 to FFFF16

Count start condition Set TBiS bit(1) to “1” (= start counting)

Count stop condition Set TBiS bit to “0” (= stop counting)

Interrupt request generation timing

Timer underflow

TBiIN pin function Count source input

Read from timer Count value can be read by reading TBi register

Write to timer

• When not counting and until the 1st count source is input after counting start

Value written to TBi register is written to both reload register and counter

• When counting (after 1st count source input)

Value written to TBi register is written to only reload register

(Transferred to counter when reloaded next)

NOTE:

1. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.

12.2.2 Event Counter Mode

In event counter mode, the timer counts pulses from an external device or overflows and underflows of

other timers (see Table 12.2.2.1) . Figure 12.2.2.1 shows TBiMR register in event counter mode.

Table 12.2.2.1 Specifications in Event Counter Mode

Figure 12.2.2.1 TBiMR Register in Event Counter Mode

Timer Bi mode register (i=0 to 2)

Symbol Address After reset

TB0MR to TB2MR 039B

to 039D

00XX0000

Bit name FunctionBit symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

Operation mode select bit 0 1 : Event counter mode

b1 b0

TMOD1

TMOD0

MR0 Count polarity select

bit

(1)

MR2

MR1

MR3

TCK1

TCK0

0 0 : Counts external signal's

falling edges

0 1 : Counts external signal's

rising edges

1 0 : Counts external signal's

falling and rising edges

1 1 : Must not be set

b3 b2

Has no effect in event counter mode.

Can be set to “0” or “1”.

Event clock select 0 : Input from TBi

(2)

1 : TBj overflow or underflow

(j = i – 1, except j = 2 if i = 0)

TB0MR register

Must be set to “0” in timer mode

TB1MR, TB2MR registers

Nothing is assigned. When write, set to “0”. When read, its

content is indeterminate.

When write in event counter mode, set to “0”. When read in event

counter mode, its content is indeterminate.

NOTES:

1. Effective when the TCK1 bit is set to “0” (input from TBiIN pin). If the TCK1 bit is set to “1” (TBj overflow or underflow), these bits

can be set to “0” or “1”.

2. The port direction bit for the TBiIN pin must be set to “0” (= input mode).

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Item Specification

Count source f1, f2, f8, f32, fC32

Count operation •Up-count

•Counter value is transferred to reload register at an effective edge of mea-

surement pulse. The counter value is set to “000016” to continue counting.

Count start condition Set TBiS (i=0 to 2) bit(3) to “1” (= start counting)

Count stop condition Set TBiS bit to “0” (= stop counting)

Interrupt request generation timing

• When an effective edge of measurement pulse is input(1)

• Timer overflow. When an overflow occurs, MR3 bit in the TBiMR register is

set to “1” (overflowed) simultaneously. MR3 bit is cleared to “0” (no over-

flow) by writing to TBiMR register at the next count timing or later after MR3

bit was set to “1”. At this time, make sure TBiS bit is set to “1” (start count-

ing).

TBiIN pin function Measurement pulse input

Read from timer

Contents of the reload register (measurement result) can be read by reading TBi register(2)

Write to timer Value written to TBi register is written to neither reload register nor counter

NOTES:

1. Interrupt request is not generated when the first effective edge is input after the timer started counting.

2. Value read from TBi register is indeterminate until the second valid edge is input after the timer starts counting.

3. The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.

12.2.3 Pulse Period and Pulse Width Measurement Mode

In pulse period and pulse width measurement mode, the timer measures pulse period or pulse width of an

external signal (see Table 12.2.3.1). Figure 12.2.3.1 shows TBiMR register in pulse period and pulse

width measurement mode. Figure 12.2.3.2 shows the operation timing when measuring a pulse period.

Figure 12.2.3.3 shows the operation timing when measuring a pulse width.

Table 12.2.3.1 Specifications in Pulse Period and Pulse Width Measurement Mode

Figure 12.2.3.1

TBiMR Register in Pulse Period and Pulse Width Measurement Mode

Timer Bi mode register (i=0 to 2)

Symbol Address After reset

TB0MR to TB2MR 039B

to 039D

00XX0000

Bit nameBit symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

Operation mode

select bit 1 0 : Pulse period / pulse width

measurement mode

b1 b0

TMOD1

TMOD0

MR0 Measurement mode

select bit

MR2

MR1

MR3

TCK1

TCK0

0 0 : Pulse period measurement

(Measurement between a falling edge and the

next falling edge of measured pulse)

0 1 : Pulse period measurement

(Measurement between a rising edge and the next

rising edge of measured pulse)

1 0 : Pulse width measurement

(Measurement between a falling edge and the

next rising edge of measured pulse and between

a rising edge and the next falling edge)

1 1 : Must not be set.

Function

b3 b2

Count source

select bit

Timer Bi overflow

flag

(1)

0 : Timer did not overflow

1 : Timer has overflowed

0 0 : f

or f

0 1 : f

1 0 : f

1 1 : f

C32

b7 b6

TB0MR register

Must be set to “0” in pulse period and pulse width measurement mode

TB1MR, TB2MR registers

Nothing is assigned. When write, set to “0”. When read, its content turns out to be

indeterminate.

NOTE:

1. This flag is indeterminate after reset. When the TBiS bit is set to "1" (start counting), the MR3 bit is cleared to “0” (no overflow) by writing to the

TBiMR register at the next count timing or later after the MR3 bit was set to “1” (overflowed). The MR3 bit cannot be set to “1” in a program. The

TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.

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Figure 12.2.3.3 Operation timing when measuring a pulse width

Measurement pulse “H”

Count source

Timing at which counter

reaches “0000

”

“1”

Transfer

(measured value) Transfer

(measured value)

“L”

“0”

“1”

“0”

(1)(1)

(1)

Transfer

(measured

value)

(1) (2)

Transfer

(indeterminate

value)

Reload register counter

transfer timing

TBiS bit

IR bit in the TBiIC

MR3 bit in the TBiMR

The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.

Set to “0” upon accepting an interrupt request or by

writing in program

i = 0 to 2

NOTES:

1. Counter is initialized at completion of measurement.

2. Timer has overflowed.

3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are “10

” (measure the

interval from a falling edge to the next rising edge and the interval from a rising edge to the next falling edge of

the measurement pulse).

Figure 12.2.3.2 Operation timing when measuring a pulse period

Count source

Measurement pulse

TBiS bit

IR bit in the TBiIC

Timing at which counter

reaches “0000

”

“H”

“1”

Transfer

(indeterminate value)

“L”

“0”

MR3 bit in theTBiMR

“1”

“0”

(1)(1) (2)

Transfer

(measured value)

“1”

Reload register counter

transfer timing

The TB0S to TB2S bits are assigned to the bit 5 to bit 7 in the TABSR register.

Set to “0” upon accepting an interrupt request or by writing in

program

i = 0 to 2

NOTES:

1. Counter is initialized at completion of measurement.

2. Timer has overflowed.

3. This timing diagram is for the case where the MR1 to MR0 bits in the TBiMR register are “00

” (measure the interval

from falling edge to falling edge of the measurement pulse).

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12.2.4 A/D Trigger Mode

A/D trigger mode is used as conversion start trigger for A/D converter in simultaneous sample sweep

mode of A/D conversion or delayed trigger mode 0. This mode is used as conversion start trigger of A/D

converter. A/D trigger mode is used in Timer B0 and Timer B1. In this mode, the timer starts counting by

one trigger until the count value becomes 000016. Figure 12.2.4.1 shows the TBiMR register in A/D

trigger mode and figure 12.2.4.2 shows the TB2SC register.

Item Specification

Count Source f1, f2, f8, f32, and fC32

Count Operation •Down count

•When the timer underflows, reload register contents are reloaded before

stopping counting

•When a trigger is generated during the count operation, the count is not

affected

Divide Ratio 1/(n+1) n: Setting value of TBi register (i=0,1)

000016-FFFF16

Count Start Condition When the TBiS (i=0,1) bit in the TABSR register is "1"(count started), TBiEN

(i=0,1) bit in TB2SC register is "1", and the following trigger is generated.

(Selection based on TB2SEL bit in the TB2SC register)

• Timer B2 overflow or underflow

• Underflow of Timer B2 interrupt generation frequency counter setting

Count Stop Condition • After the count value is 000016 and reload register contents are reloaded

• Set the TBiS bit to "0"(count stopped)

nterrupt Request Timer underflows (1)

Generation Timing

TBiIN Pin Function I/O port

Read From Timer Count value can be read by reading TBi register

Write To Timer (2) • When writing in the TBi register during count stopped.

Value is written to both reload register and counter

• When writing in the TBi register during count.

Value is written to only reload register (Transfered to counter when reloaded next)

NOTES:

1. A/D conversion is started by the timer underflow. For details refer to Section 14. A/D Converter.

2. When using in delayed trigger mode 0, set the larger value than the value of the timer B0 register

to the timer B1 register.

Table 12.2.4.1 A/D Trigger Mode Specifications

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Timer Bi mode register (i= 0 to 1)

Symbol Address After reset

TB0MR to TB1MR 039B16 to 039C16 00XX00002

Bit name Function

Bit symbol

b7 b6 b5 b4 b3 b2 b1 b0

Operation Mode Select Bit 0 0 : Timer mode or A/D trigger mode

b1 b0

TMOD1

TMOD0

MR0 Invalid in A/D trigger mode

Either "0" or "1" is enabled

MR2

MR1

MR3

0 0 : f1 or f2

0 1 : f8

1 0 : f32

1 1 : fC32

TCK1

TCK0 Count Source Select Bit

(1)

TB0MR register

Set to “0” in A/D trigger mode

b7 b6

TB1MR register

Nothing is assigned. When write, set to “0”. When read, its

content is indeterminate

When write in A/D trigger mode, set to “0”. When read in A/D

trigger mode, its content is indeterminate.

NOTE:

1. When this bit is used in dela

ed tri

er mode 0, set the same count source to the timer B0 and timer B1.

Figure 12.2.4.1 TBiMR Register in A/D Trigger Mode

PWCOM

Symbol Address After reset

TB2SC 039E16 X00000002

Timer B2 Reload Timing

Switch Bit 0 : Timer B2 underflow

1 : Timer A output at odd-numbered

Timer B2 special mode register

(1)

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

IVPCR1 Three-Phase Output Port

SD Control Bit 1 0 : Three-phase output forcible cutoff

by SD pin input (high impedance)

disabled

1 : Three-phase output forcible cutoff

by SD pin input (high impedance)

enabled

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

(b7)

TB2SEL Trigger Select Bit 0 : TB2 interrupt

1 : Underflow of TB2 interrupt

generation frequency setting counter [ICTB2]

TB0EN Timer B0 Operation Mode

Select Bit 0 : Other than A/D trigger mode

1 : A/D trigger mode

(5)

TB1EN Timer B1 Operation Mode

Select Bit 0 : Other than A/D trigger mode

1 : A/D trigger mode

(5)

(2)

(3, 4, 7)

(6)

(b6-b5) Reserved bits Must set to "0"

NOTES:

1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).

2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set this bit to

"0" (timer B2 underflow).

3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), Set the PD8_5 bit to

"0" (= input mode).

4. Related pins are U(P8

), U(P8

), V(P7

), W(P7

). When a high-level ("H") signal is applied to the SD

pin and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-impedance state.

If a low-level (“L”) signal is applied to the SD pin, three-phase motor control timer output will be disabled (INV03=0).

At this time, when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become programmable I/O ports. When the IVPCR1

bit is set to 1, pins U, U, V, V, W, and W are placed in a high-impedance state regardless of which function of those

pins is used.

5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1"(A/D trigger mode).

6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), Set the

INV02 bit to "1" (three-phase motor control timer function).

7. Refer to 16.6 Di

ital Debounce function for SD in

ut.

Figure 12.2.4.2 TB2SC Register

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Item Specification

Three-phase waveform output pin ___ ___ ___

Six pins (U, U, V, V, W, W)

Forced cutoff input (1) _____

Input “L” to SD pin

Used Timers Timer A4, A1, A2 (used in the one-shot timer mode)

___

Timer A4: U- and U-phase waveform control

___

Timer A1: V- and V-phase waveform control

___

Timer A2: W- and W-phase waveform control

Timer B2 (used in the timer mode)

Carrier wave cycle control

Dead timer timer (3 eight-bit timer and shared reload register)

Dead time control

Output waveform Triangular wave modulation, Sawtooth wave modification

Enable to output “H” or “L” for one cycle

Enable to set positive-phase level and negative-phase

level respectively

Carrier wave cycle Triangular wave modulation: count source x (m+1) x 2

Sawtooth wave modulation: count source x (m+1)

m: Setting value of TB2 register, 0 to 65535

Count source: f1, f2, f8, f32, fC32

Three-phase PWM output width Triangular wave modulation: count source x n x 2

Sawtooth wave modulation: count source x n

n: Setting value of TA4, TA1 and TA2 register (of TA4,

TA41, TA1, TA11, TA2 and TA21 registers when setting

the INV11 bit to “1”), 1 to 65535

Count source: f1, f2, f8, f32, fC32

Dead time active disable function Count source x p, or no dead time

p: Setting value of DTT register, 1 to 255

Count source: f1, f2, f1 divided by 2, f2 divided by 2

Active level Eable to select “H” or “L”

Positive and negative-phase concurrent

Positive and negative-phases concurrent active disable function

Positive and negative-phases concurrent active detect function

Interrupt frequency For Timer B2 interrupt, select a carrier wave cycle-to-cycle

basis through 15 times carrier wave cycle-to-cycle basis

12.3 Three-phase Motor Control Timer Function

Timers A1, A2, A4 and B2 can be used to output three-phase motor drive waveforms. Table 12.3.1 lists the

specifications of the three-phase motor control timer function. Figure 12.3.1 shows the block diagram for

three-phase motor control timer function. Also, the related registers are shown on Figure 12.3.2 to Figure

12.3.8.

Table 12.3.1. Three-phase Motor Control Timer Function Specifications

NOTES: _____

1. When the INV02 bit in the INVC0 register is set to “1” (three-phase motor control timer function), the SD

_____

function of the P85/SD pin is enabled. At this time, the P85 pin cannot be used as a programmable I/O

_____ _____

port. When the SD function is not used, apply “H” to the P85/SD pin. _____

2. When the IVPCR1 bit in the TB2SC register is set to “1” (enable three-phase output forced cutoff by SD

_____

pin input), and “L” is applied to the SD pin, the related pins enter high-impedance state regardless of the

functions which are used. When the IVPCR1 bit is set to “0” (disabled three-phase output forced cutoff

_____ _____

by SD pin input) and “L” is applied to the SD pin, the related pins can be selected as a programmable I/

O port and the setting of the port and port direction registers are enable.

Related pins P72/CLK2/TA1OUT/V/RxD1

_________ _________ ___

P73/CTS2/RTS2/TA1IN/V/TxD1

P74/TA2OUT/W

____

P75/TA2IN/W

P80/TA4OUT/U

___

P81/TA4IN/U

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DRQ

0INV12

Trigger

Timer B2

(Timer mode)

Signal to be

written to

timer B2

1Timer B2

interrupt request bit

DU1

bit

TQQ

Three-phase output

shift register

(U phase)

Dead time timer

n = 1 to 255

Trigger

Reload register

n = 1 to 255

Trigger

phase output signal

W phase output

control circuit

Reload

Timer A 1 counter

(One-shot timer mode)

Trigger

Reload

Timer A2

counter

(One-shot timer mode)

Trigger

Reload

Timer A4 counter

(One-shot timer mode)

Trigger

Transfer trigger

(Note 1)

Timer B2 underflow

DU0

bit

DUB0

bit

TA4 register

TA41

TA1

TA11

TA2

TA21

Timer Ai(i = 1, 2, 4) start trigger signal

Timer A4 reload control signal

Timer A4

one-shot pulse

DUB1

bit

Dead time timer

n = 1 to 255

Dead time timer

n = 1 to 255

Interrupt occurrence set circuit

ICTB2 register

n = 1 to 15

INV13

ICTB2 counter

n = 1 to 15

RESET

INV03

INV14

INV05

INV04

INV00 INV01

INV11

INV06

INV07

INV10

1/2

f1 or f2

phase output

control circuit

phase output

control circuit

phase output signal

phase output

signal

phase output signal

Reverse

control

Reverse

control

Reverse

control

Reverse

control

Reverse

control

TQD

Reverse

control

IDW

IDV

IDU

Bits 2 through 0 of Position-data-

retain function control register

(address 034E

)

PD8_0

PD8_1

PD7_2

PD7_3

PD7_4

PD7_5

RESET

IVPRC1

Data Bus

NOTE:

1. If the INV06 bit is set to "0" (triangular wave modulation mode), a transfer trigger is generated at only the first occurrence of a timer B2 underflow after writing to the IDB0 and IDB1 registers.

Set to "0" when the TA2S bit is set to "0"

Set to "0" when TA1S bit = "0"

Set to "0" when TA4S bit = "0"

Diagram for switching to P8

, P81 and P7

- P7

is not shown.

Figure 12.3.1. Three-phase Motor Control Timer Functions Block Diagram

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Figure 12.3.2. INVC0 Register

Three-phase PWM control register 0 (1)

Symbol

Address

After reset

INVC0 034816 0016

b7 b6 b5 b4 b3 b2 b1 b0

Effective interrupt output

polarity select bit

INV00

Bit symbol Bit name Description RW

INV01

Effective interrupt output

specification bit

INV02 Mode select bit

INV04 Positive and negative

phases concurrent output

disable bit

INV07 Software trigger select bit

INV06 Modulation mode select

bit

INV05 Positive and negative

phases concurrent output

detect flag

INV03 Output control bit

0: The ICTB2 counter is incremented by

one on the rising edge of the timer A1

reload control signal

1: The ICTB2 counter is incremented by

one on the falling edge of the timer A1

reload control signal

ICTB2 counter incremented by 1 at a

timer B2 underflow

1: Selected by INV00 bit

0: Three-phase motor control timer

function unused

1: Three-phase motor control timer

function

0: Three-phase motor control timer output

disabled

1: Three-phase motor control timer output

enabled

0: Simultaneous active output enabled

1: Simultaneous active output disabled

0: Not detected yet

1: Already detected

0: Triangular wave modulation mode

1: Sawtooth wave modulation mode

Setting this bit to “1” generates a transfer

trigger. If the INV06 bit is “1”, a trigger for

the dead time timer is also generated.

The value of this bit when read is “0”.

(9)

(3)

(7)

(2, 3)

(4)

(5)

(8)

Item

Mode

Timing at which transferred from IDB0 to

IDB1 registers to three-phase output shift

Timing at which dead time timer trigger is

generated when INV16 bit is “0”

INV13 bit

INV06=0

Triangular wave modulation mode

Transferred only once synchronously

with the transfer trigger after writing to

the IDB0 to IDB1 registers

Synchronous with the falling edge of

timer A1, A2, or A4 one-shot pulse

Effective when INV11 is “1” and INV06

is “0”

INV06=1

Sawtooth wave modulation mode

Transferred every transfer trigger

Synchronous with the transfer

trigger and the falling edge of timer

A1, A2, or A4 one-shot pulse

Transfer trigger: Timer B2 underflow, write to the INV07 bit or write to the TB2 register when INV10 is “1”

(6)

Has no effect

(10)

(5)

NOTES:

1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable). Note also that INV00 to INV02,

INV04 and INV06 bits can only be rewritten when timers A1, A2, A4 and B2 are idle.

2. If this bit needs to be set to “1”, set any value in the ICTB2 register before writing to it.

3. Effective when the INV11 bit is set to “1” (three-phase mode 1). If INV11 is set to “0” (three-phase mode 0), the ICTB2

counter is incremented by “1” each time the timer B2 underflows, regardless of whether the INV00 and INV01 bits are set.

When setting the INV01 bit to “1”, set the timer A1 count start flag before the first timer B2 underflow.When the INV00 bit is

set to “1”, the first interrupt is generated when the timer B2 underflows n-1 times, if n is the value set in the ICTB2 counter.

Subsequent interrupts are generated every n times the timer B2 underflow.

4. Setting the INV02 bit to “1” activates the dead time timer, U/V/W-phase output control circuits and ICTB2 counter.

5. When the INV02 bit is set to “1”(theee-phase control timer functions) and the INV03 is set to "0"(three-phase motor control

timer output disabled), U, U, V, V, W and W pins, including pins shared with other output functions, enter a high-impedance

state.

6. The INV03 bit is set to “0” in the following cases:

• When reset

• When positive and negative go active (INV05="1") simultaneously while INV04 bit is set to “1”

• When set to “0” in a program

• When input on the SD pin changes state from “H” to “L” (The INV03 bit cannot be set to “1” when SD input is “L”.) When

both the INV04 and the INV05 bits are set to “1”, the INV03 bit is set to “0”.

7. Can only be set by writing “0” in a program, and cannot be set to “1”.

8. The effects of the INV06 bit are described in the table below.

9. If the INV06 bit is “1”, set the INV11 bit to “0” (three-phase mode 0) and set the PWCON bit to “0” (timer B2 reloaded by a

timer B2 underflow).

10. Individual pins can be disabled using PFCR register.

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Figure 12.3.3. INVC1 Register

Three-phase PWM control register 1

(1)

Symbol Address After reset

INVC1 034916 0016

b7 b6 b5 b4 b3 b2 b1 b0

Timer A1, A2, A4 start

trigger signal select bit

INV10

Bit symbol Bit name Description RW

INV11

Timer A1-1, A2-1, A4-1

control bit

INV12 Dead time timer count

source select bit

INV14 Output polarity control bit

(b7) Reserved bit

INV16 Dead time timer trigger

select bit

INV15 Dead time invalid bit

INV13 Carrier wave detect flag

0: Timer B2 underflow

1: Timer B2 underflow and write to the

TB2 register

0: Three-phase mode 0

1: Three-phase mode 1

0 : f1 or f2

1 : f1 divided by 2 or f2 divided by 2

0: Timer A1 reload control signal is “0”

1: Timer A1 reload control signal is “1”

0 : Output waveform “L” active

1 : Output waveform “H” active

0: Dead time timer enabled

1: Dead time timer disabled

0: Falling edge of timer A4, A1 or A2

one-shot pulse

1: Rising edge of three-phase output shift

This bit should be set to “0”

(6)

(5)

(3)

Item

Mode

TA11, TA21, TA41 registers

INV00 bit, INV01 bit

INV13 bit

INV11=0

Three-phase mode 1

Three-phase mode 0

Not used

Has no effect. ICTB2 counted every time

timer B2 underflows regardless of

whether the INV00 to INV01 bits are set.

Has no effect

INV11=1

Used

Effect

Effective when INV11 bit is set to “1”

and INV06 bit is set to “0”

(4)

(2)

4. If the INV06 bit is set to “1” (sawtooth wave modulation mode), set this bit to “0” (three-phase mode 0). Also, if the

INV11 bit is “0”, set the PWCON bit to “0” (timer B2 reloaded by a timer B2 underflow).

5. The INV13 bit is effective only when the INV06 bit is set to “0” (triangular wave modulation mode) and the INV11 bit is

set to “1” (three-phase mode 1).

6. If all of the following conditions hold true, set the INV16 bit to “1” (dead time timer triggered by the rising edge of

three-phase output shift register output) • The INV15 bit is set to “0” (dead time timer enabled) • When the INV03 bit is

set to “1” (three-phase motor control timer output enabled), the Dij bit and DiBj bit (i:U, V, or W, j: 0 to 1) have always

different values (the positive-phase and negative-phase always output different levels during the period other than

dead time).

Conversely, if either one of the above conditions holds false, set the INV16 bit to “0” (dead time timer triggered by the

falling edge of one-shot pulse).

NOTES:

1. Write to this register after setting the PRC1 bit in the PRCR register to “1” (write enable). Note also that this register

can only be rewritten when timers A1, A2, A4 and B2 are idle.

2. A start trigger is generated by writing to the TB2 register only while timer B2 stops.

3. The effects of the INV11 bit are described in the table below.

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Three-phase output bu

er re

ister(i=0,1) (1)

Symbol Address When reset

IDB0 034A16 001111112

IDB1 034B16 001111112

RWBit name FunctionBit symbol

DUi

DUBi

DVi

U phase output buffer i

NOTE:

1. The IDB0 and IDB1 register values are transferred to the three-phase shift register by a transfer trigger. The value

written to the IDB0 register aftera transfer trigger represents the output signal of each phase, and the next value written

to the IDB1 register at the falling edge of the timer A1, A2 or A4 one-shot pulse represents the output signal of each

phase.

(b7-b6)

DVBi

Nothing is assigned. When write, set to "0". When read,

these contents are "0".

Write the output level

0: Active level

1: Inactive level

When read, these bits show the three-phase

output shift register value.

DWi

DWBi

U phase output buffer i

V phase output buffer i

W phase output buffer i

2b1b0

Dead time timer (1, 2)

Symbol Address When reset

DTT 034C

Indeterminate

RWFunction Setting range

NOTES:

1. Use MOV instruction to write to this register.

2. Effective when the INV15 bit is set to “0” (dead time timer enable). If the INV15 bit is set to “1”, the dead time timer is

disabled and has no e

ect.

1 to 255

b7 b6 b5 b4 b3 b2 b1 b0

Assuming the set value = n, upon a start trigger the timer starts

counting the count souce selected by the INV12 bit and stops

after counting it n times. The positive or negative phase

whichever is going from an inactive to an active level changes

at the same time the dead time timer stops.

Figure 12.3.4. IDB0 Register, IDB1Register, DTT Register, and ICTB2 Register

Timer B2 Interrupt Occurrences Frequency Set Counter

Symbol

ICTB2 Address

034D

After Reset

Indeterminate

Function

Setting Range

b7 b6 b5 b4 b0

If the INV01 bit is "0" (ICTB2 counter counted every

time timer B2 underflows), assuming the set value

= n, a timer B2 interrupt is generated at every níth

occurrence of a timer B2 underflow.

If the INV01 bit is "1" (ICTB2 counter count timing

selected by the INV00 bit), assuming the set value

= n, a timer B2 interrupt is generated at every níth

occurrence of a timer B2 underflow that meets the

condition selected by the INV00 bit.

1 to 15

NOTE:

1. Use MOV instruction to write to this register.

If the INV01 bit is set to "1", make sure the TB2S bit also is set to "0" (timer B2 count stopped) when writing to

this register. If the INV01 bit is set to "0", although this register can be written even when the TB2S bit is set to

"1" (timer B2 count start), do not write synchronously with a timer B2 underflow.

(1)

Nothing is assigned. When write, set to "0". When read, its content is

indeterminate.

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Figure 12.3.5.

TA1, TA2, TA4, TA11, TA21 and TA41 Registers

Symbol Address After reset

TA1 038916-038816

TA2 038B16-038A16 Indeterminate

TA4 038F16-038E16 Indeterminate

TA11 (6,7) 034316-034216 Indeterminate

TA21 (6,7) 034516-034416 Indeterminate

TA41 (6,7) 034716-034616 Indeterminate

b7 b0 b7 b0

(b15) (b8)

Assuming the set value = n, upon a start trigger the timer

starts counting the count source and stops after counting

it n times. The positive and negative phases change at

the same time timer A, A2 or A4 stops.

Function Setting range

Timer Ai, Ai-1 register (i=1, 2, 4)

(1, 2, 3, 4, 5)

000016 to FFFF16

Indeterminate

NOTES:

1. The register must be accessed in 16 bit units.

2. When the timer Ai register is set to "000016", the counter does not operate and a timer Ai interrupt does not

occur.

3.Use MOV instruction to write to these registers.

4. If the INV15 bit is "0" (dead time timer enable), the positive or negative phase whichever is going from an

inactive to an active level changes at the same time the dead time timer stops.

5. If the INV11 bit is "0" (three-phase mode 0), the TAi register value is transferred to the reload register by a

timer Ai (i = 1, 2 or 4) start trigger. If the INV11 bit is "1" (three-phase mode 1), the TAi1 register value is

transferred to the reload register by a timer Ai start trigger first and then the TAi register value is transferred

to the reload register by the next timer Ai start trigger. Thereafter, the TAi1 register and TAi register values

are transferred to the reload register alternately.

6. Do not write to TAi1 registers synchronously with a timer B2 underflow In three-phase mode 1.

7. Write to the TAi1 register as follows:

(1) Write a value to the TAi1 register

(2) Wait for one cycle of timer Ai count source.

(3) Write the same value to the TAi1 register again.

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Figure 12.3.6.

TB2SC Registers

0: Three-phase output forcible cutoff by SD pin input

(high impedance) disabled

1: Three-phase output forcible cutoff by SD pin input

(high impedance) enabled

NOTES:

1. When "L" is applied to the SD pin, INV03 bit is changed to 0 at the same time.

2. The value of the port register and the port direction register becomes effective.

3. When SD function is not used, set to 0 (Input) in PD8

and pullup to "H" in SD pin from outside.

4. To leave the high-impedance state and restart the three-phase PWM signal output after the three-phase PWM signal

output forced cutoff, set the IVPCR1 bit to 0 after the SD pin input level becomes high (“H”).

IVPCR1 bit Status of U/V/W pins Remarks

SD pin inputs

(Three-phase output

forcrible cutoff enable)

(Three-phase output

forcrible cutoff disable)

High impedance

Peripheral input/output

or input/output port

Peripheral input/output

or input/output port

Peripheral input/output

or input/output port

Three-phase output

forcrible cutoff(1)

IVPCR1 bit Status of U/V/W pins Remarks

SD pin inputs(3)

(Three-phase output

forcrible cutoff enable)

(Three-phase output

forcrible cutoff disable)

L(1)

High impedance(4) Three-phase output

forcrible cutoff

Input/output port(2)

Three-phase PWM output

The effect of SD pin input is below.

1.Case of INV03 = 1(Three-phase motor control timer output enabled)

PWCON

Symbol Address After Reset

TB2SC 039E16 X00000002

Timer B2 reload timing

switch bit

Timer B2 Special Mode Register

(1)

Bit Name FunctionBit Symbol

b7 b6 b5 b4 b3 b2 b1 b0

IVPCR1 Three-phase output port

SD control bit 1

Nothing is assigned. If necessary, set to 0.

When read, the content is 0.

(b7)

TB2SEL Trigger select bit 0: TB2 interrupt

1: Underflow of TB2 interrupt

generation frequency setting counter [ICTB2]

TB0EN Timer B0 operation mode

select bit 0: Other than A/D trigger mode

1: A/D trigger mode RW

TB1EN Timer B1 operation mode

select bit 0: Other than A/D trigger mode

1: A/D trigger mode RW

(2)

(3, 4, 7)

(5)

(6)

(b6-b5) Reserved bits Set to 0

NOTES:

1. Write to this register after setting the PRC1 bit in the PRCR register to 1 (write enabled).

2. If the INV11 bit is 0 (three-phase mode 0) or the INV06 bit is 1 (triangular wave modulation mode), set this bit to 0 (timer

B2 underflow).

3. When setting the IVPCR1 bit to 1 (three-phase output forcible cutoff by SD pin input enabled), Set the PD85 bit to 0 (= input

mode).

4. Related pins are U(P8

), U(P8

), V(P7

), W(P7

). When a high-level ("H") signal is applied to the SD pin

and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-impedance state. If a low-

level (“L”) signal is applied to the SD pin, three-phase motor control timer output will be disabled (INV03=0). At this time,

when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become programmable I/O ports. When the IVPCR1 bit is set to 1,

pins U, U, V, V, W, and W are placed in a high-impedance state regardless of which function of those pins is used.

5. When this bit is used in delayed trigger mode 0, set bits TB0EN and TB1EN to 1 (A/D trigger mode).

6. When setting the TB2SEL bit to 1 (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), set the INV02

bit to 1 (three-phase motor control timer function).

NOTE:

1. The three-phase output forcrible cutoff function becomes effective if the INPCR1 bit is set to 1 (three-phase output

forcrible cutoff function enable) even when the INV03 bit is 0 (three-phase motor control timer output disalbe)

2.Case of INV03 = 0(Three-phase motor control timer output disabled)

0: Timer B2 underflow

1: Timer A output at odd-numbered

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Figure 12.3.7. TB2 Register, TRGSR Register, and TABSR Register

TA1TGL

Symbol Address After reset

TRGSR 0383

Timer A1 event/trigger

select bit To use the V-phase output control

circuit, set these bits to “01

”(TB2

underflow).

Trigger select register

Bit name Function

Bit symbol

To use the W-phase output control

circuit, set these bits to “01

”(TB2

underflow).

0 0 :

Input on TA3

is selected (1)

0 1 :

TB2 overflow is selected (2)

1 0 :

TA2 overflow is selected

(2)

1 1 :

TA4 overflow is selected (2)

To use the U-phase output control

circuit, set these bits to “01

”(TB2

underflow).

Timer A2 event/trigger

select bit

Timer A3 event/trigger

select bit

Timer A4 event/trigger

select bit

TA1TGH

TA2TGL

TA2TGH

TA3TGL

TA3TGH

TA4TGL

TA4TGH

b5 b4

b7 b6 b5 b4 b3 b2 b1

Symbol Address After reset

TABSR 0380

Count start flag

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

Timer B2 count start flag

Timer B1 count start flag

Timer B0 count start flag

Timer A4 count start flag

Timer A3 count start flag

Timer A2 count start flag

Timer A1 count start flag

Timer A0 count start flag 0 : Stops counting

1 : Starts counting

TB2S

TB1S

TB0S

TA4S

TA3S

TA2S

TA1S

TA0S

NOTES:

1. Set the corresponding port direction bit to “0” (input mode).

2. Overflow or underflow

Symbol Address After reset

TB2 039516 to 039416 Indeterminate

b7 b0 b7 b0

(b15) (b8)

000016 to FFFF16

Function Setting range

Timer B2 register (1)

NOTE:

1. The register must be accessed in 16 bit units.

Divide the count source by n + 1 where n = set value.

Timer A1, A2 and A4 are started at every occurrence of

underflow.

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Figure 12.3.8. TA1MR, TA2MR, TA4MR, and TB2MR Registers

Bit name

Timer Ai mode register

Symbol Address After reset

TA1MR 0397

TA2MR 0398

TA4MR 039A

Function

Bit symbol

b7 b6 b5 b4 b3 b2 b1 b0

Operation mode

select bit Must set to “10

” (one-shot timer mode) for

the three-phase motor control timer function

TMOD1

TMOD0

MR0 Pulse output function

select bit Must set to “0” for the three-phase motor

control timer function

MR2

MR1

MR3 Must set to “0” for the three-phase motor control timer function

0 0 : f

or f

0 1 : f

1 0 : f

1 1 : f

C32

b7 b6

TCK1

TCK0 Count source select bit

100

Must set to “1” (selected by event/trigger

select register) for the three-phase motor

control timer function

Trigger select bit

External trigger select

bit

Timer B2 mode register

Symbol Address After reset

TB2MR 039D

00XX0000

Bit name Function

Bit symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

Operation mode select bit Set to “00

” (timer mode) for the three-

phase motor control timer function

TMOD1

TMOD0

MR0

MR2

MR1

MR3

0 0 : f

or f

0 1 : f

1 0 : f

1 1 : f

C32

TCK1

TCK0 Count source select bit

When write in three-phase motor control timer function, write “0”.

When read, its content is indeterminate.

b7 b6

Has no effect for the three-phase motor

control timer function

Has no effect for the three-phase motor control timer function.

When write, set to “0”. When read, its content is indeterminate.

Must set to “0” for the three-phase motor control timer function

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Figure 12.3.9. Triangular Wave Modulation Operation

The three-phase motor control timer function is enabled by setting the INV02 bit in the VC0 register to “1”.

When this function is on, timer B2 is used to control the carrier wave, and timers A4, A1 and A2 are used to

__ ___ ___

control three-phase PWM outputs (U, U, V, V, W and W). The dead time is controlled by a dedicated dead-

time timer. Figure 12.3.9 shows the example of triangular modulation waveform, and Figure 12.3.10 shows

the example of sawtooth modulation waveform.

Start trigger signal

for timer A4

(1)

Timer B2

U phase

Triangular wave

Signal wave

U phase

output signal

(1)

mnn pp

U phase

INV14 = 0

Triangular waveform as a Carrier Wave

Timer A4

one-shot pulse

(1)

INV14 = 1

Dead time

Rewrite registers IDB0 and IDB1

NOTE:

1. Internal signals. See Figure 12.3.1.

Examples of PWM output change are:

(1)When INV11 = 1 (three-phase mode 1)

· INV01 = 0 and ICTB2 = 2

(the timer B2 interrupt is generated

every two times the timer B2 underflows),

or INV01 = 1, INV00 = 1, and ICTB2=1

(the timer B2 interrupt is

generated at the falling edge of the timer A1 reload control signal.)

· Default value of the timer: TA41 = m, TA4 = m.

Registers TA4 and TA41 are changed whenever the timer B2

interrupt is generated.

First time, TA41 = n, TA4 = n. Second time, TA41 = p, TA4 = p.

· Default values of registers IDB0 and IDB1:

DU0 = 1, DUB0 = 0, DU1 = 0, DUB1 = 1.

They are changed to DU0 = 1, DUB0 = 0, DU1= 1 and DUB1 = 0

when the third timer B2 interrupt is generated.

(2)When INV11 = 0 (three-phase mode 0)

· INV01 = 0, ICTB2 = 1

(the timer B2 interrupt is generated

whenever timer B2 underflows)

· Default value of the timer: TA4 = m. The TA4 register is changed

whenever the timer B2 interrupt is generated.

First time: TA4 = m. Second tim:, TA4 = n.

Third time: TA4 = n. Fourth time: TA4 = p.

Fifth time: TA4 = p.

· Default values of registers IDB0 and IDB1:

DU0 = 1, DUB0 = 0, DU1 = 0, DUB1 = 1.

They are changed to DU0 = 1, DUB0 = 0, DU1 = 1, and DUB1 = 0

when the sixth timer B2 interrupt is generated.

TB2S bit in the

TABSR register

INV13

(INV11=1(three-phase

mode 1))

The above applies under the following conditions:

INVC0 = 00XX11XX

(X varies depending on each system) and INVC1 = 010XXXX0

U phase

output signal

(1)

(“L” active)

(“H” active)

The value written to registers TA4 and TA41 becomes effective at the rising edge of the timer A1 reload control signal.

Transfer the values

to the three-phase

output shift register

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Timer B2

U phase

Carrier wave

Signal wave

U phase

output signal *

U phase

output signal *

U phase

INV14 = 0

Carrier wave: sawtooth waveform

INV14 = 1

Transfer to three-phase

output shift register

Rewriting IDB0, IDB1 registers

* Internal signals. See the block diagram of the three-phase motor control timer function.

Shown here is a typical waveform for the case where INVC0= 01XX110X2 (X = set as suitable for the

system) and INVC1 = 010XXX002. An example for changing PWM outputs is shown below.

• Initial values of IDB0 and IDB1 registers: DU0=0, DUB0=1, DU1=1, DUB1=1. The register values are

changed to DU0=1, DUB0=0, DU1=1, DUB1=1 a timer B2 interrupt occurs.

Start trigger signal

for timer A4*

Timer A4

one-shot pulse*

Dead time

(“H” active)

(“L” active)

Figure 12.3.10. Sawtooth Wave Modulation Operation

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12.3.1 Position-data-retain Function

This function is used to retain the position data synchronously with the three-phase waveform

output.There are three position-data input pins for U, V, and W phases.

A trigger to retain the position data (hereafter, this trigger is referred to as "retain trigger") can be selected

by the retain-trigger polarity select bit(bit 3 of the position-data-retain function control register, at address

034E16). This bit selects the retain trigger to be the falling edge of each positive phase, or the rising edge

of each positive phase.

12.3.1.1 Operation of the Position-data-retain Function

Figure 12.3.1.1.1 shows a usage example of the position-data-retain function (U phase) when the

retain trigger is selected as the falling edge of the positive signal.

(1) At the falling edge of the U-phase waveform ouput, the state at pin IDU is transferred to the U-

phase position data retain bit ( bit2 at address 034E16 ).

(2) Until the next falling edge of the Uphase waveform output,the above value is retained.

Figure 12.3.1.1.1 Usage Example of Position-data-retain Function ( U phase )

sfe

Carrier wave

U-phase waveform output

1 2

sfe

Pin IDU

NOTE:

1. The retain trigger is the falling edge of the positive signal.

PDRU bit in the RDRF register

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12.3.1.2 Position-data-retain Function Control Register

Figure 12.3.1.2.1 shows the structure of the position-data-retain function contol register.

Figure 12.3.1.2.1. PDRF Register

12.3.1.2.1 W-phase Position Data Retain Bit (PDRW)

This bit is used to retain the input level at pin IDW.

12.3.1.2.2 V-phase Position Data Retain Bit (PDRV)

This bit is used to retain the input level at pin IDV.

12.3.1.2.3 U-phase Position Data Retain Bit (PDRU)

This bit is used to retain the input level at pin IDU.

12.3.1.2.4 Retain-trigger Polarity Select Bit (PDRT)

This bit is used to select the trigger polarity to retain the position data.

When this bit is set to "0", the rising edge of each positive phase selected.

When this bit is set to "1", the falling edge of each pocitive phase selected.

on-

ata-reta

unct

on contro

ster

(1)

Symbol Address When reset

PDRF 034E

XXXX 0000

RWBit name FunctionBit symbol

PDRW

PDRV

PDRU

W-phase position

data retain bit

Input level at pin IDU is read out.

0: "L" level

1: "H" level

Retain-trigger

polarity select bit

(b7-b4)

PDRT

V-phase position

data retain bit

Nothing is assigned. When write, set to "0". When read,

contents are indeterminate.

U-phase position

data retain bit

Input level at pin IDV is read out.

0: "L" level

1: "H" level

Input level at pin IDW is read out.

0: "L" level

1: "H" level

0: Rising edge of positive phase

1: Falling edge of positive phase

NOTE:

1. This register is valid only in the three-phase mode.

2b1b0

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Figure 12.3.2.1. Usage Example of Three-phse/Port output switch function

12.3.2 Three-phase/Port Output Switch Function

When the INVC03 bit in the INVC0 register set to “1”(Timer output enabled for three-phase motor control)

and setting the PFCi (i=0 to 5) in the PFCR register to “0”(I/O port), the three-phase PWM output pin (U,

__ __ ___

U, V, V, W and W) functions as I/O port. Each bit in the PFCi bits (i=0 to 5) is applicable for each one of

three-phase PWM output pins. Figure 12.3.2.1 shows the example of three-phase/port output switch

function. Figure 12.3.2.2 shows the PFCR register and the three-phase protect control register.

Timer B2

U phase

V Phase

W phase

Writing PFCR register(1)

PFC0 bit : "1"

PFC2 bit : "1"

PFC4 bit : "0"

Functions as port P7

Writing PFCR register(1)

PFC0 bit : "1"

PFC2 bit : "0"

PFC4 bit : "1"

NOTE:

1. A hazard may be generated at the output signal, depending on the output switch timing. Also, do not generate (short) be switching to port output

during the dead time of three-phase output.

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Figure 12.3.2.2. PFCR Register, and TPRC Register

ort

unct

on contro

ster

(1)

Symbol Address When reset

PFCR 0358

0011 1111

RWBit name FunctionBit symbol

PFC0

PFC1

PFC2

Port P80 output

function select bit

(b7-b6)

PFC3

Nothing is assigned. When write, set to "0". When read,

these contents are "0".

0: Input/Output port P8

1: Three-phase PWM output

(U phase output)

PFC4

PFC5

Port P81 output

function select bit

Port P72 output

function select bit

Port P73 output

function select bit

Port P74 output

function select bit

Port P75 output

function select bit

0: Input/Output port P8

1: Three-phase PWM output

(U phase output)

0: Input/Output port P7

1: Three-phase PWM output

(V phase output)

0: Input/Output port P7

1: Three-phase PWM output

(V phase output)

0: Input/Output port P7

1: Three-phase PWM output

(W phase output)

0: Input/Output port P7

1: Three-phase PWM output

(W phase output)

NOTE:

1. This register is valid only when the INVC03 bit in the INVC0 register is set to "1"(Three-phase motor

control timer output enabled). Write to this register after setting the TPRC0 bit in the TPRC register to

"1" (write enable).

2b1b0

ree-p

ase protect contro

ster

Symbol Address When Reset

TPRC 025A16 0016

RWBit Name FunctionBit Symbol

TPRC0

Three-phase

protect control bit

(b7-b1) Nothing is assigned. When write, set to "0". When read,

the contents are "0".

Enable write to PFCR register

0: Write protected

1: Write enabled

2b1b0

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13. Serial I/O

Note

UART0 is not available in the 42-pin package.

Serial I/O is configured with three channels: UART0 to UART2.

13.1. UARTi (i=0 to 2)

UARTi each have an exclusive timer to generate a transfer clock, so they operate independently of each

other.

Figure 13.1.1 shows the block diagram of UARTi. Figures 13.1.2 and 13.1.3 shows the block diagram of

the UARTi transmit/receive.

UARTi has the following modes:

• Clock synchronous serial I/O mode

• Clock asynchronous serial I/O mode (UART mode).

•

Special mode 1 (I2C bus mode)

: UART2

•

Special mode 2

: UART2

•

Special mode 3 (Bus collision detection function, IEBus mode)

: UART2

•

Special mode 4 (SIM mode)

: UART2

Figures 13.1.4 to 13.1.9 show the UARTi-related registers.

Refer to tables listing each mode for register setting.

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Clock synchronous type

(when internal clock is selected)

Clock synchronous type

(when external clock is selected)

Clock source selection

Internal

External

CTS/RTS disabled

CTS/RTS selected

RxD

1 / (n

+1)

1/16

1/2

U0BRG

CLK

CTS

/ RTS

1SIO or

2SIO

8SIO

32SIO

RTS

CTS

TxD

(UART0)

CLK1 to CLK0

CKDIR=0

CKDIR=1

CKPOL

CKDIR=0

CKDIR=1

CRS=1

CRS=0

CRD=0

CRD=1

RCSP=0

RCSP=1

CRD=0

CRD=1

UART reception

Clock synchronous

type

UART transmission

Clock synchronous

type

Clock synchronous type

(when internal clock is selected)

Receive

clock

Transmit

clock

Reception

control circuit

Transmission control

circuit

Transmit/

receive

unit

CLK

polarity

reversing

circuit CTS/RTS disabled

CTS

from UART1

UART reception

Clock synchronous

type

RxD

TxD

(UART1)

1 / (n

+1)

1/16

1/2

U1BRG

CLK

1SIO or

2SIO

8SIO

32SIO

CLK1 to CLK0

CKDIR=0

CKDIR=1

CKPOL

CKDIR=0

CKDIR=1

CRD=0

CRD=1

CLKMD0=0

CLKMD1=0 CRS=1

CRS=0

RCSP=0

RCSP=1

CLKMD0=1

CLKMD1=1

Clock source selection

Internal

External

UART transmission

Clock synchronous

type

Clock synchronous type

(when internal clock is selected)

Receive

clock

Transmit

clock

Reception

control circuit

Transmission

control circuit

Transmit/

receive

unit

Clock synchronous type

(when external clock is selected)

Clock synchronous type

(when internal clock is selected)

CLK

polarity

reversing

circuit

RTS1

CTS1

Clock output

pin select CTS/RTS disabled

CTS/RTS disabled

CTS/RTS selected

CTS

from UART0

CTS

/ RTS

CTS

/ CLKS

i = 0 to 2

: Values set to the UiBRG register

SMD2 to SMD0, CKDIR: Bits in the UiMR

CLK1 to CLK0, CKPOL, CRD, CRS: Bits in the UiC0 registers

CLKMD0, CLKMD1, RCSP: Bits in the UCON register

RxD

CLK

CTS

/ RTS

2RTS

CTS

TxD

(UART2)

1 / (n

+1)

1/16

1/2

U2BRG

1SIO or

2SIO

8SIO

32SIO

CLK1 to CLK0

CKDIR=0

CKDIR=1

CKPOL

CKDIR=0

CKDIR=1

CRS=1

CRS=0

CRD=0

CRD=1

Reception

control circuit

Transmission

control circuit

UART reception

Clock synchronous

type

UART transmission

Clock synchronous

type

Clock synchronous type

(when internal clock is selected)

Receive

clock

Transmit

clock

RxD polarity

reversing circuit

Internal

External

Clock source selection

TxD

polarity

reversing

circuit

Transmit/

receive

unit

Clock synchronous type

(when internal clock is selected)

Clock synchronous type

(when external clock is selected)

CLK

polarity

reversing

circuit

CTS/RTS disabled

CTS/RTS

selected

Main clock, PLL clock,

or on-chip oscillator clock

1/2

1/8

1/4

1SIO

2SIO

8SIO

32SIO

1SIO or

2SIO

PCLK1=1

PCLK1=0

SMD2 to SMD0

Figure 13.1.1. Block diagram of UARTi (i = 0 to 2)

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SP SP

PAR

2SP

1SP

UART

UART (7 bits)

UART (8 bits)

UART (7 bits)

UART (9 bits)

Clock

synchronous

type

Clock synchronous

type

TxDi

UARTi transmit register

PAR

enabled

PAR

disabled

D8D7D6D5D4D3D2D1D0

SP: Stop bit

PAR: Parity bit

UARTiÜtransmit

buffer register

MSB/LSB conversion circuit

UART (8 bits)

UART (9 bits)

Clock synchronous

type

UARTi receive

buffer register

UARTi receive register

2SP

1SP

STPS=0

PAR

enabled

PAR

disabled

UART

UART (7 bits)

UART (9 bits)

Clock

synchronous

type

Clock

synchronous type

UART (7 bits)

UART (8 bits)

RxDi

Clock

synchronous type

UART (8 bits)

UART (9 bits)

Address 03A6

Address 03A7

Address 03AE

Address 03AF

Address 03A2

Address 03A3

Address 03AA

Address 03AB

Data bus low-order bits

MSB/LSB conversion circuit

D7D6D5D4D3D2D1D0D8

0000000

SP SP

PAR

Data bus high-order bits

STPS=1

PRYE=0

PRYE=1

STPS=0

STPS=1

PRYE=0

PRYE=1

SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR : Bit in the UiMR register

000

111

SMD2 to SMD0

Figure 13.1.2. Block diagram of UARTi (i = 0, 1) transmit/receive unit

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SP SP

PAR

2SP

1SP

UART

(7 bits)

UART

(8 bits)

UART(7 bits)

UART

(9 bits)

Clock

synchronous

type

Clock

synchronous type

Data bus low-order bits

TxD2

UARTi transmit register

PAR

disabled

PAR

enabled

0UART2transmit

buffer register

UART

(8 bits)

UART

(9 bits)

Clock

synchronous type

UART2 receive

buffer register

UARTi receive register

2SP

1SP UART

(7 bits)

UART

(8 bits)

UART(7 bits)

UART

(9 bits)

Clock

synchronous type

Clock

synchronous type

RxD2

UART

(8 bits)

UART

(9 bits)

Address 037E

Address 037F

Address 037A

Address 037B

Data bus high-order bits

0000000

SP SP

PAR

Reverse

No reverse

Error signal

output circuit

RxD data

reverse circuit

Error signal output

enable

Error signal output

disable

Reverse

No reverse

Logic reverse circuit + MSB/LSB conversion circuit

PAR

enabled

PAR

disabled

UART

Clock

synchronous

type

TxD data

reverse circuit

SP: Stop bit

PAR: Parity bit

STPS=0

STPS=1

PRYE=0

PRYE=1

STPS=0

STPS=1

PRYE=0

PRYE=1

IOPOL=0

IOPOL=1

IOPOL

U2ERE

SMD2 to SMD0, STPS, PRYE, IOPOL, CKDIR : Bit in the U2MR register

U2ERE : Bit in the U2C1 register

SMD2 to SMD0

Figure 13.1.3. Block diagram of UART2 transmit/receive unit

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Figure 13.1.4. U0TB to U2TB registers, U0RB to U2RB registers, U0BRG to U2BRG registers

(b15)

b7 b0

(b8) b7 b0

UARTi Transmit Buffer Register (i=0 to 2)(1)

Function

Transmit data

Nothing is assigned.

When write, set to "0". When read, its content is indeterminate.

Symbol Address After Reset

U0TB 03A3

-03A2

Indeterminate

U1TB 03AB

-03AA

Indeterminate

U2TB 037B

-037A

Indeterminate

NOTES:

1. Use MOV instruction to write to this register.

UARTi Baud Rate Generation Register (i=0 to 2)(1, 2, 3)

Symbol Address After Reset

U0BRG 03A1

Indeterminate

U1BRG 03A9

Indeterminate

U2BRG 0379

Indeterminate

Function

Assuming that set value = n, UiBRG divides the count source

by n + 1 00

to FF

Setting Range

NOTES:

1. Write to this register while serial I/O is neither transmitting nor receiving.

2. Use MOV instruction to write to this register.

The transfer clock is shown below when the setting value in the UiBRG register is set as n.

(1) When the CKDIR bit in the UiMR register to “0” (internal clock)

• Clock synchronous serial I/O mode : fj/(2(n+1))

• Clock asynchronous serial I/O (UART) mode : fj/(16(n+1))

(2) When the CKDIR bit in the UiMR register to “1” (external clock)

• Clock synchronous serial I/O mode : f

EXT

• Clock asynchronous serial I/O (UART) mode : f

EXT

/(16(n+1))

fj : f1SIO, f2SIO, f8SIO, f32SIO

EXT

: Input from CLKi pin

3. Set the UiBRG register after setting the CLK1 and CLK0 bits in the UiC0 registers.

NOTES:

1. When the SMD2 to SMD0 bits in the UiMR register are set to “000

” (serial I/O disabled) or the RE bit in the UiC1 register is set to “0” (reception

disabled), all of the SUM, PER, FER and OER bits are set to “0” (no error). The SUM bit is set to “0” (no error) when all of the PER, FER and OER

bits are set to “0” (no error). Also, the PER and FER bits are set to “0” by reading the lower byte of the UiRB register.

2. The ABT bit is set to “0” by setting to “0” by program. (Writing “1” has no effect.)

Nothing is assigned at the bit 11 in the U0RB and U1RB registers. When write, set to "0". When read, its content is "0".

(b15)

Symbol Address After Reset

U0RB 03A7

-03A6

Indeterminate

U1RB 03AF

-03AE

Indeterminate

U2RB 037F

-037E

Indeterminate

b7 b0

(b8) b7 b0

UARTi Receive Buffer Register (i=0 to 2)

Function

Bit Name

Bit

Symbol

0 : No framing error

1 : Framing error found

0 : No parity error

1 : Parity error found

0 : No error

1 : Error found

OER

FER

PER

SUM

Overrun error flag

(1)

Framing error flag

(1)

Parity error flag

(1)

Error sum flag

(1)

0 : No overrun error

1 : Overrun error found

Receive data (D

to D

)

ABT Arbitration lost detecting

flag

(2)

0 : Not detected

1 : Detected

(b7-b0)

(b10-b9)

Receive data (D

)

(b8)

Nothing is assigned.

When write, set to "0". When read, its content is indeterminate.

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UARTi transmit/receive mode register (i = 0, 1)

Symbol Address After reset

U0MR, U1MR 03A0

, 03A8

b7 b6 b5 b4 b3 b2 b1 b0

Bit name

Bit

symbol RW

CKDIR

SMD1

SMD0 Serial I/O mode select bit

(2)

SMD2

Internal/external clock

select bit

STPS

PRY

PRYE

(b7)

Parity enable bit

0 : Internal clock

1 : External clock (1)

Stop bit length select bit

Odd/even parity select bit

Reserve bit

0 : One stop bit

1 : Two stop bits

0 : Parity disabled

1 : Parity enabled

0 0 0 : Serial I/O disabled

0 0 1 : Clock synchronous serial I/O mode

1 0 0 : UART mode transfer data 7 bits long

1 0 1 : UART mode transfer data 8 bits long

1 1 0 : UART mode transfer data 9 bits long

Do not set value other than the above

b2 b1 b0

Effective when PRYE = 1

0 : Odd parity

1 : Even parity

Write to "0"

Function

UART2 transmit/receive mode register

Symbol Address After reset

U2MR 0378

b7 b6 b5 b4 b3 b2 b1 b0

Bit name

Bit

symbol RW

CKDIR

SMD1

SMD0 Serial I/O mode select bit

(2)

SMD2

Internal/external clock

select bit

STPS

PRY

PRYE

IOPOL

Parity enable bit

0 : Internal clock

1 : External clock (1)

Stop bit length select bit

Odd/even parity select bit

TxD, RxD I/O polarity

reverse bit

0 : One stop bit

1 : Two stop bits

0 : Parity disabled

1 : Parity enabled

0 0 0 : Serial I/O disabled

0 0 1 : Clock synchronous serial I/O mode

0 1 0 : I

C bus mode

1 0 0 : UART mode transfer data 7 bits long

1 0 1 : UART mode transfer data 8 bits long

1 1 0 : UART mode transfer data 9 bits long

Must not be set except above

b2 b1 b0

Effective when PRYE = 1

0 : Odd parity

1 : Even parity

0 : No reverse

1 : Reverse

Function

(3)

NOTES:

1. Set the corresponding port direction bit for each CLKi pin to “0” (input mode).

2. To receive data, set the corresponding port direction bit for each RxDi pin to “0” (input mode).

NOTES:

1. Set the corresponding port direction bit for each CLK2 pin to “0” (input mode).

2. To receive data, set the corresponding port direction bit for each RxD2 pin to “0” (input mode).

3. Set the corresponding port direction bit for SCL2 and SDA2 pins to “0” (input mode).

Figure 13.1.5. U0MR to U2MR registers

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Figure 13.1.6. U0C0 to U2C0 registers and UCON register

UARTi Transmit/receive Control Rregister 0 (i=0 to 2)

Symbol Address After Reset

U0C0 to U2C0 03A4

, 03AC

, 037C

00001000

b7 b6 b5 b4 b3 b2 b1 b0

Function

TXEPT

CLK1

CLK0

CRS

CRD

NCH

CKPOL

BRG count source

select bit

Transmit register empty

flag

0 : Transmit data is output at falling edge of transfer clock

and receive data is input at rising edge

1 : Transmit data is output at rising edge of transfer clock

and receive data is input at falling edge

CLK polarity select bit

CTS/RTS function

select bit

CTS/RTS disable bit

Data output select bit

(5)

0 0 : f

1SIO

or f

2SIO

is selected

0 1 : f

8SIO

is selected

1 0 : f

32SIO

is selected

1 1 : Do not set

b1 b0

0 : LSB first

1 : MSB first

0 : Data in transmit register (during transmission)

1 : No data in transmit register

(transmission completed)

0 : CTS/RTS function enabled

1 : CTS/RTS function disabled

(P6

, P6

and P7

can be used as I/O ports)

(6)

0 : TxDi/SDA2 and SCL2 pins are CMOS output

1 : TxDi/SDA2 and SCL2 pins are N-channel open-drain output

(4)

UFORM Transfer format select bit

(2)

Effective when CRD is set to "0"

0 : CTS function is selected

(1)

1 : RTS function is selected

Bit Name

Bit

Symbol

NOTES:

1. Set the corresponding port direction bit for each CTSi pin to “0” (input mode).

2. Effective when the SMD2 to SMD0 bits in the UMR register to "001

"(clock synchronous serial I/O mode) or "010

" (UART mode

transfer data 8 bits long). Set the UFORM bit to "1" when the SMD2 to SMD0 bits are set to "101

" (I

C bus mode) and "0" when

they are set to"100

" (UART mode transfer data 7 bits long) or "110

" ( UART mode transfer data 9 bits long).

3. CTS

/RTS

can be used when the CLKMD1 bit in the UCON register is set to “0” (only CLK

output) and the RCSP bit in the

UCON register is set to “0” (CTS

/RTS

not separated).

4. SDA2 and SCL2 are effective when i = 2.

5. When the SMD2 to SMD0 bits in UiMR regiser are set to “000

” (serial I/O disable), do not set NCH bit to “1” (TxDi/SDA2 and

SCL2 pins are N-channel open-drain output).

6. When the U1MAP bit in PACR register is “1” (P7

to P7

), CTS/RTS pin in UART1 is assigned to P7

7. When the CLK1 and CLK0 bit settings are changed, set the UiBRG register.

(3)

(7)

UART Transmit/receive Control Register 2

Symbol Address After Reset

UCON 03B0

X0000000

b7 b6 b5 b4 b3 b2 b1 b0

Bit NameBit Symbol RWFunction

CLKMD0

CLKMD1

UART0 transmit interrupt

cause select bit

UART0 continuous

receive mode enable bit 0: Continuous receive mode disabled

1: Continuous receive mode enable

UART1 continuous

receive mode enable bit

UART1 CLK/CLKS

select bit 0

UART1 transmit interrupt

cause select bit

0: Transmit buffer empty (Tl = 1)

1: Transmission completed (TXEPT = 1)

0: Transmit buffer empty (Tl = 1)

1: Transmission completed (TXEPT = 1)

0: Continuous receive mode disabled

1: Continuous receive mode enabled

Nothing is assigned. When write, set to “0”.

When read, the content is indeterminate

U0IRS

U1IRS

U0RRM

U1RRM

UART1 CLK/CLKS

select bit 1

(1)

Effective when CLKMD1 bit is set to “1”

0: Clock output from CLK1

1: Clock output from CLKS1

RCSP Separate UART0

CTS/RTS bit

(b7)

NOTES:

1. To use more than one transfer clock output pins, set the CKDIR bit in the U1MR register to “0” (internal clock).

2. When the U1MAP bit in PACR register is set to “1” (P7

to P7

), CTS

is supplied from the P7

pin.

0: Output from CLK1 only

1: Transfer clock output from multiple

pins function selected

0: CTS/RTS shared pin

1: CTS/RTS separated (CTS

supplied

from the P6

pin)

(2)

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Figure 13.1.7. U0C1 to U2C1 registers, PACR register

Pin Assignment Control Register

(1)

Symbpl Address After Reset

PACR 025D16 0016

Bit Name FunctionBit Symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

Pin enabling bit

Nothing is assigned.

When write,

set to “0”. When read, its

content is “0”.

(b6-b3)

001 : 42 pin

100 : 48 pin

All other values are reserved. Do

not use.

PACR0

PACR1

PACR2

Reserved bits

U1MAP UART1 pin remapping bit UART1 pins assigned to

0 : P67 to P64

1 : P73 to P70

NOTES:

1. Set the PACR register by the next instruction after setting the PRC2 bit in the PRCR register to "1"(write

enable).

UARTi Transmit/receive Control Register 1 (i=0, 1)

Symbol Address After Reset

U0C1, U1C1 03A5

,03AD

00000010

b7 b6 b5 b4 b3 b2 b1 b0

Bit Name

Bit

Symbol RW

Function

Transmit enable bit

Receive enable bit

Receive complete flag

Transmit buffer

empty flag

0 : Transmission disabled

1 : Transmission enabled

0 : Data in UiTB register

1 : No data in UiTB register

0 : Reception disabled

1 : Reception enabled

0 : No data in UiRB register

1 : Data in UiRB register

Nothing is assigned.

When write, set “0”. When read, the contents are “0”.

UART2 Transmit/receive Control Register 1

Symbol Address After Reset

U2C1 037D

00000010

b7 b6 b5 b4 b3 b2 b1 b0

Bit Name

Bit

Symbol Function

Transmit enable bit

Receive enable bit

Receive complete flag

Transmit buffer

empty flag

0 : Transmission disabled

1 : Transmission enabled

0 : Reception disabled

1 : Reception enabled

U2IRS UART2 transmit interrupt

cause select bit 0 : Transmit buffer empty (TI = 1)

1 : Transmit is completed (TXEPT = 1)

U2RRM UART2 continuous

receive mode enable bit 0 : Continuous receive mode disabled

1 : Continuous receive mode enabled

Data logic select bit 0 : No reverse

1 : Reverse

U2LCH

U2ERE Error signal output

enable bit 0 : Output disabled

1 : Output enabled

(b7-b4)

0 : Data in U2TB register

1 : No data in U2TB register

0 : No data in U2RB register

1 : Data in U2RB register

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Figure 13.1.8. U2SMR register and U2SMR2 register

UART2 Special Mode Register

Symbol Address After Reset

U2SMR 037716 X00000002

b7 b6 b5 b4 b3 b2 b1 b0

Bit Name

Bit

Symbol Function

ABSCS

ACSE

SSS

I2C bus mode select bit

Bus busy flag 0 : STOP condition detected

1 : START condition detected (busy)

Bus collision detect

sampling clock select bit

Arbitration lost detecting

flag control bit

0 : Other than I2C bus mode

1 : I2C bus mode

0 : Update per bit

1 :

Update per byte

IICM

ABC

BBS

0 : Not synchronized to RXDi

1 : Synchronized to RXDi (2)

Set to “0”

Transmit start condition

select bit

0 : Rising edge of transfer clock

1 : Underflow signal of timer A0

Auto clear function

select bit of transmit

enable bit

0 : No auto clear function

1 : Auto clear at occurrence of bus collision

NOTES:

1: The BBS bit is set to “0” by writing “0" by program. (Writing “1” has no effect).

2: When a transfer begins, the SSS bit is set to “0” (Not synchronized to RXDi).

(1)

Nothing is assigned. When write, set “0”.

When read, its content is indeterminate.

(b7)

(b3) Reserved bit

UART2 Special Mode Register 2

Symbol Address After Reset

U2SMR2 0376

X0000000

b7 b6 b5 b4 b3 b2 b1 b0

Bit Name

Bit

Symbol RWFunction

STAC

SWC2

SDHI

I C bus mode select bit 2

SCL

wait output bit 0 : Disabled

1 : Enabled

SDA

output stop bit

UART initialization bit

Clock-synchronous bit

Refer to Table 13.12

0 : Disabled

1 : Enabled

IICM2

CSC

SWC

ALS 0 : Disabled

1 : Enabled

SDA

output disable bit

SCL

wait output bit 2

0: Enabled

1: Disabled (high impedance)

0 : Disabled

1 : Enabled

0: Transfer clock

1: “L” output

Nothing is assigned. When write, set “0”.

When read, its content is indeterminate.

(b7)

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UART2 special mode register 3

Symbol Address After reset

U2SMR3 0375

000X0X0X

b7 b6 b5 b4 b3 b2 b1 b0

Bit name

Bit

symbol Function

DL2

SDA digital delay

setup bit

(1, 2)

DL0

DL1

0 0 0 : Without delay

0 0 1 : 1 to 2 cycle(s) of UiBRG count source

0 1 0 : 2 to 3 cycles of UiBRG count source

0 1 1 : 3 to 4 cycles of UiBRG count source

1 0 0 : 4 to 5 cycles of UiBRG count source

1 0 1 : 5 to 6 cycles of UiBRG count source

1 1 0 : 6 to 7 cycles of UiBRG count source

1 1 1 : 7 to 8 cycles of UiBRG count source

Nothing is assigned.

When write, set “0”. When read, its content is indeterminate.

b7 b6 b5

0 : Without clock delay

1 : With clock delay

Clock phase set bit

0 : CLKi is CMOS output

1 : CLKi is N-channel open drain output

Clock output select bit

CKPH

NODC

(b0)

Nothing is assigned.

When write, set “0”. When read, its content is indeterminate.

Nothing is assigned.

When write, set “0”. When read, its content is indeterminate.

(b2)

(b4)

NOTES:

1. The DL2 to DL0 bits are used to generate a delay in SDA2 output by digital means during I

C bus mode. In other than

C bus mode, set these bits to “000

” (no delay).

2. The amount of delay varies with the load on SCL2 and SDA2 pins. Also, when using an external clock, the amount of

delay increases by about 100 ns.

Figure 13.1.9. U2SMR3 register and U2SMR4 register

UART2 Special Mode Register 4

Symbol Address After Reset

U2SMR4 037416 0016

b7 b6 b5 b4 b3 b2 b1 b0

Bit NameBit Symbol RW

Function

ACKC

SCLHI

SWC9

ACK data bit

STAREQ

RSTAREQ

STPREQ

ACKD

0: Disabled

1: Enabled

0: ACK

1: NACK

0: Serial I/O data output

1: ACK data output

NOTE:

1. Set to “0” when each condition is generated.

STSPSEL

SCL2 wait bit 3

Start condition

generate bit (1)

Restart condition

generate bit (1)

Stop condition

ACK data output

SCL2 output stop

SCL2, SDA2 output

0: Clear

1: Start

0: Clear

1: Start

0: Clear

1: Start

0: Start and stop conditions not output

1: Start and stop conditions output

0: SCL2 “L” hold disabled

1: SCL2 “L” hold enabled

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13.1.1. Clock Synchronous serial I/O Mode

The clock synchronous serial I/O mode uses a transfer clock to transmit and receive data. Table 13.1.1.1

lists the specifications of the clock synchronous serial I/O mode. Table 13.1.1.2 lists the registers used in

clock synchronous serial I/O mode and the register values set.

Table 13.1.1.1. Clock Synchronous Serial I/O Mode Specifications

Item Specification

Transfer data format • Transfer data length: 8 bits

Transfer clock • The CKDIR bit in the UiMR(i=0 to 2) register is set to “0” (internal clock) : fj/ (2(n+1))

fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16

• The CKDIR bit is set to “1” (external clock ) : Input from CLKi pin

Transmission, reception control

_______ _______ _______ _______

• Selectable from CTS function, RTS function or CTS/RTS function disable

Transmission start condition

• Before transmission can start, the following requirements must be met (1)

_ The TE bit in the UiC1 register is set to "1" (transmission enabled)

_ The TI bit in the UiC1 register is set to "0" (data present in UiTB register)

_______ _______

_ If CTS function is selected, input on the CTSi pin is “L”

Reception start condition • Before reception can start, the following requirements must be met (1)

_ The RE bit in the UiC1 register is set to "1" (reception enabled)

_ The TE bit in the UiC1 register is set to "1" (transmission enabled)

_ The TI bit in the UiC1 register is set to "0" (data present in the UiTB register)

•For transmission, one of the following conditions can be selected

_ The UiIRS bit (3) is set to "0" (transmit buffer empty): when transferring data

from the UiTB register to the UARTi transmit register (at start of transmission)

_ The UiIRS bit is set to "1" (transfer completed): when the serial I/O finished sending

data from the UARTi transmit register

• For reception

When transferring data from the UARTi receive register to the UiRB register (at

completion of reception)

Error detection • Overrun error (2)

This error occurs if the serial I/O started receiving the next data before reading the

UiRB register and received the 7th bit of the next data

Select function • CLK polarity selection

Transfer data input/output can be chosen to occur synchronously with the rising or

the falling edge of the transfer clock

• LSB first, MSB first selection

Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7

can be selected

• Continuous receive mode selection

Reception is enabled immediately by reading the UiRB register

• Switching serial data logic (UART2)

This function reverses the logic value of the transmit/receive data

• Transfer clock output from multiple pins selection (UART1)

The output pin can be selected in a program from two UART1 transfer clock pins that

have been set

_______ _______

• Separate CTS/RTS pins (UART0)

_________ _________

CTS0 and RTS0 are input/output from separate pins

• UART1 pin remapping selection

The UART1 pin can be selected from the P67 to P64 or P73 to P70.

NOTES:

1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0 register “0”

(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the

external clock is in the high state; if the CKPOL bit in the UiC0 register “1” (transmit data output at the rising edge

and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.

2. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains

unchanged.

3. The U0IRS and U1IRS bits respectively are the UCON register bits 0 and 1; the U2IRS bit is the U2C1 register bit 4.

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Table 13.1.1. 2. Registers to Be Used and Settings in Clock Synchronous Serial I/O Mode

UiTB(3) 0 to 7 Set transmission data

UiRB(3) 0 to 7 Reception data can be read

OER Overrun error flag

UiBRG 0 to 7 Set a transfer rate

UiMR(3) SMD2 to SMD0 Set to “0012”

CKDIR Select the internal clock or external clock

IOPOL(i=2)(4) Set to “0”

UiC0 CLK1 to CLK0 Select the count source for the UiBRG register

CRS _______ _______

Select CTS or RTS to use

TXEPT Transmit register empty flag

CRD _______ _______

Enable or disable the CTS or RTS function

NCH Select TxDi pin output mode

CKPOL Select the transfer clock polarity

UFORM Select the LSB first or MSB first

UiC1 TE Set this bit to “1” to enable transmission/reception

TI Transmit buffer empty flag

RE Set this bit to “1” to enable reception

RI Reception complete flag

U2IRS (1) Select the source of UART2 transmit interrupt

U2RRM (1) Set this bit to “1” to use UART2 continuous receive mode

U2LCH(3) Set this bit to “1” to use UART2 inverted data logic

U2ERE(3) Set to “0”

U2SMR 0 to 7 Set to “0”

U2SMR2 0 to 7 Set to “0”

U2SMR3 0 to 2 Set to “0”

NODC Select clock output mode

4 to 7 Set to “0”

U2SMR4 0 to 7 Set to “0”

UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt

U0RRM, U1RRM Set this bit to “1” to use continuous receive mode

CLKMD0 Select the transfer clock output pin when CLKMD1 = 1

CLKMD1 Set this bit to “1” to output UART1 transfer clock from two pins

RCSP

_________

Set this bit to “1” to accept as input the UART0 CTS

signal from the P6

pin or P7

7 Set to “0”

NOTES:

1. Set bit 4 and bit 5 in the U0C1 and U1C1 register are set to “0”. The U0IRS, U1IRS, U0RRM and U1RRM

bits are in the UCON register.

2. Not all register bits are described above. Set those bits to “0” when writing to the registers in clock synchro-

nous serial I/O mode.

3. Set the bit 6 and bit 7 in the U0C1 and U1C1 register to "0".

4. Set the bit 7 in the U0MR and U1MR register to "0".

i=0 to 2

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Table 13.1.1.3 lists the functions of the input/output pins during clock synchronous serial I/O mode. Table

13.3 shows pin functions for the case where the multiple transfer clock output pin select function is dese-

lected. Table 13.1.1.4 lists the P64 pin functions during clock synchronous serial I/O mode.

Note that for a period from when the UARTi operation mode is selected to when transfer starts, the TxDi

pin outputs an “H”. (If the N-channel open-drain output is selected, this pin is in a high-impedance state.)

Table 13.1.1.3. Pin Functions(1)

(When Not Select Multiple Transfer Clock Output Pin Function)

Pin name Function Method of selection

TxDi (i = 0 to 2)

(P63, P67, P70)Serial data output

Serial data input

Transfer clock output

Transfer clock input

I/O port

(Outputs dummy data when performing reception only)

RxDi

(P62, P66, P71)

CLKi

(P61, P65, P72)Set the CKDIR bit in the UiMR register to "0"

Set the CKDIR bit in the UiMR register to "1"

Set the PD6_1 bit and PD6_5 bit in the PD6 register, and the PD7_2 bit in the

PD7 register to "0"

Set the PD6_2 bit and PD6_6 bit in the PD6 register, and PD7_1 bit in the PD7

Set the CRD bit in the UiC0 register to "0"

Set the CRS bit in the UiC0 register to "0"

Set the PD6_0 bit and PD6_4 bit in the PD6 register’ is set to "0", the PD7_3

bit in the PD7 register to "0"

Set the CRD bit in the UiC0 register to "0"

Set the CRS bit in the UiC0 register to "1"

Set the CRD bit in the UiC0 register to "1"

CTS input

RTS output

CTSi/RTSi

(P60, P64, P73)

NOTE:

1. When the U1MAP bit in PACR register is “1” (P73 to P70), UART1 pin is assgined to P73 to P70.

Pin function Bit set value

U1C0 register UCON register PD6 register

CRD CRS RCSP CLKMD1 CLKMD0 PD6_4

P641 0 0 Input: 0, Output: 1

CTS1000 0

RTS111

CTS0

(2)

CLKS1

00 1

(3)

NOTES:

1. When the U1MAP bit in PACR register is “1” (P73 to P70), this table lists the P70 functions.

2. In addition to this, set the CRD bit in the U0C0 register to “0” (CT00/RT00 enabled) and the CRS bit in the

U0C0 register to “1” (RTS0 selected).

3. When the CLKMD1 bit is set to "1" and the CLKMD0 bit is set to "0", the following logiclevels are output:

• High if the CLKPOL bit in the U1C0 register is set to "0"

• Low if the CLKPOL bit in the U1C0 register is set to "1"

Table 13.1.1.4. P64 Pin Functions(1)

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Figure 13.1.1.1. Typical transmit/receive timings in clock synchronous serial I/O mode

D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7D0D1D2D3D4D5D6D7

CLK

Stopped pulsing because the TE bit = “0”

Write data to the UiTB register

Tc = T

CLK

= 2(n + 1) / fj

fj: frequency of UiBRG count source (f

1SIO

, f

2SIO

, f

8SIO

, f

32SIO

)

n: value set to UiBRG register

i: 0 to 2

Transfer clock

UiC1 register

TE bit

UiC1 register

TI bit

CLKi

TxDi

“H”

“L”

“0”

“1”

“0”

“1”

“0”

“1”

CTSi

“0”

“1”

Stopped pulsing because CTSi = “H”

1 / fEXT

Write dummy data to UiTB register

UiC1 register

TE bit

UiC1 register

TI bit

CLKi

RxDi

UiC1 register

RI bit

RTSi

“H”

“L”

“0”

“1”

“0”

“1”

“0”

“1”

UiC1 register

RE bit

“0”

“1”

Receive data is taken in

Transferred from UiTB register to UARTi transmit register

Read out from UiRB register

EXT

: frequency of external clock

Transferred from UARTi receive register

to UiRB register

SiRIC register

IR bit

“0”

“1”

D0D1D2D3D4D5D6D7D0D1D2D3D4D5

Transferred from UiTB register to UARTi transmit register

Make sure the following conditions are met when input

to the CLKi pin before receiving data is high:

• UiC0 register TE bit is set to "1" (transmit enabled)

• UiC0 register RE bit is set to "1" (Receive enabled)

• Write dummy data to the UiTB register

The above timing diagram applies to the case where the register bits are set as follows:

• The CKDIR bit in the UiMR register is set to "0" (internal clock)

• The CRD bit in the UiC0 register is set to "0" (CTS/RTS enabled); CRS bit is set to "0" (CTS selected)

• The CKPOL bit in the UiC0 register is set to "0" (transmit data output at the falling edge and receive data taken in at the rising edge of the

transfer clock)

• The UiIRS bit is set to "0" (an interrupt request occurs when the transmit buffer becomes empty): U0IRS bit is the bit 0 in the UCON register

U1IRS bit is the bit 1 in the UCON register, and U2IRS bit is the bit 4 in the U2C1 register.

Cleared to “0” when interrupt request is

accepted, or cleared to “0” by program

Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program

The above timing diagram applies to the case where the register bits are set

as follows:

• The CKDIR bit in the UiMR register is set to "1" (external clock)

• The CRD bit in the UiC0 register is set to "0"(CTS/RTS enabled);

The CRS bit is set to "1" (RTS selected)

• UiC0 register CKPOL bit is set to "0"(transmit data output at the falling edge and

receive data taken in at the rising edge of the transfer clock)

UiC0 register

TXEPT bit

SiTIC register

IR bit

Even if the reception is completed, the RTS

does not change. The RTS becomes “L”

when the RI bit changes to “0” from “1”.

(1) Example of Transmit Timing (Internal clock is selected)

(2) Example of Receive Timing (External clock is selected)

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13.1.1.1 Counter Measure for Communication Error Occurs

If a communication error occurs while transmitting or receiving in clock synchronous serial I/O mode,

follow the procedures below.

•Resetting the UiRB register (i=0 to 2)

(1) Set the RE bit in the UiC1 register to “0” (reception disabled)

(2) Set the SMD2 to SMD0 bits in the UiMR register to “0002” (Serial I/O disabled)

(3) Set the SMD2 to SMD0 bits in the UiMR register to “0012” (Clock synchronous serial I/O mode)

(4) Set the RE bit in the UiC1 register to “1” (reception enabled)

•Resetting the UiTB register (i=0 to 2)

(1) Set the SMD2 to SMD0 bits in the UiMR register to “0002” (Serial I/O disabled)

(2) Set the SMD2 to SMD0 bits in the UiMR register to “0012” (Clock synchronous serial I/O mode)

(3) “1” is written to RE bit in the UiC1 register (reception enabled), regardless to the TE bit in the UiC1

13.1.1.2 CLK Polarity Select Function

Use the CKPOL bit in the UiC0 register (i = 0 to 2) to select the transfer clock polarity. Figure 13.1.1.2.1

shows the polarity of the transfer clock.

Figure 13.1.1.2.1. Polarity of transfer clock

(2) When the CKPOL bit in the UiC0 register is set to "1" (transmit data output at the rising

edge and the receive data taken in at the falling edge of the transfer clock)

CLK

(1) When the CKPOL bit in the UiC0 register is set to "0" (transmit data output at the falling

edge and the receive data taken in at the rising edge of the transfer clock)

CLK

i = 0 to 2

(2)

(3)

NOTES:

1. This applies to the case where the UFORM bit in the UiC0 register is set to "0" (LSB first) and the

UiLCH bit in the UiC1 register is set to "0" (no reverse).

2. When not transferring, the CLKi pin outputs a high signal.

3. When not transferring, the CLKi pin outputs a low signal.

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13.1.1.3 LSB First/MSB First Select Function

Use the UFORM bit in the UiC0 register (i = 0 to 2) to select the transfer format. Figure 13.1.1.3.1

shows the transfer format.

Figure 13.1.1.3.1 Transfer format

13.1.1.4 Continuous receive mode

When the UiRRM bit (i = 0 to 2) is set to "1" (continuous receive mode), the TI bit in the UiC1 register

is set to “0” (data present in the UiTB register) by reading the UiRB register. In this case, i.e., UiRRM

bit is set to "1", do not write dummy data to the UiTB register in a program. The U0RRM and U1RRM

bits are the bit 2 and bit 3 in the UCON register, respectively, and the U2RRM bit is the bit 5 in the

U2C1 register.

(1) When the UFORM bit in the UiC0 register "0" (LSB first)

CLK

(2) When the UFORM bit in the UiC0 register is set to "1" (MSB first)

CLK

NOTE:

1. This applies to the case where the CKPOL bit in the UiC0 register is set to "0" (transmit

data output at the falling edge and the receive data taken in at the rising edge of the

transfer clock) and the UiLCH bit in the UiC1 register "0" (no reverse).

i = 0 to 2

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Figure 13.1.1.4.1. Serial data logic switch timing

D0 D1 D2 D3 D4 D5 D6 D7

Transfer clock

TxD2

(no reverse)

“H”

“L”

“H”

“L”

TxD2

(reverse) D0 D1 D2 D3 D4 D5 D6 D7

“H”

“L”

(1) When the U2LCH bit in the U2C1 register is set to "0" (no reverse)

Transfer clock “H”

“L”

(2) When the U2LCH bit in the U2C1 register is set to "1" (reverse)

NOTE:

1. This applies to the case where the CKPOL bit in the U2C0 register is set to "0"

(transmit data output at the falling edge and the receive data taken in at the rising

edge of the transfer clock) and the UFORM bit is set to "0" (LSB first).

13.1.1.6 Transfer clock output from multiple pins function (UART1)

The CLKMD1 to CLKMD0 bits in the UCON register can choose one from two transfer clock output

pins. (See Figure 13.1.1.6.1) This function is valid when the internal clock is selected for UART1.

Figure 13.1.1.6.1 Transfer Clock Output From Multiple Pins

13.1.1.5 Serial data logic switch function (UART2)

When the U2LCH bit in the U2C1 register is set to "1" (reverse), the data written to the U2TB register

has its logic reversed before being transmitted. Similarly, the received data has its logic reversed

when read from the U2RB register. Figure 13.1.1.4.1 shows serial data logic.

Microcomputer

TXD1 (P67)

CLKS1 (P64)

CLK1 (P65)IN

CLK

Transfer enabled

when the CLKMD0

bit in the UCON

Transfer enabled

when the CLKMD0

bit in the UCON

NOTES:

1. This applies to the case where the CKDIR bit in the U1MRregister is set to "0" (internal clock) and

the CLKMD1 bit in the UCON register is set to "1" (transfer clock output from multiple pins).

2. This applies to the case where U1MAP bit in PACR register is set to “0” (P67 to P64).

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_______ _______

13.1.1.7 CTS/RTS separate function (UART0)

_______ _______ _______ _______

This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0

from the P64 pin. To use this function, set the register bits as shown below.

_______ _______

• The CRD bit in the U0C0 register is set to "0" (enables UART0 CTS/RTS)

_______

• The CRS bit in the U0C0 register is set to "1" (outputs UART0 RTS)

_______ _______

• The CRD bit in the U1C0 register is set to "0" (enables UART1 CTS/RTS)

_______

• The CRS bit in the U1C0 register is set to "0" (inputs UART1 CTS)

_______

• The RCSP bit in the UCON register is set to "1" (inputs CTS0 from the P64 pin)

• The CLKMD1 bit in the UCON register is set to "0" (CLKS1 not used)

_______ _______ _______ _______

Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be

used.

Figure 13.1.1.7.1. CTS/RTS separate function usage

Microcomputer

(P6

)

(P6

)IN

OUT

CTS

RTS

CTS

(P6

)

RTS

(P6

)

CLK

(P6

)CLK

NOTE:

1. This applies to the case where U1MAP bit in PACR register is set to “0” (P67 to P64).

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Item Specification

Transfer data format • Character bit (transfer data): Selectable from 7, 8 or 9 bits

• Start bit: 1 bit

• Parity bit: Selectable from odd, even, or none

• Stop bit: Selectable from 1 or 2 bits

Transfer clock • The CKDIR bit in the UiMR(i=0 to 2) register is set to "0" (internal clock) : fj/(16(n+1))

fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of UiBRG register 0016 to FF16

• CKDIR bit is set to “1” (external clock ) : fEXT/(16(n+1))

fEXT: Input from CLKi pin. n :Setting value of UiBRG register 0016 to FF16

Transmission, reception control

_______ _______ _______ _______

• Selectable from CTS function, RTS function or CTS/RTS function disable

Transmission start condition • Before transmission can start, the following requirements must be met

_ The TE bit in the UiC1 register is set to "1" (transmission enabled)

_ The TI bit in the UiC1 register "0" (data present in UiTB register)

_______ _______

_ If CTS function is selected, input “L” to the CTSi pin

Reception start condition • Before reception can start, the following requirements must be met

_ The RE bit in the UiC1 register is set to "1" (reception enabled)

_ Start bit detection

•For transmission, one of the following conditions can be selected

_ The UiIRS bit (2) is set to "0" (transmit buffer empty): when transferring data from the

UiTB register to the UARTi transmit register (at start of transmission)

_ The UiIRS bit is set to "1" (transfer completed): when the serial I/O finished sending

data from the UARTi transmit register

• For reception

When transferring data from the UARTi receive register to the UiRB register (at

completion of reception)

Error detection • Overrun error (1)

This error occurs if the serial I/O started receiving the next data before reading the

UiRB register and received the bit one before the last stop bit of the next data

• Framing error

This error occurs when the number of stop bits set is not detected

• Parity error

This error occurs when if parity is enabled, the number of 1’s in parity and

character bits does not match the number of 1’s set

• Error sum flag

This flag is set (= 1) when any of the overrun, framing, and parity errors is encountered

Select function • LSB first, MSB first selection

Whether to start sending/receiving data beginning with bit 0 or beginning with bit 7

can be selected

• Serial data logic switch (UART2)

This function reverses the logic of the transmit/receive data. The start and stop bits

are not reversed.

• TXD, RXD I/O polarity switch (UART2)

This function reverses the polarities of hte TXD pin output and RXD pin input. The

logic levels of all I/O data is reversed.

_______ _______

• Separate CTS/RTS pins (UART0)

_________ _________

CTS0 and RTS0 are input/output from separate pins

•UART1 pin remapping selection

The UART1 pin can be selected from the P67 to P64 or P73 to P70.

13.1.2. Clock Asynchronous Serial I/O (UART) Mode

The UART mode allows transmitting and receiving data after setting the desired transfer rate and transfer

data format. Tables 13.1.2.1 lists the specifications of the UART mode.

Interrupt request

generation timing

Table 13.1.2.1. UART Mode Specifications

NOTES:

1. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains

unchanged.

2. The U0IRS and U1IRS bits respectively are the bits "0" and "1" in the UCON register; the U2IRS bit is the bit 4 in

the U2C1 register.

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Table 13.1.2.2. Registers to Be Used and Settings in UART Mode

UiTB 0 to 8 Set transmission data (1)

UiRB 0 to 8 Reception data can be read (1)

OER,FER,PER,SUM

Error flag

UiBRG 0 to 7 Set a transfer rate

UiMR SMD2 to SMD0 Set these bits to ‘1002’ when transfer data is 7 bits long

Set these bits to ‘1012’ when transfer data is 8 bits long

Set these bits to ‘1102’ when transfer data is 9 bits long

CKDIR Select the internal clock or external clock

STPS Select the stop bit

PRY, PRYE Select whether parity is included and whether odd or even

IOPOL(i=2)(4) Select the TxD/RxD input/output polarity

UiC0 CLK0, CLK1 Select the count source for the UiBRG register

CRS _______ _______

Select CTS or RTS to use

TXEPT Transmit register empty flag

CRD _______ _______

Enable or disable the CTS or RTS function

NCH Select TxDi pin output mode

CKPOL Set to “0”

UFORM LSB first or MSB first can be selected when transfer data is 8 bits long. Set this

bit to “0” when transfer data is 7 or 9 bits long.

UiC1 TE Set this bit to “1” to enable transmission

TI Transmit buffer empty flag

RE Set this bit to “1” to enable reception

RI Reception complete flag

U2IRS (2) Select the source of UART2 transmit interrupt

U2RRM (2) Set to “0”

U2LCH (3) Set this bit to “1” to use UART2 inverted data logic

U2ERE (3) Set to “0”

U2SMR 0 to 7 Set to “0”

U2SMR2 0 to 7 Set to “0”

U2SMR3 0 to 7 Set to “0”

U2SMR4 0 to 7 Set to “0”

UCON U0IRS, U1IRS Select the source of UART0/UART1 transmit interrupt

U0RRM, U1RRM Set to “0”

CLKMD0 Invalid because CLKMD1 = 0

CLKMD1 Set to “0”

RCSP

_________

Set this bit to “1” to accept as input the UART0 CTS

signal from the P6

pin or P7

7 Set to “0”

NOTES:

1. The bits used for transmit/receive data are as follows: Bit 0 to bit 6 when transfer data is 7 bits long; bit 0 to

bit 7 when transfer data is 8 bits long; bit 0 to bit 8 when transfer data is 9 bits long.

2. Set the bit 4 to bit 5 in the U0C1 and U1C1 registers to “0”. The U0IRS, U1IRS, U0RRM and U1RRM bits

are included in the UCON register.

3. Set the bit 6 to bit 7 in the U0C1 and U1C1 registers to “0”.

4. Set the bit 7 the U0MR and U1MR registers to “0”.

i=0 to 2

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Table 13.1.2.3 lists the functions of the input/output pins during UART mode. Table 13.1.2.4 lists the P64

pin functions during UART mode. Note that for a period from when the UARTi operation mode is selected

to when transfer starts, the TxDi pin outputs an “H”. (If the N-channel open-drain output is selected, this

pin is in a high-impedance state.)

Table 13.1.2.3. I/O Pin Functions in UART mode(1)

Pin name Function Method of selection

TxDi (i = 0 to 2)

(P63, P67, P70)Serial data output

Serial data input

Input/output port

Transfer clock input

Input/output port

(Outputs "H" when performing reception only)

RxDi

(P62, P66, P71)

CLKi

(P61, P65, P72)Set the CKDIR bit in the UiMR register to "0"

Set the CKDIR bit in the UiMR register to "1"

Set the PD6_1 bit and PD6_5 bit in the PD6 register to "0", PD7_2 bit in the PD7

PD6_2 bit, PD6_6 bit in the PD6 register and the PD7_1 bit in the PD7 register

(Can be used as an input port when performing transmission only)

Set the CRD bit in the UiC0 register to "0"

Set the CRS bit in the UiC0 register to "0"

Set the PD6_0 bit and PD6_4 bit in the PD6 register to "0", the PD7_3 bit in the

PD7 register "0"

Set the CRD bit in the UiC0 register to "0"

Set the CRS bit in the UiC0 register to "1"

Set the CRD bit in the UiC0 register "1"

CTS input

RTS output

CTSi/RTSi

(P60, P64, P73)

NOTE:

1. When the U1MAP bit in PACR register is set to “1” (P73 to P70), UART1 pin is assgined to P73 to P70.

Table 13.1.2.4. P64 Pin Functions in UART mode(1)

Pin function Bit set value

U1C0 register UCON register PD6 register

CRD CRS RCSP CLKMD1 PD6_4

P641 0 0 Input: 0, Output: 1

CTS10000

RTS110 0

CTS0 (2) 0

00 10

NOTES:

1. When the U1MAP bit in PACR register is “1” (P73 to P70), this table lists the P70 functions.

2. In addition to this, set the CRD bit in the U0C0 register to “0” (CTS0/RTS0 enabled) and the CRS bit in the U0C0

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Figure 13.1.2.1. Typical transmit timing in UART mode (UART0, UART1)

Start

bit Parity

bit

TxDi

CTSi

“1”

“0”

“1”

“L”

“H”

“0”

“1”

Tc = 16 (n + 1) / fj or 16 (n + 1) / f

EXT

fj : frequency of UiBRG count source (f

1SIO

, f

2SIO

, f

8SIO

, f

32SIO

)

EXT

: frequency of UiBRG count source (external clock)

n : value set to UiBRG

i: 0 to 2

“0”

“1”

TxDi

“0”

“1”

“0”

“1”

“0”

“1”

Transfer clock

“0”

“1”

Transfer clock

D0D1D2D3D4D5D6D7

ST PD0D1D2D3D4D5D6D7SP ST PSP D0D1

Stop

bit

Start

bit

The transfer clock stops momentarily as CTSi is “H” when the stop bit is checked.

The transfer clock starts as the transfer starts immediately CTSi changes to “L”.

D0D1D2D3D4D5D6D7

ST SP

D8D0D1D2D3D4D5D6D7

ST D8D0D1

SPSP

Stop

bit Stop

bit

“0”

Stopped pulsing

because the TE bit

= “0”

Write data to the UiTB register

UiC1 register

TE bit

UiC1 register

TI bit

UiC0 register

TXEPT bit

SiTIC register

IR bit

Transferred from UiTB register to UARTi transmit register

The above timing diagram applies to the case where the register bits are set

as follows:

• Set the PRYE bit in the UiMR register to "1" (parity enabled)

• Set the STPS bit in the UiMR register to "0" (1 stop bit)

• Set the CRD bit in the UiC0 register to "0" (CTS/RTS enabled),

the CRS bit to "0" (CTS selected)

• Set the UiIRS bit to "1" (an interrupt request occurs when transmit completed):

U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON

Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program

UiC1 register

TE bit

UiC1 register

TI bit

UiC0 register

TXEPT bit

SiTIC register

IR bit

Cleared to “0” when interrupt request is accepted, or cleared to “0” in a program

Write data to the UiTB register

Transferred from UiTB register to UARTi

transmit register

Tc = 16 (n + 1) / fj or 16 (n + 1) / f

EXT

fj : frequency of UiBRG count source (f

1SIO

, f

2SIO

, f

8SIO

, f

32SIO

)

EXT

: frequency of UiBRG count source (external clock)

n : value set to UiBRG

i: 0 to 2

The above timing diagram applies to the case where the register bits are set

as follows:

• Set the PRYE bit in the UiMR register to "0" (parity disabled)

• Set the STPS bit in the UiMR register to "1" (2 stop bits)

• Set the CRD bit in the UiC0 register to "1"(CTS/RTS disabled)

• Set the UiIRS bit to "0" (an interrupt request occurs when transmit buffer

becomes empty):

U0IRS bit is the UCON register bit 0, U1IRS bit is the UCON

• Example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit)

• Example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits)

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• Example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit)

Figure 13.1.2.2. Receive Operation

13.1.2.1. Bit Rates

In UART mode, the frequency set by the UiBRG register (i=0 to 2) divided by 16 become the bit rates.

Table 13.1.2.1.1 lists example of bit rate and settings.

Table 13.1.2.1.1 Example of Bit Rates and Settings

Bit Rate Count Source Peripheral Function Clock : 16MHz Peripheral Function Clock : 20MHz

(bps) of BRG

Set Value of BRG : n Actual Time (bps) Set Value of BRG : n Actual Time (bps)

1200 f8 103(67h) 1202 129(81h) 1202

2400 f8 51(33h) 2404 64(40h) 2404

4800 f8 25(19h) 4808 32(20h) 4735

9600 f1 103(67h) 9615 129(81h) 9615

14400 f1 68(44h) 14493 86(56h) 14368

19200 f1 51(33h) 19231 64(40h) 19231

28800 f1 34(22h) 28571 42(2Ah) 29070

31250 f1 31(1Fh) 31250 39(27h) 31250

38400 f1 25(19h) 38462 32(20h) 37879

51200

19(13h) 50000 24(18h) 50000

Start bit

Sampled “L”

UiBRG count

source

RxDi

Transfer clock

RTSi

Stop bit

“1”

“0”

“1”

“H”

“L”

“0”

“1”

Reception triggered when transfer clock

is generated by falling edge of start bit

UiC1 register

RE bit

UiC1 register

RI bit

SiRIC register

IR bit

Cleared to “0” when interrupt request is accepted, or cleared to “0” by program

Receive data taken in

D7D1

Transferred from UARTi receive

The above timing diagram applies to the case where the register bits are set as follows:

• Set the PRYE bit in the UiMR register to "0"(parity disabled)

• Set the STPS bit in the UiMR register to "0" (1 stop bit)

• Set the CRD bit in the UiC0 register to "0" (CTSi/RTSi enabled), the CRS bit to "1" (RTSi selected)

i = 0 to 2

Read out from

UiRB register

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Figure 13.1.2.3.1. Transfer Format

(1) When the UFORM bit in the UiC0 register is set to "0" (LSB first)

(2) When the UFORM bit in the UiC0 register "1" (MSB first)

D1D2D3D4D5D6SPD0

TXDi

RXDi

CLKi

D6D5D4D3D2D1D0

TXDi

RXDi

CLKi

D7P

D6D5D4D3D2D1D0

NOTE:

1. This applies to the case where the CKPOL bit in the UiC0 register is set to "0"

(transmit data output at the falling edge and the receive data taken in at the rising

edge of the transfer clock), the UiLCH bit in the UiC1 register is set to "0" (no

reverse), the STPS bit in the UiMR register is set to "0" (1 stop bit) and the PRYE

bit in the UiMR register is set to "1" (parity enabled).

i = 0 to 2

ST: Start bit

P: Parity bit

SP: Stop bit

13.1.2.2. Counter Measure for Communication Error

If a communication error occurs while transmitting or receiving in UART mode, follow the procedure

below.

• Resetting the UiRB register (i=0 to 2)

(1) Set the RE bit in the UiC1 register to “0” (reception disabled)

(2) Set the RE bit in the UiC1 register to “1” (reception enabled)

• Resetting the UiTB register (i=0 to 2)

(1) Set the SMD2 to SMD0 bits in UiMR register “0002” (Serial I/O disabled)

(2) Set the SMD2 to SMD0 bits in UiMR register “0012”, “1012”, “1102”

(3) “1” is written to RE bit in the UiC1 register (reception enabled), regardless of the TE bit in the UiC1

13.1.2.3. LSB First/MSB First Select Function

As shown in Figure 14.1.2.3.1, use the UFORM bit in the UiC0 register to select the transfer format.

This function is valid when transfer data is 8 bits long.

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13.1.2.5. TxD and RxD I/O Polarity Inverse Function (UART2)

This function inverses the polarities of the TXD2 pin output and RXD2 pin input. The logic levels of all

input/output data (including the start, stop and parity bits) are inversed. Figure 13.1.2.5.1 shows the

TXD pin output and RXD pin input polarity inverse.

Figure 13.1.2.5.1. TXD and RXD I/O Polarity Inverse

13.1.2.4. Serial Data Logic Switching Function (UART2)

The data written to the U2TB register has its logic reversed before being transmitted. Similarly, the

received data has its logic reversed when read from the U2RB register.

Figure 13.1.2.4.1 shows serial

data logic.

Figure 13.1.2.4.1. Serial Data Logic Switching

Transfer clock

“H”

“L”

D0 D1 D2 D3 D4 D5 D6 D7 PSPST

TxD

(no reverse) “H”

“L”

TxD

(reverse)

SPST D3 D4 D5 D6 D7 PD0 D1 D2

“H”

“L”

(1) When the U2LCH bit in the U2C1 register is set to "0" (no reverse)

(2) When the U2LCH bit in the U2C1 register is set "1" (reverse)

Transfer clock

“H”

“L”

NOTE:

1. This applies to the case where the CKPOL bit in the U2C0 register is set to "0"

(transmit data output at the falling edge of the transfer clock), the UFORM bit in the

U2C0 register is set to "0" (LSB first), the STPS bit in the U2MR register is set to "0"

(1 stop bit) and the PRYE bit in the U2MR register is set to "1" (parity enabled).

ST: Start bit

P: Parity bit

SP: Stop bit

(1) When the IOPOL bit in the U2MR register is set to "0" (no reverse)

(2) When the IOPOL bit in the U2MR register is set to "1" (reverse)

D0 D1 D2 D3 D4 D5 D6 D7 PSPST

SPST D3 D4 D5 D6 D7 PD0 D1 D2

D0 D1 D2 D3 D4 D5 D6 D7 PSPST

“H”

SPST D3 D4 D5 D6 D7 PD0 D1 D2

Transfer clock

TxD2

(no reverse)

RxD2

(no reverse)

Transfer clock

TxD2

(reverse)

RxD2

(reverse)

“L”

“H”

“L”

“H”

“L”

“H”

“L”

“H”

“L”

“H”

“L”

NOTE:

1. This applies to the case where the UFORM bit in the U2C0 register is set to

"0"(LSB first), the STPS bit in the U2MR register is set to "0" (1 stop bit) and the

PRYE bit in the U2MR register is set to "1"(parity enabled).

ST: Start bit

P: Parity bit

SP: Stop bit

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_______ _______

13.1.2.6. CTS/RTS Separate Function (UART0)

_______ _______ _______ _______

This function separates CTS0/RTS0, outputs RTS0 from the P60 pin, and accepts as input the CTS0

from the P64 pin. To use this function, set the register bits as shown below.

_______ _______

• Set the CRD bit in the U0C0 register to "0" (enables UART0 CTS/RTS)

_______

• Set the CRS bit in the U0C0 register to "1"(outputs UART0 RTS)

_______ _______

• Set the CRD bit in the U1C0 register to "0" (enables UART1 CTS/RTS)

_______

• Set the CRS bit in the U1C0 register to "0" (inputs UART1 CTS)

_______

• Set the RCSP bit in the UCON register to "1" (inputs CTS0 from the P64 pin)

• Set the CLKMD1 bit in the UCON register to "0" (CLKS1 not used)

_______ _______ _______ _______

Note that when using the CTS/RTS separate function, UART1 CTS/RTS separate function cannot be

used.

_______ _______

Figure 13.1.2.6.1. CTS/RTS Separate Function

Microcomputer

(P6

)

(P6

)IN

OUT

CTS

RTSCTS

(P6

)

RTS

(P6

)

NOTE:

1. This applies to the case where U1MAP bit in PACR register is set to “0” (P6

to P6

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13.1.3 Special Mode 1 (I2C bus mode)(UART2)

I2C bus mode is provided for use as a simplified I2C bus interface compatible mode. Table 13.1.3.1 lists

the specifications of the I2C bus mode. Table 13.1.3.2 and 13.1.3.3 list the registers used in the I2C bus

mode and the register values set. Table 13.1.3.4 lists the I2C bus mode fuctions. Figure 13.1.3.1 shows

the block diagram for I2C bus mode. Figure 13.1.3.2 shows SCL2 timing.

As shown in Table 13.1.3.2, the microcomputer is placed in I2C bus mode by setting the SMD2 to SMD0

bits to ‘0102’ and the IICM bit to “1”. Because SDA2 transmit output has a delay circuit attached, SDA

output does not change state until SCL2 goes low and remains stably low.

Table 13.1.3.1. I2C bus Mode Specifications

Item Specification

Transfer data format • Transfer data length: 8 bits

Transfer clock • During master

The CKDIR bit in the U2MR register is set to “0” (internal clock) : fj/ (2(n+1))

fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value in the U2BRG register 0016 to FF16

• During slave

The CKDIR bit is set to “1” (external clock) : Input from SCL2 pin

Transmission start condition • Before transmission can start, the following requirements must be met (1)

_ The TE bit in the U2C1 register is set to "1" (transmission enabled)

_ The TI bit in the U2C1 register is set to "0" (data present in U2TB register)

Reception start condition • Before reception can start, the following requirements must be met (1)

_ The RE bit in the U2C1 register is set to "1" (reception enabled)

_ The TE bit in the U2C1 register is set to "1" (transmission enabled)

_ The TI bit in the U2C1 register is set to "0" (data present in the UiTB register)

When start or stop condition is detected, acknowledge undetected, and acknowledge

detected

Error detection • Overrun error (2)

This error occurs if the serial I/O started receiving the next data before reading the

U2RB register and received the 8th bit of the next data

Select function • Arbitration lost

Timing at which the ABT bit in the U2RB register is updated can be selected

• SDA2 digital delay

No digital delay or a delay of 2 to 8 U2BRG count source clock cycles selectable

• Clock phase setting

With or without clock delay selectable

Interrupt request

generation timing

NOTES:

1. When an external clock is selected, the conditions must be met while the external clock is in the high state.

2. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains

unchanged.

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CLK

control

Falling edge

detection

External

clock

Internal clock

Start/stop condition detection

interrupt request

Start condition

detection

Stop condition

detection

Reception register

Bus

busy

Transmission

Arbitration

Noise

Filter

SDA2

SCL2

UART2

DTQ

NACK

ACK

UART2

UART2 transmit,

NACK interrupt

request

UART2 receive,

ACK interrupt request,

DMA1 request

IICM=1 and

IICM2=0

ALS

SWC

IICM=1 and

IICM2=0

IICM2=1

SWC2

SDHI

DMA0, DMA1 request

Noise

Filter

IICM : Bit in the U2SMR

IICM2, SWC, ALS, SWC2, SDHI : Bits in the U2SMR2

STSPSEL, ACKD, ACKC : Bits in the U2SMR4

IICM=0

IICM=1

DMA0

STSPSEL=0

STSPSEL=1

STSPSEL=0

SDA

STSP

SCL

STSP

ACKC=1 ACKC=0

Port register

(1)

I/O port

9th bit falling edge

9th bit

ACKD bit

Delay

circuit

This diagram applies to the case where the SMD2 to SMD0 bits in the the U2MR register is set to "010

" and the IICM bit in the U2SMR

NOTE:

1. If the IICM bit is set to "1", the pin can be read even when the PD7_1 bit is set to "1" (output mode).

Start and stop condition generation block

Figure 13.1.3.1. I2C bus Mode Block Diagram

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Table 13.1.3.2. Registers to Be Used and Settings in I2C bus Mode (1) (Continued)

Master Slave

U2TB 0 to 7 Set transmission data Set transmission data

(1)

U2RB 0 to 7 Reception data can be read Reception data can be read

(1) 8 ACK or NACK is set in this bit ACK or NACK is set in this bit

ABT Arbitration lost detection flag Invalid

OER Overrun error flag Overrun error flag

U2BRG 0 to 7 Set a transfer rate Invalid

U2MR SMD2 to SMD0 Set to ‘0102’Set to ‘0102’

(1) CKDIR Set to “0”Set to “1”

IOPOL Set to “0”Set to “0”

U2C0 CLK1, CLK0 Select the count source for the U2BRG Invalid

CRS Invalid because CRD = 1 Invalid because CRD = 1

TXEPT Transmit buffer empty flag Transmit buffer empty flag

CRD Set to “1”Set to “1”

NCH Set to “1”Set to “1”

CKPOL Set to “0”Set to “0”

UFORM Set to “1”Set to “1”

U2C1 TE Set this bit to “1” to enable transmission Set this bit to “1” to enable transmission

TI Transmit buffer empty flag Transmit buffer empty flag

RE Set this bit to “1” to enable reception Set this bit to “1” to enable reception

RI Reception complete flag Reception complete flag

U2IRS Invalid Invalid

U2RRM, Set to “0”Set to “0”

U2LCH, U2ERE

U2SMR IICM Set to “1”Set to “1”

ABC Select the timing at which arbitration-lost Invalid

is detected

BBS Bus busy flag Bus busy flag

3 to 7 Set to “0”Set to “0”

U2SMR2 IICM2

Refer to

Table 13.1.3.4 I2C bus Mode Functions

Refer to

Table 13.1.3.4 I2C bus Mode Functions

CSC Set this bit to “1” to enable clock Set to “0”

synchronization

SWC Set this bit to “1” to have SCL2 output Set this bit to “1” to have SCL2 output

fixed to “L” at the falling edge of the 9th fixed to “L” at the falling edge of the 9th

bit of clock bit of clock

ALS Set this bit to “1” to have SDA2 output Set to “0”

stopped when arbitration-lost is detected

STAC Set to “0”Set this bit to “1” to initialize UART2 at

start condition detection

SWC2 Set this bit to “1” to have SCL2 output Set this bit to “1” to have SCL2 output

forcibly pulled low forcibly pulled low

SDHI Set this bit to “1” to disable SDA2 output Set this bit to “1” to disable SDA2 output

7 Set to “0”Set to “0”

U2SMR3 0, 2, 4 and NODC Set to “0”Set to “0”

CKPH

Refer to

Table 13.1.3.4 I2C bus Mode Functions

Refer to

Table 13.1.3.4 I2C bus Mode Functions

DL2 to DL0 Set the amount of SDA2 digital delay Set the amount of SDA2 digital delay

NOTE:

1. Not all register bits are described above. Set those bits to “0” when writing to the registers in I2C bus

mode.

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U2SMR4 STAREQ Set this bit to “1” to generate start Set to “0”

condition

RSTAREQ Set this bit to “1” to generate restart Set to “0”

condition

STPREQ Set this bit to “1” to generate stop Set to “0”

condition

STSPSEL Set this bit to “1” to output each condition Set to “0”

ACKD Select ACK or NACK Select ACK or NACK

ACKC Set this bit to “1” to output ACK data Set this bit to “1” to output ACK data

SCLHI Set this bit to “1” to have SCL 2 output Set to “0”

stopped when stop condition is detected

SWC9 Set to “0”Set this bit to “1” to set the SCL2 to “L”

hold at the falling edge of the 9th bit of

clock

Master Slave

Table 13.1.3.3. Registers to Be Used and Settings in I2C bus Mode (2) (Continued)

NOTE:

1. Not all bits in the register are described above. Set those bits to “0” when writing to the registers in I2C

bus mode.

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Function I2C bus mode (SMD2 to SMD0 = 0102, IICM = 1)

Clock synchronous serial I/O

mode (SMD2 to SMD0 = 0012,

IICM = 0)

Factor of interrupt number

15 (1)

(Refer to Fig.13.1.3.2.)

No acknowledgment

detection (NACK)

Rising edge of SCL2 9th bit

Factor of interrupt number

16 (1)

1(Refer to Fig.13.1.3.2.)

Start condition detection or stop condition detection

(Refer to Figure 13.1.3.2.1. STSPSEL Bit Function)

UART2 transmission

output delay

Functions of P70 pin

Noise filter width

Read RxD2 and SCL2 pin

levels

Factor of interrupt number

10 (1)

(Refer to Fig.13.1.3.2.)

Acknowledgment detection

(ACK)

Rising edge of SCL2 9th bit

Initial value of TxD2 and

SDA2 outputs

UART2 transmission

Transmission started or

completed (selected by U2IRS)

UART2 reception

When 8th bit received

CKPOL = 0 (rising edge)

CKPOL = 1 (falling edge)

Not delayed

TxD2 output

RxD2 input

CLK2 input or output selected

15ns

Possible when the

corresponding port direction bit

= 0

CKPOL = 0 (H)

CKPOL = 1 (L)

Delayed

SDA2 input/output

SCL2 input/output

(Cannot be used in I2C mode)

Initial and end values of

SCL2H

200ns

Always possible no matter how the corresponding port direction bit is set

The value set in the port register before setting I2C bus mode (2)

Timing for transferring data

from the UART reception

shift register to the U2RB

IICM2 = 0

(NACK/ACK interrupt) IICM2 = 1

(UART transmit/ receive interrupt)

CKPH = 1

(Clock delay) CKPH = 1

(Clock delay)

UART2 transmission

Rising edge of

SCL2 9th bit

UART2 transmission

Falling edge of SCL2

next to the 9th bit

UART2 transmission

Falling edge of SCL2 9th bit

CKPOL = 0 (rising edge)

CKPOL = 1 (falling edge) Rising edge of SCL2 9th bit Falling edge of

SCL2 9th bit Falling and rising

edges of SCL2 9th

bit

DMA1 factor (Refer to Fig.

14.1.3.2.)UART2 reception Acknowledgment detection

(ACK) UART2 reception

Falling edge of SCL2

9th bi

Store received data 1st to 8th bits are stored in

U2RB register bit 0 to bit 7 1st to 8th bits are stored in

U2RB register bit 7 to bit 0 1st to 7th bits are stored in U2RB register

bit 6 to bit 0, with 8th bit stored in U2RB

Read U2RB register

Bit 6 to bit 0 as bit 7

to bit 1, and bit 8 as

bit 0 (4)

Read received data U2RB register status is read

directly as is

CKPH = 0

(No clock delay) CKPH = 0

(No clock delay)

1st to 8th bits are

stored in U2RB

(3)

Functions of P71 pin

Functions of P72 pin

NOTES:

1. If the source or cause of any interrupt is changed, the IR bit in the interrupt control register for the changed interrupt

may inadvertently be set to 1 (interrupt requested). (Refer to “Notes on interrupts” in Usage Notes) If one of the bits

shown below is changed, the interrupt source, the interrupt timing, etc. change. Therefore, always be sure to clear

the IR bit to 0 (interrupt not requested) after changing those bits. SMD2 to SMD0 bits in the U2MR register, IICM bit

in the U2SMR register, IICM2 bit in the U2SMR2 register, CKPH bit in the U2SMR3 register

2. Set the initial value of SDA2 output while the SMD2 to SMD0 bits in the U2MR register is set to ‘0002’ (serial I/O

disabled).

3. Second data transfer to U2RB register (Rising edge of SCL2 9th bit)

4. First data transfer to U2RB register (Falling edge of SCL2 9th bit)

Table 13.1.3.4. I2C bus Mode Functions

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Figure 13.1.3.2. Transfer to U2RB Register and Interrupt Timing

(4) When the IICM2 bit is set to "1" and the CKPH bit is set to "1"

(3) When the IICM2 bit is set to "1" (UART transmit or receive interrupt) and the CKPH bit is set to "0"

SDA2

SCL2

Receive interrupt

(DMA request) Transmit interrupt

SDA2

SCL2

The above timing applies to the following setting :

• The CKDIR bit in the U2MR register is set to "1" (slave)

(1) When the IICM2 bit is set to "0" (ACK or NACK interrupt) and the CKPH bit is set to "0" (No clock delay)

D6D5D4D3D2D1D8 (ACK or NACK)D7

SDA2

SCL2

ACK interrupt (DMA

request) or NACK interrupt

(2) When the IICM2 bit is set to "0" and the CKPH bit is set to "1" (clock delay)

SDA2

SCL2

1st

bit 2nd

bit 3rd

bit 4th

bit 5th

bit 6th

bit 7th

bit 8th

bit 9th

bit

b15

•••

b9 b8 b7 b0

Contents of the U2RB register

b15

•••

b9 b8 b7 b0

b15

•••

b9 b8 b7 b0

b15

•••

b9 b8 b7 b0 b15

•••

b9 b8 b7 b0

D6D5D4D3D2D1D7D0

ACK interrupt (DMA

request) or NACK interrupt

D6D5D4D3D2D1D7D0

D8 (ACK or NACK)

1st

bit 2nd

bit 3rd

bit 4th

bit 5th

bit 6th

bit 7th

bit 8th

bit 9th

bit

D8 (ACK or NACK)

1st

bit 2nd

bit 3rd

bit 4th

bit 5th

bit 6th

bit 7th

bit 8th

bit 9th

bit

D8 (ACK or NACK)

1st

bit 2nd

bit 3rd

bit 4th

bit 5th

bit 6th

bit 7th

bit 8th

bit 9th

bit

Data is transferred to the U2RB register

Receive interrupt

(DMA request) Transmit interrupt

Data is transferred to the U2RB register

Contents of the U2RB register

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13.1.3.1 Detection of Start and Stop Condition

Whether a start or a stop condition has been detected is determined.

A start condition-detected interrupt request is generated when the SDA2 pin changes state from high

to low while the SCL2 pin is in the high state. A stop condition-detected interrupt request is generated

when the SDA2 pin changes state from low to high while the SCL2 pin is in the high state.

Because the start and stop condition-detected interrupts share the interrupt control register and vec-

tor, check the BBS bit in the U2SMR register to determine which interrupt source is requesting the

interrupt.

Setup time Hold time

SCL2

SDA2(Start condition)

SDA2(Stop condition)

3 to 6 cycles < setup time

(1)

3 to 6 cycles < hold time

(1)

NOTE:

1. When the PCLK1 bit in the PCLKR register is set to "1", the cycles indicates the f1SIO's

generation frequency cycles; when PCLK1 bit is set to "0", the cycles indicated the f2SIO's

generation frequency cycles.

Figure 13.1.3.1.1. Detection of Start and Stop Condition

13.1.3.2 Output of Start and Stop Condition

A start condition is generated by setting the STAREQ bit in the U2SMR4 register to “1” (start).

A restart condition is generated by setting the RSTAREQ bit in the U2SMR4 register to “1” (start).

A stop condition is generated by setting the STPREQ bit in the U2SMR4 register to “1” (start).

The output procedure is described below.

(1) Set the STAREQ bit, RSTAREQ bit or STPREQ bit to “1” (start).

(2) Set the STSPSEL bit in the U2SMR4 register to “1” (output).

Make sure that no interrupts or DMA transfers will occur between (1) and (2).

The function of the STSPSEL bit is shown in Table 13.1.3.2.1 and Figure 13.1.3.2.1.

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Table 13.1.3.2.1. STSPSEL Bit Functions

Figure 13.1.3.2.1. STSPSEL Bit Functions

Function

Output of SCL2 and SDA2 pins

Start/stop condition interrupt

request generation timing

STSPSEL = 0

Output transfer clock and data/

Program with a port determines

how the start condition or stop

condition is output

Start/stop condition are de-

tected

STSPSEL = 1

The STAREQ, RSTAREQ and

STPREQ bit determine how the

start condition or stop condition is

output

Start/stop condition generation are

completed

SDA2

Start condition detection

interrupt Stop condition detection

interrupt

(1) In slave mode,

CKDIR is set to "1" (external clock)

SCL2

SDA2

Start condition detection

interrupt Stop condition detection

interrupt

(2) In master mode,

CKDIR is set to "0" (internal clock), CKPH is set to "1"(clock delayed)

SCL2

Set STPREQ

to "1" (start)

STPSEL bit 0

STPSEL bit

Set to "1" by

a program Set to "0" by

a program Set to "1" by

a program Set to "0" by

a program

1st 2nd 3rd 5th 6th 7th 8th 9th bit

4th

Set STAREQ to "1" (start)

1st 2nd 3rd 5th 6th 7th 8th 9th bit

4th

13.1.3.3 Arbitration

Unmatching of the transmit data and SDA2 pin input data is checked synchronously with the rising

edge of SCL2. Use the ABC bit in the U2SMR register to select the timing at which the ABT bit in the

U2RB register is updated. If the ABC bit is set to "0" (updated bitwise), the ABT bit is set to “1” at the

same time unmatching is detected during check, and is cleared to “0” when not detected. In cases

when the ABC bit is set to “1”, if unmatching is detected even once during check, the ABT bit is set to

“1” (unmatching detected) at the falling edge of the clock pulse of 9th bit. If the ABT bit needs to be

updated bytewise, clear the ABT bit to “0” (undetected) after detecting acknowledge in the first byte,

before transferring the next byte.

Setting the ALS bit in the U2SMR2 register to “1” (SDA output stop enabled) causes arbitration-lost to

occur, in which case the SDA2 pin is placed in the high-impedance state at the same time the ABT bit

is set to “1” (unmatching detected).

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13.1.3.4 Transfer Clock

Data is transmitted/received using a transfer clock like the one shown in Figure 13.1.3.2.1.

The CSC bit in the U2SMR2 register is used to synchronize the internally generated clock (internal

SCL2) and an external clock supplied to the SCL2 pin. In cases when the CSC bit is set to “1” (clock

synchronization enabled), if a falling edge on the SCL2 pin is detected while the internal SCL2 is high,

the internal SCL2 goes low, at which time the U2BRG register value is reloaded with and starts count-

ing in the low-level interval. If the internal SCL2 changes state from low to high while the SCL2 pin is

low, counting stops, and when the SCL2 pin goes high, counting restarts.

In this way, the UART2 transfer clock is comprised of the logical product of the internal SCL2 and SCL2

pin signal. The transfer clock works from a half period before the falling edge of the internal SCL2 1st

bit to the rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock.

The SWC bit in the U2SMR2 register allows to select whether the SCL2 pin should be fixed to or freed

from low-level output at the falling edge of the 9th clock pulse.

If the SCLHI bit in the U2SMR4 register is set to “1” (enabled), SCL2 output is turned off (placed in the

high-impedance state) when a stop condition is detected.

Setting the SWC2 bit in the U2SMR2 register is set to "1" (0 output) makes it possible to forcibly output

a low-level signal from the SCL2 pin even while sending or receiving data. Clearing the SWC2 bit to “0”

(transfer clock) allows the transfer clock to be output from or supplied to the SCL2 pin, instead of

outputting a low-level signal.

If the SWC9 bit in the U2SMR4 register is set to “1” (SCL hold low enabled) when the CKPH bit in the

U2SMR3 register is set to "1", the SCL2 pin is fixed to low-level output at the falling edge of the clock

pulse next to the ninth. Setting the SWC9 bit is set to "0" (SCL hold low disabled) frees the SCL2 pin

from low-level output.

13.1.3.5 SDA Output

The data written to the bit 7 to bit 0 (D7 to D0) in the U2TB register is sequentially output beginning with

D7. The ninth bit (D8) is ACK or NACK.

The initial value of SDA2 transmit output can only be set when IICM is set to "1" (I2C Bus mode) and

the SMD2 to SMD0 bits in the the U2MR register are set to ‘0002’ (serial I/O disabled).

The DL2 to DL0 bits in the U2SMR3 register allow to add no delays or a delay of 2 to 8 U2BRG count

source clock cycles to SDA2 output.

Setting the SDHI bit in the U2SMR2 register is set to "1" (SDA output disabled) forcibly places the

SDA2 pin in the high-impedance state. Do not write to the SDHI bit synchronously with the rising edge

of the UART2 transfer clock. This is because the ABT bit may inadvertently be set to “1” (detected).

13.1.3.6 SDA Input

When the IICM2 bit is set to "0", the 1st to 8th bits (D7 to D0) of received data are stored in the bit 7 to

bit 0 in the U2RB register. The 9th bit (D8) is ACK or NACK.

When the IICM2 bit is set to "1", the 1st to 7th bits (D7 to D1) of received data are stored in the bit 6 to

bit 0 in the U2RB register and the 8th bit (D0) is stored in the bit 8 in the U2RB register. Even when the

IICM2 bit is set to "1", providing the CKPH bit to "1", the same data as when the IICM2 bit is set to "0"

can be read out by reading the U2RB register after the rising edge of the corresponding clock pulse of

9th bit.

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13.1.3.7 ACK and NACK

If the STSPSEL bit in the U2SMR4 register is set to “0” (start and stop conditions not generated) and

the ACKC bit in the U2SMR4 register is set to “1” (ACK data output), the value of the ACKD bit in the

U2SMR4 register is output from the SDA2 pin.

If the IICM2 bit is set to "0", a NACK interrupt request is generated if the SDA2 pin remains high at the

rising edge of the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDA2 pin

is low at the rising edge of the 9th bit of transmit clock pulse.

If ACK2 is selected for the cause of DMA1 request, a DMA transfer can be activated by detection of an

acknowledge.

13.1.3.8 Initialization of Transmission/Reception

If a start condition is detected while the STAC bit is set to "1" (UART2 initialization enabled), the serial

I/O operates as described below.

- The transmit shift register is initialized, and the content of the U2TB register is transferred to the

transmit shift register. In this way, the serial I/O starts sending data synchronously with the next

clock pulse applied. However, the UART2 output value does not change state and remains the

same as when a start condition was detected until the first bit of data is output synchronously with

the input clock.

- The receive shift register is initialized, and the serial I/O starts receiving data synchronously with the

next clock pulse applied.

- The SWC bit is set to “1” (SCL wait output enabled). Consequently, the SCL2 pin is pulled low at the

falling edge of the ninth clock pulse.

Note that when UART2 transmission/reception is started using this function, the TI does not change

state. Note also that when using this function, the selected transfer clock should be an external clock.

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13.1.4 Special Mode 2 (UART2)

Multiple slaves can be serially communicated from one master. Transfer clock polarity and phase are

selectable. Table 13.1.4.1 lists the specifications of Special Mode 2. Table 13.1.4.2 lists the registers

used in Special Mode 2 and the register values set. Figure 13.1.4.1 shows communication control ex-

ample for Special Mode 2.

Table 13.1.4.1. Special Mode 2 Specifications

Item Specification

Transfer data format • Transfer data length: 8 bits

Transfer clock • Master mode

The CKDIR bit in the U2MR register is set to “0” (internal clock) : fj/ (2(n+1))

fj = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value of U2BRG register 0016 to FF16

• Slave mode

The CKDIR bit is set to “1” (external clock selected) : Input from CLK2 pin

Transmit/receive control Controlled by input/output ports

Transmission start condition • Before transmission can start, the following requirements must be met (1)

_ The TE bit in the U2C1 register is set to "1" (transmission enabled)

_ The TI bit in the U2C1 register is set to "0" (data present in U2TB register)

Reception start condition • Before reception can start, the following requirements must be met (1)

_ The RE bit in the U2C1 register is set to "1" (reception enabled)

_ The TE bit in the U2C1 register is set to "1" (transmission enabled)

_ The TI bit in the U2C1 register is set to "0" (data present in the U2TB register)

•While transmitting, one of the following conditions can be selected

_ The U2IRS bit in the U2C1 register is set to "0" (transmit buffer empty): when trans-

ferring data from the U2TB register to the UART2 transmit register (at start of transmission)

_ The U2IRS bit is set to "1" (transfer completed): when the serial I/O finished sending

data from the UART2 transmit register

• While receiving

When transferring data from the UART2 receive register to the U2RB register (at

completion of reception)

Error detection • Overrun error (2)

This error occurs if the serial I/O started receiving the next data before reading the

U2RB register and received the 7th bit of the next data

Select function • Clock phase setting

Selectable from four combinations of transfer clock polarities and phases

Interrupt request

generation timing

NOTES:

1. When an external clock is selected, the conditions must be met while if the CKPOL bit in the U2C0 register “0”

(transmit data output at the falling edge and the receive data taken in at the rising edge of the transfer clock), the

external clock is in the high state; if the CKPOL bit in the U2C0 register “1” (transmit data output at the rising edge

and the receive data taken in at the falling edge of the transfer clock), the external clock is in the low state.

2. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains

unchanged.

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P13

P12

P70(TxD2)

P72(CLK2)

P71(RxD2)

P93

P70(TxD2)

P72(CLK2)

P71(RxD2)

P93

P70(TxD2)

P72(CLK2)

P71(RxD2)

Microcomputer

(Master) Microcomputer

(Slave)

Microcomputer

(Slave)

Figure 13.1.4.1. Serial Bus Communication Control Example (UART2)

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Table 13.1.4.2. Registers to Be Used and Settings in Special Mode 2

U2TB(1) 0 to 7 Set transmission data

U2RB(1) 0 to 7 Reception data can be read

OER Overrun error flag

U2BRG 0 to 7 Set a transfer rate

U2MR(1) SMD2 to SMD0 Set to ‘0012’

CKDIR Set this bit to “0” for master mode or “1” for slave mode

IOPOL Set to “0”

U2C0 CLK1, CLK0 Select the count source for the U2BRG register

CRS Invalid because CRD = 1

TXEPT Transmit register empty flag

CRD Set to “1”

NCH Select TxD2 pin output format

CKPOL Clock phases can be set in combination with the CKPH bit in the U2SMR3

UFORM Set to “0”

U2C1 TE Set this bit to “1” to enable transmission

TI Transmit buffer empty flag

RE Set this bit to “1” to enable reception

RI Reception complete flag

U2IRS Select UART2 transmit interrupt cause

U2RRM, Set to “0”

U2LCH, U2ERE

U2SMR 0 to 7 Set to “0”

U2SMR2 0 to 7 Set to “0”

U2SMR3 CKPH Clock phases can be set in combination with the CKPOL bit in the U2C0 register

NODC Set to “0”

0, 2, 4 to 7 Set to “0”

U2SMR4 0 to 7 Set to “0”

NOTE:

1. Not all bits in the register are described above. Set those bits to “0” when writing to the registers in

Special Mode 2.

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13.1.4.1 Clock Phase Setting Function

One of four combinations of transfer clock phases and polarities can be selected using the CKPH bit

in the U2SMR3 register and the CKPOL bit in the U2C0 register.

Make sure the transfer clock polarity and phase are the same for the master and slave to communi-

cate.

13.1.4.1.1 Master (Internal Clock)

Figure 13.1.4.1.1.1 shows the transmission and reception timing in master (internal clock).

13.1.4.1.2 Slave (External Clock)

Figure 13.1.4.1.2.1 shows the transmission and reception timing (CKPH=0) in slave (external clock)

while Figure 13.1.4.1.2.2 shows the transmission and reception timing (CKPH=1) in slave (external

clock).

Data output timing

Data input timing

Clock output

(CKPOL=0, CKPH=0)

"H"

"L"

Clock output

(CKPOL=1, CKPH=0)

"H"

"L"

Clock output

(CKPOL=0, CKPH=1)

"H"

"L"

Clock output

(CKPOL=1, CKPH=1)

"H"

"L"

"H"

"L"

Figure 13.1.4.1.1.1. Transmission and Reception Timing in Master Mode (Internal Clock)

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Figure 13.1.4.1.2.1. Transmission and Reception Timing (CKPH=0) in Slave Mode (External Clock)

Figure 13.1.4.1.2.2. Transmission and Reception Timing (CKPH=1) in Slave Mode (External Clock)

Slave control input

Clock input

(CKPOL=0, CKPH=0)

Clock input

(CKPOL=1, CKPH=0)

Data output timing

Data input timing

"H"

"L"

"H"

"L"

"H"

"L"

"H"

"L"

D0D1D2D3D4D6D7D5

Indeterminate

Clock input

(CKPOL=0, CKPH=1)

Clock input

(CKPOL=1, CKPH=1)

Data output timing

Data input timing

"H"

"L"

"H "

"L"

"H "

"L "

"H "

"L" D

Slave control input

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13.1.5 Special Mode 3 (IE Bus mode )(UART2)

In this mode, one bit of IE Bus is approximated with one byte of UART mode waveform.

Table 13.1.5.1 lists the registers used in IE Bus mode and the register values set. Figure 13.1.5.1 shows

the functions of bus collision detect function related bits.

If the TxD2 pin output level and RxD2 pin input level do not match, a UART2 bus collision detect interrupt

request is generated.

Table 13.1.5.1. Registers to Be Used and Settings in IE Bus Mode

U2TB 0 to 8 Set transmission data

U2RB(1) 0 to 8 Reception data can be read

OER,FER,PER,SUM

Error flag

U2BRG 0 to 7 Set a transfer rate

U2MR SMD2 to SMD0 Set to ‘1102’

CKDIR Select the internal clock or external clock

STPS Set to “0”

PRY Invalid because PRYE=0

PRYE Set to “0”

IOPOL Select the TxD/RxD input/output polarity

U2C0 CLK1, CLK0 Select the count source for the U2BRG register

CRS Invalid because CRD=1

TXEPT Transmit register empty flag

CRD Set to “1”

NCH Select TxD2 pin output mode

CKPOL Set to “0”

UFORM Set to “0”

U2C1 TE Set this bit to “1” to enable transmission

TI Transmit buffer empty flag

RE Set this bit to “1” to enable reception

RI Reception complete flag

U2IRS Select the source of UART2 transmit interrupt

U2RRM, Set to “0”

U2LCH, U2ERE

U2SMR 0 to 3, 7 Set to “0”

ABSCS Select the sampling timing at which to detect a bus collision

ACSE Set this bit to “1” to use the auto clear function of transmit enable bit

SSS Select the transmit start condition

U2SMR2 0 to 7 Set to “0”

U2SMR3 0 to 7 Set to “0”

U2SMR4 0 to 7 Set to “0”

NOTE:

1. Not all bits in the registers are described above. Set those bits to “0” when writing to the registers in

IEBus mode.

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(2) The ACSE bit in the U2SMR register (auto clear of transmit enable bit)

(1) The ABSCS bit in the U2SMR register (bus collision detect sampling clock select)

If ABSCS=0, bus collision is determined at the rising edge of the transfer clock

Transfer clock

Timer A0

(3) The SSS bit in the U2SMR register (Transmit start condition select)

Transmission enable condition is met

If SSS bit = 1, the serial I/O starts sending data at the rising edge

(1)

of RxD2

TxD2

CLK2

TxD2

RxD2

TxD2

RxD2

ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP

Input to TA0IN

If ABSCS is set to "1", bus collision is determined when timer

A0 (one-shot timer mode) underflows .

TxD2

RxD2

ST D0 D1 D2 D3 D4 D5 D6 D7 D8 SP

Transfer clock

BCNIC register

IR bit (1)

U2C1 register

TE bit

If ACSE bit is set to "1"

automatically clear when bus collision

occurs), the TE bit is cleared to "0"

(transmission disabled) when

the IR bit in the BCNIC register is

set to "1" (unmatching detected).

If SSS bit is set to "0", the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.

Transfer clock

(2)

This diagram applies to the case where the IOPOL is set to "1" (reversed)

NOTES:

1. The falling edge of RxD2 when the IOPOL is set to "0"; the rising edge of RxD2 when the IOPOL is set to "1".

2. The transmit condition must be met before the falling edge (Note 1) of RxD.

Figure 13.1.5.1. Bus Collision Detect Function-Related Bits

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Item Specification

Transfer data format • Direct format

• Inverse format

Transfer clock • The CKDIR bit in the U2MR register is set to “0” (internal clock) : fi/(16(n+1))

fi = f1SIO, f2SIO, f8SIO, f32SIO. n: Setting value in U2BRG register 0016 to FF16

• The CKDIR bit is set to “1” (external clock ) : fEXT/(16(n+1))

fEXT: Input from CLK2 pin. n: Setting value in U2BRG register 0016 to FF16

Transmission start condition • Before transmission can start, the following requirements must be met

_ The TE bit in the U2C1 register is set to "1" (transmission enabled)

_ The TI bit in the U2C1 register is set to "0" (data present in U2TB register)

Reception start condition • Before reception can start, the following requirements must be met

_ The RE bit in the U2C1 register is set to "1" (reception enabled)

_ Start bit detection

•For transmission

When the serial I/O finished sending data from the U2TB transfer register (the U2IRS bit

is set to "1")

(2) • For reception

When transferring data from the UART2 receive register to the U2RB register (at

completion of reception)

Error detection • Overrun error (1)

This error occurs if the serial I/O started receiving the next data before reading the

U2RB register and received the bit one before the last stop bit of the next data

• Framing error

This error occurs when the number of stop bits set is not detected

• Parity error

During reception, if a parity error is detected, parity error signal is output from the

TxD2 pin.

During transmission, a parity error is detected by the level of input to the RXD2 pin

when a transmission interrupt occurs

• Error sum flag

This flag is set to "1" when any of the overrun, framing, and parity errors is encountered

13.1.6 Special Mode 4 (SIM Mode) (UART2)

Based on UART mode, this is an SIM interface compatible mode. Direct and inverse formats can be

implemented, and this mode allows output of a low from the TxD2 pin when a parity error is detected.

Tables 13.1.6.1 lists the specifications of SIM mode. Table 13.1.6.2 lists the registers used in the SIM

mode and the register values set.

Table 13.1.6.1. SIM Mode Specifications

Interrupt request

generation timing

NOTES:

1. If an overrun error occurs, bits 8 to 0 in UiRB register are undefined. The IR bit in the SiRIC register remains

unchanged.

2. A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to “1” (transmission com-

plete) and the U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM mode, be sure to clear

the IR bit to “0” (no interrupt request) after setting these bits.

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Table 13.1.6.2. Registers to Be Used and Settings in SIM Mode

U2TB(1) 0 to 7 Set transmission data

U2RB(1) 0 to 7 Reception data can be read

OER,FER,PER,SUM

Error flag

U2BRG 0 to 7 Set a transfer rate

U2MR SMD2 to SMD0 Set to ‘1012’

CKDIR Select the internal clock or external clock

STPS Set to “0”

PRY Set this bit to “1” for direct format or “0” for inverse format

PRYE Set to “1”

IOPOL Set to “0”

U2C0 CLK1, CLK0 Select the count source for the U2BRG register

CRS Invalid because CRD=1

TXEPT Transmit register empty flag

CRD Set to “1”

NCH Set to “0”

CKPOL Set to “0”

UFORM Set this bit to “0” for direct format or “1” for inverse format

U2C1 TE Set this bit to “1” to enable transmission

TI Transmit buffer empty flag

RE Set this bit to “1” to enable reception

RI Reception complete flag

U2IRS Set to “1”

U2RRM Set to “0”

U2LCH Set this bit to “0” for direct format or “1” for inverse format

U2ERE Set to “1”

U2SMR(1) 0 to 3 Set to “0”

U2SMR2 0 to 7 Set to “0”

U2SMR3 0 to 7 Set to “0”

U2SMR4 0 to 7 Set to “0”

NOTE:

1. Not all bits in registers are described above. Set those bits to “0” when writing to the registers in SIM

mode.

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Figure 13.1.6.1. Transmit and Receive Timing in SIM Mode

ST PD

ST P

ST PD

ST P

ST PD

ST PSP

ST PD

ST PSP

Start

bit Parity

bit

"0"

"1"

"0"

"1"

"0"

"1"

Set to "0" by an interrupt request acknowledgement or by program

Transfer Clock

Stop

bit

Data is written to

the UARTi register

An "L" signal is applied from the SIM

card due to a parity error

An interrupt routine

detects "H" or "L"

TxD2

Transfer Clock

Read the U2RB register

RxD

pin Level

(2)

TxD

RxD

pin Level

(1)

Data is transferred from the U2TB

RE bit in U2C1

RI bit in U2C1

IR bit in S2RIC

TE bit in U2C1

TI bit in U2C1

TXEPT bit in U2

C0 register

IR bit in S2TIC

Start

bit

Set to "0" by an interrupt request acknowledgement or by program

Stop

bit

TxD

outputs "L" due

to a parity error

Parity

bit

"1"

"0"

"1"

(1) Transmit Timing

(2) Receive Timing

Parity Error Signal

returned from

Receiving End

Transmit Waveform

from the

Transmitting End

"1"

An interrupt routine detects

"H" or "L"

The above timing diagram applies to the case where data is

transferred in the direct format.

• U2MR register STPS bit = 0 (1 stop bit)

• U2MR register PRY bit = 1 (even)

• U2C0 register UFORM bit = 0 (LSB first)

• U2C1 register U2LCH bit = 0 (no reverse)

• U2C1 register U2IRSCH bit = 1 (transmit is completed)

Tc = 16 (n + 1) / fi or 16 (n + 1) / f

EXT

fi : frequency of U2BRG count source (f

1SIO

, f

2SIO

, f

8SIO

, f

32SIO

)

EXT

: frequency of U2BRG count source (external clock)

n : value set to U2BRG

The above timing diagram applies to the case where data is

transferred in the direct format.

• U2MR register STPS bit = 0 (1 stop bit)

• U2MR register PRY bit = 1 (even)

• U2C0 register UFORM bit = 0 (LSB first)

• U2C1 register U2LCH bit = 0 (no reverse)

• U2C1 register U2IRSCH bit = 1 (transmit is completed)

NOTES:

1. Because TxD

and RxD

are connected, this is composite waveform consisting of the TxD

output and the parity error

signal sent back from receiver.

2. Because TxD

and RxD

are connected, this is composite waveform consisting of the transmitter's transmit waveform

and the parity error signal received.

Tc = 16 (n + 1) / fi or 16 (n + 1) / f

EXT

fi : frequency of U2BRG count source (f

1SIO

, f

2SIO

, f

8SIO

, f

32SIO

)

EXT

: frequency of U2BRG count source (external clock)

n : value set to U2BRG

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Figure 13.1.6.2 shows the example of connecting the SIM interface. Connect TXD2 and RXD2 and apply

pull-up.

Figure 13.1.6.2. SIM Interface Connection

Microcomputer SIM card

TxD2

RxD2

13.1.6.1 Parity Error Signal Output

The parity error signal is enabled by setting the U2ERE bit in the U2C1 register’ to “1”.

• When receiving

The parity error signal is output when a parity error is detected while receiving data. This is achieved

by pulling the TxD2 output low with the timing shown in Figure 13.1.6.1.1. If the R2RB register is read

while outputting a parity error signal, the PER bit is cleared to “0” and at the same time the TxD2 output

is returned high.

• When transmitting

A transmission-finished interrupt request is generated at the falling edge of the transfer clock pulse

that immediately follows the stop bit. Therefore, whether a parity signal has been returned can be

determined by reading the port that shares the RxD2 pin in a transmission-finished interrupt service

routine.

Figure 13.1.6.1.1. Parity Error Signal Output Timing

D0 D1 D2 D3 D4 D5 D6 D7 PSPST

(1)

Transfer

clock

RxD

TxD

U2C1 register

RI bit

“H”

“L”

“H”

“L”

“H”

“L”

“1”

“0”

This timing diagram applies to the case where the direct format is implemented.

NOTE:

1. The output of microcomputer is in the high-impedance state

(pulled up externally).

ST: Start bit

P: Even Parity

SP: Stop bit

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13.1.6.2 Format

• Direct Format

Set the PRY bit in the U2MR register to “1”, the UFORM bit in the U2C0 register to “0” and the U2LCH

bit in the U2C1 register to “0”.

• Inverse Format

Set the PRY bit to “0”, UFORM bit to “1” and U2LCH bit to “1”.

Figure 13.1.6.2.1 shows the SIM interface format.

Figure 13.1.6.2.1. SIM Interface Format

P : Even parity

D0 D1 D2 D3 D4 D5 D6 D7 P

Transfer

clcck

TxD

D7 D6 D5 D4 D3 D2 D1 D0 P

Transfer

clcck

(1) Direct format

“H”

“L”

“H”

“L”

(2) Inverse format

P : Odd parity

“H”

“L”

“H”

“L”

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Item Performance

A/D Conversion Method Successive approximation (capacitive coupling amplifier)

Analog Input Voltage

(1)

0V to AVCC (VCC)

Operating Clock fAD

(2)

fAD/divided-by-2 or fAD/divided-by-3 or fAD/divided-by-4 or fAD/divided-by-6

or fAD/divided-by-12 or fAD

Resolution 8-bit or 10-bit (selectable)

Integral Nonlinearity Error When AVCC = VREF = 5V

• With 8-bit resolution: ±2LSB

• With 10-bit resolution: ±3LSB

When AVCC = VREF = 3.3V

• With 8-bit resolution: ±2LSB

• With 10-bit resolution: ±5LSB

Operating Modes

One-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, repeat

sweep mode 1, simultaneous sample sweep mode and delayed trigger mode 0,1

Analog Input Pins

(3)

8 pins (AN0 to AN7) + 3 pins (AN30 to AN32) + 1 pins (AN24) (48-pin package)

8 pins (AN0 to AN7) + 2 pins (AN30, AN31) (42-pin package)

Conversion Speed Per Pin

•Without sample and hold function

8-bit resolution: 49

fAD

cycles

10-bit resolution: 59

fAD

cycles

• With sample and hold function

8-bit resolution: 28

fAD

cycles

10-bit resolution: 33

fAD

cycles

Table 14.1 A/D Converter Performance

NOTES:

1. Not dependent on use of sample and hold function.

2. Set the φAD frequency to 10 MHz or less. For M16C/26B, set it to 12 MHz or less.

Without sample-and-hold function, set the fAD frequency to 250kHZ or more.

With the sample and hold function, set the fAD frequency to 1MHZ or more.

14. A/D Converter

Note

P92 and P93 (AN32, AN24) are not available in the 42-pin package.

Do not use P92 and P93 (AN32, AN24) as analog input pins in the 42-pin package.

The microcomputer contains one A/D converter circuit based on 10-bit successive approximation method

configured with a capacitive-coupling amplifier. The analog inputs share the pins with P100 to P107 (AN0 to

___________

AN7), P90 to P93 (AN30 to AN32, AN24). Similarly, ADTRG input shares the pin with P15. Therefore, when

using these inputs, make sure the corresponding port direction bits are set to “0” (input mode).

When not using the A/D converter, set the VCUT bit to “0” (VREF unconnected), so that no current will flow

from the VREF pin into the resistor ladder, helping to reduce the power consumption of the chip.

The A/D conversion result is stored in the i bits in the A/D register for ANi, AN3i, and AN2i pins (i = 0 to 7).

Table 14.1 shows the A/D converter performance. Figure 14.1 shows the A/D converter block diagram

and Figures 14.2 to 14.4 show the A/D converter associated with registers.

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Figure 14.1 A/D Converter Block Diagram

=0002

=0012

=0102

=0112

=1002

=1012

=1102

=1112

ref

CH2 to CH0

Decoder

for channel

selection

A/D register 0(16)

Data bus low-order

REF

VCUT=0

VCUT=1

Data bus high-order

Port P10 group

Port P9 group

ADGSEL1 to ADGSEL0=012

ADGSEL1 to ADGSEL0=002

ADGSEL1 to ADGSEL0=112

CKS0=1

CKS0=0

CKS1=1

CKS1=0

1/3

CKS2=0

CKS2=1

1/21/2ø

A/D conversion rate

selection

(03C1

to 03C0

)

(03C3

to 03C2

)

(03C5

to 03C4

)

(03C7

to 03C6

)

(03C9

to 03C8

)

(03CB

to 03CA

)

(03CD

to 03CC

)

(03CF

to 03CE

)

Resistor ladder

Successive conversion register

ADCON0 register

(address 03D616)

ADCON1 register

(address 03D716)

Comparator 0

Addresses

Decoder

for A/D register

A/D register 1(16)

A/D register 2(16)

A/D register 3(16)

A/D register 4(16)

A/D register 5(16)

A/D register 6(16)

A/D register 7(16)

ADCON2 register

(address 03D4

)

Port P9 group

=0002

=0012

=0102

=1002

CH2 to CH0

SSE = 1

CH2 to CH0=0012

Comparator 1

ADGSEL1 to ADGSEL0=002

ADGSEL1 to ADGSEL0=012

IN1

(1)

NOTE:

1. AN32 and AN24 are available for only 48-pin package.

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Figure 14.2 ADCON0 to ADCON2 Registers

A/D control register 0 (1)Symbol Address After reset

ADCON0 03D6

00000XXX

b7 b6 b5 b4 b3 b2 b1 b0

Analog Input Pin Select

Bit

CH0

Bit symbol Bit name Function

CH1

CH2

A/D Operation Mode

Select Bit 0 0 0 : One-shot mode or Delayed trigger mode 0,1

0 1 : Repeat mode

1 0 : Single sweep mode or

Simultaneous sample sweep mode

1 1 : Repeat sweep mode 0 or Repeat sweep

mode 1

MD0

MD1

Trigger Select Bit 0 : Software trigger

1 : Hardware trigger

TRG

ADST A/D Conversion Start Flag 0 : A/D conversion disabled

1 : A/D conversion started

Frequency Select Bit 0 See Table 14.2 A/D Conversion

Frequency Select

CKS0

A/D control register 1 (1)

Symbol Address After reset

ADCON1 03D7

Bit name Function

Bit symbol

b7 b6 b5 b4 b3 b2 b1 b0

A/D Sweep Pin Select Bit

SCAN0

SCAN1

MD2

BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode

1 : 10-bit mode

VCUT V

REF

Connect Bit

(2)

A/D Operation Mode

Select Bit 1 0 : Other than repeat sweep mode 1

1 : Repeat sweep mode 1

0 : V

REF

not connected

1 : V

REF

connected

b4 b3

NOTE:

1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.

Frequency Select Bit 1

CKS1

Function varies with each operation mode

See Table 14.2 A/D Conversion

Frequency Select

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

(b7-b6)

NOTES:

1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.

2. If the VCUT bit is reset from “0” (V

REF

unconnected) to “1” (V

REF

connected), wait for 1 µs or more before starting

A/D conversion

NOTE:

1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.

A/D control register 2 (1)

Symbol Address After reset

ADCON2 03D416 0016

b7 b6 b5 b4 b3 b2 b1 b0

A/D Conversion Method

Select Bit 0 : Without sample and hold

1 : With sample and hold

Bit symbol Bit name Function RW

SMP

Reserved Bit Set to “0”

A/D Input Group Select Bit 0 0 : Select port P10 group

0 1 : Select port P9 group (AN3i)

1 0 : Do not set

1 1 : Select port P9 group (AN24)

b2 b1

Frequency Select Bit 2

CKS2

ADGSEL0

ADGSEL1

(b3)

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

(b7-b6)

TRG1 Trigger Select Bit

See Table 14.2 A/D Conversion

Frequency Select

Function varies with each operation

mode

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A/D trigger control register (1,2)

Symbol

Address

After reset

ADTRGCON 03D2

b7 b6 b5 b4 b3 b2 b1 b0

A/D Operation Mode

Select Bit 2 0 : Other than simultaneous sample sweep

mode or delayed trigger mode 0,1

1 : Simultaneous sample sweep mode or

delayed trigger mode 0,1

Bit symbol Bit name Function RW

SSE

A/D Operation Mode

Select Bit 3

HPTRG1

DTE

HPTRG0

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

(b7-b4)

0 : Other than delayed trigger mode 0,1

1 : Delayed trigger mode 0,1

AN1 Trigger Select Bit

AN0 Trigger Select Bit Function varies with each operation mode

Function varies with each operation mode

NOTES:

1. If the ADTRGCON register is rewritten during A/D conversion, the conversion result will be indeterminate.

2. Set “00

” in this register in one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0 and repeat sweep

mode 1.

Figure 14.3 ADTRGCON Register

CKS2 CKS1 CKS0 Ø

000

001

010

100

101

110

111

Divided-by-4 of f

Divided-by-2 of f

Divided-by-12 of f

011

Divided-by-6 of f

Divided-by-3 of f

Table 14.2 A/D Conversion Frequency Select

NOTE:

1. Set the φAD frequency to 10 MHz or less (12 MHz or less in M16C/26B). The φAD is selected with

combinations of the CKS0 bit in the ADCON0 register, CKS1 bit in the ADCON1 register, and the

CKS2 bit in the ADCON2 register.

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Figure 14.4 ADSTAT0 Register and AD0 to AD7 Registers

A/D Register i (i=0 to 7) Symbol Address After reset

AD0 03C116 to 03C016 Indeterminate

AD1 03C316 to 03C216 Indeterminate

AD2 03C516 to 03C416 Indeterminate

AD3 03C716 to 03C616 Indeterminate

AD4 03C916 to 03C816 Indeterminate

AD5 03CB16 to 03CA16 Indeterminate

AD6 03CD16 to 03CC16 Indeterminate

AD7 03CF16 to 03CE16 Indeterminate

Eight low-order bits of

A/D conversion result

Function

(b15) b7b7 b0 b0

(b8)

When the BITS bit in the ADCON1

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

When read, its content is

indeterminate

Two high-order bits of

A/D conversion result

When the BITS bit in the ADCON1

A/D conversion result

A/D conversion status register 0 (1)

Symbol

Address

After reset

ADSTAT0 03D316 0016

b7 b6 b5 b4 b3 b2 b1 b0

AN1 Trigger Status Flag 0 : AN1 trigger did not occur during

AN0 conversion

1 : AN1 trigger occured during AN0

conversion

Bit symbol Bit name Function RW

ADERR0

Conversion Termination

Flag

AN0 Conversion Status

Flag

ADSTT0

ADERR1

ADTCSF

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

(b2)

ADSTRT0 AN0 Conversion

Completion Status Flag

0 : Conversion not terminated

1 : Conversion terminated by

Timer B0 underflow

Delayed Trigger Sweep

Status Flag 0 : Sweep not in progress

1 : Sweep in progress

0 : AN0 conversion not in progress

1 : AN0 conversion in progress

ADSTT1

0 : AN0 conversion not completed

1 : AN0 conversion completed

ADSTRT1

AN1 Conversion Status

Flag 0 : AN1 conversion not in progress

1 : AN1 conversion in progress

AN1 Conversion

Completion Status Flag 0 : AN1 conversion not completed

1 : AN1 conversion completed

NOTE:

1. ADSTAT0 register is valid only when the DTE bit in the ADTRGCON register is set to “1”.

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Figure 14.5 TB2SC Register

PWCOM

Symbol Address After reset

TB2SC 039E

X0000000

Timer B2 Reload Timing

Switch Bit 0 : Timer B2 underflow

1 : Timer A output at odd-numbered

Timer B2 special mode register

(1)

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

IVPCR1 Three-Phase Output Port

SD Control Bit 1 0 : Three-phase output forcible cutoff

by SD pin input (high impedance)

disabled

1 : Three-phase output forcible cutoff

by SD pin input (high impedance)

enabled

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

(b7)

TB2SEL Trigger Select Bit 0 : TB2 interrupt

1 : Underflow of TB2 interrupt

generation frequency setting counter [ICTB2]

TB0EN Timer B0 Operation Mode

Select Bit 0 : Other than A/D trigger mode

1 : A/D trigger mode

(5)

TB1EN Timer B1 Operation Mode

Select Bit 0 : Other than A/D trigger mode

1 : A/D trigger mode

(5)

(2)

(3, 4, 7)

(6)

(b6-b5) Reserved bits Must set to "0"

NOTES:

1. Write to this register after setting the PRC1 bit in the PRCR register to "1" (write enabled).

2. If the INV11 bit is "0" (three-phase mode 0) or the INV06 bit is "1" (triangular wave modulation mode), set this bit to

"0" (timer B2 underflow).

3. When setting the IVPCR1 bit to "1" (three-phase output forcible cutoff by SD pin input enabled), Set the PD8_5 bit to

"0" (= input mode).

4. Related pins are U(P8

), U(P8

), V(P7

), W(P7

). When a high-level ("H") signal is applied to the SD

pin and set the IVPCR1 bit to 0 after forcible cutoff, pins U, U, V, V, W, and W are exit from the high-impedance state.

If a low-level (“L”) signal is applied to the SD pin, three-phase motor control timer output will be disabled (INV03=0).

At this time, when the IVPCR1 bit is 0, pins U, U, V, V, W, and W become programmable I/O ports. When the IVPCR1

bit is set to 1, pins U, U, V, V, W, and W are placed in a high-impedance state regardless of which function of those

pins is used.

5. When this bit is used in delayed trigger mode 0, set the TB0EN and TB1EN bits to "1"(A/D trigger mode).

6. When setting the TB2SEL bit to "1" (underflow of TB2 interrupt generation frequency setting counter[ICTB2]), Set the

INV02 bit to "1" (three-phase motor control timer function).

7. Re

er to 16.6 Digita

Debou

ctio

or SD input.

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14.1 Operation Modes

14.1.1 One-Shot Mode

In one-shot mode, analog voltage applied to a selected pin is once converted to a digital code. Table

14.1.1.1 shows the one-shot mode specifications. Figure 14.1.1.1 shows the operation example in one-

shot mode. Figure 14.1.1.2 shows the ADCON0 to ADCON2 registers in one-shot mode.

Table 14.1.1.1 One-shot Mode Specifications

Item Specification

Function The CH2 to CH0 bits in the ADCON0 register and the ADGSEL1 to

ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to

a selected pin is once converted to a digital code

A/D Conversion Start

• When the TRG bit in the ADCON0 register is “0” (software trigger)

Condition

Set the ADST bit in the ADCON0 register to “1” (A/D conversion started)

• When the TRG bit in the ADCON0 register is “1” (hardware trigger)

___________

The ADTRG pin input changes state from “H” to “L” after setting the

ADST bit to “1” (A/D conversion started)

A/D Conversion Stop • A/D conversion completed (If a software trigger is selected, the ADST bit is

Condition set to “0” (A/D conversion halted)).

• Set the ADST bit to “0”

Interrupt Request Generation Timing

A/D conversion completed

Analog Input Pin

Select one pin from AN

to AN

, AN

to AN

, AN

Readout of A/D Conversion Result

Readout one of the AD0 to AD7 registers that corresponds to the selected pin

Figure 14.1.1.1 Operation Example in One-Shot Mode

•Example when selecting AN2 to an analog input pin (Ch2 to CH0=0102)

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

A/D conversion started

A/D interrupt request generated

A/D pin input voltage

sampling

A/D pin conversion

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A/D control register 0 (1)

Symbol

Address

After reset

ADCON0

03D616

00000XXX2

b7 b6 b5 b4 b3 b2 b1 b0

Analog Input Pin

Select Bit (2, 3)

CH0

Bit symbol Bit name Function

CH1

CH2

A/D Operation Mode

Select Bit 0 (3)

MD0

MD1Trigger Select Bit

TRG

ADST A/D Conversion Start

Flag 0 : A/D conversion disabled

1 : A/D conversion started

Frequency Select Bit 0CKS0

A/D control register 1 (1)

Symbol

Address

After reset

ADCON1

03D716

0016

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

A/D Sweep Pin

Select Bit

SCAN0

SCAN1

MD2

BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode

1 : 10-bit mode

VCUT VREF Connect Bit (2)

A/D Operation Mode

Select Bit 1

1 : VREF connected

0 0 : One-shot mode or delayed trigger mode

0,1

b4 b3

Frequency Select Bit 1

CKS1

0 : Any mode other than repeat sweep

mode 1

See Table 14.2 A/D Conversion

Frequency Select

Refer to Table 14.2 A/D Conversion

Frequency Select

(b7-b6)

NOTE:

1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.

A/D control register 2 (1)

Symbol

Address

After reset

ADCON2 03D416 0016

b7 b6 b5 b4 b3 b2 b1 b0

A/D Conversion Method

Select Bit

Bit symbol Bit name Function RW

SMP

Reserved Bit Set to

“0”

A/D Input Group Select

Bit 0 0 : Select port P10 group (ANi)

0 1 : Select port P9 group (AN3i)

1 0 : Do not set

1 1 : Select port P9 group (AN24)

b2 b1

Frequency Select Bit 2

CKS2

ADGSEL0

ADGSEL1

(b3)

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

(b7-b6)

TRG1 Trigger Select Bit 1

b2 b1 b0

0 0 0 : Select AN0

0 0 1 : Select AN1

0 1 0 : Select AN2

0 1 1 : Select AN3

1 0 0 : Select AN4

1 0 1 : Select AN5

1 1 0 : Select AN6

1 1 1 : Select AN7

0 : Software trigger

1 : Hardware trigger (ADTRG trigger)

Invalid in one-shot mode

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

0 : Without sample and hold

1 : With sample and hold

Set to "0" in one-shot mode

See Table 14.2 A/D Conversion

Frequency Select

NOTES:

1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.

2. AN30 to AN32 and AN24 can be used in the same way as AN0 to AN7 . Use the ADGSEL1 to ADGSEL0 bits in the

ADCON2 register to select the desired pin.

3. After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using an another instruction.

NOTES:

1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.

2. If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before starting A/D

conversion.

Figure 14.1.1.2 ADCON0 to ADCON2 Registers in One-Shot Mode

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14.1.2 Repeat mode

In repeat mode, analog voltage applied to a selected pin is repeatedly converted to a digital code. Table

14.1.2.1 shows the repeat mode specifications. Figure 14.1.2.1 shows the operation example in repeat

mode. Figure 14.1.2.2 shows the ADCON0 to ADCON2 registers in repeat mode.

Item Specification

Function The CH2 to CH0 bits in the ADCON0 register and the ADGSEL1 to ADGSEL0

bits in the ADCON2 register select pins. Analog voltage applied to a selected

pin is repeatedly converted to a digital code

A/D Conversion Start

• When the TRG bit in the ADCON0 register is “0” (software trigger)

Condition

Set the ADST bit in the ADCON0 register to “1” (A/D conversion started)

• When the TRG bit in the ADCON0 register is “1” (hardware trigger)

The ADTRG pin input changes state from “H” to “L” after setting the ADST bit

to “1” (A/D conversion started)

A/D Conversion Stop Condition

Set the ADST bit to “0” (A/D conversion halted)

Interrupt Request Generation Timing

None generated

Analog Input Pin

Select one pin from AN

to AN

, AN

to AN

and AN

Readout of A/D Conversion Result

Readout one of the AD0 to AD7 registers that corresponds to the selected pin

Table 14.1.2.1 Repeat Mode Specifications

Figure 14.1.2.1 Operation Example in Repeat Mode

•Example when selecting AN

to an analog input pin

(Ch2 toCH0=010

)

A/D conversion started

A/D pin input voltage

sampling

A/D pin conversion

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A/D control register 0 (1)

Symbol

Address

After reset

ADCON0

03D6

00000XXX

b7 b6 b5 b4 b3 b2 b1 b0

Analog Input Pin

Select Bit (2, 3)

CH0

Bit symbol Bit name Function

CH1

CH2

A/D Operation Mode

Select Bit 0 (3)

MD0

MD1Trigger Select Bit

TRG

ADST A/D Conversion Start

Flag 0 : A/D conversion disabled

1 : A/D conversion started

Frequency Select Bit 0CKS0

A/D control register 1 (1)

Symbol

Address

After reset

ADCON1

03D7

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

A/D Sweep Pin

Select Bit

SCAN0

SCAN1

MD2

BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode

1 : 10-bit mode

VCUT V

REF

connect bit (2)

A/D Operation Mode

Select Bit 1

1 : V

REF

connected

0 1 : Repeat mode

b4 b3

Frequency Select Bit 1

CKS1

0 : Any mode other than repeat sweep

mode 1

Refer to Table 14.2 A/D Conversion

Frequency Select

Refer to Table 14.2 A/D Conversion

Frequency Select

(b7-b6)

NOTE:

1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.

A/D control register 2 (1)

Symbol

Address

After reset

ADCON2 03D4

b7 b6 b5 b4 b3 b2 b1 b0

A/D Conversion Method

Select Bit

Bit symbol Bit name Function RW

SMP

Reserved Bit Set to

“0”

A/D Input Group Select

Bit 0 0 : Select port P10 group (AN

)

0 1 : Select port P9 group (AN

)

1 0 : Do not set

1 1 : Select port P9 group (AN

)

b2 b1

Frequency Select Bit 2

CKS2

ADGSEL0

ADGSEL1

(b3)

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

(b7-b6)

See Table 14.2 A/D Conversion

Frequency Select

TRG1 Trigger Select Bit 1

b2 b1 b0

0 0 0 : Select AN

0 0 1 : Select AN

0 1 0 : Select AN

0 1 1 : Select AN

1 0 0 : Select AN

1 0 1 : Select AN

1 1 0 : Select AN

1 1 1 : Select AN

0 : Software trigger

1 : Hardware trigger (AD

TRG

trigger)

Invalid in repeat mode

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

0 : Without sample and hold

1 : With sample and hold

Set to "0" in repeat mode

NOTES:

1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.

2. If the VCUT bit is reset from “0” (V

REF

unconnected) to “1” (V

REF

connected), wait for 1 µs or more before starting

A/D conversion.

NOTES:

1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.

2. AN

to AN

and AN

can be used in the same way as AN

to AN

. Use the ADGSEL1 to ADGSEL0 bits in the

ADCON2 register to select the desired pin.

3. After rewriting the MD1 to MD0 bits, set the CH2 to CH0 bits over again using an another instruction.

Figure 14.1.2.2 ADCON0 to ADCON2 Registers in Repeat Mode

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14.1.3 Single Sweep Mode

In single sweep mode, analog voltages applied to the selected pins are converted one-by-one to a digital

code. Table 14.1.3.1 shows the single sweep mode specifications. Figure 14.1.3.1 shows the operation

example in single sweep mode. Figure 14.1.3.2 shows the ADCON0 to ADCON2 registers in single

sweep mode.

Item Specification

Function The SCAN1 to SCAN0 bits in the ADCON1 register and the ADGSEL1 to

ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to

the selected pins is converted one-by-one to a digital code

A/D Conversion Start Condition

• When the TRG bit in the ADCON0 register is “0” (software trigger)

Set the ADST bit in the ADCON0 register to “1” (A/D conversion started)

• When the TRG bit in the ADCON0 register is “1” (hardware trigger)

The ADTRG pin input changes state from “H” to “L” after setting the ADST bit

to “1” (A/D conversion started)

A/D Conversion Stop Condition

• A/D conversion completed(When selecting a software trigger, the ADST bit

is set to “0” (A/D conversion halted)).

• Set the ADST bit to “0”

Interrupt Request Generation Timing

A/D conversion completed

Analog Input Pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins),

AN0 to AN7 (8 pins) (1)

Readout of A/D Conversion Result

Readout one of the AD0 to AD7 registers that corresponds to the selected pin

Table 14.1.3.1 Single Sweep Mode Specifications

NOTE:

1. AN30 to AN32 can be used in the same way as AN0 to AN7. However, all input pins need to belong to

the same group.

Figure 14.1.3.1 Operation Example in Single Sweep Mode

•Example when selecting AN

to AN

to analog input pins (SCAN1 to SCAN0=01

)

A/D conversion started

A/D interrupt request generated

A/D pin input voltage

sampling

A/D pin conversion

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A/D control register 0 (1)

Symbol

Address

After reset

ADCON0

03D6

00000XXX

b7 b6 b5 b4 b3 b2 b1 b0

Analog Input Pin

Select Bit

CH0

Bit symbol Bit name Function

CH1

CH2

A/D Operation Mode

Select Bit 0

MD0

MD1Trigger Select Bit

TRG

ADST A/D Conversion Start

Flag 0 : A/D conversion disabled

1 : A/D conversion started

Frequency Select Bit 0CKS0

A/D control register 1 (1)

Symbol

Address

After reset

ADCON1

03D7

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

A/D Sweep Pin

Select Bit (2)

SCAN0

SCAN1

MD2

BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode

1 : 10-bit mode

VCUT VREF Connect Bit (3)

A/D Operation Mode

Select Bit 1

1 : VREF connected

Frequency Select Bit 1

CKS1

0 : Any mode other than repeat sweep

mode 1

Refer to Table 14.2 A/D Conversion

Frequency Select

Refer to Table 14.2 A/D Conversion

Frequency Select

(b7-b6)

NOTE:

1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.

A/D control register 2 (1)

Symbol

Address

After reset

ADCON2 03D416 0016

b7 b6 b5 b4 b3 b2 b1 b0

A/D Conversion Method

Select Bit

Bit symbol Bit name Function RW

SMP

Reserved Bit Set to

“0”

A/D Input Group

Select Bit 0 0 : Select port P10 group (AN i)

0 1 : Select port P9 group (AN3i)

1 0 : Do not set

1 1 : Do not set

b2 b1

Frequency Select Bit 2

CKS2

ADGSEL0

ADGSEL1

(b3)

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

(b7-b6)

Refer to Table 14.2 A/D Conversion

Frequency Select

TRG1 Trigger Select Bit 1

NOTE:

1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.

0 : Software trigger

1 : Hardware trigger (ADTRG trigger)

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

0 : Without sample and hold

1 : With sample and hold

Set to "0" in single sweep mode

Invalid in single sweep mode

1 0 : Single sweep mode or simultaneous

sample sweep mode

b4 b3

When selecting single sweep mode

0 0 : AN0 to AN1 (2 pins)

0 1 : AN0 to AN3 (4 pins)

1 0 : AN0 to AN5 (6 pins)

1 1 : AN0 to AN7 (8 pins)

b1 b0

NOTES:

1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.

2. AN30 to AN32 can be used in the same way as AN0 to AN7. Use the ADGSEL1 to ADGSEL0 bits in the ADCON2

3. If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREFconnected), wait for 1 µs or more before starting A/D

conversion.

Figure 14.1.3.2 ADCON0 to ADCON2 Registers in Single Sweep Mode

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Item Specification

Function The SCAN1 to SCAN0 bits in the ADCON1 register and the ADGSEL1 to

ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to

the selected pins is repeatedly converted to a digital code

A/D Conversion Start Condition

• When the TRG bit in the ADCON0 register is “0” (software trigger)

Set the ADST bit in the ADCON0 register to “1” (A/D conversion started)

• When the TRG bit in the ADCON0 register is “1” (Hardware trigger)

The ADTRG pin input changes state from “H” to “L” after setting the ADST bit

to “1” (A/D conversion started)

A/D Conversion Stop Condition

Set the ADST bit to “0” (A/D conversion halted)

Interrupt Request Generation Timing

None generated

Analog Input Pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins),

AN0 to AN7 (8 pins) (1)

Readout of A/D Conversion Result

Readout one of the AD0 to AD7 registers that corresponds to the selected pin

14.1.4 Repeat Sweep Mode 0

In repeat sweep mode 0, analog voltages applied to the selected pins are repeatedly converted to a

digital code. Table 14.1.4.1 shows the repeat sweep mode 0 specifications. Figure 14.1.4.1 shows the

operation example in repeat sweep mode 0. Figure 14.1.4.2 shows the ADCON0 to ADCON2 registers in

repeat sweep mode 0.

Table 14.1.4.1 Repeat Sweep Mode 0 Specifications

NOTE:

1. AN30 to AN32 can be used in the same way as AN0 to AN7. However, all input pins need to belong to

the same group.

Figure 14.1.4.1 Operation Example in Repeat Sweep Mode 0

•Example when selecting AN

to AN

to analog input pins (SCAN1 to SCAN0=01

)

A/D conversion started

A/D pin input voltage

sampling

A/D pin conversion

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A/D control register 1 (1)

Symbol Address After reset

ADCON1 03D7

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

A/D Sweep Pin

Select Bit

(2)

SCAN0

SCAN1

MD2

BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode

1 : 10-bit mode

VCUT V

REF

Connect Bit

(3)

A/D Operation Mode

Select Bit 1

1 : V

REF

connected

Frequency Select Bit 1

CKS1

0 : Any mode other than repeat sweep

mode 1

Refer to Table 14.2 A/D Conversion

Frequency Select

(b7-b6) Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

When selecting repeat sweep mode 0

0 0 : AN

to AN

(2 pins)

0 1 : AN

to AN

(4 pins)

1 0 : AN

to AN

(6 pins)

1 1 : AN

to AN

(8 pins)

b1 b0

NOTE:

1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.

A/D control register 2 (1)

Symbol Address After reset

ADCON2 03D4

b7 b6 b5 b4 b3 b2 b1 b0

A/D Conversion Method

Select Bit

Bit symbol Bit name Function RW

SMP

Reserved Bit Set to “0”

A/D Input Group

Select Bit 0 0 : Select port P10 group (AN

)

0 1 : Select port P9 group (AN

)

1 0 : Do not set

1 1 : Do not set

b2 b1

Frequency Select Bit 2

CKS2

ADGSEL0

ADGSEL1

(b3)

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

(b7-b6)

Refer to Table 14.2 A/D Conversion

Frequency Select

TRG1 Trigger Select Bit 1

0 : Without sample and hold

1 : With sample and hold

Set to "0" in repeat sweep mode 0

A/D control register 0 (1)

Symbol Address After reset

ADCON0 03D6

00000XXX

b7 b6 b5 b4 b3 b2 b1 b0

Analog Input Pin

Select Bit

CH0

Bit symbol Bit name Function

CH1

CH2

A/D Operation Mode

Select Bit 0

MD0

MD1

Trigger Select Bit

TRG

ADST A/D Conversion Start

Flag 0 : A/D conversion disabled

1 : A/D conversion started

Frequency Select Bit 0

CKS0

Refer to Table 14.2 A/D Conversion

Frequency Select

NOTE:

1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.

0 : Software trigger

1 : Hardware trigger (AD

TRG

trigger)

Invalid in repeat sweep mode 0

1 1 : Repeat sweep mode 0 or

Repeat sweep mode 1

b4 b3

NOTES:

1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.

2. AN

to AN

can be used in the same way as AN

to AN

. Use the ADGSEL1 to ADGSET0 bits in the ADCON2

3. If the VCUT bit is reset from “0” (V

REF

unconnected) to “1” (V

REF

connected), wait for 1 µs or more before starting A/D

conversion.

Figure 14.1.4.2 ADCON0 to ADCON2 Registers in Repeat Sweep Mode 0

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14.1.5 Repeat Sweep Mode 1

In repeat sweep mode 1, analog voltages applied to the all selected pins are converted to a digital code,

with mainly used in the selected pins. Table 14.1.5.1 shows the repeat sweep mode 1 specifications.

Figure 14.1.5.1 shows the operation example in repeat sweep mode 1. Figure 14.1.5.2 shows the

ADCON0 to ADCON2 registers in repeat sweep mode 1.

Table 14.1.5.1 Repeat Sweep Mode 1 Specifications

Item Specification

Function The SCAN1 to SCAN0 bits in the ADCON1 register and the ADGSEL1 to

ADGSEL0 bits in the ADCON2 register mainly select pins. Analog voltage

applied to the all selected pins is repeatedly converted to a digital code

Example : When selecting AN0

Analog voltage is converted to a digital code in the following order

AN0 AN1 AN0 AN2 AN0 AN3, and so on.

A/D Conversion Start Condition

• When the TRG bit in the ADCON0 register is “0” (software trigger)

Set the ADST bit in the ADCON0 register to “1” (A/D conversion started)

• When the TRG bit in the ADCON0 register is “1” (hardware trigger)

The ADTRG pin input changes state from “H” to “L” after setting the ADST bit

to “1” (A/D conversion started)

A/D Conversion Stop Condition

Set the ADST bit to “0” (A/D conversion halted)

Interrupt Request Generation Timing

None generated

Analog Input Pins Mainly Select from AN0 (1 pins), AN0 to AN1 (2 pins), AN0 to AN2 (3 pins),

Used in A/D Conversions AN0 to AN3 (4 pins) (1)

Readout of A/D Conversion Result

Readout one of the AD0 to AD7 registers that corresponds to the selected pin

NOTE:

1. AN30 to AN32 can be used in the same way as AN0 to AN7. However, all input pins need to belong to

the same group.

Figure 14.1.5.1 Operation Example in Repeat Sweep Mode 1

•Example when selecting AN

to analog input pins (SCAN1 to SCAN0=00

)

A/D conversion started

A/D pin input voltage

sampling

A/D pin conversion

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A/D control register 0 (1)

Symbol Address After reset

ADCON0 03D616 00000XXX2

b7 b6 b5 b4 b3 b2 b1 b0

Analog Input Pin

Select Bit

CH0

Bit symbol Bit name Function

CH1

CH2

A/D Operation Mode

Select Bit 0

MD0

MD1

Trigger Select Bit

TRG

ADST A/D Conversion Start

Flag 0 : A/D conversion disabled

1 : A/D conversion started

Frequency Select Bit 0CKS0

A/D control register 1 (1)

Symbol Address After reset

ADCON1 03D716 00 16

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

A/D Sweep Pin

Select Bit (2)

SCAN0

SCAN1

MD2

BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode

1 : 10-bit mode

VCUT VREF Connect Bit (3)

A/D Operation Mode

Select Bit 1

1 : VREF connected

Frequency Select Bit 1

CKS1

1 : Repeat sweep mode 1

Refer to Table 14.2 A/D Conversion

Frequency Select

Refer to Table 14.2 A/D Conversion

Frequency Select

(b7-b6)

NOTE:

1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.

A/D control register 2 (1)

Symbol Address After reset

ADCON2 03D4h 00h

b7 b6 b5 b4 b3 b2 b1 b0

A/D Conversion Method

Select Bit

Bit symbol Bit name Function RW

SMP

Reserved Bit Set to “0”

A/D Input Group

Select Bit 0 0 : Select port P10 group (ANi)

0 1 : Select port P9 group (AN3i)

1 0 : Do not set

1 1 : Do not set

b2 b1

Frequency Select Bit 2

CKS2

ADGSEL0

ADGSEL1

(b3)

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

(b7-b6)

Refer to Table 14.2 A/D Conversion

Frequency Select

TRG1 Trigger Select Bit 1

NOTE:

1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.

0 : Software trigger

1 : Hardware trigger (ADTRG trigger)

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

0 : Without sample and hold

1 : With sample and hold

Set to "0" in repeat sweep mode 1

Invalid in repeat sweep mode 1

1 1 : Repeat sweep mode 0 or

Repeat sweep mode 1

b4 b3

When selecting repeat sweep mode 1

0 0 : AN0 (1 pin)

0 1 : AN0 to AN1 (2 pins)

1 0 : AN0 to AN2 (3 pins)

1 1 : AN0 to AN3 (4 pins)

b1 b0

NOTES:

1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.

2. AN30 to AN32 can be used in the same way as AN0 to AN7. Use the ADGSEL1 to ADGSEL0 bits in the ADCON2

3. If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before starting

A/D conversion.

Figure 14.1.5.2 ADCON0 to ADCON2 Registers in Repeat Sweep Mode 1

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Item Specification

Function The SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to

ADGSEL0 bits in the ADCON2 register select pins. Analog voltage applied to

the selected pins is converted one-by-one to a digital code. At this time, the

input voltage of AN0 and AN1 are sampled simultaneously.

A/D Conversion Start Condition

When the TRG bit in the ADCON0 register is "0" (software trigger)

Set the ADST bit in the ADCON0 register to “1” (A/D conversion started)

When the TRG bit in the ADCON0 register is "1" (hardware trigger)

The trigger is selected by TRG1 and HPTRG0 bits (See Table 14.1.6.2)

The ADTRG pin input changes state from “H” to “L” after setting the ADST bit

to “1” (A/D conversion started)

Timer B0, B2 or Timer B2 interrupt generation frequency setting counter

underflow after setting the ADST bit to “1” (A/D conversion started)

A/D Conversion Stop Condition

A/D conversion completed (If selecting software trigger, the ADST bit is

automatically set to "0".

Set the ADST bit to "0" (A/D conversion halted)

Interrupt Generation Timing A/D conversion completed

Analog Input Pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins), or

AN0 to AN7 (8 pins) (1)

Readout of A/D conversion result

Readout one of the AN0 to AN7 registers that corresponds to the selected pin

NOTE:

1. AN30 to AN32 can be used in the same way as AN0 to AN7. However, all input pins need to belong to

the same group.

14.1.6 Simultaneous Sample Sweep Mode

In simultaneous sample sweep mode, analog voltages applied to the selected pins are converted one-by-

one to a digital code. At this time, the input voltage of AN0 and AN1 are sampled simultaneously using two

circuits of sample and hold circuit. Table 14.1.6.1 shows the simultaneous sample sweep mode specifica-

tions. Figure 14.1.6.1 shows the operation example in simultaneous sample sweep mode. Figure

14.1.6.2 shows ADCON0 to ADCON2 registers and Figure 14.1.6.3 shows ADTRGCON registers in

simultaneous sample sweep mode. Table 14.1.6.2 shows the trigger select bit setting in simultaneous

sample sweep mode. In simultaneous sample sweep mode, Timer B0 underflow can be selected as a

trigger by combining software trigger, ADTRG trigger, Timer B2 underflow, Timer B2 interrupt generation

frequency setting counter underflow or A/D trigger mode of Timer B.

•Example when selecting AN

to analog input pins (SCAN1 to SCAN0=01

)

A/D conversion started

A/D interrupt request generated

A/D pin input voltage

sampling

A/D pin conversion

Figure 14.1.6.1 Operation Example in Simultaneous Sample Sweep Mode

Table 14.1.6.1 Simultaneous Sample Sweep Mode Specifications

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Figure 14.1.6.2 ADCON0 to ADCON2 Registers for Simultaneous Sample Sweep Mode

A/D control register 0 (1)

Symbol

Address

After reset

ADCON0

03D6

00000XXX

b7 b6 b5 b4 b3 b2 b1 b0

Analog Input Pin

Select Bit

CH0

Bit symbol Bit name Function

CH1

CH2

A/D Operation Mode

Select Bit 0

MD0

MD1

Trigger Select Bit

TRG

ADST A/D Conversion Start Fag 0 : A/D conversion disabled

1 : A/D conversion started

Frequency Select Bit 0CKS0

A/D control register 1 (1)

Symbol

Address

After reset

ADCON1

03D7

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

A/D Sweep Pin

Select Bit

(2)

SCAN0

SCAN1

MD2

BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode

1 : 10-bit mode

VCUT V

REF

Connect Bit

(3)

A/D Operation Mode

Select Bit 1

1 : V

REF

connected

Frequency Select Bit 1

CKS1

0 : Any mode other than repeat sweep

mode 1

Refer to Table 14.2 A/D Conversion

Frequency Select

Refer to Table 14.2 A/D Conversion

Frequency Select

(b7-b6)

NOTE:

1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.

A/D control register 2 (1)

Symbol

Address

After reset

ADCON2 03D4

b7 b6 b5 b4 b3 b2 b1 b0

A/D Conversion Method

Select Bit

Bit symbol Bit name Function RW

SMP

Reserved Bit Set to

“0”

A/D Input Group

Select Bit 0 0 : Select port P10 group (AN

)

0 1 : Select port P9 group (AN

)

1 0 : Do not set

1 1 : Do not set

b2 b1

Frequency Select Bit 2

CKS2

ADGSEL0

ADGSEL1

(b3)

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

(b7-b6)

Refer to Table 14.2 A/D Conversion

Frequency Select

TRG1 Trigger select bit 1

NOTE:

1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.

Refer to Table 14.1.6.2 Trigger Select Bit

Setting in Simultaneous Sample Sweep

Mode

Invalid in simultaneous sample sweep mode

1 0 : Single sweep mode or simultaneous

sample sweep mode

b4 b3

When selecting simultaneous sample sweep

mode

0 0 : AN

to AN

(2 pins)

0 1 : AN

to AN

(4 pins)

1 0 : AN

to AN

(6 pins)

1 1 : AN

to AN

(8 pins)

b1 b0

Refer to Table 14.1.6.2 Trigger Select Bit

Setting in Simultaneous Sample Sweep

Mode

Set to “1” in simultaneous sample

sweep mode

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

NOTES:

1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.

2. AN

to AN

can be used in the same way as AN

to AN

. Use the ADGSEL1 to ADGSET0 bits in the ADCON2

3. If the VCUT bit is reset from “0” (V

REF

unconnected) to “1” (V

REF

connected), wait for 1 µs or more before starting

A/D conversion.

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Figure 14.1.6.3 ADTRGCON Register in Simultaneous Sample Sweep Mode

A/D trigger control register (1)

Symbol Address After reset

ADTRGCON 03D216 0016

b7 b6 b5 b4 b3 b2 b1 b0

A/D Operation Mode

Select Bit 2

Bit symbol Bit name Function RW

SSE

A/D Operation Mode

Select Bit 3

AN1 Trigger Select Bit

HPTRG1

DTE

HPTRG0

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

(b7-b4)

AN0 Trigger Select Bit

NOTE:

1. If ADTRGCON register is rewritten during A/D conversion, the conversion result will be indeterminate.

0 : Any mode other than delayed trigger

mode 0,1

1 : Simultaneous sample sweep mode

or delayed trigger mode 0, 1

Refer to Table 14.1.6.2 Trigger Select

Bit Setting in Simultaneous Sample

Sweep Mode

Set to "0" in simultaneous sample

sweep mode

Table 14.1.6.2 Trigger Select Bit Setting in Simultaneous Sample Sweep Mode

TRG HPTRG0TRG1 TRIGGER

Software trigger

Timer B0 underflow (1)

Timer B2 or Timer B2 interrupt generation frequency

setting counter underflow (2)

TRG

NOTE:

1. A count can be started for Timer B2, Timer B2 interrupt generation frequency setting counter underflow or

the INT5 pin falling edge as count start conditions of Timer B0.

2. Select Timer B2 or Timer B2 interrupt generation frequency setting counter using the TB2SEL bit in the

TB2SC register.

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Item Specification

Function The SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to ADGSEL0 bits in

the ADCON2 register select pins. Analog voltage applied to the input voltage of the

selected pins are converted one-by-one to the digital code. At this time, Timer B0 under

flow generation starts AN0 pin conversion. Timer B1 underflow generation starts con

version after the AN1 pin. (1)

A/D Conversion Start

AN0 pin conversion start condition

•When Timer B0 underflow is generated if Timer B0 underflow is generated again

before Timer B1 underflow is generated , the conversion is not affected

•When Timer B0 underflow is generated during A/D conversion of pins after the AN1

pin, conversion is halted and the sweep is restarted from AN0 pin

AN1 pin conversion start condition

•When Timer B1 underflow is generated during A/D conversion of the AN0 pin, the

input voltage of the AN1 pin is sampled. The AN1 conversion and the rest of the

sweep start when AN0 conversion is completed.

A/D Conversion Stop

•When single sweep conversion from the AN0 pin is completed

Condition

•Set the ADST bit to "0" (A/D conversion halted)(2)

Interrupt Request A/D conversion completed

Generation Timing

Analog Input Pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins) and

AN0 to AN7 (8 pins)(3)

Readout of A/D Conversion Result

Readout one of the AN0 to AN7 registers that corresponds to the selected pins

NOTES:

1. Set the larger value than the value of the timer B0 register to the timer B1 register.

2. Do not write “1” (A/D conversion started) to the ADST bit in delayed trigger mode 0. When write “1”, unexpected

interrupts may be generated.

3. AN30 to AN32 can be used in the same way as AN0 to AN7. However, all input pins need to belong to the same

group.

14.1.7 Delayed Trigger Mode 0

In delayed trigger mode 0, analog voltages applied to the selected pins are converted one-by-one to a

digital code. The delayed trigger mode 0 used in combination with A/D trigger mode of Timer B. The

Timer B0 underflow starts a single sweep conversion. After completing the AN0 pin conversion, the AN1

pin is not sampled and converted until the Timer B1 underflow is generated. When the Timer B1 under-

flow is generated, the single sweep conversion is restarted with the AN1 pin. Table 14.1.7.1 shows the

delayed trigger mode 0 specifications. Figure 14.1.7.1 shows the operation example in delayed trigger

mode 0. Figure 14.1.7.2 and Figure 14.1.7.3 show each flag operation in the ADSTAT0 register that

corresponds to the operation example. Figure 14.1.7.4 shows the ADCON0 to ADCON2 registers in

delayed trigger mode 0. Figure 14.1.7.5 shows the ADTRGCON register in delayed trigger mode 0 and

Table 14.1.7.2 shows the trigger select bit setting in delayed trigger mode 0.

Table 14.1.7.1 Delayed Trigger Mode 0 Specifications

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Timer B0 underflow

A/D pin input

voltage sampling

A/D pin conversion

Timrt B0 underflow

(An interrupt does not affect A/D conversion)

Timer B0 underflow

Timer B1 underflow

•Example when selecting AN

to AN

to analog input pins (SCAN1 to SCAN0=01

)

•Example 1: When Timer B1 underflow is generated during AN

pin conversion

Timer B0 underflow

Timer B1 underflow

•Example 2: When Timer B1 underflow is generated after AN

pin conversion

Timer B0 underflow

(Abort othrt pins conversion)

Timer B0 underflow

Timer B1 under flow

Timer B1 underflow

•Example 3: When Timer B0 underflow is generated during A/D conversion of any pins except AN

•Example 4: When Timer B0 underflow is generated again before Timer B1 underflow is generated

after Timer B0 underflow generation

Figure 14.1.7.1 Operation Example in Delayed Trigger Mode 0

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Figure 14.1.7.2 Each Flag Operation in ADSTAT0 Register Associated with the Operation

Example in Delayed Trigger Mode 0 (1)

AN0

AN1

AN2

AN3

Timer B0 underflow

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

AN0

AN1

AN2

AN3

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

A/D pin input

voltage sampling

A/D pin conversion

Do not set to "1" by program

Set to "0" by an interrupt request acknowledgement or a program

Set to “0" by program

Set to "0" by program

ADST flag: Bit 6 in the ADCON0 register

ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register

ADST flag

ADERR0 flag

ADERR1 flag

ADTCSF flag

ADSTT0 flag

ADSTT1 flag

ADSTRT0 flag

ADSTRT1 flag

IR bit in the ADIC

ADST flag

ADERR0 flag

ADERR1 flag

ADTCSF flag

ADSTT0 flag

ADSTT1 flag

ADSTRT0 flag

ADSTRT1 flag

IR bit in the ADIC

Timer B0 underflow

Timer B1 underflow

•Example when selecting AN0 to AN3 to analog input pins (SCAN1 to SCAN0=012)

•Example 1: When Timer B1 underflow is generated during AN0 pin conversion

•Example 2: When Timer B1 underflow is generated after AN0 pin conversion

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AN0

AN1

AN2

AN3

Timer B0 underflow

(Abort othrt pins conversion )

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

A/D pin input

voltage sampling

A/D pin conversion

Do not set to "1" by program

Set to "0" by interrupt request acknowledgement or a program

Set to "0" by program

ADST flag: Bit 6 in the ADCON0 register

ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register

ADST flag

ADERR0 flag

ADERR1 flag

ADTCSF flag

ADSTT0 flag

ADSTT1 flag

ADSTRT0 flag

ADSTRT1 flag

IR bit in the ADIC

Timer B0 underflow

Timer B1 underflow

•Example 3: When Timer B0 underflow is generated during A/D pin conversion of any pins except AN0 pin

AN0

AN1

AN2

AN3

Timrt B0 underflow

(An interrupt does not affect A/D conversion)

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

Do not set to "1" by program

Set to "0" by interrupt request acknowledgement or a program

Set to "0" by program

ADST flag

ADERR0 flag

ADERR1 flag

ADTCSF flag

ADSTT0 flag

ADSTT1 flag

ADSTRT0 flag

ADSTRT1 flag

IR bit in the ADIC

Timer B0 underflow

Timer B1 underflow

•Example 4: After Timer B0 underflow is generated and when Timer B0 underflow is generated again

before Timer B1 underflow is genetaed

Figure 14.1.7.3 Each Flag Operation in ADSTAT0 Register Associated with the Operation

Example in Delayed Trigger Mode 0 (2)

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Figure 14.1.7.4 ADCON0 to ADCON2 Registers in Delayed Trigger Mode 0

A/D control register 0 (1)

Symbol

Address

After reset

ADCON0

03D616

00000XXX2

b7 b6 b5 b4 b3 b2 b1 b0

Analog Input Pin

Select Bit

CH0

Bit symbol Bit name Function

CH1

CH2

A/D Operation Mode

Select Bit 0

MD0

MD1Trigger Select Bit Refer to Table 14.1.7.2 Trigger Select Bit

Setting in Delayed Trigger Mode 0

TRG

ADST A/D Conversion Start

Flag

(2)

0 : A/D conversion disabled

1 : A/D conversion started

Frequency Select Bit 0CKS0

A/D control register 1 (1)

Symbol

Address

After reset

ADCON1

03D716

0016

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

A/D Sweep Pin

Select Bit

(2)

SCAN0

SCAN1

MD2

BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode

1 : 10-bit mode

VCUT V

REF

Connect Bit

(3)

A/D Operation Mode

Select Bit 1

1 : V

REF

connected

When selecting delayed trigger sweep mode 0

1 1 1 : Set to "111b" in delayed trigger

mode 0

b2 b1 b0

0 0 : One-shot mode or delayed trigger mode

0,1

b4 b3

Frequency Select Bit 1

CKS1

0 : Any mode other than repeat sweep

mode 1

Refer to Table 14.2 A/D Conversion

Frequency Select

Refer to Table 14.2 A/D Conversion

Frequency Select

(b7-b6)

110

b1 b0

0 0: AN

to AN

(2 pins)

0 1: AN

to AN

(4 pins)

1 0: AN

to AN

(6 pins)

1 1: AN

to AN

(8 pins)

A/D control register 2 (1)

Symbol

Address

After reset

ADCON2 03D4

b7 b6 b5 b4 b3 b2 b1 b0

A/D Conversion Method

Select Bit

(2)

1 : With sample and hold

Bit symbol Bit name Function RW

SMP

Reserved Bit Set to

“0”

A/D Input Group

Select Bit 0 0 : Select port P10 group (AN

)

0 1 : Select port P9 group (AN

)

1 0 : Do not set

1 1 : Do not set

b2 b1

Frequency Select Bit 2

CKS2

ADGSEL0

ADGSEL1

(b3)

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

(b7-b6)

Refer to Table 14.2 A/D Conversion

Frequency Select

TRG1 Trigger Select Bit 1

Refer to Table 14.1.7.2 Trigger Select Bit

Setting in Delayed Trigger Mode 0

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

NOTES:

1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.

2. AN

to AN

can be used in the same way as AN

to AN

. Use the ADGSEL1 to ADGSEL0 bits in the ADCON2

3. If the VCUT bit is reset from “0” (V

REF

unconnected) to “1” (V

REF

connected), wait for 1 µs or more before starting

A/D conversion.

NOTES:

1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.

2. Do not write “1” in delayed trigger mode 0. When write, set to "0".

NOTES:

1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.

2. Set to “1” in delayed trigger mode 0.

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Figure 14.1.7.5 ADTRGCON Register in Delayed Trigger Mode 0

A/D trigger control register

(1)

Symbol Address After reset

ADTRGCON 03D2

b7 b6 b5 b4 b3 b2 b1 b0

A/D Operation Mode

Select Bit 2

Bit symbol Bit name Function RW

SSE

A/D Operation Mode

Select Bit 3

AN1 Trigger Select Bit

HPTRG1

DTE

HPTRG0

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

(b7-b4)

AN0 Trigger Select Bit

NOTE:

1. If ADTRGCON reigster is rewritten during A/D conversion, the conversion result will be indeterminate.

Delayed trigger mode 0, 1

Simultaneous sample sweep mode or

delayed trigger mode 0,1

Refer to Table 14.1.7.2 Trigger Select

Bit Setting in Delayed Trigger Mode 0

Refer to Table 14.1.7.2 Trigger Select

Bit Setting in Delayed Trigger Mode 0

Trigger

Timer B0, B1 underflow

TRG

HPTRG0

TRG1

HPTRG1

Table 14.1.7.2 Trigger Select Bit Setting in Delayed Trigger Mode 0

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14.1.8 Delayed Trigger Mode 1

In delayed trigger mode 1, analog voltages applied to the selected pins are converted one-by-one to a

digital code. When the input of the ADTRG pin (falling edge) changes state from “H” to “L”, a single sweep

conversion is started. After completing the AN0 pin conversion, the AN1 pin is not sampled and converted

until the second ADTRG pin falling edge is generated. When the second ADTRG falling edge is generated,

The single sweep conversion of the pins after the AN1 pin is restarted. Table 14.1.8.1 shows the delayed

trigger mode 1 specifications. Figure 14.1.8.1 shows the operation example of delayed trigger mode 1.

Figure 14.1.8.2 to Figure 14.1.8.3 show each flag operation in the ADSTAT0 register that corresponds to

the operation example. Figure 14.1.8.4 shows the ADCON0 to ADCON2 registers in delayed trigger

mode 1. Figure 14.1.8.5 shows the ADTRGCON register in delayed trigger mode 1 and Table 15.1.8.2

shows the trigger select bit setting in delayed trigger mode 1.

Table 14.1.8.1 Delayed Trigger Mode 1 Specifications

Item Specification

Function The SCAN1 to SCAN0 bits in the ADCON1 register and ADGSEL1 to ADGSEL0 bits

in the ADCON2 register select pins. Analog voltages applied to the selected pins are

converted one-by-one to a digital code. At this time, the ADTRG pin

falling edge starts AN0 pin conversion and the second ADTRG pin falling edge starts

conversion of the pins after AN1 pin

A/D Conversion Start AN0 pin conversion start condition

Condition The ADTRG pin input changes state from “H” to “L” (falling edge)(1)

AN1 pin conversion start condition (2)

The ADTRG pin input changes state from “H” to “L” (falling edge)

•When the second ADTRG pin falling edge is generated during or after A/D

conversion of the AN0 pin, input voltage of AN1 pin is sampled at the time of ADTRG

falling edge. The conversion of AN1 and the rest of the sweep starts when AN0

conversion is completed.

•When the ADTRG pin falling edge is generated again during single sweep conver

sion of pins after the AN1 pin, the conversion is not affected

A/D Conversion Stop

•

A/D conversion completed

Condition •Set the ADST bit to "0" (A/D conversion halted)(3)

Interrupt Request Single sweep conversion completed

Generation Timing

Analog Input Pin Select from AN0 to AN1 (2 pins), AN0 to AN3 (4 pins), AN0 to AN5 (6 pins) and

AN0 to AN7 (8 pins)(4)

Readout of A/D Conversion Result

Readout one of the AN0 to AN7 registers that corresponds to the selected pins

NOTES: ___________

1. Do not generate the next ADTRG pin falling edge after the AN1 pin conversion is started until all selected pins

___________

complete A/D conversion. When an ADTRG pin falling edge is generated again during A/D conversion, its trigger

___________

is ignored. The falling edge of ADTRG pin, which was input after all selected pins complete A/D conversion, is

considered to be the next AN0 pin conversion start condition.

___________ ___________

2. The ADTRG pin falling edge is detected synchronized with the operation clock φAD. Therefore, when the ADTRG pin

___________

falling edge is generated in shorter periods than φAD, the second ADTRG pin falling edge may not be detected. Do

___________

not generate the ADTRG pin falling edge in shorter periods than φAD.

3. Do not write “1” (A/D conversion started) to the ADST bit in delayed trigger mode 1. When write “1”, unexpected

interrupts may be generated.

4. AN30 to AN32 can be used in the same way as AN0 to AN7. However, all input pins need to belong to the same

group.

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•Example when selecting AN

to AN

to analog input pins (SCAN1 to SCAN0=01

)

A/D pin input

voltage sampling

A/D pin conversion

TRG

pin input

•Example 1: When AD

TRG

pin falling edge is generated during AN

pin conversion

•Example 2: When AD

TRG

pin falling edge is generated again after AN

pin conversion

TRG

pin input

•Example 3: When AD

TRG

pin falling edge is generated more than two times after AN

pin conversion

(invalid)

(valid after single sweep conversion)

TRG

pin input

Figure 14.1.8.1 Operation Example in Delayed Trigger Mode1

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•Example when selecting AN0 to AN3 to analog input pins (SCAN1 to SCAN0=012)

A/D pin input

voltage sampling

A/D pin conversion

AN0

AN1

AN2

AN3

AN0

AN1

AN2

AN3

•Example 2: When ADTRG pin falling edge is generated again after AN0 pin conversion

TRG

pin input

•Example 1: When ADTRG pin falling edge is generated during AN0 pin conversion

ADST flag

ADERR0 flag

ADERR1 flag

ADTCSF flag

ADSTT0 flag

ADSTT1 flag

ADSTRT0 flag

ADSTRT1 flag

IR bit in the ADIC

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

Set to "0" by interrupt request acknowledgement or a program

ADST flag

ADERR0 flag

ADERR1 flag

ADTCSF flag

ADSTT0 flag

ADSTT1 flag

ADSTRT0 flag

ADSTRT1 flag

IR bit in the ADIC

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

ADST flag: Bit 6 in the ADCON0 register

ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register

Set to "0" by program

Set to "0" by interrupt request acknowledgment or a program

Set to "0" by program

Do not set to "1" by program

TRG

pin input

Figure 14.1.8.2 Each Flag Operation in ADSTAT0 Register Associated with the Operation Example

in Delayed Trigger Mode 1 (1)

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•Example 3: When AD

TRG

input falling edge is generated more than two times after AN

pin conversion

(invalid)

(valid after single sweep conversion)

ADST flag

ADERR0 flag

ADERR1 flag

ADTCSF flag

ADSTT0 flag

ADSTT1 flag

ADSTRT0 flag

ADSTRT1 flag

IR bit in the ADIC

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

"1"

"0"

Set to "0" when interrupt request acknowledgement or a program

Set to "0" by program

Do not set to "1" by program

A/D pin input

voltage sampling

A/D pin conversion

ADST flag: Bit 6 in the ADCON0 register

ADERR0, ADERR1, ADTCSF, ADSTT0, ADSTT1, ADSTRT0 and ADSTRT1 flag: bits 0, 1, 3, 4, 5, 6 and 7 in the ADSTAT0 register

TRG

pin input

Figure 14.1.8.2 Each Flag Operation in ADSTAT0 Register Associated with the Operation Example

in Delayed Trigger Mode 1 (2)

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A/D control register 0

(1)

Symbol

Address

After reset

ADCON0

03D6

00000XXX

b7 b6 b5 b4 b3 b2 b1 b0

Analog Input Pin

Select Bit

CH0

Bit symbol Bit name Function

CH1

CH2

A/D Operation Mode

Select Bit 0

MD0

MD1 Trigger Select Bit Refer to Table 14.1.8.2 Trigger Select Bit

Setting in Delayed Trigger Mode 1

TRG

ADST A/D Conversion Start

Flag (2) 0 : A/D conversion disabled

1 : A/D conversion started

Frequency Select Bit 0CKS0

A/D control register 1

(1)

Symbol

Address

After reset

ADCON1

03D7

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

A/D Sweep Pin

Select Bit (2)

SCAN0

SCAN1

MD2

BITS 8/10-Bit Mode Select Bit 0 : 8-bit mode

1 : 10-bit mode

VCUT VREF Connect Bit (3)

A/D Operation Mode

Select Bit 1

1 : VREF connected

When selecting delayed trigger mode 1

1 1 1 : Set to "111b" in delayed trigger

mode 1

b2 b1 b0

0 0 : One-shot mode or delayed trigger mode

0,1

b4 b3

Frequency Select Bit 1

CKS1

0 : Any mode other than repeat sweep

mode 1

Refer to Table 14.2 A/D Conversion

Frequency Select

Refer to Table 14.2 A/D Conversion

Frequency Select

(b7-b6)

110

b1 b0

0 0: AN0 to AN1 (2 pins)

0 1: AN0 to AN3 (4 pins)

1 0: AN0 to AN5 (6 pins)

1 1: AN0 to AN7 (8 pins)

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

NOTES:

1. If the ADCON0 register is rewritten during A/D conversion, the conversion result will be indeterminate.

2. Do not write “1” in delayed trigger mode 1. When write, set to "0".

NOTES:

1. If the ADCON1 register is rewritten during A/D conversion, the conversion result will be indeterminate.

2. AN30 to AN32 can be used in the same way as AN0 to AN7. Use the ADGSEL1 to ADGSET0 bits in the ADCON2

3. If the VCUT bit is reset from “0” (VREF unconnected) to “1” (VREF connected), wait for 1 µs or more before starting A/D

conversion.

A/D control register 2

(1)

Symbol

Address

After reset

ADCON2 03D416 0016

b7 b6 b5 b4 b3 b2 b1 b0

A/D Conversion Method

Select Bit (2) 1 : With sample and hold

Bit symbol Bit name Function RW

SMP

Reserved Bit Set to

“0”

A/D Input Group

Select Bit0 0 : Select port P10 group (ANi)

0 1 : Select port P9 group (AN3i)

1 0 : Do not set

1 1 : Do not set

b2 b1

Frequency Select Bit 2

CKS2

ADGSEL0

ADGSEL1

(b3)

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

(b7-b6)

Refer to Table 14.2 A/D Conversion

Frequency Select

TRG1 Trigger Select Bit 1

Refer to Table 14.1.8.2 Trigger Select Bit

Setting in Delayed Trigger Mode 1

NOTES:

1. If the ADCON2 register is rewritten during A/D conversion, the conversion result will be indeterminate.

2. Set to “1” in delayed trigger mode 1.

Figure 14.1.8.4 ADCON0 to ADCON2 Registers in Delayed Trigger Mode 1

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A/D trigger control register (1)

Symbol Address After reset

ADTRGCON 03D2

b7 b6 b5 b4 b3 b2 b1 b0

A/D Operation Mode

Select Bit 2

Bit symbol Bit name Function RW

SSE

A/D Operation Mode

Select Bit 3

AN1 Trigger Select Bit

HPTRG1

DTE

HPTRG0

Nothing is assigned. When write, set to “0”.

When read, its content is “0”.

(b7-b4)

AN0 Trigger Select Bit

NOTE:

1. If ADTRGCON is rewritten during A/D conversion, the conversion result will be indeterminate.

Delayed trigger mode 0, 1

Simultaneous sample sweep mode or

delayed trigger mode 0,1

Refer to Table 14.1.8.2 Trigger Select

Bit Setting in Delayed Trigger Mode 1

Refer to Table 14.1.8.2 Trigger Select

Bit Setting in Delayed Trigger Mode 1

Figure 14.1.8.5 ADTRGCON Register in Delayed Trigger Mode 1

Trigger

TRG

HPTRG0

TRG1

1ADTRG

HPTRG1

Table 14.1.8.2 Trigger Select Bit Setting in Delayed Trigger Mode 1

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14.2 Resolution Select Function

The BITS bit in the ADCON1 register determines the resolution. When the BITS bit is set to “1” (10-bit

precision), the A/D conversion result is stored into bits 0 to 9 in the A/D register i (i=0 to 7). When the BITS

bit is set to “0” (8-bit precision), the A/D conversion result is stored into bits 0 to 7 in the ADi register.

14.3 Sample and Hold

When the SMP bit in the ADCON 2 register is set to “1” (with the sample and hold function), A/D conver-

sion rate per pin increases to 28 φAD cycles for 8-bit resolution or 33 φAD cycles for 10-bit resolution. The

sample and hold function is available in one-shot mode, repeat mode, single sweep mode, repeat sweep

mode 0 and repeat sweep mode 1. In these modes, start A/D conversion after selecting whether the

sample and hold circuit is to be used or not. In simultaneous sample sweep mode, delayed trigger mode

0 or delayed trigger mode 1, set to use the Sample and Hold function before starting A/D conversion.

14.4 Power Consumption Reducing Function

When the A/D converter is not used, the VCUT bit in the ADCON1 register isolates the resistor ladder of

the A/D converter from the reference voltage input pin (VREF). Power consumption is reduced by shutting

off any current flow into the resistor ladder from the VREF pin.

When using the A/D converter, set the VCUT bit to “1” (VREF connected) before setting the ADST bit in the

ADCON0 register to “1” (A/D conversion started). Do not set the ADST bit and VCUT bit to “1” simulta-

neously, nor set the VCUT bit to “0” (VREF unconnected) during A/D conversion.

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14.5 Output Impedance of Sensor under A/D Conversion

To carry out A/D conversion properly, charging the internal capacitor C shown in Figure 14.5.1 has to be

completed within a specified period of time. T (sampling time) as the specified time. Let output imped-

ance of sensor equivalent circuit be R0, microcomputer’s internal resistance be R, precision (error) of

the A/D converter be X, and the A/D converter’s resolution be Y (Y is 1024 in the 10-bit mode, and 256

in the 8-bit mode).

VC is generally VC = VIN{1-e c(R0+R) }

And when t = T, VC=VIN- VIN=VIN(1- )

e c(R0+R) =

- T = ln

Hence, R0 = - - R

Figure 14.5.1 shows analog input pin and externalsensor equivalent circuit. When the difference be-

tween VIN and VC becomes 0.1LSB, we find impedance R0 when voltage between pins. VC changes

from 0 to VIN-(0.1/1024) VIN in timer T. (0.1/1024) means that A/D precision drop due to insufficient

capacitor chage is held to 0.1LSB at time of A/D conversion in the 10-bit mode. Actual error however is

the value of absolute precision added to 0.1LSB. When f(XIN) = 10MHz, T=0.3µs in the A/D conversion

mode with sample & hold. Output inpedance R0 for sufficiently charging capacitor C within time T is

determined as follows.

T = 0.3µs, R = 7.8kΩ, C = 1.5pF, X = 0.1, and Y = 1024. Hence,

R0 = - - 7.8 X 103 ≅ 13.9 X 103

Thus, the allowable output impedance of the sensor circuit capable of thoroughly driving the A/D con-

verter turns out of be approximately 13.9kΩ.

Figure 14.5.1 Analog Input Pin and External Sensor Equivalent Circuit

C(R0+R)

C•ln X

1.5X10-12•ln 0.1

1024

0.3X10-6

R0R (7.8kΩ)

C (1.5pF)

VIN

Sampling time

Sample-and-hold function enabled:

Sample-and-hold function disabled:

φAD

Microcomputer

Sensor equivalent

circuit

φAD

(1)

NOTES:

1. Reference value

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15. CRC Calculation Circuit

The Cyclic Redundancy Check (CRC) operation detects an error in data blocks. The microcomputer uses

a generator polynomial of CRC_CCITT (X16 + X12 + X5 + 1) or CRC-16 (X16 + X15 + X2 + 1) to generate

CRC code.

The CRC code is a 16-bit code generated for a block of a given data length in multiples of bytes. The code

is updated in the CRC data register everytime one byte of data is transferred to a CRC input register. The

data register needs to be initialized before use. Generation of CRC code for one byte of data is completed

in two machine cycles.

Figure 15.1 shows the block diagram of the CRC circuit. Figure 15.2 shows the CRC-related registers.

Figure 15.3 shows the calculation example using the CRC_CCITT operation.

15.1. CRC Snoop

The CRC circuit includes the ability to snoop reads and writes to certain SFR addresses. This can be

used to accumulate the CRC value on a stream of data without using extra bandwidth to explicitly write

data into the CRCIN register. All SFR addresses after 002016 are subject to the CRC snoop. The CRC

snoop is useful to snoop the writes to a UART TX buffer, or the reads from a UART RX buffer.

To snoop an SFR address, the target address is written to the CRC snoop Address Register (bits 9 to

0 in the CRCSAR register). The two most significant bits in this register enable snooping on reads or

writes to the target address. If the target SFR is written to by the CPU or DMA, and the CRC snoop write

bit is set (the CRCSW bit is set to "1"), the CRC will latch the data into the CRCIN register. The new

CRC code will be set in the CRCD register.

Similarly, if the target SFR is read by the CRC or DMA, and the CRC snoop read bit is set (the CRCSR

bit is set to "1"), the CRC will latch the data from the target into the CRCIN register and calculate the

CRC.

The CRC circuit can only calculate CRC codes on data byte at a time. Therefore, if a target SFR is

accessed in a word (16 bit) bus cycle, only the byte of data going to or from the target snooped into

CRCIN, the other byte of the word access is ignored.

Figure 15.1 CRC circuit block diagram

AAAAA

Eight low-order bits

AAAAA

Eight high-order bits

Data bus high-order

Data bus low-order

AAAAAAAAAA

AAAAA

CRCD register (16)

CRC input register (8)

AAAAAAAAAA

AAAAAAAA

AAAAAAAAAA

CRC code generating circuit

+ x

+ 1 OR x

+ x

+ 1

Address Bus

SnoopB

lock

Snoop

enable

Snoop Address

AAAAAAAA

Equal?

(Address 03BD16, 03BC16)

(Address 03BE16)

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Symbol Address After Reset

CRCD 03BD16 to 03BC16 Undefined

b7 b0 b7 b0

(b15) (b8)

CRC Data Register

Function Setting Range

0000

16 to FFFF16

Symbol Address After Reset

CRCIN 03BE

Undefined

b7 b0

CRC Input Register

Data input

Function

0016 to FF16

Setting Range

CRC calculation result output

Symbol Address After Reset

CRCMR 03B616 0XXXXXX02

b7 b0

CRC Mode Register

CRC mode polynomial

selection bit

Function

0: LSB first

1: MSB first

Bit nameBit symbol

CRC mode selection bit

CRCPS

CRCMS RW

Nothing is assigned.

Write "0" when writing to this bit. The value is indeterminate if read.

0: X16+X12+X5+1 (CRC-CCITT)

1: X16+X15+X2+1 (CRC-16)

CRC mode polynomial

selection bit

Function

0: LSB first

1: MSB first

Bit NameBit Symbol

CRC mode selection bit

CRCPS

CRCMS RW

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined

0: X16+X12+X5+1 (CRC-CCITT)

1: X16+X15+X2+1 (CRC-16)

(b6-b1)

Symbol Address After Reset

CRCSAR 03B516 to 03B416 00XXXXXX XXXXXXXX2

b7 b0 b7 b0

(b15) (b8)

SFR Snoop Address Register

CRC mode polynomial

selection bit

Function RW

Bit Name

Bit Symbol

CRCSR RW

Nothing is assigned. If necessary, set to 0.

When read, the content is undefined

SFR address to snoop

Function

0: Disabled

1: Enabled

(1)

CRCSW

CRCSAR9-0

CRC snoop on read

enable bit

CRC snoop on write

enable bit 0: Disabled

1: Enabled

(1)

(b13-b10)

NOTE:

1. Set bits CRCSR and CRCSW to 0 if the PLC07 bit in the PLC0 register is set to 1 (PLL on) and the PM20 bit in

the PM2 register is set to 0 (SFR access 2 wait).

Figure 15.2. CRCD, CRCIN, CRCMR, CRCSAR Register

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Figure 15.3. CRC Calculation

(1) Setting 0000

(initial value)

b15 b0

1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000

1000 1000 0001 0000 1

1000 0001 0000 1000 0

1000 1000 0001 0000 1

1001 0001 1000 1000

1000 1000 MSB

Modulo-2 operation is

operation that complies

with the law given below.

0 + 0 = 0

0 + 1 = 1

1 + 0 = 1

1 + 1 = 0

-1 = 1

The code resulting from sending 01

in LSB first mode is (10000 0000).This the CRC code in the generating polynomial,

+ X

+ 1), becomes the remainder resulting from dividing(1000 0000)X

by ( 1 0001 0000 0010 0001) in

conformity with the modulo-2 operation.

(2) Setting 01

b0b7

b15 b0

1189

2 cycles

After CRC calculation is complete

Thus the CRC code becomes ( 1001 0001 1000 1000). Since the operation is in LSB first mode, the (1001 0001 1000 1000)

corresponds to 1189

in hexadecimal notation. If the CRC operation in MSB first mode is necessary, set the CRC mode

selection bit to "1". CRC data register stores CRC code for MSB first mode.

CRD data register CRCD

[03BD

, 03BC

]

CRC input register CRCIN

[03BE

]

CRD data register CRCD

[03BD

, 03BC

]

CRC input register CRCIN

[03BE

]

(3) Setting 23

b0b7

b15 b0

0A41

After CRC calculation is complete

CRD data register CRCD

[03BD

, 03BC

]

98 11

MSB

LSB

Stores CRC code

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16. Programmable I/O Ports

Note

P60 to P63, P92 and P93 are not available in the 42-pin package.

The programmable input/output ports (hereafter referred to simply as “I/O ports”) consist of 39 lines P15 to

P17, P6, P7, P8, P90 to P93, P10 for the 48-pin package, or 33 lines P15 to P17, P64 to P67, P7, P8, P90 to

P91, P10 for the 42-pin package. Each port can be set for input or output every line by using a direction

Figures 16.1 to 16.4 show the I/O ports. Figure 16.5 shows the I/O pins.

Each pin functions as an I/O port, a peripheral function input/output.

For details on how to set peripheral functions, refer to each functional description in this manual. If any pin

is used as a peripheral function input, set the direction bit for that pin to “0” (input mode). Any pin used as an

output pin for peripheral functions is directed for output no matter how the corresponding direction bit is set.

16.1 Port Pi Direction Register (PDi Register, i = 1, 6 to 10)

Figure 16.1.1 shows the direction registers.

This register selects whether the I/O port is to be used for input or output. The bits in this register corre-

spond one for one to each port.

16.2 Port Pi Register (Pi Register, i = 1, 6 to 10)

Figure 16.2.1 shows the Pi registers.

Data input/output to and from external devices are accomplished by reading and writing to the Pi register.

The Pi register consists of a port latch to hold the output data and a circuit to read the pin status. For ports

set for input mode, the input level of the pin can be read by reading the corresponding Pi register, and data

can be written to the port latch by writing to the Pi register.

For ports set for output mode, the port latch can be read by reading the corresponding Pi register, and data

can be written to the port latch by writing to the Pi register. The data written to the port latch is output from

the pin. The bits in the Pi register correspond one for one to each port.

16.3 Pull-up Control Register 0 to Pull-up Control Register 2 (PUR0 to PUR2 Registers)

Figure 16.3.1 shows the PUR0 to PUR2 registers.

The PUR0 to PUR2 registers select whether the ports, divided into groups of four ports, are pulled up or not.

The ports, selected by setting the bits in registers PUR2 to PUR0 to “1” (pull-up), are pulled up when the

direction registers are set to “0” (input mode). The ports are pulled up regardless of their function.

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16.4 Port Control Register

Figure 16.4.1 shows the port control register.

When the P1 register is read after setting the PCR0 bit in the PCR register to “1”, the corresponding port

latch can be read no matter how the PD1 register is set.

16.5 Pin Assignment Control register (PACR)

Figure 16.5.1 shows the PACR. After reset set the PACR2 to PACR0 bit before you input and output it to

each pin. When the PACR register isn’t set up, the input and output function of some of the pins doesn’t

work.

PACR2 to PACR0 bits: control the pins enabled for use.

At reset, these bits are “000”.

In 48-pin package, set these bits to “1002”.

In 42-pin package, set these bits to “0012”.

U1MAP: controls the assignment of UART1 pins.

If the U1MAP bit is set to “0” (P67 to P64) the UART1 functions are mapped to P64/CTS1/RTS1,

P65/CLK1, P66/RxD1, and P67/TxD1.

If the U1MAP bit is set to “1” (P73 to P70) the UART1 functions are mapped to P70/CTS1/RTS1,

P71/CLK1, P72/RxD1, and P73/TxD1.

PACR is write protected by PRC2 bit in the PRCR register. PRC2 bit must be set immediately before the

write to PACR.

16.6 Digital Debounce function

Two digital debounce function circuits are provided. Level is determined when level is held, after applying

either a falling edge or rising edge to the pin, longer than the programmed filter width time. This enables

noise reduction. ________ _______ _____

This function is assigned to INT5/INPC17 and NMI/SD. Digital filter width is set in the NDDR register and

the P17DDR register respectively. Additionally, a digital debounce function is disabled to the port P17

input and port P85 input. Figure 16.6.1 shows the NDDR register and the P17DDR register.

Filter width : (n+1) × 1/ f8 n: count value set in the NDDR register and P17DDr register

The NDDR register and the P17DDR register decrement count value with f8 as the count source. The

NDDR register and the P17DDR register indicate count time. Count value is reloaded if a falling edge or

a rising edge is applied to the pin.

The NDDR register and the P17DDR register can be set 0016 to FF16 when using the digital debounce

function. Setting to FF16 disables the digital filter. See Figure 16.6.2 for details.

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Figure 16.1. I/O Ports (1)

P100 to P103

Data bus

(1)

Analog input

Pull-up selection

Direction register

Port latch

P15, P16

Data bus

P17

(inside dotted-line not included)

(inside dotted-line included)

Direction register

Port latch

Pull-up selection

(1)

Port P1 control register

Input to respective peripheral functions

Digital

debounce

INPC17/INT5

"1"

Output

Data bus

Direction

Port latch

Pull-up selection

(1)

Input to respective peripheral functions

NOTE:

1. symbolizes a parasitic diode.

Make sure the input voltage on each port will not exceed Vcc.

P60, P61, P64, P65, P74 to P76,

P80, P81

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Figure 16.2. I/O Ports (2)

Data bus

Pull-up selection

Direction register

Port latch

Data bus

Pull-up selection

Direction register

Port latch

Input to respective peripheral functions

"1"

Output

Data bus

Direction

Port latch

Pull-up selection

(1)

Input to respective peripheral functions

Switching

between

CMOS and

Nch

(1)

NOTE:

1. symbolizes a parasitic diode.

Make sure the input voltage on each port will not exceed Vcc.

to P7

to P8

, P6

, P7

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Figure 16.3. I/O Ports (3)

, P6

Output

“1”

Data bus

Pull-up selection

Direction register

Port latch

Switching between CMOS and Nch

NOTE:

1. symbolizes a parasitic diode.

Make sure the input voltage on each port will not exceed Vcc.

Data bus

Pull-up selection

Direction register

Port latch

NMI Interrupt Input

NMI Enable

Digital Debounce

NMI Enable

(1)

Data bus

Direction register

Pull-up selection

Port latch

Analog input

Input to respective peripheral functions

(1)

, P9

P10

to P10

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Figure 16.4. I/O Ports (4)

Output

Direction register

Data bus Port latch

Analog input

Pull-up selection

(1)

P87

P86

Data bus

Direction register

Pull-up selection

Port latch

Direction register

Pull-up selection

Port latch

Data bus

(1)

Input to respective peripheral functions

P90

(inside dotted-line

included)

P93

(inside dotted-line

not included)

NOTE:

1. symbolizes a parasitic diode.

Make sure the input voltage on each port will not exceed Vcc.

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Figure 16.5. I/O Pins

CNVSS CNVSS signal input

RESET RESET signal input

(1)

NOTE:

1. symbolizes a parasitic diode. Make sure the

input voltage on each port will not exceed Vcc.

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Figure 16.1.1. PD1, PD6, PD7, PD8, PD9, and PD10 Registers

Port Pi direction register (i=6 to 8, and 10) (1)

Symbol Address After reset

PD6 to PD8 03EE16, 03EF16, 03F216 0016

PD10 03F616 0016

Bit name FunctionBit symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

PDi_0 Port Pi0 direction bit

PDi_1 Port Pi1 direction bit

PDi_2 Port Pi2 direction bit

PDi_3 Port Pi3 direction bit

PDi_4 Port Pi4 direction bit

PDi_5 Port Pi5 direction bit

PDi_6 Port Pi6 direction bit

PDi_7 Port Pi7 direction bit

0 : Input mode

(Functions as an input port)

1 : Output mode

(Functions as an output port)

(i = 6 to 8, and 10)

Port P1 direction register (1)

Symbol

Address After reset

PD1 03E316 0016

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

0 : Input mode

(Functions as an input port)

1 : Output mode

(Functions as an output port)

PD1_5 Port P15 direction bit RW

PD1_6 Port P16 direction bit RW

PD1_7 Port P17 direction bit RW

Nothing is assigned. In an attempt to write to this bit, write “0”.

The value, if read, turns out to be indeterminate.

(b4-b0)

Port P9 direction register (1,2)

Symbol

Address After reset

PD9 03F316 XXXX00002

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

PD9_0 Port P90 direction bit

PD9_1 Port P91 direction bit

PD9_2 Port P92 direction bit

PD9_3 Port P93 direction bit

0 : Input mode

(Functions as an input port)

1 : Output mode

(Functions as an output port)

Nothing is assigned. In an attempt to write to this bit, write “0”.

The value, if read, turns out to be indeterminate.

(B7-b4)

NOTE:

1. Ports must be enabled using the PACR register.

In 48-pin package, set PACR2, PACR1, PACR0 to "100

In 42-pin package, set PACR2, PACR1, PACR0 to "001

NOTE:

1. Ports must be enabled using the PACR register.

In 48-pin package, set PACR2, PACR1, PACR0 to "100

In 42-pin package, set PACR2, PACR1, PACR0 to "001

NOTE:

1. Make sure the PD9 register is written to by the next instruction after setting the PRC2 bit in the PRCR

2. Ports must be enabled using the PACR register.

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Symbol Address After reset

P6 to P8 03EC16, 03ED16, 03F016 Indeterminate

P10 03F416 Indeterminate

Port Pi register (i=6 to 8 and 10) (1)

Bit name FunctionBit symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

Pi_0 Port Pi0 bit

Pi_1 Port Pi1 bit

Pi_2 Port Pi2 bit

Pi_3 Port Pi3 bit

Pi_4 Port Pi4 bit

Pi_5 Port Pi5 bit

Pi_6 Port Pi6 bit

Pi_7 Port Pi7 bit

The pin level on any I/O port which is

set for input mode can be read by

reading the corresponding bit in this

The pin level on any I/O port which is

set for output mode can be controlled

by writing to the corresponding bit in

this register

0 : “L” level

1 : “H” level (1)

(i = 6 to 8 and 10)

Port P1 register (1)

Symbol Address After reset

P1 03E116 Indeterminate

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

P1_5 Port P15 bit

P1_6 Port P16 bit

P1_7 Port P17 bit

The pin level on any I/O port which is

set for input mode can be read by

reading the corresponding bit in this

The pin level on any I/O port which is

set for output mode can be controlled

by writing to the corresponding bit in

this register

0 : “L” level

1 : “H” level

Nothing is assigned. In an attempt to write to this bit, write “0”.

The value, if read, turns out to be indeterminate.

(b4-b0)

Port P9 register (1)

Symbol Address After reset

P9 03F116 Indeterminate

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

P9_0 Port P90 bit

P9_1 Port P91 bit

P9_2 Port P92 bit

P9_3 Port P93 bit

The pin level on any I/O port which is

set for input mode can be read by

reading the corresponding bit in this

The pin level on any I/O port which is

set for output mode can be controlled

by writing to the corresponding bit in

this register

0 : “L” level

1 : “H” level

Nothing is assigned. In an attempt to write to this bit, write “0”.

The value, if read, turns out to be indeterminate.

(b7-b4)

NOTE:

1. Ports must be enabled using the PACR register.

In 48-pin package, set PACR2, PACR1, PACR0 to "1002"

In 42-pin package, set PACR2, PACR1, PACR0 to "0012"

NOTE:

1. Ports must be enabled using the PACR register.

In 48-pin package, set PACR2, PACR1, PACR0 to "1002"

In 42-pin package, set PACR2, PACR1, PACR0 to "0012"

NOTE:

1. Ports must be enabled using the PACR register.

In 48-pin package, set PACR2, PACR1, PACR0 to "1002"

In 42-pin package, set PACR2, PACR1, PACR0 to "0012"

Figure 16.2.1. P1, P6, P7, P8, P9, and P10 Registers

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Figure 16.3.1. PUR0 to PUR2 Registers

Pull-up control register 0

Symbol Address After reset

PUR0 03FC16 0016

Bit name Function Bit symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

PU03 P15 to P17 pull-up 0 : Not pulled high

1 : Pulled high (1) RW

NOTE:

1. The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.

Pull-up control register 2

Symbol Address After reset

PUR2 03FE16 0016

Bit name FunctionBit symbol

b7 b6 b5 b4 b3 b2 b1 b0

PU20 P80 to P83 pull-up

PU21 P84 to P87 pull-up

PU22 P90 to P93 pull-up

PU24 P100 to P103 pull-up

PU25 P104 to P107 pull-up

Nothing is assigned. In an attempt to write to these bits, write

“0”. The value, if read, turns out to be “0”.

0 : Not pulled high

1 : Pulled high (1)

(b7-b6)

NOTE:

1. The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.

Nothing is assigned. In an attempt to write to these bits, write

“0”. The value, if read, turns out to be “0”.

(b2-b0)

Nothing is assigned. In an attempt to write to these bits, write

“0”. The value, if read, turns out to be “0”.

(b7-b4)

Pull-up control register 1

Symbol Address After reset

PUR1 03FD16 000000002

Bit name Function Bit symbol

b7 b6 b5 b4 b3 b2 b1 b0

PU14 P60 to P63 pull-up

PU15 P64 to P67 pull-up

PU16 P70 to P73 pull-up

PU17 P74 to P77 pull-up

0 : Not pulled high

1 : Pulled high (1)

NOTE:

1. The pin for which this bit is “1” (pulled high) and the direction bit is “0” (input mode) is pulled high.

Nothing is assigned. In an attempt to write to these bits, write

“0”. The value, if read, turns out to be “0”.

(b3-b0)

0 : Not pulled high

1 : Pulled high (1)

Nothing is assigned. In an attempt to write to these bits, write

“0”. The value, if read, turns out to be “0”.

(b3)

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Figure 16.4.1. PCR Register

Port control register

Symbpl Address After reset

PCR 03FF16 00

Bit name FunctionBit symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

PCR0 Port P1 control bit

Nothing is assigned.

In an attempt to write to these bits,

write “0”. The value, if read, turns out to be “0”.

(b7-b1)

Operation performed when the P1

0: When the port is set for input,

the input levels of P10 to P17

pins are read. When set for

output, the port latch is read.

1: The port latch is read

regardless of whether the port

is set for input or output.

Figure 16.5.1. PACR Register

Pin Assignment Control Register

(1)

Symbpl Address After Reset

PACR 025D

0016

Bit Name FunctionBit Symbol RW

b7 b6 b5 b4 b3 b2 b1 b0

Pin enabling bit

Nothing is assigned.

When write,

set to “0”. When read, its

content is “0”.

(b6-b3)

001 : 42 pin

100 : 48 pin

All other values are reserved. Do

not use.

PACR0

PACR1

PACR2

Reserved bits

U1MAP UART1 pin remapping bit UART1 pins assigned to

0 : P6

to P64

1 : P73 to P70

NOTES:

1. Set the PACR register by the next instruction after setting the PRC2 bit in the PRCR register to "1"(write

enable).

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Figure 16.6.1. NDDR and P17DDR Registers

NMI Digital Debounce Register (1,2)

Symbol Address After Reset

NDDR 033E

16 FF16

b7 b0

Function RW

Setting Range

to FF

If the set value =n,

- n = 0 to FE16; a signal with pulse width, greater than

(n+1)/f8, is input into NMI / SD

- n = FF16; the digital debounce filter is disabled and all

signals are input

P17 Digital Debounce Register

(1)

Symbol Address After Reset

P17DDR 033F16 FF16

b7 b0

Function RW

Setting Range

to FF

If the set value =n,

- n = 0 to FE16; a signal with pulse width, greater than

(n+1)/f8, is input into INPC17/ INT5

- n = FF16; the digital debounce filter is disabled and all

signals are input

NOTE:

1. When using the INT5 interrupt to exit from stop mode, set the P17DDR registert to "FF16" before entering

stop mode.

NOTES:

1. Set the PACR register by the next instruction after setting the PRC2 bit in the PRCR register to "1"(write

enable).

2. When using the NMI interrupt to exit from stop mode, set the NDDR registert to "FF16" before entering

stop mode.

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Figure 16.6.2. Functioning of Digital Debounce Filter

P85 / P17

Data Bus

1. (Condition after reset). Reload = FF, Port In = signal Out continuosly.

2. Reload = 03. At edge of Port In != Signal Out, Counter gets Reload Value and

stats counting down.

3. Port In = Signal Out, counting stops.

4. At edge of Port In != Signal Out, Counter gets Reload Value and starts counting.

5. Counter underflows, stops, and Port In is driven to Signal Out.

6. At edge of Port In != Signal Out, counter gets Reload Value and starts counting.

7. Counter underflows, stops, and Port In is driven to Signal Out.

8. At edge of Port In != Signal Out, counter gets Reload Value and starts counting.

9. FF is written to Reload Value. Counter is stopped and loaded with FF.

Port In = Signal Out continuously.

Clock

Port In

Reload Value

(write)

Digital Debounce Filter

Signal Out

Count Value

(read)

To NMI and SD / INT5 and INPC17

Data Bus

Reload Value

Port In

Signal Out

Count Value

Reload Value

(continued)

Port In

(continued)

Signal Out

(continued)

Count Value

(continued)

FF 03

FF 03 02 01 03 02 01 00 FF

03 FF

03 02 01 00

FF FF 03 02 FF

1 2 345

6789

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Pin name Connection

Ports P1, P6 to P10

OUT

(3)

, V

REF

After setting for input mode, connect every pin to V

via a resistor(pull-down);

or after setting for output mode, leave these pins open.

(1, 2, 4)

Open

Connect to V

Connect via resistor to V

(pull-up)

(5)

NOTES:

1. When setting the port for output mode and leave it open, be aware that the port remains in input mode until it is

switched to output mode in a program after reset. For this reason, the voltage level on the pin becomes

indeterminate, causing the power supply current to increase while the port remains in input mode. Futhermore,

by considering a possibility that the contents of the direction registers could be changed by noise or noise-

induced runaway, it is recommended that the contents of the direction registers be periodically reset in software,

for the increased reliability of the program.

2. Make sure the unused pins are processed with the shortest possible wiring from the microcomputer pins (within 2

cm).

3. With external clock or VCC input to XIN pin.

4. When using the 48-pin package, set PACR2, PACR1, PACR0 to "100

". When using the 42-pin package, set

PACR2, PACR1, PACR0 to "001

5. When the main clock oscillation circuit is not used, set the CM05 bit in the CM0 register to “0” (main clock stops)

to reduce power consumption.

Table 16.1. Unassigned Pin Handling in Single-chip Mode

Figure 16.7. Unassigned Pins Handling

(Input mode)

(Output mode)

OUT

REF

Microcomputer

In single-chip mode

Open

(1)

Port P1, P6 to P10

NOTE:

1. When using the 48-pin package, set PACR2, PACR1, PACR0 to "1002".

When using the 42pin-package, set PACR2, PACR1, PACR0 to "0012".

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Table 17.1. Flash Memory Version Specifications

Item

Flash memory operating mode

Erase block

Program method

Erase method

Program, erase control method

Protect method

Number of commands

Program/Erase

Endurance(1)

ROM code protection

Specification

3 modes (CPU rewrite, standard serial I/O, parallel I/O)

See Figure 17.2.1 to 17.2.3 Flash Memory Block Diagram

In units of word

Block erase

Program and erase controlled by software command

All user blocks are write protected by bit FMR16.

In addition, the block 0 and block 1 are write protected by bit FMR02

5 commands

100 times, 1,000 times (See Tables 1.7, 1.9, and 1.10 )

100 times, 10,000 times (See Tables 1.7, 1.9, and 1.10 )

Parallel I/O and standard serial I/O modes are supported.

Data Retention 20 years (Topr = 55°C)

Block 0 to 3 (program area)

Block A and B (data are) (2)

NOTES:

1. Program and erase endurance definition Program and erase endurance are the erase endurance of each block. If

the program and erase endurance are n times (n=100,1,000,10,000), each block can be erased n times. For

example, if a 2-Kbyte block A is erased after writing 1 word data 1024 times, each to different addresses, this is

counted as one program and erasure.However, data cannot be written to the same address more than once

without erasing the block. (Rewrite disabled)

2. To use the limited number of erasure efficiently, write to unused address within the block instead of rewrite. Erase

block only after all possible address are used. For example, an 8-word program can be written 128 times before

erase is necessary. Maintaining an equal number of erasure between Block A and B will also improve efficiency.

We recommend keeping track of the number of times erasure is used.

17. Flash Memory Version

17.1 Flash Memory Performance

The flash memory version is functionally the same as the mask ROM version except that it internally con-

tains flash memory.

In the flash memory version, the flash memory can perform in three rewrite mode : CPU rewrite mode,

standard serial I/O mode and parallel I/O mode.

Table 17.1 shows the flash memory version specifications. (Refer to Table 1.1 or Table 1.2 for the items not

listed in Table 17.1.)

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Table 17.2. Flash Memory Rewrite Modes Overview

Flash memory CPU rewrite mode Standard serial I/O mode Parallel I/O mode

rewrite mode

Function

Area which User ROM area User ROM area User ROM area

can be rewritten

Operation Single chip mode Boot mode Parallel I/O mode

mode

ROM None Serial programmer Parallel programmer

programmer

The user ROM area is rewrit-

ten when the CPU executes

software command

EW0 mode:

Rewrite in area other than

flash memory

EW1 mode:

Rewrite in flash memory

The user ROM area is rewrit-

ten using a dedicated serial

programmer.

Standard serial I/O mode 1:

Clock synchronous serial

I/O

Standard serial I/O mode 2:

UART

The user ROM area is rewrit-

ten using a dedicated paral-

lel programmer

17.1.1 Boot Mode

The MCU enters boot mode when a hardware reset is performed while a high-level ("H") signal is applied

to pins CNVSS and P86 or while an "H" signal is applied to pins CNVSS and P16 and a low-level ("L")

signal is applied to the P85. A program in the boot ROM area is executed.

The boot ROM area is reserved. The boot ROM area stores the rewrite control program for a standard

serial I/O mode before shipping. Do not rewrite the boot ROM area.

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17.2 Memory Map

The flash memory contains the user ROM area and the boot ROM area (reserved area). Figures 17.2.1 to

17.2.3 show the flash memory block diagram. The user ROM area has space to store the microcomputer

operation program in single-chip mode and a separate 2-Kbyte space as the block A and B.

The user ROM area is divided into several blocks. The user ROM area can be rewritten in CPU rewrite,

standard serial input/output, and parallel input/output modes. However, if block 0 and 1 are rewritten in

CPU rewrite mode, setting the FMR02 bit in the FMR0 register to “1” (block 0, 1 rewrite enabled) and the

FMR16 bit in the FMR1 register to “1”(blocks 0 to 3 rewrite enabled) enable rewriting. Also, if blocks 2 to 3

are rewritten in CPU rewrite mode, setting the FMR16 bit in the FMR1 register to “1” (blocks 0 to 3 rewrite

enabled) enables writing. Setting the PM10 bit in the PM1 register to “1”(data area access enabled) for

block A and B enables to use.

(2)

(4)

(2)

(5)

(3)

NOTES:

1. To specify a block, use the maximum even address in the block.

2. Blocks A and B are enabled to use when the PM10 bit in the PM1

3. Blocks 0 and 1 are enabled for programs and erases when the

FMR02 bit in the FMR0 register is set to "1" and the FMR16 bit in

the FMR1 register is set to "1". (CPU rewrite mode only)

4. The boot ROM area is reserved. Do not access.

5. Blocks 2 and 3 are enabled for programs and erases when the

FMR16 bit in the FMR1 register is set to "1". (CPU rewrite mode

only)

Figure 17.2.1. Flash Memory Block Diagram (ROM capacity 64K byte)

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(2)

(4)

(5)

(2)

(3)

(5)

NOTES:

1. To specify a block, use the maximum even address in the block.

2. Blocks A and B are enabled to use when the PM10 bit in the PM1

3. Blocks 0 and 1 are enabled for programs and erases when the

FMR02 bit in the FMR0 register is set to "1" and the FMR16 bit in

the FMR1 register is set to "1". (CPU rewrite mode only)

4. The boot ROM area is reserved. Do not access.

5. Blocks 2 and 3 are enabled for programs and erases when the

FMR16 bit in the FMR1 register is set to "1". (CPU rewrite mode

only)

00F000

00F7FF

00F800

00FFFF

Figure 17.2.2. Flash Memory Block Diagram (ROM capacity 48K byte)

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(2)

(4)

(2)

(5)

(3)

NOTES:

1. To specify a block, use the maximum even address in the block.

2. Blocks A and B are enabled to use when the PM10 bit in the PM1

3. Blocks 0 and 1 are enabled for programs and erases when the

FMR02 bit in the FMR0 register is set to "1" and the FMR16 bit in

the FMR1 register is set to "1". (CPU rewrite mode only)

4. The boot ROM area is reserved. Do not access.

5. Blocks 2 are enabled for programs and erases when the FMR16 bit

in the FMR1 register is set to "1". (CPU rewrite mode only)

Figure 17.2.3. Flash Memory Block Diagram (ROM capacity 24K byte)

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17.3 Functions To Prevent Flash Memory from Rewriting

The flash memory has a built-in ROM code protect function for parallel I/O mode and a built-in ID code

check function for standard input/output mode to prevent the flash memory from reading or rewriting.

17.3.1 ROM Code Protect Function

The ROM code protect function disables reading or changing the contents of the on-chip flash memory in

parallel I/O mode. Figure 17.3.1.1 shows the ROMCP address. The ROMCP address is located in a user

ROM area.

To enable ROM code protect, set the ROMCP1 bit to “002”, “012”, or “102” and set the bit 5 to bit 0 to

“1111112”.

To cancel ROM code protect, erase the block including the the ROMCP address in CPU rewrite mode or

standard serial I/O mode.

17.3.2 ID Code Check Function

Use the ID code check function in standard serial input/output mode. Unless the flash memory is blank,

the ID codes sent from the programmer and the seven bytes ID codes written in the flash memory are

compared to see if they match. If the ID codes do not match, the commands sent from the programmer

are not acknowledged. The ID code consists of 8-bit data, starting with the first byte, into addresses,

0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716, and 0FFFFB16. The flash memory

has a program with the ID code set in these addresses.

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Figure 17.3.1.1. ROMCP Address

Figure 17.3.2.1. Address for ID Code Stored

Symbol Address Factory Setting

ROMCP 0FFFFF

(4)

ROM Code Protect Control Address

(5)

Bit Name Function

Bit Symbol

b7 b6 b5 b4 b3 b2 b1 b0

00:

01:

10:

11: Disables protect

ROM Code Protect Level

1 Set Bit

(1, 2, 3, 4)

ROMCP1 b7 b6

Reserved Bit Set to 1

Enables protect

}

NOTES:

1. When the ROM code protect is active by the ROMCP1 bit setting, the flash memory is protected

against reading or rewriting in parallel I/O mode.

2. Set the bit 5 to bit 0 to 111111

when the ROMCP1 bit is set to a value other than 11

. If the bit 5 to bit

0 are set to values other than 111111

, the ROM code protection may not become active by setting the

ROMCP1 bit to a value other than 11

3. To make the ROM code protection inactive, erase a block including the ROMCP address in standard

serial I/O mode or CPU rewrite mode.

4. The ROMCP address is set to FF

when a block, including the ROMCP address, is erased.

5. When a value of the ROMCP address is 00

or FF

, the ROM code protect function is disabled.

(b5-b0)

Reset vector

Watchdog timer vector

Single step vector

Address match vector

BRK instruction vector

Overflow vector

Undefined instruction vector

ID7

ID6

ID5

ID4

ID3

ID2

ID1

DBC vector

NMI vector

0FFFFF

to 0FFFFC

0FFFFB

to 0FFFF8

0FFFF7

to 0FFFF4

0FFFF3

to 0FFFF0

0FFFEF

to 0FFFEC

0FFFEB

to 0FFFE8

0FFFE7

to 0FFFE4

0FFFE3

to 0FFFE0

0FFFDF

to 0FFFDC

4 bytes

Address

ROMCP

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Item EW0 mode EW1 mode

Operation mode Single chip mode Single chip mode

Area where User ROM area User ROM area

rewrite control

program can be placed

Area where The rewrite control program must be The rewrite control program can be

rewrite control transferred to any area other than executed in the user ROM area

program can be the flash memory (e.g., RAM) before

executed being executed

Area which can be User ROM area User ROM area

rewritten However, this excludes blocks

with the rewrite control program

Software command None • Program, block erase command

Restrictions Cannot be executed in a block having

the rewrite control program

• Read status register command

Can not be used

Mode after programming Read Status Register mode Read Array mode

or erasing

CPU state during auto- Operation Hold state (I/O ports retain the state

write and auto-erase before the command is executed

(1)

Flash memory status • Read the FMR00, FMR06 and Read the FMR0 register's FMR00,

detection (2) FMR07 bits in the FMR0 register by FMR06, and FMR07 bits in a program

a program

• Execute the read status register

command and read the SR7, SR5

and SR4 bits

Condition for transferring

Set the FMR40 and FMR41 bits in The FMR40 bit in the FMR4 register

to erase-suspend (3)

the FMR4 register to "1" by program. is set to "1" and the interrupt request of

17.4 CPU Rewrite Mode

In CPU rewrite mode, the user ROM area can be rewritten when the CPU executes software commands.

Therefore, the user ROM area can be rewritten directly while the microcomputer is mounted on-board

without using a ROM programmer, etc. Verify the Program and the Block Erase commands are executed

only on blocks in the user ROM area.

For interrupts requested during an erasing operation in CPU rewrite mode, the M16C/26A Group flash

module offers an erase-suspend function which the erasing operation to be suspended, and access made

available to the flash. Erase-write 0 (EW0) mode and erase-write 1 (EW1) mode are provided as CPU

rewrite mode. Table 17.4.1 shows the differences between erase-write 0 (EW0) and erase-write 1 (EW1)

modes. 1 wait is required for the CPU erase-write control.

Table 17.4.1. EW0 Mode and EW1 Mode

NOTES:

1. Do not generate a DMA transfer.

2. Block 1 and 0 are enabled to rewrite by setting the FMR02 bit in the FMR0 register to "1" and

setting the FMR16 bit in the FMR1 register to "1". Block 2 to 3 are enabled to rewrite by setting the

FMR16 bit in the FMR1 register to "1".

3. The time, until entering erase suspend and reading flash is enabled, is maximum td (SR-ES) after

satisfying the conditions.

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17.4.1 EW0 Mode

The microcomputer enters CPU rewrite mode by setting the FMR01 bit in the FMR0 register to “1” (CPU

rewrite mode enabled) and is ready to acknowledge the software commands. EW0 mode is selected by

setting the FMR11 bit in the FMR1 register to “0”.

When setting the FMR01 bit to “1”, set to “1” after first writing “0”. The software commands control pro-

gramming and erasing. The FMR0 register or the status register indicates whether a programming or

erasing operations is completed.

When entering the erase-suspend during the auto-erasing, set the FMR40 bit to “1” (erase-suspend

enabled) and the FMR41 bit to “1” (suspend request). And wait for td(SR-ES). After verifying the FMR46

bit is set to “1” (auto-erase stop), access to the user ROM area. When setting the FMR41 bit to “0” (erase

restart), auto-erasing is restarted.

17.4.2 EW1 Mode

EW1 mode is selected by setting the FMR11 bit to “1” after the FMR01 bit is set to “1”. (set to “1” after first

writing “0”). The FMR0 register indicates whether or not a programming or an erasing operation is com-

pleted. Do not execute the software commands of read status register in EW1 mode.

When an erase/program operation is initiated the CPU halts all program execution until the operation is

completed or erase-suspend is requested.

When enabling an erase suspend function, set the FMR40 bit to “1” (erase suspend enabled) and ex-

ecute block erase commands. Also, preliminarily set an interrupt to enter the erase-suspend to an inter-

rupt enabled status. After td(SR-ES) from an interrupt request and entering erase suspend, an interrupt

can be acknowledged.

When an interrupt request is generated, the FMR41 bit is automatically set to “1” (suspend request) and

an auto-erasing is halted. If an auto-erasing is not completed (the FMR00 bit is “0”) after an interrupt

process completed, set the FMR41 bit to “0” (erase restart) and execute block erase commands again.

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17.5 Register Description

Figure 17.5.1 shows the flash memory control register 0 and flash memory control register 1. Figure 17.5.2

shows the flash memory control register 4.

17.5.1 Flash memory control register 0 (FMR0)

•FMR 00 Bit

This bit indicates the operation status of the flash memory. The bit is “0” during programming, erasing,

or erase-suspend mode; otherwise, the bit is “1”.

•FMR01 Bit

The microcomputer enables to acknowledge commands by setting the FMR01 bit to “1” (CPU rewrite

mode). To set this bit to “1”, it is necessary to set to “1” after first setting to “0”. Set this bit to “0” by only

writing “0”.

•FMR02 Bit

The combined setting of the FMR02 bit and the FMR16 bit enable to program and erase in the user

ROM area. See Table 17.5.2.1 for setting details. To set this bit to “1”, it is necessary to set to “1” after

first setting to “0”. Set this bit to “0” by only writing “0”. This bit is enabled only when the FMR01 bit is

“1” (CPU rewrite mode enable).

•FMSTP Bit

This bit resets the flash memory control circuits and minimizes power consumption in the flash

memory. Access to the flash memory is disabled when the FMSTP bit is set to “1”. Set the FMSTP bit

by a program in a space other than the flash memory.

Set the FMSTP bit to “1” if one of the following occurs:

•A flash memory access error occurs during erasing or programming in EW0 mode (FMR00 bit does

not switch back to “1” (ready)).

•Low-power consumption mode or on-chip oscillator low-power consumption mode is entered.

Figure 17.5.1.3 shows a flow chart illustrating how to start and stop the flash memory before and after

entering low power mode. Follow the procedure on this flow chart.

To enter stop or wait mode when CPU rewrite mode is disabled, do not set the FMR0 register. The

flash memory is automatically turned off when entering and turned back on when exiting.

•FMR06 Bit

This is a read-only bit indicating an auto-program operation status. This bit is set to “1” when a pro-

gram error occurs; otherwise, it is set to “0”. For details, refer to 17.8.4 Full Status Check.

•FMR07 Bit

This is a read-only bit indicating an auto-erase operation status. The bit is set to “1” when an erase

error occurs; otherwise, it is set to “0”. For details, refer to 17.8.4 Full Status Check.

Figure 17.5.1.1 shows a EW0 mode set/reset flowchart, figure 17.5.1.2 shows a EW1 mode set/reset

flowchart.

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17.5.2 Flash memory control register 1 (FMR1)

•FMR11 Bit

EW1 mode is entered by setting the FMR11 bit to “1” (EW1 mode). This bit is enabled only when the

FMR01 bit is “1”.

•FMR16 Bit

The combined setting of the FMR02 bit and the FMR16 bit enables to program and erase in the user

ROM area. To set this bit to “1”, it is necessary to set to “1” after first setting to “0”. Set this bit to “0” by

only writing “0”. This bit is enabled only when the FMR01 bit is “1”.

•FMR17 Bit

If FMR17 bit is “1” (with wait state), regardless of the content of the PM17 bit, 1 wait is inserted at the

access to block A and block B. Regardless of the content of the FMR17 bit, access to other block and

the internal RAM is determined by PM17 bit setting.

Set this bit to “1” (with wait state) when rewriting more than 100 times (U7 and U9).

Table 17.5.2.1. Protection using FMR16 and FMR02

FMR16 FMR02 Block A, Block B Block 0, Block 1 other user block

0 0 write enabled write disabled write disabled

0 1 write enabled write disabled write disabled

1 0 write enabled write disabled write enabled

1 1 write enabled write enabled write enabled

17.5.3 Flash memory control register 4 (FMR4)

•FMR40 Bit

The erase-suspend function is enabled by setting the FMR40 bit is set to “1” (enabled).

•FMR41 Bit

When setting the FMR41 bit to “1” in a program during auto-erasing in EW0 mode the flash module

enters erase suspend mode. In EW1 mode, the FMR41 bit is automatically set to “1” (suspend re-

quest) when an interrupt request of an enabled interrupt is generated, the FMR41 bit is automatically

set to “1” (suspend request) and when an auto-erasing operation is restarted, set the FMR41 bit to “0”

(erase restart).

•FMR46 Bit

The FMR46 bit is set to “0” during auto-erasing execution and set to “1” during erase-suspend mode.

Do not access to flash memory while this bit is “0”.

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Figure 17.5.1. FMR0 and FMR1 register

Flash memory control register 0

Symbol Address After reset

FMR0 01B7

00000001

b7 b6 b5 b4 b3 b2 b1 b0

FMR00

Bit symbol

Bit name Function RW

0: Busy (during writing or erasing)

1: Ready

CPU rewrite mode select bit

(1) 0: Disables CPU rewrite mode

(Disables software command)

1: Enables CPU rewrite mode

(Enables software commands)

FMR01

Block 0, 1 rewrite enable bit

(2) Set write protection for user ROM area

(see Table 17.5.2.1)

Flash memory stop bit

(3, 5)

FMR02

FMSTP

RY/BY status flag

Reserved bit Set to “0”

0: Terminated normally

1: Terminated in error

Program status flag

FMR06

0: Terminated normally

1: Terminated in error

Erase status flag

FMR07

(b5-b4)

0: Starts flash memory operation

1: Stops flash memory operation

(Enters low-power consumption state

and flash memory reset)

(4)

Flash memory control register 1

Symbol

Address

After reset

FMR1 01B5

000XXX0X

b7 b6 b5 b4 b3 b2 b1 b0

Bit symbol

Bit name Function

EW1 mode select bit (1) 0: EW0 mode

1: EW1 mode

FMR11

Block A, B access wait bit

(3)

Reserved bit When read, its content is indeterminate

Reserved bit Set to “0”

Nothing is assigned. When write, set to “0”.

When read, its contect is indeterminate.

(b0)

(b4)

Reserved bit

(b3-b2)

(b5)

FMR16

Block 0 to 3 rewrite enable

bit (2)

FMR17

Set write protection for user ROM area

(see Table 17.5.2.1)

0: Disable

1: Enable

0: PM17 enabled

1: With wait state (1 wait)

When read, its content is indeterminate

NOTES:

1. When setting this bit to “1”, set to “1” immdediately after setting it first to “0”. Do not generate an interrupt

or a DMA transfer between setting the bit to “0” and setting it to “1”. Set this bit while the P8

/NMI/SD pin

is “H” when selecting the NMI function. Set by program in a space other than the flash memory in EW0

mode. Set this bit to read alley mode and “0”

2. Set this bit to “1” immediately after setting it first to “0” while the FMR01 bit is set to “1”. Do not generate

an interrupt or a DMA transfer between setting this bit to “0” and setting it to “1”.

3. Set this bit in a pace other than the flash memory by program. When this bit is set to 1, access to flash

memory will be denied. To set this bit to 0 after setting it to 1, wait for 10 µsec. or more after setting it to

1. To read data from flash memory after setting this bit to 0, maintain tps wait time before accessing

flash memory.

4. This bit is set to “0” by executing the clear status command.

5. This bit is enabled when the FMR01 bit is set to “1” (CPU rewrite mode). This bit can be set to “1” when

the FMR01 bit is set to “0”. However, the flash memory does not enter low-power consumption status

NOTES:

1. Set this bit to “1” immediately after setting it first to “0”. Do not generate an interrupt or a DMA transfer

between setting the bit to “0” and setting it to “1”. Set this bit while the P8

/NMI/SD pin is “H” when the

NMI function is selected. If the FMR01 bit is set to “0”, the FMR01 bit and FMR11 bit are both set to “0”

2. Set this bit to “1” immediately after setting it first to “0”. Do not generate an interrupt or a DMA transfer

after setting to “0”.

3. When rewriting more than 100 times, set this bit to “1” (with wait state). When the FMR17 bit is “1” (with

wait state), regardless of the content of the PM17 bit, 1 wait is inserted at the access to the block A and

B. Regardless of the content of the FMR17 bit, access to other block and the internal RAM is

determined be PM17 bit setting.

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Figure 17.5.2. FMR4 register

Flash Memory Control Register 4

Symbol

Address

After Reset

FMR4 01B3

01000000

b7 b6 b5 b4 b3 b2 b1 b0

Bit Symbol

Bit Name Function

Erase suspend

request bit

(2)

0: Erase restart

1: Suspend request

FMR41

Reserved bit Set to 0

Erase suspend function

enable bit

(1)

0: Disabled

1: Enabled

Reserved bit Set to 0

FMR40

(b5-b2)

(b7)

FMR46

Erase status 0: During auto-erase operation

1: Auto-erase stop

(erase suspend mode)

NOTES:

1. Set the FMR40 bit to 1 immediately after setting it first to 0. Do not generate any interrupt or DMA

transfer between setting the bit to 0 and setting it to 1. Set by program in space other than the flash

memory in EW mode 0.

2. The FMR41 bit is valid only when the FMR40 bit is set to 1. The FMR41 bit can be written only

between executing an erase command and completing erase (this bit is set to 0 other than the

above duration). The FMR41 bit can be set to 0 or 1 by program in EW mode 0. In EW mode 1, the

FMR41 bit is automatically set to 1 when the FMR40 bit is 1 and a maskable interrupt is generated

during erasing. The FMR41 bit cannot be set to 1 by program (it can be set to 0 by program).

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Execute the Read Array command (3)

Single-chip mode

Set CM0, CM1, and PM1 registers (1) Execute software commands

Jump to the rewrite control program transfered to an

internal RAM area (in the following steps, use the

rewrite control program internal RAM area)

Transfer a rewrite control program to internal RAM

area

Write “0” to the FMR01 bit

(CPU rewrite mode disabled)

Set the FMR01 bit to “1” after writing “0”

(CPU rewrite mode enabled) (2)

EW0 mode operation procedure

Rewrite control program

Jump to a specified address in the flash memory

NOTES:

1. Select 10 MHz or below for CPU clock using the CM06 bit in the CM0 register and CM17 to 16 bits in the CM1

2. Set the FMR01 bit to “1” immediately after setting it to “0”. Do not generate an interrupt or a DMA transfer between

setting the bit to “0” and setting it to “1”. Set the FMR01 bit in a space other than the internal flash memory. Also,

set only when the P85/NMI/SD pin is “H” at the time of the NMI function selected.

3. Disables the CPU rewrite mode after executing the read array command.

Figure 17.5.1.1. Setting and Resetting of EW0 Mode

Figure 17.5.1.2. Setting and Resetting of EW1 Mode

Single-chip mode

Set CM0, CM1, and PM1 registers (1)

Set the FMR01 bit to “1” (CPU rewrite mode

enabled) after writing “0”

Set the FMR11 bit to “1” (EW mode 1) after writing

“0” (2, 3)

Program in ROM

EW mode 1 operation procedure

Execute software commands

Set the FMR01 bit to “0”

(CPU rewrite mode disabled)

NOTES:

1. Select 10 MHz or below for CPU clock using the CM06 bit in the CM0 register and CM17 to 16 bits.

in the CM1 register. Also, set the PM17 bit in the PM1 register to “1” (with wait state).

2. Set the FMR01 bits to “1” immediately after setting it to “0”. Do not generate an interrupt or a DMA

transfer between setting the bit to “0” and setting the bit to “1”. Set the FMR01 bit in a space other

than the internal flash memory. Set only when the P85/NMI/SD pin is “H” at the time of the NMI

function selected.

3. Set the FMR11 bit to "1" immediately after setting it to "0" while the FMR01 bit is set to "1". Do not

generate an interrupt or a DMA transfer between setting the FMR11 bit to "0" and setting it to "1".

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Figure 17.5.1.3. Processing Before and After Low Power Dissipation Mode

Start main clock oscillation

Transfer a low power internal consumption mode

program to RAM area

Switch the clock source of CPU clock.

Turn main clock off. (2)

Jump to the low power consumption mode

program transferred to internal RAM area.

(In the following steps, use the low-power

consumption mode program or internal RAM area)

Wait until the flash memory circuit stabilizes (tPS)(3)

Set the FMSTP bit to “0” (flash memory operation)

Set the FMSTP bit to “1” (flash memory stopped.

Low power consumption state)(1)

Process of low power consumption mode or

on-chip oscillator low power consumption mode

switch the clock source of the CPU clock (2)

Low power consumption

mode program

Set the FMR01 bit to “0”

(CPU rewrite mode disabled)

Set the FMR01 bit to “1” after setting “0”

(CPU rewrite mode enabled)

Jump to a desired address in the flash memory

wait until oscillation stabilizes

NOTES:

1. Set the FMRSTP bit to “1” after setting the FMR01 bit to “1”(CPU rewrite mode).

2. Wait until the clock stabilizes to switch the clock source of the CPU clock to the main clock or the sub clock.

3. Add a tPS wait time by a program. Do not access the flash memory during this wait time.

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17.6 Precautions in CPU Rewrite Mode

Described below are the precautions to be observed when rewriting the flash memory in CPU rewrite mode.

17.6.1 Operation Speed

When CPU clock source is the main clock, before entering CPU rewrite mode (EW0 or EW1 mode),

select 10 MHz or below for CPU clock using the CM06 bit in the CM0 register and the CM17 to CM16

bits in the CM1 register. Also, when selecting f3(ROC) of a on-chip oscillator as a CPU clock source,

before entering CPU rewrite mode (EW0 or EW1 mode), the ROCR3 to ROCR2 bits in the ROCR

On both cases, set the PM17 bit in the PM1 register to “1” (with wait state).

17.6.2 Prohibited Instructions

The following instructions cannot be used in EW0 mode because the CPU tries to read data in the

flash memory: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK in-

struction

17.6.3 Interrupts

EW0 Mode

• To use interrupts having vectors in a relocatable vector table, the vectors must be relocated to the

RAM area.

_______

• The NMI and watchdog timer interrupts can be used since the FMR0 and FMR1 registers are

forcibly reset when either interrupt is generated. However, the jump addresses for each interrupt

service routines to the fixed vector table are set and interrupt programs are required. Flash

memory rewrite operation is halted when the NMI or watchdog timer interrupt is generated. Set the

FMR01 bit to “1” and execute the rewrite and erase program again after exiting the interrupt rou-

tine.

• The address match interrupt can not be used since the CPU tries to read data in the flash memory.

EW1 Mode

• Do not acknowledge any interrupts with vectors in the relocatable vector table or the address

match interrupt during the auto-program or erase-suspend function.

17.6.4 How to Access

To set the FMR01, FMR02, FMR11 or FMR16 bit to “1”, write “1” after first setting the bit to “0”. Do not

generate an interrupt or a DMA transfer between the instruction to set the bit to “0” and the instruction

_______

to set it to “1”. When the NMI function is selected, set the bit while an “H” signal is applied to the P85/

_______ _____

NMI/SD pin.

17.6.5 Writing in the User ROM Space

17.6.5.1 EW0 Mode

• If the supply voltage drops while rewriting the block where the rewrite control program is stored,

the flash memory can not be rewritten, because the rewrite control program is not correctly rewrit-

ten. If this error occurs, rewrite the user ROM area in standard serial I/O mode or parallel I/O

mode.

17.6.5.2 EW1 Mode

• Do not rewrite the block where the rewrite control program is stored.

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17.6.6 DMA Transfer

In EW1 mode, do not perform a DMA transfer while the FMR00 bit in the FMR0 register is set to “0”.

(the auto-programming or auto-erasing duration ).

17.6.7 Writing Command and Data

Write the command code and data to even addresses in the user ROM area.

17.6.8 Wait Mode

When entering wait mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) before executing the

WAIT instruction.

17.6.9 Stop Mode

When entering stop mode, set the FMR01 bit to “0” (CPU rewrite mode disabled) and disable the DMA

transfer before setting the CM10 bit to “1” (stop mode).

17.6.10 Low Power Consumption Mode and On-chip Oscillator-Low Power Consump-

tion Mode

If the CM05 bit is set to “1” (main clock stopped), do not execute the following commands.

• Program

• Block erase

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17.7 Software Commands

Read or write 16-bit commands and data from or to even addresses in the user ROM area. When writing

a command code, 8 high-order bits (D15–D8) are ignored.

Table 17.7.1. Software Commands

17.7.1 Read Array Command (FF16)

This command reads the flash memory.

By writing command code ‘xxFF16’ in the first bus cycle, read array mode is entered. Content of a

specified address can be read in 16-bit unit after the next bus cycle. The microcomputer remains in

read array mode until an another command is written. Therefore, contents of multiple addresses can

be read consecutively.

17.7.2 Read Status Register Command (7016)

This command reads the status register.

By writing command code ‘xx7016’ in the first bus cycle, the status register can be read in the second

bus cycle (Refer to 17.8 Status Register). Read an even address in the user ROM area. Do not

execute this command in EW1 mode.

Command

Program

Clear status register

Read array

Read status register

First bus cycle Second bus cycle

Block erase

Write

Mode

Read

Write

Mode

Address

SRD

xxD016

Data

(D15 to D0)

xxFF16

xx7016

xx5016

xx4016

xx2016

Data

(D15 to D0)

Address

SRD: Status register data (D7 to D0)

WA : Write address (However,even address)

WD : Write data (16 bits)

BA : Highest-order block address (However,even address)

X : Any even address in the user ROM area

xx : 8 high-order bits of command code (ignored)

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Start

Program

completed

YES

Write command code ‘xx40

’ to

the write address

(1)

Write data to the write address

(1)

FMR00=1?

Full status check

(2)

NOTE:

1: Write the command code and data at even address.Note 2: Refer to "Figure 17.8.4.1. Full Status

Check and Handling Procedure for Each Error"

Figure 17.7.4.1. Flow Chart of Program Command

17.7.3 Clear Status Register Command (5016)

This command clears the status register to “0”.

By writing ‘xx5016’ in the first bus cycle, and the FMR06 to FMR07 bits in the FMR0 register and SR4

to SR5 bits in the status register are set to “0”.

17.7.4 Program Command (4016)

The program command writes 2-byte data to the flash memory. By writing ‘xx4016’ in the first bus cycle

and data to the write address specified in the second bus cycle, the auto-programming/erasing (data

prorgramming and verify) start. Set the address value specified in the first bus cycle to same and even

address as the write address specified in the second bus cycle. The FMR00 bit in the FMR0 register

indicates whether an auto-programming operation has been completed. The FMR00 bit is set to “0”

during the auto-programming and “1” when the auto-programming operation is completed. After the

auto-programming operation is completed, the FMR06 bit in the FMR0 register indicates whether or

not the auto-programming operation has been completed as expected. (Refer to 17.8.4 Full Status

Check). Also, each block disables writing (Refer to “Table 17.5.2.1”). Do not write additions to the

address which is already programmed. When commands other than a program command are ex-

ecuted immediately after a program command, set the same address as the write address specified in

the second bus cycle of the program command, to the specified address value in the first bus cycle of

the following command. In EW1 mode, do not execute this command on the blocks where the rewrite

control program is allocated. In EW0 mode, the microcomputer enters read status register mode as

soon as the auto-programming operation starts and the status register can be read. The SR7 bit in the

status register is set to “0” as soon as the auto-programming operation starts. This bit is set to “1”

when the auto-programming operation is completed. The microcomputer remains in read status regis-

ter mode until the read array command is written. After completion of the auto-programming operation,

the status register indicates whether or not the auto-programming operation has been completed as

expected.

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Write ‘xxD0

’ to the highest-order

block address(1)

Start

Block erase completed

YES

Write command code ‘xx20

’(1)

FMR00=1?

Full status check(2,3)

NOTES:

1. Write the command code and data at even address.

2. Refer to "Figure 17.8.4.1. Full Status Check and Handling Porcedure for Each Error".

3. Execute the clear status register command and block erase command at least 3 times until an erase error is

not generated when an erase error is generated.

Figure 17.7.5.1. Flow Chart of Block Erase Command (when not using erase suspend function)

17.7.5 Block Erase

By writing ‘xx2016’ in the first bus cycle and ‘xxD016’ in the second bus cycle to the highest-order (even

addresse of a block) and the auto-programming/erasing (erase and erase verify) start. The FMR00 bit

in the FMR0 register indicates whether the auto-programming operation has been completed. The

FMR00 bit is set to “0” (busy) during the auto-erasing operation and “1” (ready) when the auto-erasing

operation is completed. When using the erase-suspend function in EW0 mode, the FMR46 bit in the

FMR4 register indicates whether a flash memory has entered erase-suspend mode. The FMR46 bit is

set to “0” during auto-erasing operation and “1” when the auto-erasing operation is completed (enter-

ing erase-suspend). After the completion of an auto-erasing operation, the FMR07 bit in the FMR0

to 17.8.4 Full Status Check). Also, each block disables erasing. (Refer to “Table 17.5.2.1”). Figure

17.7.5.1 shows a flow chart of the block erase command programming when not using the erase-

suspend function. Figure 17.7.5.2 shows a flow chart of the block erase command programming when

using an erase-suspend function. In EW1 mode, do not execute this command on the block where the

rewrite control program is allocated. In EW0 mode, the microcomputer enters read status register

mode as soon as the auto-erasing operation starts and the status register can be read. The SR7 bit in

the status register is set to “0” as soon as the auto-erasing operation starts. This bit is set to “1” when

the auto-erasing operation is completed. The microcomputer remains in read status register mode

until the read array command is written. Also excute the clear status register command and block

erase command at least 3 times until an erase error is not generated when an erase error is gener-

ated.

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Start

Block erase completed

Write the command code ‘xx20

’

(1)

Write ‘xxD0

’ to the highest-order

block address (1)

YES

FMR00=1?

Full status check(2,4)

FMR40=1

Interrupt service routine (3)

FMR41=1

YES

FMR46=1?

Access Flash Memory

Return

(Interrupt service routine end)

FMR41=0

(EW0 mode)

(EW1 mode)

Start

Block erase completed

Write the command code ‘xx20

’

(1)

Write ‘xxD0

’ to the highest-order

block address (1)

YES

FMR00=1?

Full status check(2,4)

FMR40=1

FMR41=0

Interrupt service routine (3)

Access Flash Memory

Return

(Interrupt service routine end)

NOTES:

1. Write the command code and data to even address.

2. Execute the clear status register command and block erase command at least 3 times until an erase

error is not generated when an erase error is generated.

3. In EW0 mode, allocate an interrupt vector table of an interrupt, to be used, to a RAM area.

4. Refer to "Figure 17.8.4.1 Full Status Check and Handling Procedure for Each Error."

Figure 17.7.5.2. Block Erase Command (at use erase suspend)

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Bits in the

SRD register

SR4 (D

)

SR5 (D

)

SR7 (D

)

SR6 (D

)

Status name Contents

SR1 (D

)

SR2 (D

)

SR3 (D

)

SR0 (D

)

Program status

Erase status

Sequence status

Reserved

"1"

Ready

Terminated by error

"0"

Busy

Completed normally

Reserved

Bits in the

FMR0

FMR00

FMR07

FMR06

Value

after

reset

Table 17.8.1. Status Register

17.8 Status Register

The status register indicates the operating status of the flash memory and whether an erasing or a pro-

gramming operates normally and an error ends. The FMR00, FMR06, and FMR07 bits in the FMR0

Table 17.8.1 shows the status register.

In EW0 mode, the status register can be read in the following cases:

(1) When a given even address in the user ROM area is read after writing the read status register

command

(2) When a given even address in the user ROM area is read after executing the program or block

erase command but before executing the read a rray command.

17.8.1 Sequence Status (SR7 and FMR00 Bits )

The sequence status indicates the operating status of the flash memory. This bit is set to “0” (busy)

during an auto-programming and auto-erasing and “1” (ready) as soon as these operations are com-

pleted. This bit indicates “0” (busy) in erase-suspend mode.

17.8.2 Erase Status (SR5 and FMR07 Bits)

Refer to 17.8.4 Full Status Check.

17.8.3 Program Status (SR4 and FMR06 Bits)

Refer to 17.8.4 Full Status Check.

• D7 to D0: Indicates the data bus which is read out when executing the read status register command.

• The FMR07 bit (SR5) and FMR06 bit (SR4) are set to “0” by executing the clear status register command.

• When the FMR07 bit (SR5) or FMR06 bit (SR4) is 1, the program, and block erase command are not

acknowledged.

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17.8.4 Full Status Check

When an error occurs, the FMR06 to FMR07 bits in the FMR0 register are set to “1”, indicating occur-

rence of each specific error. Therefore, execution results can be verified by checking these status bits

(full status check). Table 17.8.4.1 shows errors and the status of FMR0 register. Figure 17.8.4.1

shows a flow chart of the full status check and handling procedure for each error.

Table 17.8.4.1. Errors and FMR0 Register Status

FMR0 register

(SRD register)

status Error Error occurrence condition

FMR07 FMR06

(SR5) (SR4)

1 1 Command • When any commands are not written correctly

sequence error • A value other than ‘xxD016’ or ‘xxFF16’ is written in the second

bus cycle of the block erase command (1)

• When the block erase command is executed on protected blocks

• When the program command is executed on protected blocks

1 0 Erase error • When the block erase command is executed on unprotected

blocks but the blocks are not automatically erased correctly

0 1 Program error • When the program command is executed on unprotected blocks

but the blocks are not automatically programmed correctly.

NOTE:

1. The flash memory enters read array mode by writing command code ‘xxFF16’ in the second bus

cycle of these commands. The command code written in the first bus cycle becomes invalid.

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Full status check

FMR06 =1

and

FMR07=1?

Command

sequence error

YES

FMR07=0?

YES

Erase error

(1) Execute the clear status register command and set

the status flag to “0” whether the command is

entered.

(2) Reexecute the command after checking that it is

entered correctly or the program command or the

block erase command is not executed for the

blocks which are protected.

(1) Execute the clear status register command and set

the erase status flag to “0”.

(2) Reexecute the block erase command.

(3) Execute (1) and (2) at least 3 times until an erase

error is not generated.

Note 3: If the FMR06 or FMR07 bits is “1”, any of the Program or Block Erase command can not

be aknowledged. Execute the clear status register command before executing those

commands.

FMR06=0?

YES

Program error

Full status check completed

Note 1: If the error still occurs, the block can not be

used.

(1) Execute the clear status register command and set

the program status flag to “0”.

(2) Reexecute the Program command.

Note 2: If the error still occurs, the block can not be

used.

[During programming]

Figure 17.8.4.1. Full Status Check and Handling Procedure for Each Error

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17.9 Standard Serial I/O Mode

In standard serial input/output mode, the user ROM area can be rewritten while the microcomputer is

mounted on-board by using a serial programmer which is applicable for the M16C/26A group. For more

information about serial programmers, contact the manufacturer of your serial programmer. For details on

how to use the serial programmer, refer to the user’s manual included with your serial programmer.

Table 17.9.1 shows pin functions (flash memory standard serial input/output mode). Figures 17.9.1 and

17.9.2 show pin connections for standard serial input/output mode.

17.9.1 ID Code Check Function

This function determines whether the ID codes sent from the serial programmer and those written in the

flash memory match. (Refer to 17.3 Functions To Prevent Flash Memory from Rewriting.)

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Table 17.9.1. Pin Functions (Flash Memory Standard Serial I/O Mode)

NOTES:

1. When using standard serial input/output mode 1, to input “H” to the TxD pin is necessary while the

___________

RESET pin is “L”. Therefore, connect this pin to VCC via a resistor. Adjust the pull-up resistor value on

a system not to affect a data transfer after reset, because this pin changes to a data-output pin

2. Set following either or both

_____

•Connect the CE pin to VCC.

_____

•Connect the RP pin to VSS and the P16 pin to VCC.

Pin Description

VCC,VSS Apply the voltage guaranteed for Program and Erase to Vcc pin and 0

V to Vss pin.

CNVSS Connect to Vcc pin.

RESET

XIN Connect a ceramic resonator or crystal oscillator between X IN and

XOUT pins. To input an externally generated clock, input it to X IN pin

and open XOUT pin.

XOUT

AVCC, AVSS

VREF

Connect AVss to Vss and AVcc to Vcc, respectively.

Enter the reference voltage for AD from this pin.

P15, P17Input "H" or "L" level signal or open.

P60 to P63Input "H" or "L" level signal or open.

P64Standard serial I/O mode 1: BUSY signal output pin

Standard serial I/O mode 2: Monitor signal output pin for boot program

operation check

P65

P66Serial data input pin

P67Serial data output pin

P70 to P77Input "H" or "L" level signal or open.

P80 to P84,

P87Input "H" or "L" level signal or open.

P90 to P93,Input "H" or "L" level signal or open.

P100 to P107Input "H" or "L" level signal or open.

Name

Power input

CNVSS

Reset input

Clock input

Clock output

Analog power supply input

Reference voltage input

Input port P1

Input port P6

BUSY output

SCLK input

RxD input

TxD output

Input port P7

Input port P8

Input port P9

Input port P10

I/O

P85RP input I Connect this pin to Vss while RESET is low. (2)

Standard serial I/O mode 1: Serial clock input pin

Standard serial I/O mode 2: Input "L".

Reset input pin. While RESET pin is "L" level, wait for td(ROC).

(1)

P86CE input IConnect this pin to Vcc while RESET is low. (2)

P16P16 input Connect this pin to Vcc while RESET is low. (2)

17. Flash Memory Version

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Figure 17.9.1. Pin Connections for Serial I/O Mode (1)

M16C/26A Group

(M16C/26A)

(Flash memory version)

PRSP0042GA-B (42P2R)

BUSY SCLK

RxD TxD

Vcc

Vss

RESET

Connect

oscillator

circuit

Mode setup method

Signal

CNVss

Reset

Value

Vcc

Vss to Vcc

(1)

NOTE:

1. Set following either or both in serial I/O mode while the RESET pin is held “L”.

⋅ Connect the CE pin to V

⋅ Connect the RP pin to V

and the P1

pin to V

(1)

17. Flash Memory Version

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Figure 17.9.2. Pin Connections for Serial I/O Mode (2)

M16C/26A Group

(M16C/26A, M16C/26B, M16C/26T)

(Flash memory version)

PLQP0048KB-A (48P6Q)

Mode setup method

Signal

CNVss

Reset

Value

Vcc

Vss to Vcc

BUSY SCLK

RxD TxD

Connect

oscillator

circuit

Vcc

Vss

RESET

(1)

NOTE:

1. Set following either or both in serial I/O mode while the RESET pin is held “L”.

⋅ Connect the CE pin to V

⋅ Connect the RP pin to V

and the P16 pin to V

17. Flash Memory Version

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17.9.2 Example of Circuit Application in Standard Serial I/O Mode

Figure 17.9.2.1 shows an example of a circuit application in standard serial I/O mode 1 and Figure

17.9.2.2 shows an example of a circuit application in standard serial I/O mode 2. Refer to the user's

manual for a serial writer to handle pins controlled by the serial writer.

Figure 17.9.2.1. Circuit Application in Standard Serial I/O Mode 1

SCLK input

BUSY output

TxD output

RxD input

BUSY

SCLK

TXD

CNVss

P86(CE)

RESET

RxD

Reset input

User reset

singnal

Microcomputer

(1) Controlling pins and external circuits vary with the serial programmer. For more

information, refer to the user's manual included with the serial programmer.

(2) In this example, a selector controls the input voltage applied to CNVss to switch

between single-chip mode and standard serial I/O mode.

(3) In standard serial input/output mode 1, if the user reset signal becomes “L” while

the microcomputer is communicating with the serial programmer, break the

connection between the user reset signal and the RESET pin using a jumper

switch.

P85(RP)

(1)

NOTE:

1. Set following either or both

• Connect the CE pin to VCC

• Connect the RP pin to VSS and the P16 pin to VCC

P16

(1)

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Monitor output

RxD input

TxD output

BUSY

SCLK

TxD

CNVss

P86(CE)

RxD

Microcomputer

(1) In this example, a selector controls the input voltage applied to CNVss to switch

between single-chip mode and standard serial I/O mode.

P85(RP) (1)

(1)

NOTE:

1. Set following either or both

• Connect the CE pin to VCC

• Connect the RP pin to VSS and the P16 pin to VCC

P16

(1)

Figure 17.9.2.2. Circuit Application in Standard Serial I/o Mode 2

17. Flash Memory Version

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17.10 Parallel I/O Mode

In parallel input/output mode, the user ROM can be rewritten using a parallel programmer which is appli-

cable for the M16C/26A group. For more information about the parallel programmer, contact your parallel

programmer manufacturer. For details on how to use the parallel programmer, refer to the user’s manual of

the parallel programmer.

17.10.1 ROM Code Protect Function

The ROM code protect function prevents the flash memory from being read or rewritten. (Refer to 17.3

Function to Prevent Flash Memory from Rewriting.)

18. Electrical Characteristics (M16C/26A, M16C/26B)

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18. Electrical Characteristics

Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor

for electrical characteristics of V-ver.

18.1. M16C/26A, M16C/26B (Normal version)

Table 18.1. Absolute Maximum Ratings

lobmySretemaraPnoitidnoCeulaVtinU

egatloVylppuSV

VA=

5.6ot3.0-V

egatloVylppuSgolanAV

VA=

5.6ot3.0-V

egatloVtupnI1P

1Pot

6P,

6Pot

7P,

7Pot

8Pot

9P,

9Pot

01P,

01Pot

FER

VNC,TESER,

Vot3.0-

3.0+V

egatloVtuptuO1P

1Pot

6P,

6Pot

7P,

7Pot

8Pot

9P,

9Pot

01P,

01Pot

TUO

Vot3.0-

3.0+V

dPnoitapissiDrewoP04-< rpoT< C°58003Wm

rpoTgnitarepO tneibmA erutarepmeT

noitarepoUPCgnirud /58ot02- 58ot04-

)1(

C°

yromemhsalfgnirud esarednamargorp noitarepo

ecapSmargorP )3kcolBot0kcolB( 06ot0C°

ecapSataD )BkcolB,AkcolB( /06ot0 /58ot02- 58ot04-

)1(

C°

gtsTerutarepmeTegarotS 051ot56-C°

NOTE:

1. Refer to Tables 1.7 and 1.8.

18. Electrical Characteristics (M16C/26A, M16C/26B)

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Table 18.2.

Recommended Operating Conditions

(

lobmySretemaraP dradnatS tinU

.niM.pyT.xaM

VCC egatloVylppuS 7.25.5V

VA CC egatloVylppuSgolanA V CC V

VSS egatloVylppuS 0V

VA SS egatloVylppuSgolanA 0V

VHI )"H"(hgiHtupnI egatloV 1P 51Pot 76P, 06Pot 77P, 07Pot 7,

8P 08Pot 79P, 09Pot 301P, 001Pot 7

V7.0 CC VCC V

SSVNC,TESER,NIX V8.0 CC VCC V

VLI )"L"(woLtupnI egatloV 1P 51Pot 76P, 06Pot 77P, 07Pot 7,

8P 08Pot 79P, 09Pot 301P, 001Pot 7

0V3.0 CC V

SSVNC,TESER,NIX 0V2.0 CC V

)kaep(HO

hgiHtuptuOkaeP tnerruC)"H"(

1P 51Pot 76P, 06Pot 77P, 07Pot 7,

8P 08Pot 79P, 09Pot 301P, 001Pot 7

0.01-Am

I)gva(HO

tuptuOegarevA tnerruC)"H"(hgiH

1P 51Pot 76P, 06Pot 77P, 07Pot 7,

8P 08Pot 79P, 09Pot 301P, 001Pot 7

0.5-Am

I)kaep(LO

woLtuptuOkaeP tnerruC)"L"(

1P 51Pot 76P, 06Pot 77P, 07Pot 7,

8P 08Pot 79P, 09Pot 301P, 001Pot 7

0.01Am

I)gva(LO

tuptuOegarevA tnerruC)"L"(woL

1P 51Pot 76P, 06Pot 77P, 07Pot 7,

8P 08Pot 79P, 09Pot 301P, 001Pot 7

0.5Am

X(f NI )ycneuqerFnoitallicsOtupnIkcolCniaM )4( VCC V5.5ot0.3= 002zHM

VCC V0.3ot7.2=0VX33 CC 08-zHM

X(f NIC )ycneuqerFnoitallicsOkcolCbuS 867.2305zHk

f1)COR(1ycneuqerFrotallicsOpihc-nO 5.01 2 zHM

)COR(2f2ycneuqerFrotallicsOpihc-nO 12 4 zHM

)COR(3f3ycneuqerFrotallicsOpihc-nO 86162zHM

)LLP(fycneuqerFnoitallicsOkcolCLLP )4( VCC )B62/C61M(V5.5ot2.4=0142zHM

VCC )B62/C61M(V2.4ot0.3=01VX33.3 +CC 01zHM

VCC )A62/C61M(V5.5ot0.3=0102zHM

VCC V0.3ot7.2=01VX33 CC 08-zHM

)KLCB(fycneuqerFkcolCnoitarepOUPC A62/C61M002zHM

B62/C61M042zHM

tUS )LLP(ycneuqerFLLPezilibatSotemiTtiaW rezisehtnyS VCC V0.5=02sm

VCC V0.3=05sm

:SETON VotdecnerefeR.1 CC .deificepsesiwrehtosselnuC°58ot04-/C°58ot02-=rpoTtaV5.5ot7.2= .sm001nihtiweulavnaemehtsitnerructuptuonaemehT.2 IlatotehT.3 )kaep(LO IlatotehT.sselroAm08ebtsumstropllarof )kaep(HO .sselroAm08-ebtsumstropllarof .egatlovylppusdnaycneuqerfnoitallicsokcolcLLP,ycneuqerfnoitallicsokcolcniamgnomapihsnoitaleR.4

Main clock input oscillation frequency

f(X

) operating maximum

frequency

[MH

]

[V] (main clock: no division)

PLL clock oscillation frequency (M16C/26A)

f(PLL) operating maximum

frequency

[MH

]

[V] (PLL clock oscillation)

AAAAA

20.0

0.0 5.53.0

10.0

2.7

33.3 x V

-80 MH

20.0

0.0 5.5

10.0

2.7 3.0

33.3 x V

-80 MH

20.0

0.0 5.5

10.0

2.7 3.0

33.3 x V

-80 MH

4.2

24.0

AAAAA

3.33 x V

+10 MH

PLL clock oscillation frequency (M16C/26B)

[V] (PLL clock oscillation)

f(PLL) operating maximum

frequency

[MH

]

18. Electrical Characteristics (M16C/26A, M16C/26B)

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Table 18.3. A /D Conversion Characteristics

(

lobmySretemaraPnoitidnoCtnemerusaeM dradnatS tinU

.niM.pyT.xaM

-noituloseRV

FER

01stiB

LNI ytiraenilnoNlargetnI rorrE tib01 V

FER

V5=3±BSL

FER

V3.3=5±BSL

tib8V

FER

V5,V3.3=2±BSL

-ycaruccAetulosbA tib01 V

FER

V5=3±BSL

FER

V3.3=5±BSL

tib8V

FER

V5,V3.3=2±BSL

LNDrorrEytiraenilnoNlaitnereffiD 1±BSL

-rorrEtesffO 3±BSL

-rorrEniaG 3±BSL

REDDAL

reddaLrotsiseRV

=FER

0104kΩ

VNOC

emiTnoisrevnoCtib-01 elbaliavAnoitcnuFdloH&elpmaS V

FER

,V5= φzHM01=DA3.3 µs

VNOC

emiTnoisrevnoCtib-8 elbaliavAnoitcnuFdloH&elpmaS V

FER

,V5= φzHM01=DA8.2 µs

FER

egatloVecnerefeR 0.2V

egatloVtupnIgolanA 0V

FER

:SETON VotdecnerefeR.1

VA=

FER

V,V5.5ot3.3=

VA=

esiwrehtosselnuC°58ot04-/C°58ot02-=rpoTtaV0=

.deificeps peeK.2 φfehtedivid,yllanoitiddA.)B62/C61MnisselrozHM21(sselrozHM01taycneuqerfDA

Vfi

nahtsselsi

ekamdna,V2.4 φfnahtrewolrootlauqeycneuqerfDA

.2/

.3peek,delbasidsinoitcnufdloh&elpmasnehW φ.2etoNninoitatimilehtotnoitiddanieromrozHk052taycneuqerfDA

peek,delbanesinoitcnufdloh&elpmasnehW φ.2etoNninoitatimilehtotnoitiddanieromrozHM1taycneuqerfDA /3siemitgnilpmas,delbanesinoitcnufdloh&elpmasnehW.4 φ.ycneuqerfDA

/2siemitgnilpmas,delbasidsinoitcnufdloh&elpmasnehW φ.ycneuqerfDA

18. Electrical Characteristics (M16C/26A, M16C/26B)

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Table 18.4. Flash Memory Version Electrical Characteristic (1):

Program Space and Data Space for U3 and U5, Program Space for U7 and U9

Table 18.5. Flash Memory Version Electrical Characteristics (6): Data Space for U7 and U9 (7)

Erase suspend

request

(interrupt request)

FMR46

td(SR-ES)

lobmySretemaraP dradnatS tinU

.niM.pyT )2( .xaM

-ecnarudnEesarEdnamargorP )3( 0001/001 )11,4( selcyc

-V(emiTmargorPdroW CC 52=rpoT,V0.5=C°)57006 µs

-emiTesarEkcolBV( CC 52=rpoT,V0.5=C°)kcolBetybK-2 2.09s

kcolBetybK-8 4.09s

kcolBetybK-61 7.09s

kcolBetybK-23 2.19s

)SE-RS(dtdnepsuSesarEdnatseuqeRdnepsuSneewtebnoitaruD 8sm

tSP tiucriCyromeMhsalFezilibatSotemiTtiaW 51 µs

-emiTdloHataD )5( 02sraey

lobmySretemaraP dradnatS tinU

.niM.pyT

)2(

.xaM

-ecnarudnEesarEdnamargorP

)9,8,3(

00001

)01,4(

selcyc

-V(emiTmargorPdroW

52=rpoT,V0.5=C°)001 µs

-emiTesarEkcolBV(

52=rpoT,V0.5=C°))kcolbetybK-2( 3.0s

)SE-RS(dtdnepsuSesarEdnatseuqeRdnepsuSneewtebnoitaruD 8sm

tiucriCyromeMhsalFezilibatSotemiTtiaW 51 µs

-emiTdloHataD

)5(

02sraey

:SETON VotdecnerefeR.1

°06ot0=rpoTtaV5.5ot7.2= sselnu,)ecapsatad(C°58ot04-,)ecapsmargorp(C

.deificepsesiwrehto

V.2

T;V0.5=

rpo

C°52= .kcolbrepselcycesare-margorpforebmunsadenifedsiecnarudneesarednamargorP.3 siecnarudneesarednamargorpfI n(elcyc ndemmargorpdnadesareebnackcolbhcae,)00001,0001,001= n

rpo

C°55= VotdecnerefeR.6

TtaV5.5ot7.2=

rpo

.deificepsesiwrehtosselnu)9U(C°58ot02-/)7U(C°58ot04-= .selcyc000,1nahteromsiecnarudneesarednamargorpnehw9Udna7Uniecapsatadrofseilppa5.81elbaT.7 .4.81elbaTesu,esiwrehtO ,setirwersuoremungniriuqersmetsyshtiwgnikrownehwecnarudneesarednamargorpforebmunehtecuderoT.8 sesserddaelbissopllaretfaylnokcolbesarE.etirwerfodaetsnikcolbehtnihtiwsesserddadrowdesunuotetirw .yrassecensemocebesareerofebmumixamsemit821nettirwebnacmargorpdrow-8na,elpmaxeroF.desuera sitI.ycneiciffeevorpmioslalliwBkcolbdnaAkcolbneewteberusaresemitforebmunlauqenagniniatniaM .erusareforebmunehttimilotdnakcolbrepdemrofreperusareforebmunlatotehtkcartotdednemmocer tonsirorreesarenalitnusemit3tsaeltadnammocesarekcolbdnadnammocretsigersutatsraelcehtetucexE.9 .detarenegsirorreesarenanehwdetareneg nitib71RMFehtgnittesybsseccakcolbrepetatstiawenotes,setirwersemit001nahteromgnitucexenehW.01 ebnacetatstiaw,MARlanretnidnaskcolbrehtollaotgnisseccanehW.)etatstiaw("1"ot1retsiger1RMFeht .eulavgnittestib71RMFehtfosseldrager,tib71MPehtybtes 000,1;5Udna3Uniecapsataddnaecapsmargorprofselcyc001siecnarudneesarednamargorpehT.11 .9Udna7Uniecapsmargorprofselcyc .evitatneserpertroppuslacinhcetsaseneRriehttcatnocdluohsnoitamrofnietareruliafW/EgnirisedsremotsuC.21

18. Electrical Characteristics (M16C/26A, M16C/26B)

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Table 18.6.

Voltage Detection Circuit Electrical Characteristics

(1, 3

)

Table 18.7.

Power Supply Circuit Timing Characteristics

lobmySretemaraPnoitidnoCtnemerusaeM dradnatS tinU

.niM.pyT.xaM

4tedVegatloVnoitceteDegatloVwoL

)1(

V5.5ot8.0=

2.38.354.4V

3tedVegatloVnoitceteDleveLteseR

)1(

3.28.24.3V

s3tedV egatloVdloHteseRegatloVwoL

)2(

7.1V

r3tedVegatloVesaeleRteseRegatloVwoL 53.29.25.3V

:SETON 3tedV>4tedV.1 ."2tesererawdrah"niatniamotegatlovmumnimehtsis3tedV.2 VnehwesuotdengisedsitiucricnoitcetedegatlovehT.3

.V5ottessi noitcetedlevelteserehtnehwegatlovnoitcetedlevelteserehtnahtretaergsiegatlovrewopylppusehtfI.4 )KLCB(ftanoitarepoeht,V7.2nahtsselsiegatlov ≤,O/Ilaires,noisrevnocD/A,revewoH.deetnarugsizHM01

.dedulcxeeraesarednamargorpyromemhsalf

lobmySretemaraPnoitidnoCtnemerusaeM dradnatS tinU

.niM.pyT.xaM

)R-P(dtno-rewoPnehwegatloVylppuSlanretnIezilibatSotemiTtiaW

VCC V5.5ot7.2=

2sm

)COR(dt no-rewoPnehwrotallicsOpihc-nOlanretnIezilibatSotemiTtiaW 04 µs

)S-R(dtemiTesaeleRPOTS 051 µs

)S-W(dtemiTesaeleRedoMtiaWedoMnoitapissiDrewoPwoL 051 µs

)R-S(dtemiTtiaWesaeleR2teseRerawdraHV

CC V5.5otr3tedV=6

)1( 02sm

)A-E(dtemiTtratSnoitarepOtiucriCnoitceteDegatloVV

CC V5.5ot7.2=02µs

:SETON VnehW.1 CC V5=

d(P-R)

Wait time to stabilize internal

supply voltage when power-on

CPU clock

d(R-S)

(a)

(b) t

d(W-S)

d(R-S)

STOP release time

d(W-S)

Low power dissipation mode

wait mode release time

d(S-R)

Vdet3r

CPU clock

VC26, VC27

d(E-A)

Stop Operate

Interrupt for

(a) Stop mode release

(b) Wait mode release

d(S-R)

Brown-out detection

reset (hardware reset 2)

release wait time

d(E-A)

Voltage detection circuit

operation start time

Voltage Detection Circuit

d(ROC)

Wait time to stabilize internal

on-chip oscillator when power-

ROC

RESET

VCC

td(P-R) td(ROC)

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VCC = 5V

Table 18.8.

Electrical Characteristics

(

lobmySretemaraPnoitidnoC dradnatS

tinU

.niM.pyT.xaM

VHO hgiHtuptuO egatloV)"H"( 1P 51Pot 76P, 06Pot 77P, 07Pot 7,

8P 08Pot 79P, 09Pot 301P, 001Pot 7

IHO Am5-= VCC

0.2 VCC V

VHO hgiHtuptuO egatloV)"H"( 1P 51Pot 76P, 06Pot 77P, 07Pot 7,

8P 08Pot 79P, 09Pot 301P, 001Pot 7

IHO 002-= µAVCC

3.0 VCC V

VHO

egatloV)"H"(hgiHtuptuOXTUO rewoPhgiH IHO Am1-= VCC

0.2 VCC V

rewoPwoL IHO Am5.0-= VCC

0.2 VCC

egatloV)"H"(hgiHtuptuOXTUOC rewoPhgiH deilppadaoloN5.2 V

rewoPwoL deilppadaoloN6.1

VLO woLtuptuO egatloV)"L"( 1P 51Pot 76P, 06Pot 77P, 07Pot 7,

8P 08Pot 79P, 09Pot 301P, 001Pot 7

ILO Am5=0.2V

VLO woLtuptuO egatloV)"L"( 1P 51Pot 76P, 06Pot 77P, 07Pot 7,

8P 08Pot 79P, 09Pot 301P, 001Pot 7

ILO 002= µA54.0V

VLO

egatloV)"L"(woLtuptuOXTUO rewoPhgiH ILO Am1=0.2 V

rewoPwoL ILO Am5.0=0.2

egatloV)"L"(woLtuptuOX

TUOC rewoPhgiH deilppadaoloN0

rewoPwoL deilppadaoloN0

V+T V- -T siseretsyH 0AT NI 4AT- NI 0BT, NI 2BT- NI TNI, 0TNI- 5DA,IMN, GRT ,

STC 0STC- 2KLC, 0KLC- 22AT, TUO 4AT- TUO IK, 0IK- 3,

R0DX R- 2DX

2.00.1V

V+T V- -T siseretsyH TESER 2.05.2V

V+T V- -T siseretsyH XNI 2.08.0 V

IHI hgiHtupnI tnerruC)"H"( 1P 51Pot 76P, 06Pot 77P, 07Pot 7,

8P 08Pot 79P, 09Pot 301P, 001Pot ,7

XNI VNC,TESER, SS

VIV5=0.5 µA

ILI woLtupnI tnerruC)"L"( 1P 51Pot 76P, 06Pot 77P, 07Pot 7,

8P 08Pot 79P, 09Pot 301P, 001Pot ,7

XNI VNC,TESER, SS

VIV0=0.5- µA

PULLUP

pu-lluP ecnatsiseR 1P 51Pot 76P, 06Pot 77P, 07Pot 7,

8P 08Pot 79P, 09Pot 301P, 001Pot 7

VIV0=0305071kΩ

fR NIX ecnatsiseRkcabdeeFXNI 5.1MΩ

fR NICX ecnatsiseRkcabdeeFXNIC 51MΩ

VMAR egatloVybdnatSMAR edompotsnI0.2V

:ETON otdecnerefeR.1VCC V,V5.5ot2.4= SS esiwrehtosselnuzHM02=)KLCB(f,C°58ot04-/C°58ot02-=rpoTtaV0=

.deificeps

18. Electrical Characteristics (M16C/26A, M16C/26B)

page 267

923fo7002,51.beF00.2.veR 0020-2020B90JER

)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

VCC = 5V

Table 18.9.

Electrical Characteristics (2)

(

lobmySretemaraPnoitidnoCtnemerusaeM dradnatS tinU

.niM.pyT.xaM

ICC ylppuSrewoP tnerruC

V( CC )V5.5ot0.4=

erasniptuptuO dnanepotfel erasniprehto Votdetcennoc SS

MORksaM,zHM02=)KLCB(f noisividon,kcolcniam 2171Am

noitallicsopihc-nO

f)COR(2 zHM1=)KLCB(f,detceles 1Am

yromemhsalF,zHM42=)KLCB(f )B62/C61M(setarepoLLP 0232Am

,kcolcniam,zHM02=)KLCB(f noisividon 6191Am

,setareporotallicsopihc-nO

f)COR(2 zHM1=)KLCB(f,detceles 1Am

yromemhsalF margorp V0.5=ccV,zHM01=)KLCB(f 11Am

yromemhsalF esare V0.5=ccV,zHM01=)KLCB(f 21Am

MORksaM,zHk23=)KLCB(f ,edomnoitpmusnocrewop-wolnI MORnogninnurmargorP )3(

52 µA

,setareporotallicsopihc-nO

f)COR(2 ,zHM1=)KLCB(f,detceles edomtiawnI

03 µA

yromemhsalFzHk23=)KLCB(f,

edomnoitpmusnocrewop-wolnI,

MARnogninnurmargorP )3(

52 µA

,zHk23=)KLCB(f ,edomnoitpmusnocrewop-wolnI yromemhsalfnogninnurmargorP )3(

054 µA

,setareporotallicsopihc-nO

f)COR(2 ,zHM1=)KLCB(f,detceles edomtiawnI

05 µA

,MORksaM yromemhsalF edomtiawnI,zHk23=)KLCB(f )2( ,

HGIHyticapacnoitallicsO 01 µA

,zHk23=)KLCB(fedomtiawnI )2( ,

WOLyticapacnoitallicsO 3µA

,edompotsnI52=rpoTC°8.03

µA

4tedItnerrucnoitapissidnoitcetedegatlovwoL )4( 7.04

µA

3tedItnerrucnoitapissidnoitcetedlevelteseR )4( 2.18

µA

:SETON .1otdecnerefeRV

CC V,V5.5ot2.4= SS esiwrehtosselnuzHM02=)KLCB(f,C°58ot04-/C°58ot02-=rpoTtaV0=

.deificeps fgnisu,setareporemitenohtiW.2 23C ..stsixedetucexeebotmargorpehthcihwniyromemehtsetacidnisihT.3 .)delbanetiucricnoitceted("1"ottessitibgniwollofehtnehwtnerrucnoitapissidsitedI.4 retsiger2RCVehtnitib72CV:4tedI retsiger2RCVehtnitib62CV:3tedI

18. Electrical Characteristics (M16C/26A, M16C/26B)

page 268

923fo7002,51.beF00.2.veR 0020-2020B90JER

)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

VCC = 5V

Timing Requirements

(VCC = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)

Table 18.10. External Clock Input (XIN input)

lobmySretemaraP dradnatS tinU

.niM.xaM

ctemiTelcyCtupnIkcolClanretxE 05sn

)H(

htdiW)"H"(hgiHtupnIkcolClanretxE 02sn

)L(

htdiW)"L"(woLtupnIkcolClanretxE 02sn

rtemiTesiRkcolClanretxE 9sn

ftemiTllaFkcolClanretxE 9sn

18. Electrical Characteristics (M16C/26A, M16C/26B)

page 269

923fo7002,51.beF00.2.veR 0020-2020B90JER

)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

VCC = 5V

Timing Requirements

(VCC = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)

Table 18.12. Timer A Input (Gating Input in Timer Mode)

Table 18.13. Timer A Input (External Trigger Input in One-shot Timer Mode)

Table 18.14. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)

Table 18.15. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)

Table 18.11. Timer A Input (Counter Input in Event Counter Mode)

Table 18.16. Timer A Input (Two-phase Pulse Input in Event Counter Mode)

Standard

Max.

TAiIN input LOW pulse width

tw(TAL)

Min. ns

Unit

TAiIN input HIGH pulse width

tw(TAH)

ParameterSymbol

tc(TA) TAiIN input cycle time

100

Standard

Max.

Min. ns

Unit

TAiIN input cycle time

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

tc(TA)

tw(TAH)

tw(TAL)

Symbol Parameter

400

200

Standard

Max.

Min. ns

Unit

TAiIN input cycle time

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

tc(TA)

tw(TAH)

tw(TAL)

Symbol Parameter

200

100

Standard

Max.

Min. ns

Unit

tw(TAH)

tw(TAL)

Symbol Parameter

TAiIN input HIGH pulse width

TAiIN input LOW pulse width 100

100

Standard

Max.

Min. ns

Unit

Symbol Parameter

TAiOUT input cycle time

TAiOUT input HIGH pulse width

TAiOUT input LOW pulse width

TAiOUT input setup time

TAiOUT input hold time

tc(UP)

tw(UPH)

tw(UPL)

tsu(UP-TIN)

th(TIN-UP)

2000

1000

400

Standard

Max.

Min. ns

Unit

Symbol Parameter

TAiIN input cycle time

TAiOUT input setup time

TAiIN input setup time

tc(TA)

tsu(TAIN-TAOUT)

tsu(TAOUT-TAIN)

800

200

18. Electrical Characteristics (M16C/26A, M16C/26B)

page 270

923fo7002,51.beF00.2.veR 0020-2020B90JER

)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

Timing Requirements

(VCC = 5V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)

Table 18.17. Timer B Input (Counter Input in Event Counter Mode)

Table 18.18. Timer B Input (Pulse Period Measurement Mode)

Table 18.19. Timer B Input (Pulse Width Measurement Mode)

Table 18.20. A/D Trigger Input

Table 18.21. Serial I/O

_______

Table 18.22. External Interrupt INTi Input

VCC = 5V

Standard

Max.Min.

TBiIN input cycle time (counted on one edge)

TBiIN input HIGH pulse width (counted on one edge)

TBiIN input LOW pulse width (counted on one edge)

tc(TB)

tw(TBH)

tw(TBL)

ParameterSymbol Unit

tc(TB)

tw(TBL)

tw(TBH)

TBiIN input HIGH pulse width (counted on both edges)

TBiIN input LOW pulse width (counted on both edges)

TBiIN input cycle time (counted on both edges)

Standard

Max.

Min. ns

tc(TB)

tw(TBH)

Symbol Parameter Unit

tw(TBL) ns

TBiIN input HIGH pulse width

TBiIN input cycle time

TBiIN input LOW pulse width

Standard

Max.

Min. ns

tc(TB)

Symbol Parameter Unit

tw(TBL) ns

tw(TBH) TBiIN input cycle time

TBiIN input HIGH pulse width

TBiIN input LOW pulse width

Standard

Max.

Min. ns

tc(AD)

tw(ADL)

Symbol Parameter Unit

ADTRG input cycle time (trigger able minimum)

ADTRG input LOW pulse width

Standard

Max.

Min. ns

tw(INH)

tw(INL)

Symbol Parameter Unit

INTi input LOW pulse width

INTi input HIGH pulse width

Standard

Max.Min.

CLKi input cycle time

CLKi input HIGH pulse width

CLKi input LOW pulse width

tc(CK)

tw(CKH)

tw(CKL)

ParameterSymbol Unit

td(C-Q)

tsu(D-C)

th(C-Q) TxDi hold time

RxDi input setup time

TxDi output delay time

th(C-D) RxDi input hold time

100

200

400

200

400

200

1000

125

250

200

100

18. Electrical Characteristics (M16C/26A, M16C/26B)

page 271

923fo7002,51.beF00.2.veR 0020-2020B90JER

)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

VCC = 5V

TAiIN input

TAiOUT input

During event counter mode

TBiIN input

ADTRG input

c(TA)

w(TAH)

w(TAL)

c(UP)

w(UPH)

w(UPL)

c(TB)

w(TBH)

w(TBL)

c(AD)

w(ADL)

h(TIN-UP)

su(UP-TIN)

TAiIN input

(When count on falling

edge is selected)

TAiIN input

(When count on rising

edge is selected)

TAiOUT input

(Up/down input)

TAiIN input

Two-phase pulse input in event counter mode

c(TA)

su(TAIN-TAOUT)

su(TAOUT-TAIN)

su(TAIN-TAOUT)

su(TAOUT-TAIN)

TAiOUT input

XIN input

w(H)

w(L)

Figure 18.1. Timing Diagram (1)

18. Electrical Characteristics (M16C/26A, M16C/26B)

page 272

923fo7002,51.beF00.2.veR 0020-2020B90JER

)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

VCC = 5V

Figure 18.2. Timing Diagram (2)

su(D–C)

CLKi

TxDi

RxDi

c(CK)

w(CKH)

w(CKL)

w(INL)

w(INH)

d(C–Q)

h(C–D)

h(C–Q)

INTi input

18. Electrical Characteristics (M16C/26A, M16C/26B)

page 273

923fo7002,51.beF00.2.veR 0020-2020B90JER

)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

VCC = 3V

Table 18.23. Electrical Characteristics

(

lobmySretemaraPnoitidnoC dradnatS

tinU

.niM.pyT.xaM

VHO hgiHtuptuO egatloV)"H"( 1P 51Pot 76P, 06Pot 77P, 07Pot 7,

8P 08Pot 79P, 09Pot 301P, 001Pot 7

IHO Am1-= VCC

5.0 VCC V

VHO

egatloV)"H"(hgiHtuptuOXTUO rewoPhgiH IHO Am1.0-= VCC

5.0 VCC V

rewoPwoL IHO 05-= µAVCC

5.0 VCC

egatloV)"H"(hgiHtuptuOXTUOC rewoPhgiH deilppadaoloN5.2 V

rewoPwoL deilppadaoloN6.1

VLO woLtuptuO egatloV)"L"( 1P 51Pot 76P, 06Pot 77P, 07Pot 7,

8P 08Pot 79P, 09Pot 301P, 001Pot 7

ILO Am1=5.0V

VLO

egatloV)"L"(woLtuptuOXTUO rewoPhgiH ILO Am1.0=5.0 V

rewoPwoL ILO 05= µA5.0

egatloV)"L"(woLtuptuOX

TUOC rewoPhgiH deilppadaoloN0

rewoPwoL deilppadaoloN0

V+T V- -T siseretsyH 0AT NI 4AT- NI 0BT, NI 2BT- NI TNI, 0TNI- 5DA,IMN, GRT ,

STC 0STC- 2KLC, 0KLC- 22AT, TUO 4AT- TUO IK, 0IK- 3,

R0DX R- 2DX

8.0V

V+T V- -T siseretsyH TESER 8.1V

V+T V- -T siseretsyH XNI 8.0 V

IHI hgiHtupnI tnerruC)"H"( 1P 51Pot 76P, 06Pot 77P, 07Pot 7,

8P 08Pot 79P, 09Pot 301P, 001Pot 7

XNI VNC,TESER, SS

VIV3=0.4 µA

ILI woLtupnI tnerruC)"L"( 1P 51Pot 76P, 06Pot 77P, 07Pot 7,

8P 08Pot 79P, 09Pot 301P, 001Pot 7

XNI VNC,TESER, SS

VIV0=0.4- µA

PULLUP

pu-lluP ecnatsiseR 1P 51Pot 76P, 06Pot 77P, 07Pot 7,

8P 08Pot 79P, 09Pot 301P, 001Pot 7

VIV0=05001005kΩ

fR NIX ecnatsiseRkcabdeeFXNI 0.3MΩ

fR NICX ecnatsiseRkcabdeeFXNIC 52MΩ

VMAR egatloVybdnatSMAR edompotsnI0.2V

:ETON otdecnerefeR.1V

CC V,V6.3ot7.2= SS esiwrehtosselnuzHM01=)KLCB(f,C°58ot04-/C°58ot02-=rpoTtaV0=

.deificeps

18. Electrical Characteristics (M16C/26A, M16C/26B)

page 274

923fo7002,51.beF00.2.veR 0020-2020B90JER

)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

VCC = 3V

Table 18.24. Electrical Characteristics (2)

(

lobmySretemaraPnoitidnoCtnemerusaeM dradnatS tinU

.niM.pyT.xaM

ylppuSrewoP tnerruC

)V6.3ot7.2=

erasniptuptuO dnanepotfel erasniprehto Votdetcennoc

MORksaM(fKLCB,zHM01=) noisividon,kcolcniaM 701Am

,setareporotallicsopihc-nO

)COR(2

zHM1=)KLCB(f,detceles 1Am

yromemhsalF(fKLCB,zHM01=) noisividon,kcolcniaM 721Am

,setareporotallicsopihc-nO

)COR(2

zHM1=)KLCB(f,detceles 1Am

yromemhsalF margorp V0.3=ccV,zHM01=)KLCB(f 01Am

yromemhsalF esare V0.3=ccV,zHM01=)KLCB(f 11Am

MORksaMzHk23=)KLCB(f,

edomnoitpmusnocrewop-wolnI,

MORnogninnurmargorP

)3(

52 µA

,setareporotallicsopihc-nO

)COR(2

,zHM1=)KLCB(f,detceles edomtiawnI

52 µA

yromemhsalFzHk23=)KLCB(f,

edomnoitpmusnocrewop-wolnI,

MARnogninnurmargorP

)3(

52 µA

,zHk23=)KLCB(f ,edomnoitpmusnocrewop-wolnI yromemhsalfnogninnurmargorP

)3(

054 µA

,setareporotallicsopihc-nO

)COR(2

,zHM1=)KLCB(f,detceles edomtiawnI

54 µA

,MORksaM yromemhsalF edomtiawnI,zHk23=)KLCB(f

)2(

HGIHyticapacnoitallicsO 01 µA

,zHk23=)KLCB(fedomtiawnI

)2(

WOLyticapacnoitallicsO 3µA

,spotskcolcelihW52=rpoTC°7.03

µA

4tedItnerrucnoitapissidnoitcetedegatlovwoL

)4(

6.04

µA

3tedItnerrucnoitapissidnoitcetedlevelteseR

)4(

0.15

µA

:SETON otdecnerefeR.1V

V,V6.3ot7.2=

esiwrehtosselnuzHM01=)KLCB(f,C°58ot04-/C°58ot02-=rpoTtaV0=

.deificeps fgnisu,setareporemitenohtiW.2

23C

..stsixedetucexeebotmargorpehthcihwniyromemehtsetacidnisihT.3 .)delbanetiucricnoitceted(1ottessitibgniwollofehtnehwtnerrucnoitapissidsitedI.4 retsiger2RCVehtfotib72CVeht:4tedI retsiger2RCVehtnitib62CVeht:3tedI

18. Electrical Characteristics (M16C/26A, M16C/26B)

page 275

923fo7002,51.beF00.2.veR 0020-2020B90JER

)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

VCC = 3V

Timing Requirements

(VCC = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)

Table 18.25. External Clock Input (XIN input)

lobmySretemaraP dradnatS tinU

.niM.xaM

ctemiTelcyCtupnIkcolClanretxE 001sn

)H(

htdiW)"H"(hgiHtupnIkcolClanretxE 04sn

)L(

htdiW)"L"(woLtupnIkcolClanretxE 04sn

rtemiTesiRkcolClanretxE 81sn

ftemiTllaFkcolClanretxE 81sn

18. Electrical Characteristics (M16C/26A, M16C/26B)

page 276

923fo7002,51.beF00.2.veR 0020-2020B90JER

)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

VCC = 3V

Timing Requirements

(VCC = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)

Table 18.26. Timer A Input (Counter Input in Event Counter Mode)

Table 18.27. Timer A Input (Gating Input in Timer Mode)

Table 18.28. Timer A Input (External Trigger Input in One-shot Timer Mode)

Table 18.29. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)

Table 18.30. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)

Table 18.31. Timer A Input (Two-phase Pulse Input in Event Counter Mode)

Standard

Max.

TAi

input LOW pulse width

w(TAL)

Min. ns

Unit

TAi

input HIGH pulse width

w(TAH)

ParameterSymbol

c(TA)

TAi

input cycle time

150

Standard

Max.

Min. ns

Unit

TAi

input cycle time

TAi

input HIGH pulse width

TAi

input LOW pulse width

c(TA)

w(TAH)

w(TAL)

Symbol Parameter

600

300

Standard

Max.

Min. ns

Unit

TAi

input cycle time

TAi

input HIGH pulse width

TAi

input LOW pulse width

c(TA)

w(TAH)

w(TAL)

Symbol Parameter

300

150

Standard

Max.

Min. ns

Unit

w(TAH)

w(TAL)

Symbol Parameter

TAi

input HIGH pulse width

TAi

input LOW pulse width 150

150

Standard

Max.Min. ns

Unit

Symbol Parameter

TAi

OUT

input cycle time

TAi

OUT

input HIGH pulse width

TAi

OUT

input LOW pulse width

TAi

OUT

input setup time

TAi

OUT

input hold time

c(UP)

w(UPH)

w(UPL)

su(UP-TIN)

h(TIN-UP)

3000

1500

600

Standard

Max.

Min. µs

Unit

Symbol Parameter

TAi

input cycle time

TAi

OUT

input setup time

TAi

input setup time

c(TA)

su(TAIN-TAOUT)

su(TAOUT-TAIN)

500

18. Electrical Characteristics (M16C/26A, M16C/26B)

page 277

923fo7002,51.beF00.2.veR 0020-2020B90JER

)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

VCC = 3V

Table 18.32. Timer B Input (Counter Input in Event Counter Mode)

Table 18.33. Timer B Input (Pulse Period Measurement Mode)

Table 18.34. Timer B Input (Pulse Width Measurement Mode)

Table 18.35. A/D Trigger Input

Table 18.36. Serial I/O

_______

Table 18.37. External Interrupt INTi Input

Timing Requirements

(VCC = 3V, VSS = 0V, at Topr = – 20 to 85oC / – 40 to 85oC unless otherwise specified)

Standard

Min.

TBiIN input cycle time (counted on one edge)

TBiIN input HIGH pulse width (counted on one edge)

TBiIN input LOW pulse width (counted on one edge)

tc(TB)

tw(TBH)

tw(TBL)

Paramete

Symbo

lUni

tc(TB)

tw(TBL)

tw(TBH)

TBiIN input HIGH pulse width (counted on both edges)

TBiIN input LOW pulse width (counted on both edges)

TBiIN input cycle time (counted on both edges)

Standard

Max.

Min. ns

tc(TB)

tw(TBH)

Symbol Parameter Unit

tw(TBL) ns

TBiIN input HIGH pulse width

TBiIN input cycle time

TBiIN input LOW pulse width

Standar

dMa

n. ns

tc(TB)

Symbol Parameter Unit

tw(TBL) ns

tw(TBH) TBiIN input cycle time

TBiIN input HIGH pulse width

TBiIN input LOW pulse width

Standar

dMa

n. ns

tc(AD)

tw(ADL)

Symbo

lParamete

rUnit

ADTRG input cycle time (trigger able minimum)

ADTRG input LOW pulse width

Standard

Min. ns

tw(INH)

tw(INL)

Symbo

lParamete

rUnit

INTi input LOW pulse width

INTi input HIGH pulse width

Standard

Max.Mi

CLKi input cycle time

CLKi input HIGH pulse width

CLKi input LOW pulse width

tc(CK)

tw(CKH)

tw(CKL)

ParameterSymbol Unit

td(C-Q)

tsu(D-C)

th(C-Q) TxDi hold time

RxDi input setup time

TxDi output delay time

th(C-D) RxDi input hold time

150

120

300

600

300

600

300

1500

200

380

300

150

100

160

18. Electrical Characteristics (M16C/26A, M16C/26B)

page 278

923fo7002,51.beF00.2.veR 0020-2020B90JER

)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

VCC = 3V

Figure 18.3. Timing Diagram (1)

TAiIN input

TAiOUT input

During Event Counter Mode

TBiIN input

ADTRG input

c(TA)

w(TAH)

w(TAL)

c(UP)

w(UPH)

w(UPL)

c(TB)

w(TBH)

w(TBL)

c(AD)

w(ADL)

h(TIN-UP)

su(UP-TIN)

TAiIN input

(When count on falling

edge is selected)

TAiIN input

(When count on rising

edge is selected)

TAiOUT input

(Up/down input)

TAiIN input

Two-Phase Pulse Input in Event Counter Mode

c(TA)

su(TAIN-TAOUT)

su(TAOUT-TAIN)

su(TAIN-TAOUT)

su(TAOUT-TAIN)

TAiOUT input

XIN input

w(H)

w(L)

18. Electrical Characteristics (M16C/26A, M16C/26B)

page 279

923fo7002,51.beF00.2.veR 0020-2020B90JER

)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

VCC = 3V

Figure 18.4. Timing Diagram (2)

su(D–C)

CLKi

TxDi

RxDi

c(CK)

w(CKH)

w(CKL)

w(INL)

w(INH)

d(C–Q)

h(C–D)

h(C–Q)

INTi input

18. Electrical Characteristics (M16C/26T)

page 280

923fo7002,51.beF00.2.veR 0020-2020B90JER

)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

18.2. M16C/26T (T version)

Table 18.38. Absolute Maximum Ratings

lobmySretemaraPnoitidnoCeulaVtinU

VCC egatloVylppuSVCC VA= CC 5.6ot3.0- V

VA CC egatloVylppuSgolanAVCC VA= CC 5.6ot3.0- V

VIegatloVtupnI1P51Pot 76P, 06Pot 77P, 07Pot 7,

8P 08Pot 79P, 09Pot 301P, 001Pot 7,

XNI V, FER VNC,TESER, SS

Vot3.0- CC 3.0+V

VOegatloVtuptuO1P51Pot 76P, 06Pot 77P, 07Pot 7,

8P 08Pot 79P, 09Pot 301P, 001Pot 7,

XTUO

Vot3.0- CC 3.0+V

dPnoitapissiDrewoP04-< rpoT< C°58003Wm

rpoT gnitarepO tneibmA erutarepmeT

noitarepoUPCgnirud 58ot04-C°

yromemhsalfgnirud esarednamargorp noitarepo

ecapSmargorP )3kcolBot0kcolB( 06ot0C°

ecapSataD )BkcolB,AkcolB( 58ot04-C°

gtsTerutarepmeTegarotS 051ot56-C°

18. Electrical Characteristics (M16C/26T)

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Table 18.39.

Recommended Operating Conditions

(

Main clock input oscillation frequency

20.0

0.0

f(X

) operating maximum

frequency

[MH

]

VCC[V] (main clock: no division) 5.53.0

10.0

2.7

AAAAA

20MHZ

PLL clock oscillation frequency

20.0

0.0

f(PLL) operating maximum

frequency

[MH

]

VCC[V] (PLL clock oscillation) 5.5

10.0

AAAAA

3.0

20MHZ

lobmySretemaraP dradnatS tinU

.niM.pyT.xaM

egatloVylppuS 0.35.5V

egatloVylppuSgolanA V

egatloVylppuS 0V

egatloVylppuSgolanA 0V

)"H"(hgiHtupnI egatloV 1P

1Pot

6P,

6Pot

7P,

7Pot

8Pot

9P,

9Pot

01P,

01Pot

V7.0

SSVNC,TESER,NIX V8.0

)"L"(woLtupnI egatloV 1P

1Pot

6P,

6Pot

7P,

7Pot

8Pot

9P,

9Pot

01P,

01Pot

0V3.0

SSVNC,TESER,NIX 0V2.0

)kaep(HO

hgiHtuptuOkaeP tnerruC)"H"(

1Pot

6P,

6Pot

7P,

7Pot

8Pot

9P,

9Pot

01P,

01Pot

0.01-Am

)gva(HO

tuptuOegarevA tnerruC)"H"(hgiH

1Pot

6P,

6Pot

7P,

7Pot

8Pot

9P,

9Pot

01P,

01Pot

0.5-Am

)kaep(LO

woLtuptuOkaeP tnerruC)"L"(

1Pot

6P,

6Pot

7P,

7Pot

8Pot

9P,

9Pot

01P,

01Pot

0.01Am

)gva(LO

tuptuOegarevA tnerruC)"L"(woL

1Pot

6P,

6Pot

7P,

7Pot

8Pot

9P,

9Pot

01P,

01Pot

0.5Am

X(f

)ycneuqerFnoitallicsOtupnIkcolCniaM

)4(

002zHM

X(f

NIC

)ycneuqerFnoitallicsOkcolCbuS 867.2305zHk

)COR(1ycneuqerFrotallicsOpihc-nO 5.01 2 zHM

)COR(2f2ycneuqerFrotallicsOpihc-nO 12 4 zHM

)COR(3f3ycneuqerFrotallicsOpihc-nO 86162zHM

)LLP(fycneuqerFnoitallicsOkcolCLLP

)4(

0102zHM

)KLCB(fycneuqerFkcolCnoitarepOUPC 002zHM

)LLP(rezisehtnySycneuqerFLLPezilibatSotemiTtiaWV

V0.5=02sm

V0.3=05sm

:SETON VotdecnerefeR.1

.deificepsesiwrehtosselnuC°58ot04-=rpoTtaV5.5ot0.3= .sm001nihtiweulavnaemehtsitnerructuptuonaemehT.2 IlatotehT.3

)kaep(LO

IlatotehT.sselroAm08ebtsumstropllarof

)kaep(HO

.sselroAm08-ebtsumstropllarof .egatlovylppusdnaycneuqerfnoitallicsokcolcLLP,ycneuqerfnoitallicsokcolcniamgnomapihsnoitaleR.4

18. Electrical Characteristics (M16C/26T)

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Table 18.40. A/D Conversion Characteristics

(

lobmySretemaraPnoitidnoCtnemerusaeM dradnatS tinU

.niM.pyT.xaM

-noituloseRV

FER

01stiB

LNI ytiraenilnoNlargetnI rorrE tib01 V

FER

V5=3±BSL

FER

V3.3=5±BSL

tib8V

FER

V5,V3.3=2±BSL

-ycaruccAetulosbA tib01 V

FER

V5=3±BSL

FER

V3.3=5±BSL

tib8V

FER

V5,V3.3=2±BSL

LNDrorrEytiraenilnoNlaitnereffiD 1±BSL

-rorrEtesffO 3±BSL

-rorrEniaG 3±BSL

REDDAL

reddaLrotsiseRV

FER

0104kΩ

VNOC

emiTnoisrevnoCtib-01 elbaliavAnoitcnuFdloH&elpmaS V

FER

,V5= φzHM01=DA3.3 µs

VNOC

emiTnoisrevnoCtib-8 elbaliavAnoitcnuFdloH&elpmaS V

FER

,V5= φzHM01=DA8.2 µs

FER

egatloVecnerefeR 0.2V

egatloVtupnIgolanA 0V

FER

:SETON VotdecnerefeR.1

VA=

FER

V,V5.5ot3.3=

VA=

esiwrehtosselnuC°58ot04-=rpoTtaV0=

.deificeps peeK.2 φfehtedivid,yllanoitiddA.sselrozHM01taycneuqerfDA

Vfi

ekamdna,V2.4nahtsselsi φDA

fnahtrewolrootlauqeycneuqerf

.2/

.3peek,delbasidsinoitcnufdloh&elpmasnehW φ.2etoNninoitatimilehtotnoitiddanieromrozHk052taycneuqerfDA

peek,delbanesinoitcnufdloh&elpmasnehW φ.2etoNninoitatimilehtotnoitiddanieromrozHM1taycneuqerfDA /3siemitgnilpmas,delbanesinoitcnufdloh&elpmasnehW.4 φ.ycneuqerfDA

/2siemitgnilpmas,delbasidsinoitcnufdloh&elpmasnehW φ.ycneuqerfDA

18. Electrical Characteristics (M16C/26T)

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Table 18.41. Flash Memory Version Electrical Characteristics (1):

Program Space and Data Space for U3, Program Space for U7

Table 18.42. Flash Memory Version Electrical Characteristics (6): Data Space for U7(7)

Erase suspend

request

(interrupt request)

FMR46

td(SR-ES)

lobmySretemaraP dradnatS tinU

.niM.pyT )2( .xaM

-ecnarudnEesarEdnamargorP )3( 0001/001 )11,4( selcyc

-V(emiTmargorPdroW CC 52=rpoT,V0.5=C°)57006 µs

-emiTesarEkcolBV( CC 52=rpoT,V0.5=C°)kcolBetybK-2 2.09s

kcolBetybK-8 4.09s

kcolBetybK-61 7.09s

kcolBetybK-23 2.19s

)SE-RS(dtdnepsuSesarEdnatseuqeRdnepsuSneewtebnoitaruD 8sm

tSP tiucriCyromeMhsalFezilibatSotemiTtiaW 51 µs

-emiTdloHataD )5( 02sraey

lobmySretemaraP dradnatS tinU

.niM.pyT

)2(

.xaM

-ecnarudnEesarEdnamargorP

)9,8,3(

00001

)01,4(

selcyc

-V(emiTmargorPdroW

52=rpoT,V0.5=C°)001 µs

-emiTesarEkcolBV(

52=rpoT,V0.5=C°)

)kcolbetybK-2( 3.0s

)SE-RS(dtdnepsuSesarEdnatseuqeRdnepsuSneewtebnoitaruD 8sm

tiucriCyromeMhsalFezilibatSotemiTtiaW 51 µs

-emiTdloHataD

)5(

02sraey

:SETON °06ot0=rpoTtaV5.5ot0.3=CCVotdecnerefeR.1 sselnu,)ecapsatad(C°58ot04-=rpoT/)ecapsmargorp(C

.deificepsesiwrehto

V.2

T;V0.5=

RPO

C°52= .kcolbrepselcycesare-margorpforebmunsadenifedsiecnarudneesarednamargorP.3 siecnarudneesarednamargorpfI n(elcyc ndemmargorpdnadesareebnackcolbhcae,)00001,0001,001= n

.selcyc ,semit420,1sserddahcaeotataddrow-enognimmargorpretfadesaresiAkcolbetybK-2afi,elpmaxeroF nahteromsserddaemasehtotdemmargorpebtonnacataD.ecnarudneesarednamargorpenosastnuocsiht .)detibihorpetirwer(.kcolbehtgnisaretuohtiwecno .)deetnarugeraeulavmuminimot1(deetnarugsinoitarepohcihwrofselcycW/EforebmuN.4 C°55=rpoT.5 .deificepsesiwrehtosselnuC°58ot04-=rpoTtaV5.5ot0.3=CCVotdecnerefeR.6.7 24.81elbaT .selcyc000,1nahteromsiecnarudneesarednamargorpnehw7Uniecapsatadrofseilppaesu,esiwrehtO 14.81elbaT .,setirwersuoremungniriuqersmetsyshtiwgnikrownehwecnarudneesarednamargorpforebmunehtecuderoT.8 sesserddaelbissopllaretfaylnokcolbesarE.etirwerfodaetsnikcolbehtnihtiwsesserddadrowdesunuotetirw .yrassecensemocebesareerofebmumixamsemit821nettirwebnacmargorpdrow-8na,elpmaxeroF.desuera sitI.ycneiciffeevorpmioslalliwBkcolbdnaAkcolbneewteberusaresemitforebmunlauqenagniniatniaM .erusareforebmunehttimilotdnakcolbrepdemrofreperusareforebmunlatotehtkcartotdednemmocer esarekcolbdnadnammocretsigersutatsraelcehtetucexe,esarekcolbgniruddetarenegsirorreesarenafI.9 .detarenegtonsirorreesarenalitnusemit3tsaeltadnammoc nitib71RMFehtgnittesybsseccakcolbrepetatstiawenotes,setirwersemit001nahteromgnitucexenehW.01 tesebnacetatstiaw,MARlanretnidnaskcolbrehtollaotgnisseccanehW.)etatstiaw(1otretsiger1RMFeht .eulavgnittestib71RMFehtfosseldrager,tib71MPehtyb selcyc000,1;3Uniecapsataddnaecapsmargorprofselcyc001siecnarudneesarednamargorpehT.11 .7Uniecapsmargorprof rofrotubirtsidtcudorp.proCygolonhceTsaseneRdezirohtuanaro.proCygolonhceTsaseneRtcatnocesaelP.21 .etareruliafW/Eehtnosliatedrehtruf

18. Electrical Characteristics (M16C/26T)

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Table 18.43.

Power Supply Circuit Timing Characteristics

lobmySretemaraPnoitidnoCtnemerusaeM dradnatS tinU

.niM.pyT.xaM

)R-P(dtno-rewoPnehwegatloVylppuSlanretnIezilibatSotemiTtiaW

V5.5ot0.3=

2sm

)COR(dt no-rewoPnehwrotallicsOpihc-nOlanretnIezilibatSotemiTtiaW 04 µs

)S-R(dtemiTesaeleRPOTS

)1(

5.1sm

)S-W(dtemiTesaeleRedoMtiaWedoMnoitapissiDrewoPwoL 052 µs

d(P-R)

Wait time to stabilize internal

supply voltage when power-on

CPU clock

td(R-S)

(a)

(b) td(W-S)

d(R-S)

STOP release time

d(W-S)

Low power dissipation mode

wait mode release time

Interrupt for

(a) Stop mode release

(b) Wait mode release

d(ROC)

Wait time to stabilize internal

on-chip oscillator when power-

ROC

RESET

VCC

td(P-R) td(ROC)

18. Electrical Characteristics (M16C/26T)

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VCC = 5V

Table 18.44.

Electrical Characteristics

(

lobmySretemaraPnoitidnoC dradnatS

tinU

.niM.pyT.xaM

hgiHtuptuO egatloV)"H"( 1P

1Pot

6P,

6Pot

7P,

7Pot

8Pot

9P,

9Pot

01P,

01Pot

Am5-= V

0.2 V

hgiHtuptuO egatloV)"H"( 1P

1Pot

6P,

6Pot

7P,

7Pot

8Pot

9P,

9Pot

01P,

01Pot

002-= µAV

3.0 V

egatloV)"H"(hgiHtuptuOX

TUO

rewoPhgiH I

Am1-= V

0.2 V

rewoPwoL I

Am5.0-= V

0.2 V

egatloV)"H"(hgiHtuptuOX

TUOC

rewoPhgiH deilppadaoloN5.2 V

rewoPwoL deilppadaoloN6.1

woLtuptuO egatloV)"L"( 1P

1Pot

6P,

6Pot

7P,

7Pot

8Pot

9P,

9Pot

01P,

01Pot

Am5=0.2V

woLtuptuO egatloV)"L"( 1P

1Pot

6P,

6Pot

7P,

7Pot

8Pot

9P,

9Pot

01P,

01Pot

002= µA54.0V

egatloV)"L"(woLtuptuOX

TUO

rewoPhgiH I

Am1=0.2 V

rewoPwoL I

Am5.0=0.2

egatloV)"L"(woLtuptuOX

TUOC

rewoPhgiH deilppadaoloN0

rewoPwoL deilppadaoloN0

V-

-T

siseretsyH 0AT

4AT-

0BT,

2BT-

TNI,

TNI-

DA,IMN,

GRT

STC

STC-

KLC,

KLC-

2AT,

TUO

4AT-

TUO

IK,

IK-

0DX

R-

2DX

2.00.1V

V-

-T

siseretsyH TESER 2.05.2V

V-

-T

siseretsyH X

2.08.0 V

hgiHtupnI tnerruC)"H"( 1P

1Pot

6P,

6Pot

7P,

7Pot

8Pot

9P,

9Pot

01P,

01Pot

VNC,TESER,

V5=0.5 µA

woLtupnI tnerruC)"L"( 1P

1Pot

6P,

6Pot

7P,

7Pot

8Pot

9P,

9Pot

01P,

01Pot

VNC,TESER,

V0=0.5- µA

PULLUP

pu-lluP ecnatsiseR 1P

1Pot

6P,

6Pot

7P,

7Pot

8Pot

9P,

9Pot

01P,

01Pot

V0=0305071kΩ

NIX

ecnatsiseRkcabdeeFX

5.1MΩ

NICX

ecnatsiseRkcabdeeFX

NIC

51MΩ

MAR

egatloVybdnatSMAR edompotsnI0.2V

:ETON otdecnerefeR.1V

V,V5.5ot2.4=

.deificepsesiwrehtosselnuzHM02=)KLCB(f,C°58ot04-=rpoTtaV0=

18. Electrical Characteristics (M16C/26T)

page 286

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VCC = 5V

Table 18.45.

Electrical Characteristics (2)

(

lobmySretemaraPnoitidnoCtnemerusaeM dradnatS tinU

.niM.pyT.xaM

ylppuSrewoP tnerruC

)V5.5ot0.4=

erasniptuptuO dnanepotfel erasniprehto Votdetcennoc

yromemhsalF(fKLCB,zHM02=) noisividon,kcolcniaM 6191Am

,setareporotallicsopihc-nO

)COR(2

zHM1=)KLCB(f,detceles 1Am

yromemhsalF margorp V0.5=ccV,zHM01=)KLCB(f 11Am

yromemhsalF esare V0.5=ccV,zHM01=)KLCB(f 21Am

yromemhsalFzHk23=)KLCB(f,

edomnoitpmusnocrewop-wolnI,

MARnogninnurmargorP

)3(

52 µA

,zHk23=)KLCB(f ,edomnoitpmusnocrewop-wolnI yromemhsalfnogninnurmargorP

)3(

054 µA

,noitallicsopihc-nO

)COR(2

,zHM1=)KLCB(f,detceles edomtiawnI

05 µA

edomtiawnI,zHk23=)KLCB(f

)2(

HGIHyticapacnoitallicsO 01 µA

,zHk23=)KLCB(fedomtiawnI

)2(

WOLyticapacnoitallicsO 3µA

,spotskcolcelihW52=rpoTC°8.03

µA

:SETON otdecnerefeR.1V

V,V5.5ot2.4=

.deificepsesiwrehtosselnuzHM02=)KLCB(f,C°58ot04-=rpoTtaV0=

fgnisu,setareporemitenohtiW.2

23C

..stsixedetucexeebotmargorpehthcihwniyromemehtsetacidnisihT.3

18. Electrical Characteristics (M16C/26T)

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VCC = 5V

Timing Requirements

(VCC = 5V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified)

Table 18.46. External Clock Input (XIN input)

Max.

External clock rise time

Min.

External clock input cycle time

External clock input HIGH pulse width

External clock input LOW pulse width

External clock fall time

w(H

)

w(L)

ParameterSymbol Unit

Standard

20 9

18. Electrical Characteristics (M16C/26T)

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VCC = 5V

Timing Requirements

(VCC = 5V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified)

Table 18.48. Timer A Input (Gating Input in Timer Mode)

Table 18.49. Timer A Input (External Trigger Input in One-shot Timer Mode)

Table 18.50. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)

Table 18.51. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)

Table 18.47. Timer A Input (Counter Input in Event Counter Mode)

Table 18.52. Timer A Input (Two-phase Pulse Input in Event Counter Mode)

Standard

Max.

TAiIN input LOW pulse width

tw(TAL)

Min. ns

Unit

TAiIN input HIGH pulse width

tw(TAH)

ParameterSymbol

tc(TA) TAiIN input cycle time

100

Standard

Max.

Min. ns

Unit

TAiIN input cycle time

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

tc(TA)

tw(TAH)

tw(TAL)

Symbol Parameter

400

200

Standard

Max.

Min. ns

Unit

TAiIN input cycle time

TAiIN input HIGH pulse width

TAiIN input LOW pulse width

tc(TA)

tw(TAH)

tw(TAL)

Symbol Parameter

200

100

Standard

Max.

Min. ns

Unit

tw(TAH)

tw(TAL)

Symbol Parameter

TAiIN input HIGH pulse width

TAiIN input LOW pulse width 100

100

Standard

Max.

Min. ns

Unit

Symbol Parameter

TAiOUT input cycle time

TAiOUT input HIGH pulse width

TAiOUT input LOW pulse width

TAiOUT input setup time

TAiOUT input hold time

tc(UP)

tw(UPH)

tw(UPL)

tsu(UP-TIN)

th(TIN-UP)

2000

1000

400

Standard

Max.

Min. ns

Unit

Symbol Parameter

TAiIN input cycle time

TAiOUT input setup time

TAiIN input setup time

tc(TA)

tsu(TAIN-TAOUT)

tsu(TAOUT-TAIN)

800

200

18. Electrical Characteristics (M16C/26T)

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)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

Timing Requirements

(VCC = 5V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified)

Table 18.53. Timer B Input (Counter Input in Event Counter Mode)

Table 18.54. Timer B Input (Pulse Period Measurement Mode)

Table 18.55. Timer B Input (Pulse Width Measurement Mode)

Table 18.56. A/D Trigger Input

Table 18.57. Serial I/O

_______

Table 18.58. External Interrupt INTi Input

VCC = 5V

Standard

Max.Min.

TBiIN input cycle time (counted on one edge)

TBiIN input HIGH pulse width (counted on one edge)

TBiIN input LOW pulse width (counted on one edge)

tc(TB)

tw(TBH)

tw(TBL)

ParameterSymbol Unit

tc(TB)

tw(TBL)

tw(TBH)

TBiIN input HIGH pulse width (counted on both edges)

TBiIN input LOW pulse width (counted on both edges)

TBiIN input cycle time (counted on both edges)

Standard

Max.

Min. ns

tc(TB)

tw(TBH)

Symbol Parameter Unit

tw(TBL) ns

TBiIN input HIGH pulse width

TBiIN input cycle time

TBiIN input LOW pulse width

Standard

Max.

Min. ns

tc(TB)

Symbol Parameter Unit

tw(TBL) ns

tw(TBH) TBiIN input cycle time

TBiIN input HIGH pulse width

TBiIN input LOW pulse width

Standard

Max.

Min. ns

tc(AD)

tw(ADL)

Symbol Parameter Unit

ADTRG input cycle time (trigger able minimum)

ADTRG input LOW pulse width

Standard

Max.

Min. ns

tw(INH)

tw(INL)

Symbol Parameter Unit

INTi input LOW pulse width

INTi input HIGH pulse width

Standard

Max.Min.

CLKi input cycle time

CLKi input HIGH pulse width

CLKi input LOW pulse width

tc(CK)

tw(CKH)

tw(CKL)

ParameterSymbol Unit

td(C-Q)

tsu(D-C)

th(C-Q) TxDi hold time

RxDi input setup time

TxDi output delay time

th(C-D) RxDi input hold time

100

200

400

200

400

200

1000

125

250

200

100

18. Electrical Characteristics (M16C/26T)

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)T62/C61M,B62/C61M,A62/C61M(puorGA62/C61M

VCC = 5V

TAiIN input

TAiOUT input

During event counter mode

TBiIN input

ADTRG input

c(TA)

w(TAH)

w(TAL)

c(UP)

w(UPH)

w(UPL)

c(TB)

w(TBH)

w(TBL)

c(AD)

w(ADL)

h(TIN-UP)

su(UP-TIN)

TAiIN input

(When count on falling

edge is selected)

TAiIN input

(When count on rising

edge is selected)

TAiOUT input

(Up/down input)

TAiIN input

Two-phase pulse input in event counter mode

c(TA)

su(TAIN-TAOUT)

su(TAOUT-TAIN)

su(TAIN-TAOUT)

su(TAOUT-TAIN)

TAiOUT input

XIN input

w(H)

w(L)

Figure 18.5. Timing Diagram (1)

18. Electrical Characteristics (M16C/26T)

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VCC = 5V

Figure 18.6. Timing Diagram (2)

tsu(D–C)

CLKi

TxDi

RxDi

tc(CK)

tw(CKH)

tw(CKL)

tw(INL)

tw(INH)

td(C–Q) th(C–D)

th(C–Q)

INTi input

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VCC = 3V

Table 18.59. Electrical Characteristics

(

lobmySretemaraPnoitidnoC dradnatS

tinU

.niM.pyT.xaM

hgiHtuptuO egatloV)"H"( 1P

1Pot

6P,

6Pot

7P,

7Pot

8Pot

9P,

9Pot

01P,

01Pot

Am1-= V

5.0 V

egatloV)"H"(hgiHtuptuOX

TUO

rewoPhgiH I

Am1.0-= V

5.0 V

rewoPwoL I

05-= µAV

5.0 V

egatloV)"H"(hgiHtuptuOX

TUOC

rewoPhgiH deilppadaoloN5.2 V

rewoPwoL deilppadaoloN6.1

woLtuptuO egatloV)"L"( 1P

1Pot

6P,

6Pot

7P,

7Pot

8Pot

9P,

9Pot

01P,

01Pot

Am1=5.0V

egatloV)"L"(woLtuptuOX

TUO

rewoPhgiH I

Am1.0=5.0 V

rewoPwoL I

05= µA5.0

egatloV)"L"(woLtuptuOX

TUOC

rewoPhgiH deilppadaoloN0

rewoPwoL deilppadaoloN0

V-

-T

siseretsyH 0AT

4AT-

0BT,

2BT-

TNI,

TNI-

DA,IMN,

GRT

STC

STC-

KLC,

KLC-

2AT,

TUO

4AT-

TUO

IK,

IK-

0DX

R-

2DX

8.0V

V-

-T

siseretsyH TESER 8.1V

V-

-T

siseretsyH X

8.0 V

hgiHtupnI tnerruC)"H"( 1P

1Pot

6P,

6Pot

7P,

7Pot

8Pot

9P,

9Pot

01P,

01Pot

VNC,TESER,

V3=0.4 µA

woLtupnI tnerruC)"L"( 1P

1Pot

6P,

6Pot

7P,

7Pot

8Pot

9P,

9Pot

01P,

01Pot

VNC,TESER,

V0=0.4- µA

PULLUP

pu-lluP ecnatsiseR 1P

1Pot

6P,

6Pot

7P,

7Pot

8Pot

9P,

9Pot

01P,

01Pot

V0=05001005kΩ

NIX

ecnatsiseRkcabdeeFX

0.3MΩ

NICX

ecnatsiseRkcabdeeFX

NIC

52MΩ

MAR

egatloVybdnatSMAR edompotsnI0.2V

:ETON otdecnerefeR.1V

V,V6.3ot0.3=

.deificepsesiwrehtosselnuzHM02=)KLCB(f,C°58ot04-=rpoTtaV0=

18. Electrical Characteristics (M16C/26T)

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Table 18.60. Electrical Characteristics (2)

(

VCC = 3V

lobmySretemaraPnoitidnoCtnemerusaeM dradnatS tinU

.niM.pyT.xaM

ylppuSrewoP tnerruC

)V6.3ot0.3=

erasniptuptuO dnanepotfel erasniprehto Votdetcennoc

yromemhsalF(fKLCB,zHM01=) noisividon,kcolcniaM 721Am

,setareporotallicsopihc-nO

)COR(2

zHM1=)KLCB(f,detceles 1Am

yromemhsalF margorp V0.3=ccV,zHM01=)KLCB(f 01Am

yromemhsalF esare V0.3=ccV,zHM01=)KLCB(f 11Am

yromemhsalFzHk23=)KLCB(f,

edomnoitpmusnocrewop-wolnI,

MARnogninnurmargorP

)3(

52 µA

,zHk23=)KLCB(f ,edomnoitpmusnocrewop-wolnI yromemhsalfnogninnurmargorP

)3(

054 µA

,setareporotallicsopihc-nO

)COR(2

,zHM1=)KLCB(f,detceles edomtiawnI

54 µA

edomtiawnI,zHk23=)KLCB(f

)2(

HGIHyticapacnoitallicsO 01 µA

,zHk23=)KLCB(fedomtiawnI

)2(

WOLyticapacnoitallicsO 3µA

,spotskcolcelihW52=rpoTC°7.03

µA

:SETON otdecnerefeR.1V

V,V6.3ot0.3=

.deificepsesiwrehtosselnuzHM02=)KLCB(f,C°58ot04-=rpoTtaV0=

fgnisu,setareporemitenohtiW.2

23C

..stsixedetucexeebotmargorpehthcihwniyromemehtsetacidnisihT.3

18. Electrical Characteristics (M16C/26T)

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Timing Requirements

(VCC = 3V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified)

Table 18.61. External Clock Input (XIN input)

Max.

External clock rise time

Min.

External clock input cycle time

External clock input HIGH pulse width

External clock input LOW pulse width

External clock fall time

tw(H)

tw(L)

ParameterSymbol Unit

Standard

100

40 18

VCC = 3V

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VCC = 3V

Timing Requirements

(VCC = 3V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified)

Table 18.62. Timer A Input (Counter Input in Event Counter Mode)

Table 18.63. Timer A Input (Gating Input in Timer Mode)

Table 18.64. Timer A Input (External Trigger Input in One-shot Timer Mode)

Table 18.65. Timer A Input (External Trigger Input in Pulse Width Modulation Mode)

Table 18.66. Timer A Input (Counter Increment/decrement Input in Event Counter Mode)

Table 18.67. Timer A Input (Two-phase Pulse Input in Event Counter Mode)

Standard

Max.

TAi

input LOW pulse width

w(TAL)

Min. ns

Unit

TAi

input HIGH pulse width

w(TAH)

ParameterSymbol

c(TA)

TAi

input cycle time

150

Standard

Max.

Min. ns

Unit

TAi

input cycle time

TAi

input HIGH pulse width

TAi

input LOW pulse width

c(TA)

w(TAH)

w(TAL)

Symbol Parameter

600

300

Standard

Max.

Min. ns

Unit

TAi

input cycle time

TAi

input HIGH pulse width

TAi

input LOW pulse width

c(TA)

w(TAH)

w(TAL)

Symbol Parameter

300

150

Standard

Max.

Min. ns

Unit

w(TAH)

w(TAL)

Symbol Parameter

TAi

input HIGH pulse width

TAi

input LOW pulse width 150

150

Standard

Max.Min. ns

Unit

Symbol Parameter

TAi

OUT

input cycle time

TAi

OUT

input HIGH pulse width

TAi

OUT

input LOW pulse width

TAi

OUT

input setup time

TAi

OUT

input hold time

c(UP)

w(UPH)

w(UPL)

su(UP-T

)

h(T

IN-

UP)

3000

1500

600

Standard

Max.

Min. µs

Unit

Symbol Parameter

TAi

input cycle time

TAi

OUT

input setup time

TAi

input setup time

c(TA)

su(TA

-TA

OUT

)

su(TA

OUT

-TA

)

500

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VCC = 3V

Table 18.68. Timer B Input (Counter Input in Event Counter Mode)

Table 18.69. Timer B Input (Pulse Period Measurement Mode)

Table 18.70. Timer B Input (Pulse Width Measurement Mode)

Table 18.71. A/D Trigger Input

Table 18.72. Serial I/O

_______

Table 18.73. External Interrupt INTi Input

Timing Requirements

(VCC = 3V, VSS = 0V, at Topr = – 40 to 85oC unless otherwise specified)

Standard

Max.Min.

TBi

input cycle time (counted on one edge)

TBi

input HIGH pulse width (counted on one edge)

TBi

input LOW pulse width (counted on one edge)

c(TB)

w(TBH)

w(TBL)

ParameterSymbol Unit

c(TB)

w(TBL)

w(TBH)

TBi

input HIGH pulse width (counted on both edges)

TBi

input LOW pulse width (counted on both edges)

TBi

input cycle time (counted on both edges)

Standard

Max.

Min. ns

c(TB)

w(TBH)

Symbol Parameter Unit

w(TBL)

TBi

input HIGH pulse width

TBi

input cycle time

TBi

input LOW pulse width

Standard

Max.

Min. ns

c(TB)

Symbol Parameter Unit

w(TBL)

w(TBH)

TBi

input cycle time

TBi

input HIGH pulse width

TBi

input LOW pulse width

Standard

Max.

Min. ns

c(AD)

w(ADL)

Symbol Parameter Unit

TRG

input cycle time (trigger able minimum)

TRG

input LOW pulse width

Standard

Max.

Min. ns

w(INH)

w(INL)

Symbol Parameter Unit

INTi input LOW pulse width

INTi input HIGH pulse width

Standard

Max.Min.

CLKi input cycle time

CLKi input HIGH pulse width

CLKi input LOW pulse width

c(CK)

w(CKH)

w(CKL)

ParameterSymbol Unit

d(C-Q)

su(D-C)

h(C-Q)

TxDi hold time

RxDi input setup time

TxDi output delay time

h(C-D)

RxDi input hold time

150

120

300

600

300

600

300

1500

200

380

300

150

100

160

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VCC = 3V

Figure 18.7. Timing Diagram (1)

TAiIN input

TAiOUT input

During Event Counter Mode

TBiIN input

ADTRG input

c(TA)

w(TAH)

w(TAL)

c(UP)

w(UPH)

w(UPL)

c(TB)

w(TBH)

w(TBL)

c(AD)

w(ADL)

h(TIN-UP)

su(UP-TIN)

TAiIN input

(When count on falling

edge is selected)

TAiIN input

(When count on rising

edge is selected)

TAiOUT input

(Up/down input)

TAiIN input

Two-Phase Pulse Input in Event Counter Mode

c(TA)

su(TAIN-TAOUT)

su(TAOUT-TAIN)

su(TAIN-TAOUT)

su(TAOUT-TAIN)

TAiOUT input

XIN input

w(H)

w(L)

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VCC = 3V

Figure 18.8. Timing Diagram (2)

tsu(D–C)

CLKi

TxDi

RxDi

tc(CK)

tw(CKH)

tw(CKL)

tw(INL)

tw(INH)

td(C–Q) th(C–D)

th(C–Q)

INTi input

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19. Usage Notes

19.1 SFR

19.1.1 Precaution for 48-pin package

Set the IFSR20 bit in the IFSR2A register to "1" after reset and set the PACR2 to PACR0 bits in the PACR

19.1.2 Precaution for 42-pin package

Set the IFSR20 bit in the IFSR2A register to "1" after reset and set the PACR2 to PACR0 bits in the PACR

19.1.3 Register Setting

Immediate values should be set in the registers containing write-only bits. When establishing a new value

by modifying a previous value, write the previous value into RAM as well as the register. Change the

contents of the RAM and then transfer the new value to the register.

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19.2 PLL Frequency Synthesizer

Stabilize supply voltage so that the standard of the power supply ripple is met.

Typ. Max. Unit

Parameter

f(ripple) Power supply ripple allowable frequency(VCC)

Symbol Min. Standard

kHz

Power supply ripple allowabled amplitude

voltage

Power supply ripple rising/falling gradient

(VCC=5V)

(VCC=3V)

(VCC=5V)

(VCC=3V)

Vp-p(ripple)

VCC(|∆V/∆T|)

0.5

0.3

V/ms

Vp-p(ripple)

f(ripple)

VCC

(ripple)

Power supply ripple allowable frequency

)

p-p(ripple)

Power supply ripple allowable amplitude

voltage

Figure 19.1 Timing of Voltage Fluctuation

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19.3 Power Control

1. When exiting stop mode by hardware reset, the device will startup using the on-chip oscillator.

2. Set the MR0 bit in the TAiMR register(i=0 to 4) to “0”(pulse is not output) to use the timer A to exit stop

mode.

3. When entering wait mode, insert a JMP.B instruction before a WAIT instruction. Do not excute any

instructions which can generate a write to RAM between the JMP.B and WAIT instructions. Disable the

DMA transfers, if a DMA transfer may occur between the JMP.B and WAIT instructions. After the WAIT

instruction, insert at least 4 NOP instructions. When entering wait mode, the instruction queue reads

ahead the instructions following WAIT, and depending on timing, some of these may execute before the

microcomputer enters wait mode.

Program example when entering wait mode

Program Example: JMP.B L1 ; Insert JMP.B instruction before WAIT instruction

L1: FSET I ;

WAIT ; Enter wait mode

NOP ; More than 4 NOP instructions

NOP

4. When entering stop mode, insert a JMP.B instruction immediately after executing an instruction which

sets the CM10 bit in the CM1 register to “1”, and then insert at least 4 NOP instructions. When entering

stop mode, the instruction queue reads ahead the instructions following the instruction which sets the

CM10 bit to “1” (all clock stops), and, some of these may execute before the microcomputer enters stop

mode or before the interrupt routine for returning from stop mode.

Program example when entering stop mode

Program Example: FSET I

BSET CM10 ; Enter stop mode

JMP.B L1 ; Insert JMP.B instruction

L1: NOP ; More than 4 NOP instructions

NOP

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5. Wait until the main clock oscillation stabilization time, before switching the CPU clock source to the

main clock.

Similarly, wait until the sub clock oscillates stably before switching the CPU clock source to the sub

clock.

6. Suggestions to reduce power consumption

(a) Ports

The processor retains the state of each I/O port even when it goes to wait mode or to stop mode. A

current flows in active I/O ports. A dash current may flow through the input ports in high impedance

state, if the input is floating. When entering wait mode or stop mode, set non-used ports to input and

stabilize the potential.

(b) A/D converter

When A/D conversion is not performed, set the VCUT bit in the ADCON1 register to “0” (no VREF

connection). When A/D conversion is performed, start the A/D conversion at least 1 µs or longer after

setting the VCUT bit to “1” (VREF connection).

Use the CM02 bit in the CM0 register to stop the unnecessary peripheral functions during wait mode.

However, because the peripheral function clock (fC32) generated from the sub-clock does not stop,

this measure is not conducive to reducing the power consumption of the chip. If low speed mode or

low power dissipation mode is to be changed to wait mode, set the CM02 bit to “0” (do not stop

peripheral function clocks in wait mode), before changing wait mode.

(d) Switching the oscillation-driving capacity

Set the driving capacity to “LOW” when oscillation is stable.

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19.4 Protect

Set the PRC2 bit to “1” (write enabled) and then write to any address, and the PRC2 bit will be cleared to “0”

(write protected). The registers protected by the PRC2 bit should be changed in the next instruction after

setting the PRC2 bit to “1”. Make sure no interrupts or DMA transfers will occur between the instruction in

which the PRC2 bit is set to “1” and the next instruction.

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19.5 Interrupts

19.5.1 Reading address 0000016

Do not read the address 0000016 in a program. When a maskable interrupt request is accepted, the CPU

reads interrupt information (interrupt number and interrupt request priority level) from the address

0000016 during the interrupt sequence. At this time, the IR bit for the accepted interrupt is cleared to “0”.

If the address 0000016 is read in a program, the IR bit for the interrupt which has the highest priority

among the enabled interrupts is cleared to “0”. This causes a problem that the interrupt is canceled, or an

unexpected interrupt request is generated.

19.5.2 Setting the SP

Set any value in the SP(USP, ISP) before accepting an interrupt. The SP(USP, ISP) is cleared to ‘000016’

after reset. Therefore, if an interrupt is accepted before setting any value in the SP(USP, ISP), the pro-

gram may go out of control.

_______

19.5.3 The NMI Interrupt

_______ _______

1. The NMI interrupt is invalid after reset. The NMI interrupt becomes effective by setting to “1” the PM24

_______

bit in the PM2 register. Set the PM24 bit to "1" when a high-level signal ("H") is applied to the NMI pin.

_______ _______

If the PM24 bit is set to "1" when a low-level signal ("L") is applied, NMI interrupt is generated. Once NMI

interrupt is enabled, it will not be disabled unless a reset is applied.

_______

2. The input level of the NMI pin can be read by accessing the P8_5 bit in the P8 register.

_______ _______

3. When selecting NMI function, stop mode cannot be entered into while input on the NMI pin is low. This

_______

is because while input on the NMI pin is low the CM10 bit in the CM1 register is fixed to “0”.

_______ _______

4. When selecting NMI function, do not go to wait mode while input on the NMI pin is low. This is because

_______

when input on the NMI pin goes low, the CPU stops but CPU clock remains active; therefore, the current

consumption in the chip does not drop. In this case, normal condition is restored by an interrupt gener-

ated thereafter. _______ _______

5. When selecting NMI function, the low and high level durations of the input signal to the NMI pin must

each be 2 CPU clock cycles + 300 ns or more.

_______

6. When using the NMI interrupt for exiting stop mode, set the NDDR register to “FF16” (disable digital

debounce filter) before entering stop mode.

19.5.4 Changing the Interrupt Generation Factor

If the interrupt generate factor is changed, the IR bit in the interrupt control register for the changed

interrupt may inadvertently be set to “1” (interrupt requested). If you changed the interrupt generate factor

for an interrupt that needs to be used, be sure to clear the IR bit for that interrupt to “0” (interrupt not

requested).

“Changing the interrupt generate factor” referred to here means any act of changing the source, polarity

or timing of the interrupt assigned to each software interrupt number. Therefore, if a mode change of any

peripheral function involves changing the generate factor, polarity or timing of an interrupt, be sure to

clear the IR bit for that interrupt to “0” (interrupt not requested) after making such changes. Refer to the

description of each peripheral function for details about the interrupts from peripheral functions.

Figure 19.2 shows the procedure for changing the interrupt generate factor.

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______

19.5.5 INT Interrupt

1. Either an “L” level of at least tW(INH) or an “H” level of at least tW(INL) width is necessary for the signal

_______ _______

input to pins INT0 through INT5 regardless of the CPU operation clock.

2. If the POL bit in the INT0IC to INT5IC registers or the IFSR7 to IFSR0 bits in the IFSR register are

changed, the IR bit may inadvertently set to 1 (interrupt requested). Be sure to clear the IR bit to 0

(interrupt not requested) after changing any of those register bits.

3. When using the INT5 interrupt for exiting stop mode, set the P17DDR register to “FF16” (disable digital

debounce filter) before entering stop mode.

Figure 19.2. Procedure for Changing the Interrupt Generate Factor

Changing the interrupt source

Disable interrupts (2, 3)

Use the MOV instruction to clear the IR bit to “0” (interrupt not requested) (3)

Change the interrupt generate factor (including a mode change of peripheral function)

Enable interrupts (2, 3)

End of change

IR bit: A bit in the interrupt control register for the interrupt whose interrupt generate factor is to

be changed

NOTES:

1. The above settings must be executed individually. Do not execute two or more settings simultaneously

(using one instruction).

2. Use the I flag for the INTi interrupt (i = 0 to 5).

For the interrupts from peripheral functions other than the INTi interrupt, turn off the peripheral function that

is the source of the interrupt in order not to generate an interrupt request before changing the interrupt

generate factor. In this case, if the maskable interrupts can all be disabled without causing a problem, use

the I flag. Otherwise, use the corresponding

3. Refer to 19.5.6 Rewrite the Interrupt Control Register for details about the instructions to use and the

notes to be taken for instruction execution.

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19.5.6 Rewrite the Interrupt Control Register

(1) The interrupt control register for any interrupt should be modified in places where no requests for that

interrupt may occur. Otherwise, disable the interrupt before rewriting the interrupt control register.

(2) To rewrite the interrupt control register for any interrupt after disabling that interrupt, be careful with the

instruction to be used.

Changing any bit other than the IR bit

If while executing an instruction, a request for an interrupt controlled by the register being modified

occurs, the IR bit in the register may not be set to “1” (interrupt requested), with the result that the

interrupt request is ignored. If such a situation presents a problem, use the instructions shown below

to modify the register.

Usable instructions: AND, OR, BCLR, BSET

Changing the IR bit

Depending on the instruction used, the IR bit may not always be cleared to “0” (interrupt not re-

quested). Therefore, be sure to use the MOV instruction to clear the IR bit.

(3) When using the I flag to disable an interrupt, refer to the sample program fragments shown below as

you set the I flag. (Refer to (2) for details about rewrite the interrupt control registers in the sample

program fragments.)

Examples 1 through 3 show how to prevent the I flag from being set to “1” (interrupts enabled) before the

interrupt control register is rewritten, due to the internal bus and the instruction queue buffer timing.

Example 1: Using the NOP instruction to keep the program waiting until the

interrupt control register is modified

INT_SWITCH1:

FCLR I ; Disable interrupts

AND.B #00h, 0055h ;Set the TA0IC register to 00

NOP ;

NOP

FSET I ; Enable interrupts

The number of NOP instruction is as follows.

PM20 = 1 (1 wait) : 2, PM20 = 0 (2 waits): 3

Example 2:Using the dummy read to keep the FSET instruction waiting

INT_SWITCH2:

FCLR I ; Disable interrupts

AND.B #00h, 0055h ; Set the TA0IC register to 00

MOV.W MEM, R0 ; Dummy read

FSET I ; Enable interrupts

Example 3:Using the POPC instruction to changing the I flag

INT_SWITCH3:

PUSHC FLG

FCLR I ; Disable interrupts

AND.B #00h, 0055h ; Set the TA0IC register to 00

POPC FLG ; Enable interrupts

19.5.7 Watchdog Timer Interrupt

Initialize the watchdog timer after the watchdog timer interrupt occurs.

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19.6 DMAC

19.6.1 Write to DMAE Bit in DMiCON Register

When both of the conditions below are met, follow the steps below.

Conditions

• The DMAE bit is set to “1” again while it remains set (DMAi is in an active state).

• A DMA request may occur simultaneously when the DMAE bit is being written.

Step 1: Write “1” to the DMAE bit and DMAS bit in DMiCON register simultaneously(*1).

Step 2: Make sure that the DMAi is in an initial state(*2) in a program.

If the DMAi is not in an initial state, the above steps should be repeated.

Notes:

1. The DMAS bit remains unchanged even if “1” is written. However, if “0” is written to this bit, it is set to

“0” (DMA not requested). In order to prevent the DMAS bit from being modified to “0”, “1” should be

written to the DMAS bit when “1” is written to the DMAE bit. In this way the state of the DMAS bit

immediately before being written can be maintained.

Similarly, when writing to the DMAE bit with a read-modify-write instruction, “1” should be written to

the DMAS bit in order to maintain a DMA request which is generated during execution.

2. Read the TCRi register to verify whether the DMAi is in an initial state. If the read value is equal to a

value which was written to the TCRi register before DMA transfer start, the DMAi is in an initial state.

(If a DMA request occurs after writing to the DMAE bit, the value written to the TCRi register is “1”.) If

the read value is a value in the middle of transfer, the DMAi is not in an initial state.

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19.7 Timer

19.7.1 Timer A

19.7.1.1 Timer A (Timer Mode)

1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR

(i = 0 to 4) register and the TAi register before setting the TAiS bit in the TABSR register to “1” (count

starts).

Always make sure the TAiMR register is modified while the TAiS bit remains “0” (count stops)

regardless whether after reset or not.

2. While counting is in progress, the counter value can be read out at any time by reading the TAi

is always “FFFF16”. If the TAi register is read after setting a value in it, but before the counter starts

counting, the read value is the one that has been set in the register.

_____

3. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”

_____

(three-phase output forcible cutoff by input on SD pin enabled), the TA1OUT, TA2OUT and TA4OUT

pins go to a high-impedance state.

19.7.1.2 Timer A (Event Counter Mode)

1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR

(i = 0 to 4) register, the TAi register, the UDF register, the TAZIE, TA0TGL and TA0TGH bits in the

ONSF register and the TRGSR register before setting the TAiS bit in the TABSR register to “1”

(count starts).

Always make sure the TAiMR register, the UDF register, the TAZIE, TA0TGL and TA0TGH bits and

the TRGSR register are modified while the TAiS bit remains “0” (count stops) regardless whether

after reset or not.

2. While counting is in progress, the counter value can be read out at any time by reading the TAi

is always “FFFF16” when the timer counter underflows and “000016” when the timer counter over-

flows. If the TAi register is read after setting a value in it, but before the counter starts counting, the

read value is the one that has been set in the register.

_____

3. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”

_____

(three-phase output forcible cutoff by input on SD pin enabled), the TA1OUT, TA2OUT and TA4OUT

pins go to a high-impedance state.

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19.7.1.3 Timer A (One-shot Timer Mode)

1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR

(i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the

TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts).

Always make sure the TAiMR register, the TA0TGL and TA0TGH bits and the TRGSR register are

modified while the TAiS bit remains “0” (count stops) regardless whether after reset or not.

2. When setting TAiS bit to “0” (count stop), the following occur:

• The counter stops counting and the content of reload register is reloaded.

• TAiOUT pin outputs “L”.

• After one cycle of the CPU clock, the IR bit in the TAiIC register is set to “1” (interrupt request).

3. Output in one-shot timer mode synchronizes with a count source internally generated. When the

external trigger has been selected, a maximun delay of one cycle of the count source occurs be-

tween the trigger input to TAiIN pin and output in one-shot timer mode.

4. The IR bit is set to “1” when timer operation mode is set with any of the following procedures:

• Select one-shot timer mode after reset.

•Change the operation mode from timer mode to one-shot timer mode.

• Change the operation mode from event counter mode to one-shot timer mode.

To use the timer Ai interrupt (the IR bit), set the IR bit to “0” after the changes listed above have

been made.

5. When a trigger occurs while the timer is counting, the counter reloads the reload register value, and

continues counting after a second trigger is generated and the counter is decremented once. To

generate a trigger while counting, space more than one cycle of the timer count source from the first

trigger and generate again.

6. When selecting the external trigger for the count start conditions in timer A one-shot timer mode, do

generate an external trigger 300ns before the count value of timer A is set to “000016”. The one-shot

timer does not continue counting and may stop.

_____

7. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”

_____

(three-phase output forcible cutoff by input on SD pin enabled), the TA1OUT, TA2OUT and TA4OUT

pins go to a high-impedance state.

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19.7.1.4 Timer A (Pulse Width Modulation Mode)

1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TAiMR

(i = 0 to 4) register, the TAi register, the TA0TGL and TA0TGH bits in the ONSF register and the

TRGSR register before setting the TAiS bit in the TABSR register to “1” (count starts).

Always make sure the TAiMR register, the TA0TGL and TA0TGH bits and the TRGSR register are

modified while the TAiS bit remains “0” (count stops) regardless whether after reset or not.

2. The IR bit is set to “1” when setting a timer operation mode with any of the following procedures:

• Select the PWM mode after reset.

•Change an operation mode from timer mode to PWM mode.

•Change an operation mode from event counter mode to PWM mode.

To use the timer Ai interrupt (interrupt request bit), set the IR bit to “0” by program after the above

listed changes have been made.

3. When setting TAiS register to “0” (count stop) during PWM pulse output, the following action occurs:

• Stop counting.

• When TAiOUT pin is output “H”, output level is set to “L” and the IR bit is set to “1”.

• When TAiOUT pin is output “L”, both output level and the IR bit remains unchanged.

_____

4. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”

_____

(three-phase output forcible cutoff by input on SD pin enabled), the TA1OUT, TA2OUT and TA4OUT

pins go to a high-impedance state.

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19.7.2 Timer B

19.7.2.1 Timer B (Timer Mode)

1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR

(i = 0 to 2) register and TBi register before setting the TBiS bit in the TABSR register to “1” (count

starts).

Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)

regardless whether after reset or not.

2. The counter value can be read out at any time by reading the TBi register. However, if this register

is read at the same time the counter is reloaded, the read value is always “FFFF16.” If the TBi

one that has been set in the register.

19.7.2.2 Timer B (Event Counter Mode)

1. The timer remains idle after reset. Set the mode, count source, counter value, etc. using the TBiMR

(i = 0 to 2) register and TBi register before setting the TBiS bit in the TABSR register to “1” (count

starts).

Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)

regardless whether after reset or not.

2. The counter value can be read out at any time by reading the TBi register. However, if this register

is read at the same time the counter is reloaded, the read value is always “FFFF16.” If the TBi

one that has been set in the register.

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19.7.2.3 Timer B (Pulse Period/pulse Width Measurement Mode)

1. The timer remains idle after reset. Set the mode, count source, etc. using the TBiMR (i = 0 to 2)

Always make sure the TBiMR register is modified while the TBiS bit remains “0” (count stops)

regardless whether after reset or not. To clear the MR3 bit to “0” by writing to the TBiMR register

while the TBiS bit is set to “1” (count starts), be sure to set the TM0D0, TM0D1, MR0, MR1, TCK0

and TCK1 bits to the same value as previously written and the MR2 bit to "0".

2. The IR bit in the TBiIC register (i=0 to 2) goes to “1” (interrupt request), when an effective edge of

a measurement pulse is input or timer Bi is overflowed. The factor of interrupt request can be

determined by use of the MR3 bit in the TBiMR register within the interrupt routine.

3. If the source of interrupt cannot be identified by the MR3 bit such as when the measurement pulse

input and a timer overflow occur at the same time, use another timer to count the number of times

timer B has overflowed.

4. To set the MR3 bit to “0” (no overflow), set TBiMR register with setting the TBiS bit to “1” and

counting the next count source after setting the MR3 bit to “1” (overflow).

5. Use the IR bit in the TBiIC register to detect only overflows. Use the MR3 bit only to determine the

interrupt factor within the interrupt routine.

6. When the count is started and the first effective edge is input, an indeterminate value is transferred

to the reload register. At this time, timer Bi interrupt request is not generated.

7. The value of the counter is indeterminate at the beginning of a count. MR3 may be set to “1” and

timer Bi interrupt request may be generated between the count start and an effective edge input.

8. For pulse width measurement, pulse widths are successively measured. Use program to check

whether the measurement result is an “H” level width or an “L” level width.

19.7.3 Three-phase Motor Control Timer Function

When the IVPCR1 bit in the TB2SC register is set to 1 (three-phase output forced cutoff by SD pin input

(high-impedance) enabled), the INV03 bit in the INVC0 register is set to 1 (three-phase motor control

_____

timer output enabled), and a low-level ("L") signal is applied to the SD pin while a three-phase PWM

___ ___ ___

signal is output, the MCU is forced to cutoff and pins U, U, V, V, W, and W are placed in a high-impedance

state and the INV03 bit is set to 0 (three-phase motor control timer output disabled).

___ ___ ___

To resume the three-phase PWM signal output from pins U, U, V, V, W, and W, set the INV03 bit to 1 and

_____

the IVPCR1 bit to 0 (three-phase output forced cutoff disabled) after the SD pin level becomes "H". Then

set the IVPCR1 bit to 1 (three-phase output forced cutoff enabled) in order to enable the three-phase

output forced cutoff function by input to the SD pin again. _____

The INV03 bit cannot be set to 1 while an "L" signal is input to the SD pin. To set the INV03 bit to 1 after

forcible cutoff, write 1 to the INV03 bit and read the bit to ensure that it is set to 1 by program. Then set the

IVPCR1 bit to 1 after setting it to 0.

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19.8 Serial I/O

19.8.1 Clock-Synchronous Serial I/O

19.8.1.1 Transmission/reception _______ ________

1. With an external clock selected, and choosing the RTS function, the output level of the RTSi pin

goes to “L” when the data-receivable status becomes ready, which informs the transmission side

________

that the reception has become ready. The output level of the RTSi pin goes to “H” when reception

________ ________

starts. So if the RTSi pin is connected to the CTSi pin on the transmission side, the circuit can

_______

transmit and receive data with consistent timing. With the internal clock, the RTS function has no

effect. _____

2. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”

_____ _________

(three-phase output forcible cutoff by input on SD pin enabled), the P73/RTS2/TxD1(when the

U1MAP bit in PACR register is “1”) and CLK2 pins go to a high-impedance state.

19.8.1.2 Transmission

When an external clock is selected, the conditions must be met while if the CKPOL bit in the UiC0

rising edge of the transfer clock), the external clock is in the high state; if the CKPOL bit in the UiC0

falling edge of the transfer clock), the external clock is in the low state.

• The TE bit in the UiC1 register is set to “1” (transmission enabled)

• The TI bit in the UiC1 register is set to “0” (data present in UiTB register)

_______ _______

• If CTS function is selected, input on the CTSi pin is “L”

19.8.1.3 Reception

1. In operating the clock-synchronous serial I/O, operating the transmitter generates a clock for the

receiver shift register. Fix settings for transmission even when using the device only for reception.

Dummy data is output to the outside from the TxDi pin when receiving data.

2. When an internal clock is selected, set the TE bit in the UiC1 register (i = 0 to 2) to 1 (transmission

enabled) and write dummy data to the UiTB register, and the clock for the receiver shift register will

thereby be generated. When an external clock is selected, set the TE bit to "1" and write dummy

data to the UiTB register, and the clock for the receiver shift register will be generated when the

external clock is fed to the CLKi input pin.

3. When successively receiving data, if all bits of the next receive data are prepared in the UARTi

receive register while the RE bit in the UiC1 register (i = 0 to 2) is set to “1” (data present in the UiRB

occurred). In this case, because the content of the UiRB register is indeterminate, a corrective

measure must be taken by programs on the transmit and receive sides so that the valid data before

the overrun error occurred will be retransmitted. Note that when an overrun error occurred, the IR

bit in the SiRIC register does not change state.

4. To receive data in succession, set dummy data in the lower-order byte of the UiTB register every

time reception is made.

5. When an external clock is selected, make sure the external clock is in high state if the CKPOL bit is

set to “0”, and in low state if the CKPOL bit is set to “1” before the following conditions are met:

• Set the RE bit in the UiC1 register to “1” (reception enabled)

• Set the TE bit in the UiC1 register to “1” (transmission enabled)

• Set the TI bit in the UiC1 register to “0” (data present in the UiTB register)

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19.8.2 Serial I/O (UART Mode)

19.8.1.1 Special Mode 1 (I2C bus Mode)

When generating start, stop and restart conditions, set the STSPSEL bit in the U2SMR4 register to “0”

and wait for more than half cycle of the transfer clock before setting each condition generate bit

(STAREQ, RSTAREQ and STPREQ) from “0” to “1”.

19.8.1.2 Special Mode 2 _______ _____

If a low-level signal is applied to the P85/NMI/SD pin when the IVPCR1 bit in the TB2SC register is set

_____

to "1" (three-phase output forcible cutoff by input on SD pin enabled), the P73/RTS2/TxD1(when the

U1MAP bit in PACR register is “1”) and CLK2 pins go to a high-impedance state.

19.8.1.3 Special Mode 4 (SIM Mode)

A transmit interrupt request is generated by setting the U2IRS bit in the U2C1 register to “1” (transmis-

sion complete) and U2ERE bit to “1” (error signal output) after reset. Therefore, when using SIM

mode, be sure to clear the IR bit to “0” (no interrupt request) after setting these bits.

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19.9 A/D Converter

1. Set ADCON0 (except bit 6), ADCON1 and ADCON2 registers when A/D conversion is stopped (before

a trigger occurs).

2. When the VCUT bit in the ADCON1 register is changed from “0” (Vref not connected) to “1” (VREF

connected), start A/D conversion after waiting 1 µs or longer.

3. To prevent noise-induced device malfunction or latchup, as well as to reduce conversion errors, insert

capacitors between the AVCC, VREF, and analog input pins (ANi(i=0 to 7), AN24, AN3i(i=0 to 2)) each

and the AVSS pin. Similarly, insert a capacitor between the VCC pin and the VSS pin. Figure 19.4 is an

example connection of each pin.

4. Make sure the port direction bits for those pins that are used as analog inputs are set to “0” (input

mode). Also, if the TGR bit in ADCON0 register is set to "1" (external trigger), make sure the port

___________

direction bit for the ADTRG pin is set to “0” (input mode).

5. When using key input interrupts, do not use any of the four AN4 to AN7 pins as analog inputs. (A key

input interrupt request is generated when the A/D input voltage goes low.)

6. The φAD frequency must be 10 MHz or less (12 MHz or less in M16C/26B). Without sample-and-hold

function, limit the φAD frequency to 250kHZ or more. With the sample and hold function, limit the φAD

frequency to 1MHZ or more.

7. When changing an A/D operation mode, select analog input pin again in the CH2 to CH0 bits in the

ADCON0 register and the SCAN1 to SCAN0 bits in the ADCON1 register.

Figure 19.3. Use of capacitors to reduce noise

Microcomputer

REF

C1 C2

: AN

(i=0 to 7), AN

, and AN

(i=0 to 2)

NOTES:

1. C1 ≥ 0.47 µF, C2 ≥ 0.47 µF, C3 ≥ 100 pF, C4 ≥ 0.1 µF (reference)

2. Use thick and shortest possible wiring to connect capacitors.

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8. If the CPU reads the A/D register i (i = 0 to 7) at the same time the conversion result is stored in the A/

D register i after completion of A/D conversion, an incorrect value may be stored in the A/D register i.

This problem occurs when a divide-by-n clock derived from the main clock or a subclock is selected for

CPU clock.

• When operating in one-shot mode, single-sweep mode, simultaneous sample sweep mode, delayed

trigger mode 0 or delayed trigger mode 1

Check to see that A/D conversion is completed before reading the target A/D register i. (Check the IR

bit in the ADIC register to see if A/D conversion is completed.)

• When operating in repeat mode or repeat sweep mode 0 or 1

Use the main clock for CPU clock directly without dividing it.

9. If A/D conversion is forcibly terminated while in progress by setting the ADST bit in the ADCON0

contents of A/D register i irrelevant to A/D conversion may also become indeterminate. If while A/D

conversion is underway the ADST bit is cleared to “0” in a program, ignore the values of all A/D register

10.When setting the ADST bit in the ADCON register to "0" to terminate a conversion forcefully by the

program in single sweep conversion mode, A/D delayed trigger mode 0 and A/D delayed trigger mode

1 during A/D conversion operation, the A/D interrupt request may be generated. If this causes a prob-

lem, set the ADST bit to "0" after the interrupt is disabled.

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19.10 Programmable I/O Ports _____

1. If a low-level signal is applied to the SD pin when the IVPCR1 bit in the TB2SC register is set to “1”

_____

(three-phase output forcible cutoff by input on SD pin enabled), the P72 to P75, P80 and P81 pins go to

a high-impedance state.

2. The input threshold voltage of pins differs between programmable input/output ports and peripheral

functions.

Therefore, if any pin is shared by a programmable input/output port and a peripheral function and the

input level at this pin is outside the range of recommended operating conditions VIH and VIL (neither

“high” nor “low”), the input level may be determined differently depending on which side—the program-

mable input/output port or the peripheral function—is currently selected.

3. When the INV03 bit in the INVC0 register is "1"(three-phase motor control timer output enabled), an "L"

_______ _____

input on the P85/NMI/SD pin, has the following effect:

•When the IVPCR1 bit in the TB2SC register is set to “1” (three-phase output forcible cutoff by input

_____ __ __ ___

on the SD pin enabled), the U/ U/ V/ V/ W/ W pins go to a high-impedance state._____

•When the IVPCR1 bit is set to “0” (three-phase output forcible cutoff by input on SD pin

__ __ ___

disabled), the U/ U/ V/ V/ W/ W pins go to a normal port.

Therefore, the P85 pin can not be used as programmable I/O port when the INV03 bit is set to "1".

_____ _______ _____

When the SD function isn't used, set PD85 to “0” (Input) and pull the P85/NMI/SD pin to “H” externally.

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19.11 Electric Characteristic Differences Between Mask ROM and Flash Memory Ver-

sion Microcomputers

Flash memory version and mask ROM version may have different characteristics, operating margin, noise

tolerated dose, noise width dose in electrical characteristics due to internal ROM, different layout pattern,

etc. When switching to the mask ROM version, conduct equivalent tests as system evaluation tests con-

ducted in the flash memory version.

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19.12 Mask ROM Version

19.12.1 Internal ROM area

When using the masked ROM version, write nothing to internal ROM area. Writing to the area may

increase power consumption.

19.12.2 Reserve bit

The b3 to b0 in address 0FFFFF16 are reserved bits. Set these bits to “11112”.

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19.13 Flash Memory Version

19.13.1 Functions to Inhibit Rewriting Flash Memory

ID codes are stored in addresses 0FFFDF16, 0FFFE316, 0FFFEB16, 0FFFEF16, 0FFFF316, 0FFFF716,

and 0FFFFB16. If wrong data is written to these addresses, the flash memory cannot be read or written in

standard serial I/O mode.

The ROMCP register is mapped in address 0FFFFF16. If wrong data is written to this address, the flash

memory cannot be read or written in parallel I/O mode.

In the flash memory version of microcomputer, these addresses are allocated to the vector addresses (H)

of fixed vectors.The b3 to b0 in address 0FFFFF16 are reserved bits. Set these bits to “11112”.

19.13.2 Stop mode

When the microcomputer enters stop mode, execute the instruction which sets the CM10 bit to “1”(stop

mode) after setting the FMR01 bit to “0”(CPU rewrite mode disabled) and disabling the DMA transfer.

19.13.3 Wait mode

When the microcomputer enters wait mode, excute the WAIT instruction after setting the FMR01 bit to

“0”(CPU rewrite mode disabled).

19.13.4

Low power dissipation mode, on-chip oscillator low power dissipation mode

If the CM05 bit is set to “1” (main clock stop), the following commands must not be executed.

• Program

• Block erase

19.13.5 Writing command and data

Write the command code and data at even addresses.

19.13.6 Program Command

Write ‘xx4016’ in the first bus cycle and write data to the write address in the second bus cycle, and an

auto program operation (data program and verify) will start. Make sure the address value specified in the

first bus cycle is the same even address as the write address specified in the second bus cycle.

19.13.7 Operation speed

When CPU clock source is main clock, before entering CPU rewrite mode (EW0 or EW1 mode), select 10

MHz or less for BCLK using the CM06 bit in the CM0 register and the CM17 to CM16 bits in the CM1

(EW0 or EW1 mode), set the ROCR3 to ROCR2 bits in the ROCR register to “divied by 4” or “divide by 8”.

On both cases, set the PM17 bit in the PM1 register to “1” (with wait state).

19.13.8 Instructions prohibited in EW0 Mode

The following instructions cannot be used in EW0 mode because the flash memory’s internal data is

referenced: UND instruction, INTO instruction, JMPS instruction, JSRS instruction, and BRK instruction

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19.13.9 Interrupts

EW0 Mode

• Any interrupt which has a vector in the variable vector table can be used, providing that its vector

is transferred into the RAM area.

_______

• The NMI and watchdog timer interrupts can be used because the FMR0 register and FMR1 regis-

ter are initialized when one of those interrupts occurs. The jump addresses for those interrupt

service routines should be set in the fixed vector table.

_______

Because the rewrite operation is halted when a NMI or watchdog timer interrupt occurs, the rewrite

program must be executed again after exiting the interrupt service routine.

• The address match interrupt cannot be used because the flash memory’s internal data is refer-

enced.

EW1 Mode

• Make sure that any interrupt which has a vector in the relocatable vector table or address match

interrupt will not be accepted during the auto program period or auto erase period with erase-

suspend function disabled.

_______

• The NMI interrupt can be used because the FMR0 register and FMR1 register are initialized when

this interrupt occurs. The jump address for the interrupt service routine should be set in the fixed

vector table. _______

Because the rewrite operation is halted when a NMI interrupt occurs, the rewrite program must be

executed again after exiting the interrupt service routine.

19.13.10 How to access

To set the FMR01, FMR02, FMR11 or FMR16 bit to “1”, set the subject bit to “1” immediately after setting

to “0”. Do not generate an interrupt or a DMA transfer between the instruction to set the bit to “0” and the

_______

instruction to set the bit to “1”. When the PM24 bit is set to “1” (NMI funciton), apply a high-level (“H”)

_______

signal to the NMI pin to set those bits.

19.13.11 Writing in the user ROM area

EW0 Mode

• If the power supply voltage drops while rewriting any block in which the rewrite control program is

stored, a problem may occur that the rewrite control program is not correctly rewritten and, conse-

quently, the flash memory becomes unable to be rewritten thereafter. In this case, standard serial

I/O or parallel I/O mode should be used.

EW1 Mode

• Avoid rewriting any block in which the rewrite control program is stored.

19.13.12 DMA transfer

In EW1 mode, make sure that no DMA transfers will occur while the FMR00 bit in the FMR0 register is set

to "0" (during the auto program or auto erase period).

19.13.13 Regarding Programming/Erasure Times and Execution Time

As the number of programming/erasure times increases, so does the execution time for software com-

mands (Program, and Block Erase). _______

The software commands are aborted by hardware reset 1, hardware reset 2, NMI interrupt, and watchdog

timer interrupt. If a software command is aborted by such reset or interrupt, the affected block must be

erased before reexecuting the aborted command.

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19. Usage Notes

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19.13.14 Definition of Programming/Erasure Times

"Number of programs and erasure" refers to the number of erasure per block.

If the number of program and erasure is n (n=100 1,000 10,000) each block can be erased n times.

For example, if a 2K byte block A is erased after writing 1 word data 1024 times, each to a different

address, this is counted as one program and erasure. However, data cannot be written to the same

adrress more than once without erasing the block. (Rewrite prohibited)

19.13.15

Flash Memory Version Electrical Characteristics 10,000 E/W cycle products (U7, U9)

When Block A or B E/W cycles exceed 100, select one wait state per block access. When FMR17 is set

to "1", one wait state is inserted per access to Block A or B - regardless of the value of PM17. Wait state

insertion during access to all other blocks, as well as to internal RAM, is controlled by PM17 - regardless

of the setting of FMR17.

To use the limited number of erasure efficiently, write to unused address within the block instead of

rewite. Erase block only after all possible address are used. For example, an 8-word program can be

written 128 times before erase becomes necessary.

Maintaining an equal number of erasure between Block A and B will also improve efficiency.

We recommend keeping track of the number of times erasure is used.

19.13.16 Boot Mode

An indeterminate value is sometimes output in the I/O port until the internal power supply becomes stable

_____________

when "H" is applied to the CNVSS pin and "L" is applied to the RESET pin.

When setting the CNVSS pin to "H", the following procedure is required:

____________

(1) Apply an "L" signal to the RESET pin and the CNVSS pin.

(2) Bring VCC to more than 2.7V, and wait at least 2msec.

(Internal power supply stable waiting time)

(3) Apply an "H" signal to the CNVSS pin.

____________

(4) Apply an "H" signal to the RESET pin.

When the CNVSS pin is “H” and RESET pin is “L”, P67 pin is connected to the pull-up resister.

page 323

19. Usage Notes

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19.14 Noise

Connect a bypass capacitor (approximately 0.1µF) across the VCC and VSS pins using the shortest and

thicker possible wiring. Figure 19.4 shows the bypass capacitor connection.

M16C/26A Group

(M16C/26A, M16C/26B, M16C/26T)

Bypass Capacitor

Connecting PatternConnecting Pattern

VSS VCC

Figure 19.4 Bypass Capacitor Connection

page 324

19. Usage Notes

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19.15 Instruction for a Device Use

When handling a device, extra attention is necessary to prevent it from crashing during the electrostatic

discharge period.

Appendix 1. Package Dimensions

page 325

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Appendix 1. Package Dimensions

2.4

11.

12.2

17.

7.7

mbo

Min

P-

SSO

P42-

.4x17.

0.6

MASS[T

]

A-

RENE

JEITA Packa

e Cod

IMEN

AND "

NOTE

)

IMEN

" D

DE TRIM

x m

rmin

oss

sec

IMEN

AND "

NOTE

)

IMEN

" D

DE TRIM

x m

JEITA Packa

e Cod

RENE

P0048KB-

48P6

MASS[T

]

0.2

P-L

FP48-7x7-0.5

.12

.14

Min

Dimension in Millimeters

mbol

7.1

0.1

Appendix 2. Functional Difference

page 326

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Appendix 2. Functional Difference

Appendix 2.1 Differences between M16C/26A, M16C/26B, and M16C/26T

Item M16C/26A, M16C/26B M16C/26T

Main Clock during Oscillating Stoped

and after Reset (Default value “0” while and after the (Default value “1” while and after the

CM05 bit is reset.) CM05 bit is reset.)

Voltage Detection Available Not available

Circuit (VCR1 register, VCR2 register, (reserved register)

(Function of 001916, D4INT register)

001A16, 001F16)

Package

PLQP0048KB-A(48P6Q), PRSP0042GA-B(42P2R)

PLP0048KB-A(48P6Q)

NOTE:

1. Since the emulator between the M16C/26A Group and M16C/29 Group are the same, all functions of

M16C/29 are built in the emulator. When evaluating M16C/26A Group, do not access to the SFR which

is not built in M16C/26A Group. Refer to Hardware Manual about detail and electrical characteristics.

Appendix 2. Functional Difference

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Appendix 2.2 Differences between M16C/26A Group and M16C/26 Group

Item M16C/26A Group M16C/26 Group

Clock Generation 4 circuits (Main clock oscillation circuit, 3 circuits (Main clock oscillation circuit,

Circuit Sub clock oscillation circuit, Sub clock oscillation circuit,

on-chip oscillator, on-chip oscillator)

PLL frequency synthesizer)

System Clock On-chip oscillator Main clock

Source After Reset (Initial value "1" of CM21 bit) (Initial value "0" of CM21 bit)

(Initial value of the CM21

bit in the CM2 register)

On-chip Oscillator Clock

Selectable (8MHz/1MHz/500KHz) Fixed (1MHz)

PACR2 to PACR0 in Necessary to set after reset No PACR register

the PACR register 48pin:"1002", 42pin:"0012"

IFSR20 bit in the Necessary to set to "1" after reset No IFSR2A register

IFSR2A register

External Interrupt ________

8 causes (INT2 added) 7 causes

13 pin

(48-pin version)

________

P84/INT2/ZP IVCC

Function

P70, P71N-ch open drain output and CMOS N-ch open drain output

output are selectable by S/W

A/D Input Pin 12 channels 8 channels

(48-pin version)

A/D operation Mode 8 modes (single, repeat, single sweep, 5 modes (single, repeat, single sweep,

repeat sweep mode 0, repeat sweep repeat sweep mode 0, repeat sweep

mode 1, simultaneous sampling, mode 1)

delayed trigger mode 0, delayed

trigger mode 1)

1 shunt current measurement function

is available

Timer B Operation 5 modes (timer, event counter, pulse 4 modes (timer, event counter, pulse

Mode periods measurement, pulse width periods measurement, pulse width

measurment, A/D trigger) measurment)

1 shunt current measurement function

is available

CRC Calculation Available (compatible to CRC-CCITT Not available

and CRC-16 methods)

Three-phase motor •Waveform output/Switching port output •Waveform output/Switching port output

Control by software is enabled by software is disabled

•Position data retention function •No position data retention function

Digital Debounce _______ _____

This function is in the NMI/SD pin and Not available

Function ________

INT5 pin

3 pin

(48-pin version)

P90/CLKOUT/TB0IN/AN30P90/TB0IN

function (CLKOUT: f1, f8, f32, and fC output)

UART1 Compatible Switching to P64 to P67 or P70 to P73P64 to P67

pin is enabled

Flash Memory Protection to blocks 0, 1 by FMR02 bit Protection to blocks 0,1 by FMR02 bit

Protect Function Protection to the blocks 0 to 3 by

FMR16 bit

Package

PLQP0048KB-A(48P6Q), PRSP0042GA-B(42P2R)

PLQP0048KB-A(48P6Q)

NOTE:

1. Since the emulator between the M16C/26A Group and M16C/29 Group are the same, all functions of

M16C/29 are built in the emulator. When evaluating M16C/26A Group, do not access to the SFR which

is not built in M16C/26A Group. Refer to Hardware Manual about detail and electrical characteristics.

page 328

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AD0 to AD7 184

ADCON0 to ADCON2 182

ADIC 67

ADSTAT0 184

ADTRGCON 183

AIER 79

BCNIC 67

CM0 40

CM1 41

CM2 42

CPSRF 96,110

CRCD 214

CRCIN 214

CRCMR 214

CRCSAR 214

D4INT 30

DAR0 86

DAR1 86

DM0CON 85

DM0IC 67

DM0SL 84

DM1CON 85

DM1IC 67

DM1SL 85

DTT 121

FMR0 241

FMR1 241

FMR4 242

ICTB2 121

IDB0 121

IDB1 121

IFSR 68,76

IFSR2A 68

INT0IC to INT2IC 67

INT3IC 67

INT4IC 67

INT5IC 67

INVC0 119

INVC1 120

KUPIC 67

NDDR 227

ONSF 96

P0 to P13 224

P17DDR 227

PACR 139,226

PCLKR 43

PCR 226

PD0 to PD13 223

PDRF 129

PFCR 131

PLC0 44

PM0 35

PM1 35

PM2 36,43

PRCR 60

PUR0 to PUR2 225

RMAD0 79

RMAD1 79

ROCR 41

ROMCP 236

S0RIC to S2RIC 67

S0TIC to S2TIC 67

SAR0 86

SAR1 86

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TA0 to TA4 95

TA0IC to TA4IC 67

TA0MR to TA4MR 94

TA1 122

TA11 122

TA1MR 125

TA2 122

TA21 122

TA2MR 125

TA2MR to TA4MR 101

TA4 122

TA41 122

TA4MR 125

TABSR 95,110,124

TAiMR 99,106

TB0 to TB5 110

TB0IC TO TB2IC 67

TB0MR to TB5MR 109

TB2 124

TB2MR 125

TB2SC 123,185

TCR0 86

TCR1 86

TPRC 131

TRGSR 96,124

U0BRG to U2BRG 136

U0C0 to U2C0 138

U0C1 to U2C1 139

U0MR to U2MR 137

U0RB to U2RB 136

U0TB to U2TB 136

U2SMR 140

U2SMR2 140

U2SMR3 141

U2SMR4 141

UCON 138

UDF 95

VCR1 30

VCR2 30

WDC 81

WDTS 81

REVISION HISTORY M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual

Rev. Date Description

Page Summary

C-1

2.00 Feb.15,07 - M16C/26B newly added, word standardized: on-chip oscillator, development tool

Overview

1 •Description partially deleted

2 - 3 •1.2 Performance Outline modified

4 - 5 •Figure 1.1 and 1.2 Block Diagrams updated

6•1.4 Product List updated

7•Figure 1.3 Product Numbering System updated

8•Tables 1.7 to 1.10 Product Codes updated

12, 14 •Tables 1.11 and 1.12 Pin Characteristics newly added

15 - 16 •Tables 1.13 Pin Description newly added

SFRs

20 •Table 4.1 SFR Information(1) Note about WDC register is deleted

22 •Table 4.3 SFR Information(3) Value after reset for ROCR register modified

23 •Table 4.4 SFR Information(4) Note 2 added to IFSR2A register

Reset

28 •Figure 5.1.1.2. Reset Sequence Vcc line and ROC line are modified

29 •Figure 5.5.1. Voltage Detection Circuit Block WDC register’s block is deleted

Processor Mode

35 •Figure 6.1 PM1 Register Note 2 partially added

36 •Figure 6.2 PM2 Register newly added

37 •Figure 6.3 Bus Block Diagram and Table 6.1 Accessible Area and Bus Cycle

newly added

Clock Generation Circuit

41 •Figure 7.4 ROCR Register modified

43 •Figure 7.6 PM2 Register Notes 2, 5, 6 modified

45 - 46 •Figure 7.1.1 and 7.2.1 Examples of Main Clock Connection Circuit updated

47 •7.4 PLL Clock Description modified for M16C/26B

•Table 7.4.1 Example for Setting PLL Clock Frequencies Note 1 modified

50 •7.6.1 Normal Operation Mode Description modified

51 •Table 7.6.1.1 Setting Clock Related Bit and Modes modified

54 •Figure 7.6.1 State Transition to Stop Mode and Wait Mode modified

55 •Figure 7.6.1.1. State Transtion in Normal Mode modified

56 •Table 7.6.1 Allowed Transition and Setting modified, Notes 1 and 2 modified

59 •Figure 7.8.3.1 Procedure to Switch Clock Source From On-chip Oscillator

to Main Clock upadated

Protection

60 •Description partially modified

Interrupt

76 ______

•9.6 INT Interrupt Description partially added

REVISION HISTORY M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual

Rev. Date Description

Page Summary

C-2

77 ______

•9.7 NMI Interrupt Description partially added

78 •Table 9.9.1 Value of the PC that is saved to the stack area when an address

match interrupt request is accepted modified, note 1 added

Watchdog Timer

- •Section of Cold Start/Warm Start deleted

80 •Description partially added

•Figure 10.1 Watchdog Timer Block Diagram partially modified

81 •Figure 10.2 WDC Register and WDTS Register notes deleted, WDC5 bit de-

leted

•10.1 Count source protective mode description partially added

Timer

108 •Description about A/D trigger mode modified

•Figure 12.2.1 Timber B Block Diagram A/D trigger mode added

115 •12.2.4 A/D Trigger Mode Description modified

121 •Figure 12.3.4 IDB0 Register, IDB1 Register, DTT Register, and ICTB2 Regis-

ter modified

123 •Figure 12.3.6 TB2SC Register modified, note 4 added

131 •Figure 12.3.2.2 TPRC Register bit map modified

Serial I/O

133 •Figure 13.1.1 Block Diagram of UARTi (i = 0 to 2) PLL clock added

136 •Figure 13.1.4 U0TB to U2TB Registers, U0RB to U2RB Registers, U0BRG to

U2BRG Registers modified, note 3 for UiBRG added

138 •Figure 13.1.6 U0C0 to U2C0 Registers Note 2 modified, note 7 added

139 •Figure 13.1.7 PACR Register note 1 modified

142 •Table 13.1.1.1 Clock Synchronous Serial I/O Mode Specification note 2 modi-

fied

145 •Figure 13.1.1.1 Typical Transmit/Receive Timings in Clock Synchronous

Serial I/O Mode partially modified

150 •Table 13.1.2.1 UART Mode Specifications Note 1 modified

154 •Figure 13.1.2.2 Receive Operation Figure modified

158 •Table 13.1.3.1 I2C bus Mode Specifications note 2 modified

168 •Table 13.1.4.1 Special Mode 2 Specifications note 2 modified

175 •Table 13.1.6.1 SIM Mode Specifications note 1 modified

177 •Figure 13.1.6.1 Transmit and Receive Timing in SIM Mode timing modified

A/D Converter

180 •Table 14.1 A/D Converter Performance note 2 partially added

183 •Table 14.2 A/D Conversion Frequency Select note 1 partially added

205 •Table 14.1.8.1 Delayed Trigger Mode 1 Specifications note 1 modified

212 •Figure 14.5.1 Analog Input Pin and External Sensor Equivalent Circuit note

REVISION HISTORY M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual

Rev. Date Description

Page Summary

C-3

1 added

CRC Calculation Circuit

213 •15.1 CRC Snoop Description partially modified

214 •Figure 15.2 CRCSAR Register note 1 added

Programable I/O Ports

216 •16.3 Pull-up Control Register 0 to Pull-up Control Register 2 description

modified

217 •16.6 Digital Debounce function equation modified

218 - 221 •Figure 16.1 I/O Ports (1) to 16.4 I/O Ports (4) modified

227 •Figure 16.6.1 NDDR and P17DDR Registers equation modified, note 2 modi-

fied

Flash Memory Version

231 •17.1.1 Boot Mode newly added

232 •17.2 Memory Map partially deleted

235 •17.3.1 ROM Code Protect Function description modified

236 •Figure 17.3.1.1 ROMCP Address modified

237 •Table 17.4.1 EW0 Mode and EW1 Mode note 2 mark deleted

239 •17.5.1 Flash Memory Control Register 0 Description about low power con-

sumption mode or on-chip oscillator low-power consumption mode is entered

partially modified

240 •17.5.2 Flash Memory Control Register 1 Description about FMR17 bit modified

241 •Figure 17.5.1 FMR0 Register note 3 modified, FMR1 Register: bit map modi-

fied

242 •Figure 17.5.2 FMR4 Register note 2 modified

243 •Figure 17.5.1.2 Setting and Resetting of EW1 Mode note for single-chip mode

deleted, note 3 for FMR11 bit added

Electrical Characteristics

261 •Table 18.1 Absolute Maximum Ratings Rated value modifed, note 1 added

262 •Table 18.2 Recommended Operating Conditions value partially added, fig-

ures in note 4 partially added

263 •Table 18.3 A/D Conversion Characteristics note 4 modified

264 •Table 18.4 and Table 18.5 Flash Memory Version Electrical Characteristic

note 4 partially added, note 6 and note 7 modified

265 •Table 18.6 Voltage Detection Circuit Electrical Characteristics conditions modi-

fied

•Figure for td(P-R) and td(ROC) modified

267 •Table 18.9 eElectrical Characteristics (2) flash memory’s value for M16C/26B

added, note 5 deleted

274 •Table 18.24 Electrical Characteristics (2) note 5 deleted

REVISION HISTORY M16C/26A Group (M16C/26A, M16C/26B, M16C/26T) Hardware Manual

Rev. Date Description

Page Summary

C-4

283 •Tables 18.41 and 18.42 Flash Memory Version Electrical Characteristics note

4 , note 10, note 11 modified

284 •Figure for td(P-R) and td(ROC) modified

286 •Table 18.45 Electrical Characteristics note 4 deleted

293 •Table 18.60 Electrical Characteristics (2) note 4 deleted

Usage Notes

299 •19.1.3 Register Setting newly added

306 •19.5.6 Rewrite the Interrupt Control Register Example 1 modified

312 •19.7.3 Three-phase Motor Control Timer Function newly added

315 •19.9 A/D Converter Description of section 6 modified

319 •19.12.1 Internal ROM Area description partially added

321 •19.13.9 Interrupts description of EW1 Mode modified, note on watchdog timer

interrupts deleted

•19.13.10 How to Access description modified

Appendix 2. functional Difference

326 •Appendix 2.1 Differences between M16C/26A and M16C/26T description on

cold start/warm start detection function deleted

RENESAS 16-BIT CMOS SINGLE-CHIP MICROCOMPUTER

HARDWARE MANUAL

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)

Publication Date: Rev.1.00 Mar.15, 2005

Rev.2.00 Feb.15, 2007

Published by: Sales Strategic Planning Div.

Renesas Technology Corp.

M16C/26A Group (M16C/26A, M16C/26B, M16C/26T)

Hardware Manual

2-6-2, Ote-machi, Chiyoda-ku, Tokyo,1 00-0004, Japan