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availability and additional information.
MOS INTEGRATED CIRCUIT
µ
µµ
µ
PD45128441, 45128841, 45128163
128M-bit Synchronous DRAM
4-bank, LVTTL
DATA SHEET
Document No. E0031N30 (Ver. 3.0)
Date Published August 2001 CP (K)
Printed in Japan Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
Description
The
µ
PD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access
memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
Features
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0(A13) and BA1(A12)
• Byte control (×16) by LDQM and UDQM
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• ×4, ×8, ×16 organization
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64 ms
• Burst termination by Burst stop command and Precharge command
Data Sheet E0031N30
2
µ
µµ
µ
PD45128441, 45128841, 45128163
Ordering Information
Part number Organization
(word × bit × bank)
Clock frequency
MHz (MAX.) Package
µ
PD45128441G5-A75A-9JF 8M
× 4 × 4 133 54-pin Plastic TSOP (II)
µ
PD45128441G5-A75-9JF
133 (10.16mm (400))
µ
PD45128441G5-A80-9JF 125
µ
PD45128441G5-A10-9JF 100
µ
PD45128841G5-A75A-9JF 4M × 8 × 4 133
µ
PD45128841G5-A75-9JF
133
µ
PD45128841G5-A80-9JF 125
µ
PD45128841G5-A10-9JF 100
µ
PD45128163G5-A75A-9JF 2M × 16 × 4 133
µ
PD45128163G5-A75-9JF
133
µ
PD45128163G5-A80-9JF 125
µ
PD45128163G5-A10-9JF 100
µ
PD45128441G5-A75L-9JF 8M
× 4 × 4 133
µ
PD45128441G5-A80L-9JF 125
µ
PD45128841G5-A75L-9JF 4M
× 8 × 4 133
µ
PD45128841G5-A80L-9JF 125
µ
PD45128163G5-A75L-9JF 2M
× 16 × 4 133
µ
PD45128163G5-A80L-9JF 125
Data Sheet E0031N30 3
µ
µµ
µ
PD45128441, 45128841, 45128163
Part Number
µ
PD45128841G5 - A75L
Interface
1 : LVTTL
Number of banks
4 : 4 banks
Organization
4 : x4
8 : x8
Memory density
128 : 128M bits
Synchronous DRAM
NEC Memory
Package
G5 : TSOP (II)
Low voltage
A : 3.3 V
±
0.3 V
Minimum cycle time
75A : 7.5 ns (133 MHz @CL=2)
75 : 7.5 ns (133 MHz @CL=3)
80 : 8 ns (125 MHz)
10 : 10 ns (100 MHz)
Low Power
[ x4, x8 ]
163
[ x16 ]
Number of banks
and Interface
3 : 4 banks, LVTTL
Organization
16 : x16
Data Sheet E0031N30
4
µ
µµ
µ
PD45128441, 45128841, 45128163
Pin Configurations
/xxx indicates active low signal.
[
µ
µµ
µ
PD45128441]
54-pin Plastic TSOP (II) (10.16mm (400))
8M words ×
××
× 4 bits ×
××
× 4 banks
V
CC
NC
V
CC
Q
NC
DQ0
V
SS
Q
NC
NC
V
CC
Q
NC
DQ1
V
SS
Q
NC
V
CC
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A0
A1
A2
A3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
Vss
NC
VssQ
NC
DQ3
VccQ
NC
NC
VssQ
NC
DQ2
VccQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
A0 to A11 Note : Address inputs
BA0(A13), BA1(A12) : Bank select
DQ0 to DQ3 : Data inputs / outputs
CLK : Clock input
CKE : Clock enable
/CS : Chip select
/RAS : Row address strobe
/CAS : Column address strobe
/WE : Write enable
DQM : DQ mask enable
VCC : Supply voltage
VSS : Ground
VCCQ : Supply voltage for DQ
VSSQ : Ground for DQ
NC : No connection
Note A0 to A11 : Row address inputs
A0 to A9, A11 : Column address inputs
Data Sheet E0031N30 5
µ
µµ
µ
PD45128441, 45128841, 45128163
[
µ
µµ
µ
PD45128841]
54-pin Plastic TSOP (II) (10.16mm (400))
4M words ×
××
× 8 bits ×
××
× 4 banks
V
CC
DQ0
V
CC
Q
NC
DQ1
V
SS
Q
NC
DQ2
V
CC
Q
NC
DQ3
V
SS
Q
NC
V
CC
NC
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A0
A1
A2
A3
V
CC
Vss
DQ7
VssQ
NC
DQ6
VccQ
NC
DQ5
VssQ
NC
DQ4
VccQ
NC
Vss
NC
DQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
A0 to A11 Note : Address inputs
BA0(A13), BA1(A12) : Bank select
DQ0 to DQ7 : Data inputs / outputs
CLK : Clock input
CKE : Clock enable
/CS : Chip select
/RAS : Row address strobe
/CAS : Column address strobe
/WE : Write enable
DQM : DQ mask enable
VCC : Supply voltage
VSS : Ground
VCCQ : Supply voltage for DQ
VSSQ : Ground for DQ
NC : No connection
Note A0 to A11 : Row address inputs
A0 to A9 : Column address inputs
Data Sheet E0031N30
6
µ
µµ
µ
PD45128441, 45128841, 45128163
[
µ
µµ
µ
PD45128163]
54-pin Plastic TSOP (II) (10.16mm (400))
2M words ×
××
× 16 bits ×
××
× 4 banks
V
CC
DQ0
V
CC
Q
DQ1
DQ2
V
SS
Q
DQ3
DQ4
V
CC
Q
DQ5
DQ6
V
SS
Q
DQ7
V
CC
LDQM
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A0
A1
A2
A3
V
CC
Vss
DQ15
VssQ
DQ14
DQ13
VccQ
DQ12
DQ11
VssQ
DQ10
DQ9
VccQ
DQ8
Vss
NC
UDQM
CLK
CKE
NC
A11
A9
A8
A7
A6
A5
A4
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
A0 to A11 Note : Address inputs
BA0(A13), BA1(A12) : Bank select
DQ0 to DQ15 : Data inputs / outputs
CLK : Clock input
CKE : Clock enable
/CS : Chip select
/RAS : Row address strobe
/CAS : Column address strobe
/WE : Write enable
LDQM : Lower DQ mask enable
UDQM : Upper DQ mask enable
VCC : Supply voltage
VSS : Ground
VCCQ : Supply voltage for DQ
VSSQ : Ground for DQ
NC : No connection
Note A0 to A11 : Row address inputs
A0 to A8 : Column address inputs
Data Sheet E0031N30 7
µ
µµ
µ
PD45128441, 45128841, 45128163
Block Diagram
Clock
Generator
Mode
Register
Command Decoder
Control Logic
Row
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Burst
Counter Data Control Circuit
Latch Circuit
Input & Output
Buffer
DQ
DQM
CLK
CKE
Address
/CS
/RAS
/CAS
/WE
Bank D
Bank C
Bank B
Sense Amplifier
Column Decoder &
Latch Circuit
Bank A
Row Decoder
Data Sheet E0031N30
8
µ
µµ
µ
PD45128441, 45128841, 45128163
CONTENTS
1. Input / Output Pin Function ........................................................................................................... 10
2. Commands ...................................................................................................................................... 11
3. Simplified State Diagram ............................................................................................................... 14
4. Truth Table ...................................................................................................................................... 15
4.1 Command Truth Table ............................................................................................................................ 15
4.2 DQM Truth Table ..................................................................................................................................... 15
4.3 CKE Truth Table ...................................................................................................................................... 15
4.4 Operative Command Table .................................................................................................................... 16
4.5 Command Truth Table for CKE ............................................................................................................. 19
5. Initialization .................................................................................................................................... 20
6. Programming the Mode Register ................................................................................................. 21
7. Mode Register ................................................................................................................................ 22
7.1 Burst Length and Sequence .................................................................................................................. 23
8. Address Bits of Bank-Select and Precharge ............................................................................... 24
9. Precharge ........................................................................................................................................ 25
10. Auto Precharge ............................................................................................................................... 26
10.1 Read with Auto Precharge .................................................................................................................. 26
10.2 Write with Auto Precharge .................................................................................................................. 27
11. Read / Write Command Interval .................................................................................................... 28
11.1 Read to Read Command Interval ....................................................................................................... 28
11.2 Write to Write Command Interval ....................................................................................................... 28
11.3 Write to Read Command Interval ....................................................................................................... 29
11.4 Read to Write Command Interval ....................................................................................................... 30
12. Burst Termination .......................................................................................................................... 31
12.1 Burst Stop Command .......................................................................................................................... 31
12.2 Precharge Termination ....................................................................................................................... 32
12.2.1 Precharge Termination in READ Cycle ................................................................................... 32
12.2.2 Precharge Termination in WRITE Cycle ................................................................................. 33
Data Sheet E0031N30 9
µ
µµ
µ
PD45128441, 45128841, 45128163
13. Electrical Specifications ................................................................................................................ 34
13.1 AC Parameters for Read Timing ......................................................................................................... 39
13.2 AC Parameters for Write Timing ........................................................................................................ 41
13.3 Relationship between Frequency and Latency ................................................................................. 42
13.4 Mode Register Set ............................................................................................................................... 43
13.5 Power on Sequence and CBR (Auto) Refresh .................................................................................. 44
13.6 /CS Function ........................................................................................................................................ 45
13.7 Clock Suspension during Burst Read (using CKE Function) ......................................................... 46
13.8 Clock Suspension during Burst Write (using CKE Function) ......................................................... 48
13.9 Power Down Mode and Clock Mask .................................................................................................. 50
13.10 CBR (Auto) Refresh ............................................................................................................................. 51
13.11 Self Refresh (Entry and Exit) .............................................................................................................. 52
13.12 Random Column Read (Page with Same Bank) ............................................................................... 53
13.13 Random Column Write (Page with Same Bank) ............................................................................... 55
13.14 Random Row Read (Ping-Pong Banks) ............................................................................................. 57
13.15 Random Row Write (Ping-Pong Banks) ............................................................................................ 59
13.16 Read and Write .................................................................................................................................... 61
13.17 Interleaved Column Read Cycle ......................................................................................................... 63
13.18 Interleaved Column Write Cycle ......................................................................................................... 65
13.19 Auto Precharge after Read Burst ....................................................................................................... 67
13.20 Auto Precharge after Write Burst ....................................................................................................... 69
13.21 Full Page Read Cycle .......................................................................................................................... 71
13.22 Full Page Write Cycle .......................................................................................................................... 73
13.23 Byte Write Operation ........................................................................................................................... 75
13.24 Burst Read and Single Write (Option) ............................................................................................... 77
13.25 Full Page Random Column Read ....................................................................................................... 79
13.26 Full Page Random Column Write ....................................................................................................... 81
13.27 PRE (Precharge) Termination of Burst .............................................................................................. 83
14. Package Drawing ........................................................................................................................... 85
15. Recommended Soldering Conditions .......................................................................................... 86
16. Revision History ............................................................................................................................. 87
Data Sheet E0031N30
10
µ
µµ
µ
PD45128441, 45128841, 45128163
1. Input / Output Pin Function
Pin name Input / Output Function
CLK Input CLK is the master clock input. Other inputs signals are referenced to the CLK rising
edge.
CKE Input CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge
is valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock is not
issued and the
µ
PD45128xxx suspends operation.
When the
µ
PD45128xxx is not in burst mode and CKE is negated, the device enters
power down mode. During power down mode, CKE must remain low.
/CS Input /CS low starts the command input cycle. When /CS is high, commands are ignored but
operations continue.
/RAS, /CAS, /WE Input /RAS, /CAS and /WE have the same symbols on conventional DRAM but different
functions. For details, refer to the command table.
A0 - A11 Input Row Address is determined by A0 - A11 at the CLK (clock) rising edge in the active
command cycle. It does not depend on the bit organization.
Column Address is determined by A0 - A9, A11 at the CLK rising edge in the read or
write command cycle. It depends on the bit organization: A0 - A9, A11 for ×4 device, A0
- A9 for ×8 device, A0 - A8 for ×16 device.
A10 defines the precharge mode. When A10 is high in the precharge command cycle,
all banks are precharged; when A10 is low, only the bank selected by BA0(A13) and
BA1(A12) is precharged.
When A10 is high in read or write command cycle, the precharge starts automatically
after the burst access.
BA0, BA1 Input BA0(A13) and BA1(A12) are the bank select signal. In command cycle, BA0(A13) and
BA1(A12) low select bank A, BA0(A13) high and BA1(A12) low select bank B, BA0(A13)
low and BA1(A12) high select bank C and then BA0(A13) and BA1(A12) high select
bank D.
DQM, UDQM, LDQM Input DQM controls I/O buffers. In ×16 products, UDQM and LDQM control upper byte and
lower byte I/O buffers, respectively.
In read mode, DQM controls the output buffers like a conventional /OE pin.
DQM high and DQM low turn the output buffers off and on, respectively.
The DQM latency for the read is two clocks.
In write mode, DQM controls the word mask. Input data is written to the memory cell if
DQM is low but not if DQM is high.
The DQM latency for the write is zero.
DQ0 - DQ15 Input / Output DQ pins have the same function as I/O pins on a conventional DRAM.
VCC, VSS, VCCQ, VSSQ (Power supply) VCC and VSS are power supply pins for internal circuits. VCCQ and VSSQ are power
supply pins for the output buffers.
Data Sheet E0031N30 11
µ
µµ
µ
PD45128441, 45128841, 45128163
2. Commands
Mode register set command
(/CS, /RAS, /CAS, /WE = Low)
The
µ
PD45128xxx has a mode register that defines how the device
operates. In this command, A0 through A11, BA0(A13) and BA1(A12)
are the data input pins. After power on, the mode register set
command must be executed to initialize the device.
The mode register can be set only when all banks are in idle state.
During 2 CLK (tRSC) following this command, the
µ
PD45128xx
x
cannot accept any other commands.
Fig.1 Mode register set command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0(A13), BA1(A12)
Activate command
(/CS, /RAS = Low, /CAS, /WE = High)
The
µ
PD45128xxx has four banks, each with 4,096 rows.
This command activates the bank selected by BA0(A13) and
BA1(A12) and a row address selected by A0 through A11.
This command corresponds to a conventional DRAM’s /RAS falling.
Fig.2 Row address strobe and
bank activate command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0(A13), BA1(A12)
Row
Row
Precharge command
(/CS, /RAS, /WE = Low, /CAS = High)
This command begins precharge operation of the bank selected by
BA0(A13) and BA1(A12). When A10 is High, all banks are
precharged, regardless of BA0(A13) and BA1(A12). When A10 is
Low, only the bank selected by BA0(A13) and BA1(A12) is
precharged.
After this command, the
µ
PD45128xxx can’t accept the activate
command to the precharging bank during tRP (precharge to activate
command period).
This command corresponds to a conventional DRAM’s /RAS rising.
Fig.3 Precharge command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0(A13), BA1(A12)
(Precharge select)
Data Sheet E0031N30
12
µ
µµ
µ
PD45128441, 45128841, 45128163
Write command
(/CS, /CAS, /WE = Low, /RAS = High)
If the mode register is in the burst write mode, this command sets the
burst start address given by the column address to begin the burst
write operation. The first write data in burst mode can input with this
command with subsequent data on following clocks.
Fig.4 Column address and write command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0(A13), BA1(A12)
Col.
Read command
(/CS, /CAS = Low, /RAS, /WE = High)
Read data is available after /CAS latency requirements have been
met. This command sets the burst start address given by the column
address.
Fig.5 Column address and read command
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0(A13), BA1(A12)
Col.
CBR (auto) refresh command
(/CS, /RAS, /CAS = Low, /WE, CKE = High)
This command is a request to begin the CBR (auto) refresh
operation. The refresh address is generated internally.
Before executing CBR (auto) refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and
ready for a row activate command.
During tRC period (from refresh command to refresh or activate
command), the
µ
PD45128xxx cannot accept any other command.
Fig.6 CBR (auto) refresh command
Add
A10
BA0(A13), BA1(A12)
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Data Sheet E0031N30 13
µ
µµ
µ
PD45128441, 45128841, 45128163
Self refresh entry command
(/CS, /RAS, /CAS, CKE = Low, /WE = High)
After the command execution, self refresh operation continues while
CKE remains low. When CKE goes high, the
µ
PD45128xxx exits the
self refresh mode.
During self refresh mode, refresh interval and refresh operation are
performed internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
Fig.7 Self refresh entry command
/WE
/CAS
/RAS
/CS
CKE
CLK
Add
A10
BA0(A13), BA1(A12)
Burst stop command
(/CS, /WE = Low, /RAS, /CAS = High)
This command can stop the current burst operation.
Fig.8 Burst stop command in Full Page
Mode
/WE
/CAS
/RAS
/CS
CKE
CLK
Add
A10
BA0(A13), BA1(A12)
H
No operation
(/CS = Low, /RAS, /CAS, /WE = High)
This command is not an execution command. No operations begin
or terminate by this command.
Fig.9 No operation
/WE
/CAS
/RAS
/CS
CKE
CLK
H
Add
A10
BA0(A13), BA1(A12)
Data Sheet E0031N30
14
µ
µµ
µ
PD45128441, 45128841, 45128163
3. Simplified State Diagram
CKE
CKE
CKE
CKE
CKE
CKE
CKE
CKE
Precharge
Auto precharge
PRE
Read with
Auto precharge
Read
BST
BST
PRE (Precharge termination)
PRE (Precharge termination)
ACT
MRS REF
CKE
CKE
SELF
SELF exit
IDLE
Mode
Register
Set
CBR (Auto)
Refresh
ROW
ACTIVE
Self
Refresh
Power
Down
Active
Power
Down
Precharge
READ
READA
READ
SUSPEND
READA
SUSPEND
WRITE
WRITEA
WRITE
SUSPEND
WRITEA
SUSPEND
POWER
ON
Write Read
Automatic sequence
Manual input
CKE
CKE
Read
Write
Write with
Write
Data Sheet E0031N30 15
µ
µµ
µ
PD45128441, 45128841, 45128163
4. Truth Table
4.1 Command Truth Table
Function Symbol CKE /CS /RAS /CAS /WE BA1, A10 A11,
n – 1 n BA0 A9 - A0
Device deselect DESL H × H × × × × × ×
No operation NOP H × L H H H × × ×
Burst stop BST H × L H H L × × ×
Read READ H × L H L H V L V
Read with auto precharge READA H × L H L H V H V
Write WRIT H × L H L L V L V
Write with auto precharge WRITA H × L H L L V H V
Bank activate ACT H × L L H H V V V
Precharge select bank PRE H × L L H L V L ×
Precharge all banks PALL H × L L H L × H ×
Mode register set MRS H × L L L L L L V
Remark H = High level, L = Low level, × = High or Low level (Don't care), V = Valid data input
4.2 DQM Truth Table
Function Symbol CKE DQM
n – 1 n U L
Data write / output enable ENB H × L
Data mask / output disable MASK H × H
Upper byte write enable / output enable ENBU H × L ×
Lower byte write enable / output enable ENBL H × × L
Upper byte write inhibit / output disable MASKU H × H ×
Lower byte write inhibit / output disable MASKL H × × H
Remark H = High level, L = Low level, × = High or Low level (Don't care)
4.3 CKE Truth Table
Current state Function Symbol CKE /CS /RAS /CAS /WE Address
n – 1 n
Activating Clock suspend mode entry H L × × × × ×
Any Clock suspend mode L L × × × × ×
Clock suspend Clock suspend mode exit L H × × × × ×
Idle CBR (auto) refresh command REF H H L L L H ×
Idle Self refresh entry SELF H L L L L H ×
Self refresh Self refresh exit L H L H H H ×
L H H × × × ×
Idle Power down entry H L × × × × ×
Power down Power down exit L H H × × × ×
L H L H H H ×
Remark H = High level, L = Low level, × = High or Low level (Don't care)
Data Sheet E0031N30
16
µ
µµ
µ
PD45128441, 45128841, 45128163
4.4 Operative Command Table Note1 (1/3)
Current state /CS /RAS /CAS /WE Address Command Action Notes
Idle H × × × × DESL Nop or power down 2
L H H × × NOP or BST Nop or power down 2
L H L H BA, CA, A10 READ/READA ILLEGAL 3
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3
L L H H BA, RA ACT Row activating
L L H L BA, A10 PRE/PALL Nop
L L L H
× REF/SELF CBR (auto) refresh or self refresh 4
L L L L Op-Code MRS Mode register accessing
Row active H × × × × DESL Nop
L H H × × NOP or BST Nop
L H L H BA, CA, A10 READ/READA Begin read : Determine AP 5
L H L L BA, CA, A10 WRIT/WRITA Begin write : Determine AP 5
L L H H BA, RA ACT ILLEGAL 3
L L H L BA, A10 PRE/PALL Precharge 6
L L L H
× REF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
Read H
× × × × DESL Continue burst to end → Row active
L H H H × NOP Continue burst to end → Row active
L H H L
× BST Burst stop
→ Row active
L H L H BA, CA, A10 READ/READA Terminate burst, new read : Determine AP 7
L H L L BA, CA, A10 WRIT/WRITA Terminate burst, start write : Determine AP 7, 8
L L H H BA, RA ACT ILLEGAL 3
L L H L BA, A10 PRE/PALL Terminate burst, precharging
L L L H × REF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
Write H × × × × DESL Continue burst to end → Write recovering
L H H H
× NOP Continue burst to end → Write recovering
L H H L × BST Burst stop → Row active
L H L H BA, CA, A10 READ/READA Terminate burst, start read : Determine AP 7, 8
L H L L BA, CA, A10 WRIT/WRITA Terminate burst, new write : Determine AP 7
L L H H BA, RA ACT ILLEGAL 3
L L H L BA, A10 PRE/PALL Terminate burst, precharging 9
L L L H
× REF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
Data Sheet E0031N30 17
µ
µµ
µ
PD45128441, 45128841, 45128163
(2/3)
Current state /CS /RAS /CAS /WE Address Command Action Notes
Read with auto H × × × × DESL Continue burst to end → Precharging
precharge L H H H × NOP Continue burst to end → Precharging
L H H L
× BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL 3
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3
L L H H BA, RA ACT ILLEGAL 3
L L H L BA, A10 PRE/PALL ILLEGAL 3
L L L H × REF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
Write with auto
precharge
H
×
×
×
×
DESL
Continue burst to end → Write
recovering with auto precharge
L
H
H
H
×
NOP
Continue burst to end → Write
recovering with auto precharge
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL 3
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3
L L H H BA, RA ACT ILLEGAL 3
L L H L BA, A10 PRE/PALL ILLEGAL 3
L L L H
× REF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
Precharging H
× × × × DESL Nop
→ Enter idle after tRP
L H H H × NOP Nop → Enter idle after tRP
L H H L
× BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL 3
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3
L L H H BA, RA ACT ILLEGAL 3
L L H L BA, A10 PRE/PALL Nop
→ Enter idle after tRP
L L L H × REF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
Row activating H × × × × DESL Nop → Enter bank active after tRCD
L H H H
× NOP Nop
→ Enter bank active after tRCD
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL 3
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3
L L H H BA, RA ACT ILLEGAL 3, 10
L L H L BA, A10 PRE/PALL ILLEGAL 3
L L L H
× REF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
Data Sheet E0031N30
18
µ
µµ
µ
PD45128441, 45128841, 45128163
(3/3)
Current state /CS /RAS /CAS /WE Address Command Action Notes
Write recovering H × × × × DESL Nop → Enter row active after tDPL
L H H H × NOP Nop → Enter row active after tDPL
L H H L
× BST Nop
→ Enter row active after tDPL
L H L H BA, CA, A10 READ/READA Start read, Determine AP 8
L H L L BA, CA, A10 WRIT/WRITA New write, Determine AP
L L H H BA, RA ACT ILLEGAL 3
L L H L BA, A10 PRE/PALL ILLEGAL 3
L L L H × REF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
Write recovering H × × × × DESL Nop → Enter precharge after tDPL
with auto precharge L H H H × NOP Nop
→ Enter precharge after tDPL
L H H L × BST Nop → Enter precharge after tDPL
L H L H BA, CA, A10 READ/READA ILLEGAL 3, 8
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL 3
L L H H BA, RA ACT ILLEGAL 3
L L H L BA, A10 PRE/PALL ILLEGAL
L L L H
× REF/SELF ILLEGAL
L L L L Op-Code MRS ILLEGAL
Refreshing H
× × × × DESL Nop
→ Enter idle after tRC
L H H × × NOP/BST Nop → Enter idle after tRC
L H L
× × READ/WRIT ILLEGAL
L L H × × ACT/PRE/PALL ILLEGAL
L L L × × REF/SELF/MRS ILLEGAL
Mode register H × × × × DESL Nop → Enter idle after tRSC
accessing L H H H
× NOP Nop
→ Enter idle after tRSC
L H H L × BST ILLEGAL
L H L
× × READ/WRIT ILLEGAL
L
L
×
×
×
ACT/PRE/PALL/
REF/SELF/MRS
ILLEGAL
Notes 1. All entries assume that CKE was active (High level) during the preceding clock cycle.
2. If all banks are idle, and CKE is inactive (Low level),
µ
PD45128xxx will enter Power down mode.
All input buffers except CKE will be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA),
depending on the state of that bank.
4. If all banks are idle, and CKE is inactive (Low level),
µ
PD45128xxx will enter Self refresh mode. All input
buffers except CKE will be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don't satisfy tDPL.
10. Illegal if tRRD is not satisfied.
Remark H = High level, L = Low level, × = High or Low level (Don’t care), V = Valid data
Data Sheet E0031N30 19
µ
µµ
µ
PD45128441, 45128841, 45128163
4.5 Command Truth Table for CKE
Current State CKE /CS /RAS /CAS /WE Address Action Notes
n – 1 n
Self refresh H × × × × × × INVALID, CLK (n – 1) would exit self refresh
L H H × × × × Self refresh recovery
L H L H H × × Self refresh recovery
L H L H L × × ILLEGAL
L H L L × × × ILLEGAL
L L
× × × × × Maintain self refresh
Self refresh recovery H H H × × × × Idle after tRC
H H L H H × × Idle after tRC
H H L H L × × ILLEGAL
H H L L × × × ILLEGAL
H L H
× × × × ILLEGAL
H L L H H × × ILLEGAL
H L L H L × × ILLEGAL
H L L L × × × ILLEGAL
Power down H × × × × × INVALID, CLK (n – 1) would exit power down
L H H
× × × × EXIT power down → Idle
L H L H H H × EXIT power down → Idle
L L × × × × × Maintain power down mode
All banks idle H H H × × × Refer to operations in Operative Command Table
H H L H × × Refer to operations in Operative Command Table
H H L L H × Refer to operations in Operative Command Table
H H L L L H × CBR (auto) Refresh
H H L L L L Op-Code Refer to operations in Operative Command Table
H L H
× × × Refer to operations in Operative Command Table
H L L H × × Refer to operations in Operative Command Table
H L L L H × Refer to operations in Operative Command Table
H L L L L H
× Self refresh 1
H L L L L L Op-Code Refer to operations in Operative Command Table
L
× × × × × × Power down 1
Row active H × × × × × × Refer to operations in Operative Command Table
L × × × × × × Power down 1
Any state other than H H × × × × Refer to operations in Operative Command Table
listed above H L × × × × × Begin clock suspend next cycle 2
L H
× × × × × Exit clock suspend next cycle
L L
× × × × × Maintain clock suspend
Notes 1. Self refresh can be entered only from the all banks idle state. Power down can be entered only from all
banks idle or row active state.
2.
Must be legal command as defined in Operative Command Table.
Remark H = High level, L = Low level, × = High or Low level (Don't care)
Data Sheet E0031N30
20
µ
µµ
µ
PD45128441, 45128841, 45128163
5. Initialization
The synchronous DRAM is initialized in the power-on sequence according to the following.
(1) To stabilize internal circuits, when power is applied, a 100
µ
s or longer pause must precede any signal toggling.
(2) After the pause, all banks must be precharged using the Precharge command (The Precharge all banks
command is convenient).
(3) Once the precharge is completed and the minimum tRP is satisfied, the mode register can be programmed.
After the mode register set cycle, tRSC (2 CLK minimum) pause must be satisfied as well.
(4) Two or more CBR (Auto) refresh must be performed.
Remarks 1. The sequence of Mode register programming and Refresh above may be transposed.
2. CKE and DQM must be held high until the Precharge command is issued to ensure data-bus Hi-Z.
Data Sheet E0031N30 21
µ
µµ
µ
PD45128441, 45128841, 45128163
6. Programming the Mode Register
The mode register is programmed by the Mode register set command using address bits A11 through A0, BA0(A13)
and BA1(A12) as data inputs. The register retains data until it is reprogrammed or the device loses power.
The mode register has four fields;
Options : A11 through A7, BA0(A13), BA1(A12)
/CAS latency : A6 through A4
Wrap type : A3
Burst length : A2 through A0
Following mode register programming, no command can be issued before at least 2 CLK have elapsed.
/CAS Latency
/CAS latency is the most critical of the parameters being set. It tells the device how many clocks must elapse
before the data will be available.
The value is determined by the frequency of the clock and the speed grade of the device. 13.3 Relationship
between Frequency and Latency shows the relationship of /CAS latency to the clock period and the speed grade of
the device.
Burst Length
Burst Length is the number of words that will be output or input in a read or write cycle. After a read burst is
completed, the output bus will become Hi-Z.
The burst length is programmable as 1, 2, 4, 8 or full page.
Wrap Type (Burst Sequence)
The wrap type specifies the order in which the burst data will be addressed. This order is programmable as either
“Sequential” or “Interleave”. The method chosen will depend on the type of CPU in the system.
Some microprocessor cache systems are optimized for sequential addressing and others for interleaved
addressing. 7.1 Burst Length and Sequence shows the addressing sequence for each burst length using them.
Both sequences support bursts of 1, 2, 4 and 8. Additionally, sequence supports the full page length.
Data Sheet E0031N30
22
µ
µµ
µ
PD45128441, 45128841, 45128163
7. Mode Register
WT = 1
1
2
4
8
R
R
R
R
10000 JEDEC Standard Test Set (refresh counter test)
BLWTLTMODE001xx Burst Read and Single Write
(for Write Through Cache)
01 Use in future
VVVVVV1V1xxx Vender Specific
BLWTLTMODE00000 Mode Register Set
V = Valid
x = Don’t care
WT = 0
1
2
4
8
R
R
R
Full page
Bits2-0
000
001
010
011
100
101
110
111
Burst length
Sequential
Interleave
0
1
Wrap type
/CAS latency
R
R
2
3
R
R
R
R
Bits6-4
000
001
010
011
100
101
110
111
Latency
mode
00
A0A1A2A3A4A5A7 A6A8A9A10A11
BA1
(A12)
BA0
(A13)
A0A1A2A3A4A5A7 A6A8A9A10A11
BA1
(A12)
BA0
(A13)
A0A1A2A3A4A5A7 A6A8A9A10A11
BA1
(A12)
BA0
(A13)
A0A1A2A3A4A5A7 A6A8A9A10A11
BA1
(A12)
BA0
(A13)
A0A1A2A3A4A5A7 A6A8A9A10A11
BA1
(A12)
BA0
(A13)
xx
xx
00
Remark R : Reserved
CLK
CKE
/CS
/RAS
/CAS
/WE
A0 - A11,
BA0(13), BA1(A12)
Mode Register Set
Mode Register Set Timing
Data Sheet E0031N30 23
µ
µµ
µ
PD45128441, 45128841, 45128163
7.1 Burst Length and Sequence
[Burst of Two]
Starting address
(column address A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
0 0, 1 0, 1
1 1, 0 1, 0
[Burst of Four]
Starting address
(column address A1 - A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
00 0, 1, 2, 3 0, 1, 2, 3
01 1, 2, 3, 0 1, 0, 3, 2
10 2, 3, 0, 1 2, 3, 0, 1
11 3, 0, 1, 2 3, 2, 1, 0
[Burst of Eight]
Starting address
(column address A2 - A0, binary)
Sequential addressing sequence
(decimal)
Interleave addressing sequence
(decimal)
000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7
001 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6
010 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5
011 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4
100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3
101 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2
110 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1
111 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0
Full page burst is an extension of the above tables of sequential addressing, with the length being 2,048 (for 32M ×4
device), 1,024 (for 16M ×8 device), and 512 (for 8M ×16 device).
Data Sheet E0031N30
24
µ
µµ
µ
PD45128441, 45128841, 45128163
8. Address Bits of Bank-Select and Precharge
A11A10A9A8A7A6A4 A5A3A2A1A0Row
(Activate command)
A11A10A9A8A7A6A4 A5A3A2A1A0
(Precharge command)
disables Auto-Precharge
(End of Burst)
0
enables Auto-Precharge
(End of Burst)
1
xA10A9A8A7A6A4 A5A3A2A1A0Col.
(/CAS strobes)
x : Don’t care
Select Bank A
“Activate” command
0
Select Bank B
“Activate” command
0
1
1
0
1
0
1
BA1(A12) BA0(A13)
BA1(A12) BA0(A13)
BA1(A12) BA0(A13)
Result
Select Bank C
“Activate” command
Select Bank D
“Activate” command
enables Read/Write
commands for Bank A
0
enables Read/Write
commands for Bank B
0
1
1
0
1
0
1
Result
enables Read/Write
commands for Bank C
enables Read/Write
commands for Bank D
Result
Precharge Bank A
Precharge Bank B
Precharge Bank C
Precharge Bank D
Precharge All Banks
A10
0
0
0
0
1
0
0
1
1
x
0
1
0
1
x
BA1
(A12)
BA0
(A13)
BA1
(A12)
BA0
(A13)
BA1
(A12)
BA0
(A13)
Data Sheet E0031N30 25
µ
µµ
µ
PD45128441, 45128841, 45128163
9. Precharge
The precharge command can be issued anytime after tRAS (MIN.) is satisfied.
Soon after the precharge command is issued, precharge operation performed and the synchronous DRAM enters
the idle state after tRP is satisfied. The parameter tRP is the time required to perform the precharge.
The earliest timing in a read cycle that a precharge command can be issued without losing any data in the burst is
as follows.
It is depending on the /CAS latency and clock cycle time.
T0 T1 T2 T3 T4 T5 T6 T7
Burst length=4
READ
READ
Q1 Q2 Q3 Q4
PRE
Hi-Z
Q1 Q2 Q3 Q4
PRE
Hi-Z
(t
RAS
must be satisfied)
CLK
Command
/CAS latency = 2
DQ
Command
/CAS latency = 3
DQ
T8
In order to write all data to the memory cell correctly, the asynchronous parameter “tDPL” must be satisfied. The tDPL
(MIN.) specification defines the earliest time that a precharge command can be issued. Minimum number of clocks is
calculated by dividing tDPL (MIN.) with clock cycle time.
In summary, the precharge command can be issued relative to reference clock that indicates the last data word is
valid. In the following table, minus means clocks before the reference; plus means time after the reference.
/CAS latency Read Write
2 –1 +tDPL (MIN.)
3 –2 +tDPL (MIN.)
Data Sheet E0031N30
26
µ
µµ
µ
PD45128441, 45128841, 45128163
10. Auto Precharge
During a read or write command cycle, A10 controls whether auto precharge is selected. A10 high in the Read or
Write command (Read with Auto precharge command or Write with Auto precharge command), auto precharge is
selected and begins automatically.
The tRAS must be satisfied with a read with auto precharge or a write with auto precharge operation. In addition, the
next activate command to the bank being precharged cannot be executed until the precharge cycle ends.
In read cycle, once auto precharge has started, an activate command to the bank can be issued after tRP has been
satisfied.
In write cycle, the tDAL must be satisfied to issue the next activate command to the bank being precharged.
The timing that begins the auto precharge cycle depends on both the /CAS latency programmed into the mode
register and whether read or write cycle.
10.1 Read with Auto Precharge
During a read cycle, the auto precharge begins one clock earlier (/CAS latency of 2) or two clocks earlier (/CAS
latency of 3) the last data word output.
QB1 QB2 QB3 QB4
Auto precharge starts
READA B
Hi-Z
QB1 QB2 QB3 QB4
Auto precharge starts
READA B
Hi-Z
DQ
Command
DQ
Command
/CAS latency = 2
/CAS latency = 3
CLK
T0 T2T1 T3 T4 T5 T6 T7 T8
Burst length = 4
(tRAS must be satisfied)
T9
Remark READA means Read with Auto precharge
Data Sheet E0031N30 27
µ
µµ
µ
PD45128441, 45128841, 45128163
10.2 Write with Auto Precharge
During a write cycle, the auto precharge starts at the timing that is equal to the value of the tDPL (MIN.) after the last
data word input to the device.
DB1 DB2 DB3 DB4
Auto precharge starts
WRITA B
Hi-Z
DB1 DB2 DB3 DB4
Auto precharge starts
WRITA B
Hi-Z
DQ
Command
DQ
Command
/CAS latency = 2
/CAS latency = 3
CLK
T0 T2T1 T3 T4 T5 T6 T7 T8
Burst length = 4
(tRAS must be satisfied)
tDPL(MIN.)
tDPL(MIN.)
Remark WRITA means Write with Auto Precharge
In summary, the auto precharge begins relative to a reference clock that indicates the last data word is valid.
In the table below, minus means clocks before the reference; plus means after the reference.
/CAS latency Read Write
2 –1 +tDPL (MIN.)
3 –2 +tDPL (MIN.)
Data Sheet E0031N30
28
µ
µµ
µ
PD45128441, 45128841, 45128163
11. Read / Write Command Interval
11.1 Read to Read Command Interval
During a read cycle, when new Read command is issued, it will be effective after /CAS latency, even if the previous
read operation does not completed. READ will be interrupted by another READ.
The interval between the commands is 1 cycle minimum. Each Read command can be issued in every clock
without any restriction.
QB1 QB2 QB3 QB4 Hi-Z
READ A
DQ
Command
CLK
T0 T2T1 T3 T4 T5 T6 T7 T8
Burst length = 4, /CAS latency = 2
READ B
QA1
1cycle
T9
11.2 Write to Write Command Interval
During a write cycle, when a new Write command is issued, the previous burst will terminate and the new burst will
begin with a new Write command. WRITE will be interrupted by another WRITE.
The interval between the commands is minimum 1 cycle. Each Write command can be issued in every clock
without any restriction.
DB1 DB2 DB3 DB4 Hi-Z
WRITE A
DQ
Command
CLK
T0 T2T1 T3 T4 T5 T6 T7 T8
Burst length = 4, /CAS latency = 2
WRITE B
DA1
1cycle
Data Sheet E0031N30 29
µ
µµ
µ
PD45128441, 45128841, 45128163
11.3 Write to Read Command Interval
Write command and Read command interval is also 1 cycle.
Only the write data before Read command will be written.
The data bus must be Hi-Z at least one cycle prior to the first DOUT.
QB1 QB2 QB3 QB4
WRITE A
Hi-Z
QB1 QB2 QB3 QB4
WRITE A
Hi-Z
DQ
Command
DQ
Command
/CAS latency = 2
/CAS latency = 3
CLK
T0 T2T1 T3 T4 T5 T6 T7 T8
Burst length = 4
DA1
DA1
READ B
READ B
Data Sheet E0031N30
30
µ
µµ
µ
PD45128441, 45128841, 45128163
11.4 Read to Write Command Interval
During a read cycle, READ can be interrupted by WRITE.
The Read and Write command interval is 1 cycle minimum. There is a restriction to avoid data conflict. The Data
bus must be Hi-Z using DQM before WRITE.
D1 D2 D3 D4
READ
DQ
Command
CLK T0 T2T1 T3 T4 T5 T6 T7 T8
Burst length = 4
WRITE
DQM
Hi-Z
1cycle
READ can be interrupted by WRITE. DQM must be High at least 3 clocks prior to the Write command.
CLK T0 T2T1 T3 T4 T5 T6 T7 T8 Burst length = 8
T9
Q1 Q2 Q3
READ
DQ
Command
D1 D2 D3
WRITE
DQM
Hi-Z is
necessary
Q1 Q2
READ
DQ
Command
D1 D2 D3
WRITE
DQM
Hi-Z is
necessary
/CAS latency = 2
/CAS latency = 3
Data Sheet E0031N30 31
µ
µµ
µ
PD45128441, 45128841, 45128163
12. Burst Termination
There are two methods to terminate a burst operation other than using a Read or a Write command. One is the
burst stop command and the other is the precharge command.
12.1 Burst Stop Command
During a read cycle, when the burst stop command is issued, the burst read data are terminated and the data bus
goes to Hi-Z after the /CAS latency from the burst stop command.
READCommand
CLK T0 T2T1 T3 T4 T5 T6 T7
Burst length = X
Q1 Q2 Q3DQ
/CAS latency = 2 Hi-Z
Q1 Q2 Q3DQ
/CAS latency = 3 Hi-Z
BST
Remark BST: Burst stop command
During a write cycle, when the burst stop command is issued, the burst write data are terminated and data bus goes
to Hi-Z at the same clock with the burst stop command.
D2 D3 D4
WRITE
DQ
Command
/CAS latency = 2, 3
CLK T0 T2T1 T3 T4 T5 T6 T7
Burst length = X
BST
Hi-Z
D1
Remark BST: Burst stop command
Data Sheet E0031N30
32
µ
µµ
µ
PD45128441, 45128841, 45128163
12.2 Precharge Termination
12.2.1 Precharge Termination in READ Cycle
During a read cycle, the burst read operation is terminated by a precharge command.
When the precharge command is issued, the burst read operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command.
To issue a precharge command, tRAS must be satisfied.
When /CAS latency is 2, the read data will remain valid until one clock after the precharge command.
READ
CLK T0 T2T1 T3 T4 T5 T6 T7
Burst length = X, /CAS latency = 2
Q1DQ
Command
Q2 Q3 Q4
ACT
t
RP
PRE
Hi-Z
(t
RAS
must be satisfied)
When /CAS latency is 3, the read data will remain valid until two clocks after the precharge command.
READ
CLK T0 T2T1 T3 T4 T5 T6 T7
Burst length = X, /CAS latency = 3
DQ
Command
Q1 Q2 Q3
ACT
tRP
PRE
Hi-Z
T8
Q4
(t
RAS
must be satisfied)
Data Sheet E0031N30 33
µ
µµ
µ
PD45128441, 45128841, 45128163
12.2.2 Precharge Termination in WRITE Cycle
During a write cycle, the burst write operation is terminated by a precharge command.
When the precharge command is issued, the burst write operation is terminated and precharge starts.
The same bank can be activated again after tRP from the precharge command.
To issue a precharge command, tRAS must be satisfied.
When /CAS latency is 2, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
WRITE
CLK T0 T2T1 T3 T4 T5 T6 T7
Burst length = X, /CAS latency = 2
DQ
Command
D1 D2 D3
ACT
DQM
t
RP
PRE
Hi-Z
D4 D5
(t
RAS
must be satisfied)
When /CAS latency is 3, the write data written prior to the precharge command will be correctly stored. However,
invalid data may be written at the same clock as the precharge command. To prevent this from happening, DQM
must be high at the same clock as the precharge command. This will mask the invalid data.
WRITE
CLK T0 T2T1 T3 T4 T5 T6 T7
Burst length = X, /CAS latency = 3
DQ
Command
D1 D2 D3
ACT
DQM
tRP
PRE
Hi-Z
D5
T8
D4
(tRAS must be satisfied)
Data Sheet E0031N30
34
µ
µµ
µ
PD45128441, 45128841, 45128163
13. Electrical Specifications
• All voltages are referenced to VSS (GND).
• After power up, wait more than 100
µ
s and then, execute Power on sequence and CBR (auto) Refresh before
proper device operation is achieved.
Absolute Maximum Ratings
Parameter Symbol Condition Rating Unit
Voltage on power supply pin relative to GND VCC, VCCQ −0.5 to +4.6 V
Voltage on any pin relative to GND VT −0.5 to +4.6 V
Short circuit output current IO 50 mA
Power dissipation PD 1 W
Operating ambient temperature TA 0 to 70 °C
Storage temperature Tstg −55 to + 125 °C
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Parameter Symbol Condition MIN. TYP. MAX. Unit
Supply voltage VCC, VCCQ 3.0 3.3 3.6 V
High level input voltage VIH 2.0 VCC+0.3Note1 V
Low level input voltage VIL −0.3Note2 +0.8 V
Operating ambient temperature TA 0 70 °C
Notes 1. V
IH (MAX.) = VCC + 1.5 V (Pulse width ≤ 5 ns)
2. V
IL (MIN.) = –1.5 V (Pulse width ≤ 5 ns)
Pin Capacitance (TA = 25 °
°°
°C, f = 1 MHz)
Parameter Symbol Condition MIN. TYP. MAX. Unit
Input capacitance CI1 CLK 2.5 3.5 pF
C
I2 A0 - A11, BA0(A13), BA1(A12), CKE,
/CS, /RAS, /CAS, /WE, DQM, UDQM,
LDQM
2.5 3.8
Data input / output capacitance CI/O DQ0 - DQ15 4 6.5 pF
Data Sheet E0031N30 35
µ
µµ
µ
PD45128441, 45128841, 45128163
DC Characteristics 1 (Recommended Operating Conditions unless otherwise noted)
Parameter Symbol Test condition /CAS Grade Maximum Unit Notes
latency ×4 ×8 ×16
Operating current ICC1 Burst length = 1, CL = 2 -A75A 110 110 120 mA 1
t
RC ≥ tRC (MIN.), Io = 0 mA, -A75 100 100 110
One bank active -A80 100 100 110
-A10 100 100 110
CL = 3 -A75A 110 110 120
-A75 105 105 115
-A80 100 100 110
-A10 100 100 110
Precharge standby current ICC2P CKE ≤ VIL (MAX.), tCK = 15 ns 1 1 1 mA
in power down mode ICC2PS CKE
≤ VIL (MAX.), tCK = ∞ 1 1 1
Precharge standby current
in non power down mode
ICC2N
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
Input signals are changed one time during 30 ns.
20 20 20 mA
ICC2NS
CKE ≥ VIH (MIN.), tCK = ∞,
Input signals are stable.
8 8 8
Active standby current ICC3P CKE ≤ VIL (MAX.), tCK = 15 ns 5 5 5 mA
in power down mode ICC3PS CKE ≤ VIL (MAX.), tCK = ∞ 4 4 4
Active standby current
in non power down mode
ICC3N
CKE ≥ VIH (MIN.), tCK = 15 ns, /CS ≥ VIH (MIN.),
Input signals are changed one time during 30 ns.
30 30 30 mA
I
CC3NS
CKE ≥ VIH (MIN.), tCK = ∞ ,
Input signals are stable.
20 20 20
Operating current ICC4 t
CK ≥ tCK (MIN.), Io = 0 mA, CL = 2 -A75A 140 155 185 mA 2
(Burst mode) All banks active -A75 105 120 145
-A80 105 120 145
-A10 85 95 110
CL = 3 -A75A 140 155 185
-A75 140 155 185
-A80 130 145 175
-A10 110 125 140
CBR (auto) refresh current ICC5 t
RC ≥ tRC (MIN.) CL = 2 -A75A 270 270 270 mA 3
-A75 230 230 230
-A80 230 230 230
-A10 230 230 230
CL = 3 -A75A 270 270 270
-A75 240 240 240
-A80 230 230 230
-A10 230 230 230
Self refresh current ICC6 CKE ≤ 0.2 V -** 2 2 2 mA
-**L 0.8 0.8 0.8 mA
Notes 1. I
CC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC1 is measured condition that addresses are changed only one time during tCK (MIN.).
2. I
CC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, ICC4 is measured condition that addresses are changed only one time during tCK (MIN.).
3. I
CC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
Data Sheet E0031N30
36
µ
µµ
µ
PD45128441, 45128841, 45128163
DC Characteristics 2 (Recommended Operating Conditions unless otherwise noted)
Parameter Symbol Test condition MIN. TYP. MAX. Unit Note
Input leakage current
II (L)
0 ≤ VI ≤ VCCQ, VCCQ = VCC
All other pins not under test = 0 V
−1.0
+1.0
µ
A
Output leakage current IO (L) 0 ≤ VO ≤ VCCQ, DOUT is disabled −1.5 +1.5
µ
A
High level output voltage VOH I
O = −4 mA 2.4 V
Low level output voltage VOL I
O = +4 mA 0.4 V
AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions
Parameter Value Unit
AC high level input voltage / low level input voltage 2.4 / 0.4 V
Input timing measurement reference level 1.4 V
Transition time (Input rise and fall time) 1 ns
Output timing measurement reference level 1.4 V
tCK
tCH tCL
2.4 V
1.4 V
0.4 V
CLK
2.4 V
1.4 V
0.4 V
Input
tSETUP tHOLD
Output
tAC
tOH
Data Sheet E0031N30 37
µ
µµ
µ
PD45128441, 45128841, 45128163
Synchronous Characteristics
Parameter Symbol -A75A -A75 -A80 -A10 Unit Note
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
Clock cycle time /CAS latency = 3 tCK3 7.5
(133 MHz) 7.5 (133 MHz) 8
(
125 MHz
)
10
(
100 MHz
)
ns
/CAS latency = 2 tCK2 7.5
(133 MHz) 10 (100 MHz) 10
(
100 MHz
)
13 (77 MHz) ns
Access time from CLK /CAS latency = 3 tAC3 5.4 5.4 6 6 ns 1
/CAS latency = 2 tAC2 5.4 6 6 7 ns 1
CLK high level width tCH 2.5 2.5 3 3 ns
CLK low level width tCL 2.5 2.5 3 3 ns
Data-out hold time tOH 3 3 3 3 ns 1
Data-out low-impedance time tLZ 0 0 0 0 ns
Data-out high-impedance time /CAS latency = 3 tHZ3 3 5.4 3 5.4 3 6 3 6 ns
/CAS latency = 2 tHZ2 3 5.4 3 6 3 6 3 7 ns
Data-in setup time tDS 1.5 1.5 2 2 ns
Data-in hold time tDH 0.8 0.8 1 1 ns
Address setup time tAS 1.5 1.5 2 2 ns
Address hold time tAH 0.8 0.8 1 1 ns
CKE setup time tCKS 1.5 1.5 2 2 ns
CKE hold time tCKH 0.8 0.8 1 1 ns
CKE setup time (Power down exit) tCKSP 1.5 1.5 2 2 ns
Command (/CS, /RAS, /CAS, /WE, DQM)
setup time
t
CMS
1.5 1.5 2 2 ns
Command (/CS, /RAS, /CAS, /WE, DQM)
hold time
t
CMH
0.8 0.8 1 1 ns
Note 1. Output load
Output Z = 50
Ω
50 pF
Data Sheet E0031N30
38
µ
µµ
µ
PD45128441, 45128841, 45128163
Asynchronous Characteristics
Parameter Symbol -A75A -A75 -A 80 -A10 Unit Note
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
ACT to REF/ACT command period (operation) tRC 60 67.5 70 70 ns
REF to REF/ACT command period (refresh) tRC1 60 67.5 70 70 ns
ACT to PRE command period tRAS 45
120,000 45 120,000 48 120,000 50 120,000 ns
PRE to ACT command period tRP 15 20 20 20 ns
Delay time ACT to READ/WRITE command tRCD 15 20 20 20 ns
ACT (one) to ACT (another) command period tRRD 15 15 16 20 ns
Data-in to PRE command period tDPL 8 8 8 10 ns
Data-in to ACT (REF)
command period
/CAS latency = 3
tDAL3
1CLK
+22.5
1CLK
+22.5
1CLK
+20
1CLK
+20
ns 1
(Auto precharge) /CAS latency = 2
tDAL2
1CLK
+20
1CLK
+20
1CLK
+20
1CLK
+20
ns
Mode register set cycle time tRSC 2 2 2 2 CLK
Transition time tT 0.5 30 0.5 30 0.5 30 1 30 ns
Refresh time (4,096 refresh cycles) tREF 64 64 64 64 ms
Note 1. The –A75A and –A75 grade device can satisfy the tDAL3 spec of 1CLK+20 ns for up to and including 125MHz
operation.
Data Sheet E0031N30 39
µ
µµ
µ
PD45128441, 45128841, 45128163
13.1 AC Parameters for Read Timing (Manual Precharge, Burst Length = 4, /CAS Latency = 3)
;
;
;
;
;
;;
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;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
t
OH
;
;
;
;
t
LZ
t
AC
t
OH
t
AC
t
AC
t
OH
;
;
;
t
OH
t
AC
t
HZ
t
RAS
t
RC
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BA0
tCKH
t
RP
;;
;;
;;
;;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
;;
;;
;;
;
;
;;
;;
;
;
;;
;;
;
;
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
t
RCD
t
CKS
t
CH
t
CL
t
CK
t
CMS
t
CMH
t
AS
t
AH
L
Hi-Z
Activate
Command
for Bank A
Precharge
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank A
Data Sheet E0031N30
40
µ
µµ
µ
PD45128441, 45128841, 45128163
tCKS
AC Parameters for Read Timing (Auto Precharge, Burst Length = 4, /CAS Latency = 3)
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;
;
;
;
tOH
;
;
;
;
;
tLZ
tAC
tOH
tAC tAC
tOH
;
;
;
tOH
tAC tHZ
tRAS
tRRD
tRC
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BA0
t
CKH
;
;
;
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13
;
;
;
;
;
;
;
;
;
;
;
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ tRCD
tCH tCL
tCK
t
CMS
t
CMH
t
AS
t
AH
L
Hi-Z
;
;
;
;
;
;
;
;
Auto Precharge
Start for Bank C
Activate
Command
for Bank C
Activate
Command
for Bank D
Read with
Auto Precharge
Command
for Bank C
Activate
Command
for Bank C
Data Sheet E0031N30 41
µ
µµ
µ
PD45128441, 45128841, 45128163
13.2 AC Parameters for Write Timing (Burst Length = 4, /CAS Latency = 3)
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;
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;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
CLK
CKE
BA0
A10
ADD
DQM
DQ Hi-Z
t
AS
t
AH
t
DS
t
DH
t
RCD
t
DAL
t
RC
t
RRD
t
RCD
t
RAS
t
RC
t
DPL
t
RP
tCKH
;
;
tCMS tCMH
t
CKS
/CS
/RAS
/CAS
/WE
;
;
;
;
;
;
;
;
;
;
;
BA1
;
;
Auto Precharge
Start for Bank C
L
;
;
Activate
Command
for Bank C
Activate
Command
for Bank B
Write
Command
for Bank B
Activate
Command
for Bank B
Write with
Auto Precharge
Command
for Bank C
Precharge
Command
for Bank B
Activate
Command
for Bank C
Data Sheet E0031N30
42
µ
µµ
µ
PD45128441, 45128841, 45128163
13.3 Relationship between Frequency and Latency
Speed version -75A -75 -80 - 10
Clock cycle time [ns] 7.5 7.5 7.5 10 8 10 10 13
Frequency [MHz] 133 133 133 100 125 100 100 77
/CAS latency 3 2 3 2 3 2 3 2
[tRCD] 2 2 3 2 3 2 2 2
/RAS latency (/CAS latency + [tRCD]) 5 4 6 4 6 4 5 4
[tRC] 8 8 9 7 9 7 7 6
[tRC1] 8 8 9 7 9 7 8 6
[tRAS] 6 6 6 5 6 5 5 4
[tRRD] 2 2 2 2 2 2 2 2
[tRP] 2 2 3 2 3 2 2 2
[tDPL] 2 2 2 1 1 1 1 1
[tDAL] 4 4 4 3 4 3 3 3
[tRSC] 2 2 2 2 2 2 2 2
Data Sheet E0031N30 43
µ
µµ
µ
PD45128441, 45128841, 45128163
13.4 Mode Register Set (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
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BA1
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
Hi-Z
ADDRESS KEY
tRP
Precharge
All Banks
Command
Mode
Register Set
Command
Activate
Command
is valid
HtRSC
2 CLK (MIN.)
Data Sheet E0031N30
44
µ
µµ
µ
PD45128441, 45128841, 45128163
13.5 Power On Sequence and CBR (Auto) Refresh
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
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;;
;
;
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;
;
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;
;
;
;
;
;
;
;
;
;
;
Hi-Z
t
RSC
ADDRESS KEY
t
RP
;
;
;
;
;
;
;
;;
;;
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;;
;
;
;
;
;
;
;
;
;
;
High level is necessary
2 refresh cycles are necessary
t
RC1
t
RC1
Precharge
All Banks
Command
is necessary
Mode
Register Set
Command
is necessary
CBR (Auto)
Refresh
Command
is necessary
Activate
Command
CBR (Auto)
Refresh
Command
is necessary
BA0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
High level is necessary
Clock cycle is necessary
Data Sheet E0031N30 45
µ
µµ
µ
PD45128441, 45128841, 45128163
13.6 /CS Function (Burst Length = 4, /CAS Latency = 3)
Only /CS signal needs to be issued at minimum rate
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
H
L
Hi-Z
L
BA0 L
RAa
QAa1 QAa2 QAa3 QAa4 DAb1 DAb2 DAb3 DAb4
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
Precharge
Command
for Bank A
RAa CAa CAb
Data Sheet E0031N30
46
µ
µµ
µ
PD45128441, 45128841, 45128163
13.7 Clock Suspension during Burst Read (using CKE Function) (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
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;
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;
QAa1 QAa2 QAa3 QAa4
CAa
;
;
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;;
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BA0
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
L
Hi-Z
RAa
RAa
Activate
Command
for Bank A
Read
Command
for Bank A
1-CLOCK
SUSPENDED 2-CLOCK
SUSPENDED 3-CLOCK
SUSPENDED Hi-Z (turn off)
at the end of burst
;
;
;
Data Sheet E0031N30 47
µ
µµ
µ
PD45128441, 45128841, 45128163
Clock Suspension during Burst Read (using CKE Function) (2/2) (Burst Length = 4, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;;
;;
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;;
;;
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;;
;;
;;
;
;
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;
QAa1 QAa2 QAa3 QAa4
CAa
;
;
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;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
BA0
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
L
Hi-Z
RAa
RAa
Activate
Command
for Bank A
Read
Command
for Bank A
1-CLOCK
SUSPENDED 2-CLOCK
SUSPENDED 3-CLOCK
SUSPENDED Hi-Z (turn off)
at the end of burst
Data Sheet E0031N30
48
µ
µµ
µ
PD45128441, 45128841, 45128163
13.8 Clock Suspension during Burst Write (using CKE Function) (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
CAa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BA0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
L
Hi-Z
RAa
RAa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
DAa1 DAa2 DAa3 DAa4
Activate
Command
for Bank A
1-CLOCK
SUSPENDED 2-CLOCK
SUSPENDED 3-CLOCK
SUSPENDED
Write
Command
for Bank A
Data Sheet E0031N30 49
µ
µµ
µ
PD45128441, 45128841, 45128163
Clock Suspension during Burst Write (using CKE Function) (2/2) (Burst Length = 4, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;;
;;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
CAa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;;
;;
;
;
BA0
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
L
Hi-Z
RAa
RAa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
DAa1 DAa2 DAa3 DAa4
Activate
Command
for Bank A
1-CLOCK
SUSPENDED 2-CLOCK
SUSPENDED 3-CLOCK
SUSPENDED
Write
Command
for Bank A
Data Sheet E0031N30
50
µ
µµ
µ
PD45128441, 45128841, 45128163
13.9 Power Down Mode and Clock Mask (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
QAa3
CAa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
L
Hi-Z
RAa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BA0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
t
CKSP
t
CKSP
QAa1 QAa2
VALID
Activate
Command
for Bank A
Power Down
Mode Entry
ACTIVE STANDBY
Power Down
Mode Exit
Read
Command
for Bank A
Clock Mask
Start Clock Mask
End Power Down
Mode Entry
Precharge
Command
for Bank A
PRECHARGE STANDBY
Power Down
Mode Exit
QAa4
RAa
;
Data Sheet E0031N30 51
µ
µµ
µ
PD45128441, 45128841, 45128163
13.10 CBR (Auto) Refresh
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
T0 T1 T2 T3 T4 T5 T6 Tn Tn + 1Tn + 2Tn + 3Tn + 4Tn + 5Tn + 6TmTm + 1Tm + 2Tm + 3Tm + 4Tm + 5Tm + 6Tm + 7
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
BA0
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;
;
L
Hi-Z
tRP
H
tRC1 tRC1
Q1
Precharge
Command
(if necessary)
CBR (Auto) Refresh CBR (Auto) Refresh Activate
Command Read
Command
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Data Sheet E0031N30
52
µ
µµ
µ
PD45128441, 45128841, 45128163
13.11 Self Refresh (Entry and Exit)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
;
;
;;
;;
;;
;;
;
;
;
;
;;
;;
;;
;;
;
;
;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
T0 T1 T2 T3 T4 Tn Tn + 1Tn + 2TmTm + 1TkTk + 1Tk + 2Tk + 3Tk + 4
tRP
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
tRC1 tRC1
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BA0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Precharge
Command
(if necessary)
Self Refresh
Entry Self Refresh
Exit
Next Clock
Enable
Self Refresh
Entry
(or Activate Command)
Activate
Command
Self Refresh
Exit
Next Clock
Enable
L
Hi-Z
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
Data Sheet E0031N30 53
µ
µµ
µ
PD45128441, 45128841, 45128163
13.12 Random Column Read (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
;;
;;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;
;
;
;;
;;
;;
;
;
;;
;;
;
;
;
;
;;
;;
;;
;;
QAa1 QAa2
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
;;
;;
;;
;;
;
;
;
;
;
;
;
;;
;;
;;
;
;
;
;
;
;
;;
;;
;;
;
;
;;
;;
;;
QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4 QAd1 QAd2 QAd3
;
;
;
;
;
;
;
;
;
H
RAd
RAa CAdCAcCAa RAdCAb
;;
;;
;
;
;
;
;
;
;
;
BA0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
RAa
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
L
Hi-Z
Data Sheet E0031N30
54
µ
µµ
µ
PD45128441, 45128841, 45128163
Random Column Read (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
QAa1 QAa2
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
QAa3 QAa4 QAb1 QAb2 QAc1 QAc2 QAc3 QAc4
;
;
;
;
;
;
;
;
;
;
H
RAa
RAa CAaCAc
CAa RAaCAb
;
;
;
;
;
;
;
;
;
;
;
;
;
BA0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa
;
;
L
Hi-Z
Data Sheet E0031N30 55
µ
µµ
µ
PD45128441, 45128841, 45128163
13.13 Random Column Write (Page with Same Bank) (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
;;
;;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;;
;;
;;
;
;
;
;;
;;
;;
;;
L
Hi-Z
;
;;
;
;
;
;
;;
;;
;;
;;
DDa1 DDa2
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;
;
;
;
;
;
;;
;;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;;
;;
;;
;
;
;;
;;
;;
DDa3 DDa4 DDb1 DDb2 DDc1 DDc2 DDc3 DDc4 DDd1 DDd2 DDd3
;
;
;
;
;
;
;
;
;
H
RDd
RDa CDdCDcCDa RDdCDb
;;
;;
;
;
;
;
;
;
BA0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;
;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
RDa
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
DDd4
Activate
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Precharge
Command
for Bank D
Activate
Command
for Bank D
Write
Command
for Bank D
Data Sheet E0031N30
56
µ
µµ
µ
PD45128441, 45128841, 45128163
Random Column Write (Page with Same Bank) (2/2) (Burst Length = 4, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
L
Hi-Z
;
;
;
;
;
;
;
;
DDa1 DDa2
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
DDa3 DDa4 DDb1 DDb2 DDc1 DDc2 DDc3 DDc4
;
;
;
;
;
;
;
;
;
H
RDd
RDa CDdCDcCDa RDdCDb
;
;
;
;
;
;
;
;
;
;
;
BA0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RDa
DDd1
;
;
;
;
;
;
;
;
;
;
;
;
;
Activate
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Write
Command
for Bank D
Precharge
Command
for Bank D
Activate
Command
for Bank D
Write
Command
for Bank D
DDd2
Data Sheet E0031N30 57
µ
µµ
µ
PD45128441, 45128841, 45128163
13.14 Random Row Read (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
L
Hi-Z
;
;
;
;
;
;
QDa1 QDa2
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
QDa3 QDa4 QDa5 QDa6 QDa7 QDa8 QBa1 QBa2 QBa3 QBa4 QBa5
H
RDb
RDa CDbCBaCDa RDbRBa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RDa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BA0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RBa
;
;
;
;
;
;
QBa6 QBa7 QBa8
Activate
Command
for Bank D
Read
Command
for Bank D
Activate
Command
for Bank B
Read
Command
for Bank B
Precharge
Command
for Bank D
Activate
Command
for Bank D
Read
Command
for Bank D
Data Sheet E0031N30
58
µ
µµ
µ
PD45128441, 45128841, 45128163
Random Row Read (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
;;
;;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;;
;;
;;
;;
;
;
;
;
;;
;;
;;
;;
;;
L
Hi-Z
;
;
;
QBa1 QBa2
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;
;
;
;;
;;
QBa3 QBa4 QBa5 QBa6 QBa7 QBa8 QAa1 QAa2 QAa3 QAa4 QAa5
H
RBb
RBa CBbCAaCBa RBbRAa
;;
;;
;;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
RBa
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
;
;
;
;
RAa
;;
;;
;;
;;
;;
;;
;;
QAa6 QAa7
;
;
;;
;;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;;
;;
;
;
;
;
;;
;;
;
;
;
;;
;;
;;
;;
;;
;;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
BA1
Activate
Command
for Bank B
Read
Command
for Bank B
Activate
Command
for Bank A
Read
Command
for Bank A
Precharge
Command
for Bank B
Activate
Command
for Bank B
Read
Command
for Bank B
Precharge
Command
for Bank A
;;
;;
;;
;;
Data Sheet E0031N30 59
µ
µµ
µ
PD45128441, 45128841, 45128163
13.15 Random Row Write (Ping-Pong Banks) (1/2) (Burst Length = 8, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;
;
;
L
Hi-Z
;
;
DAa5 DAa6
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
DAa7 DAa8 DDa1 DDa2 DDa3 DDa4 DDa5 DDa6 DDa7 DDa8 DAb1
H
RAa CAbCDaCAa RDa
;
;
;;
;;
;;
;;
;;
;;
;
RAa
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
RDa
;
;
;
;
;
;
;
DAb2 DAb3
;;
;;
;
;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
;;
;;
;;
;;
;;
;;
BA0
;;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
RAb
RAb
;
;
;
;
;
;
DAa1 DAa2 DAa3 DAa4
Activate
Command
for Bank A
Write
Command
for Bank A
Write
Command
for Bank D
Activate
Command
for Bank D Precharge
Command
for Bank A
Activate
Command
for Bank A
Write
Command
for Bank A
Precharge
Command
for Bank D
Data Sheet E0031N30
60
µ
µµ
µ
PD45128441, 45128841, 45128163
Random Row Write (Ping-Pong Banks) (2/2) (Burst Length = 8, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;;
;;
;
;
;
;
;
;;
;;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;
;
;
;
;
DAa3 DAa4
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
DAa5 DAa6 DAa7 DAa8 DDa1 DDa2 DDa3 DDa5 DDa6 DDa7
H
RAa CAbCDaRDa
;
;
;
;;
;;
;;
;;
;;
;
;
;
;
RAa
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
RDa
;
;
;
;
;
;
;
DDa8 DAb1 DAb2
;
;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;;
;;
;;
;;
;
;
;
;
;;
;;
;;
;;
;
;
;
;
;
RAb
;
;
;
;
DAa1 DAa2
;
;
BA0
;;
;;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;;
;;
;;
;;
;
;
CAa
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
RAb
;;
;;
;;
;;
Activate
Command
for Bank A
Write
Command
for Bank A
Write
Command
for Bank D
Activate
Command
for Bank D
Precharge
Command
for Bank A
Activate
Command
for Bank A
Precharge
Command
for Bank D
Write
Command
for Bank A
L
Hi-Z DDa4
Data Sheet E0031N30 61
µ
µµ
µ
PD45128441, 45128841, 45128163
13.16 Read and Write (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
0-Clock Latency 2-Clock Latency
Read
Command
for Bank A
;;
;;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;
;
;
;
;
;;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
QAa1 QAa2
;
;
;
;
;
;
;
;
;;
;;
;;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
QAa3 QAa4 DAb1 DAb2 QAc1 QAc2 QAc4
;
;
;
;
;
;
H
RAa CAcCAb
;
;
;
;
;
DAb4
;
;
BA0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;;
;;
CAa
;
Write Latency = 0
RAa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Word Masking
L
Hi-Z
Hi-Z at the end of wrap function
Data Sheet E0031N30
62
µ
µµ
µ
PD45128441, 45128841, 45128163
Read and Write (2/2) (Burst Length = 4, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
;;
;;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;;
;
;
;
;
;
;;
;;
;;
;;
;;
QAa1 QAa2
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;
;
;
;
;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
QAa3 QAa4 DAb1 DAb2 QAc1 QAc2
;
;
H
RAa CAcCAb
;
;
;
;
;
;
DAb4
;
;
;
;
;
;
;;
;;
;;
;
;
;
;;
;;
;;
CAa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa
;
;
;
BA0
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Activate
Command
for Bank A
Read
Command
for Bank A
Write
Command
for Bank A
0-Clock Latency
Read
Command
for Bank A
Word Masking
Write Latency = 0
L
Hi-Z
Hi-Z at the end of wrap function 2-Clock Latency
Data Sheet E0031N30 63
µ
µµ
µ
PD45128441, 45128841, 45128163
13.17 Interleaved Column Read Cycle (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;;
;;
;;
;;
;
;
;
;
;
;
L
Hi-Z
;
;
;
;
;
;
Aa1 Aa2
;
;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Aa3 Aa4 Da1 Da2 Dc1 Dc2 Dd1 Dd2 Dd3 Dd4
;
;
H
RAa RDa
;;
;;
;;
;;
;
;
;;
;;
;
;
;
;;
;;
;
;
;;
;;
;
;
;;
;;
;
;
;
;
;
;
;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;;
;;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Ab1 Ab2Db1 Db2
;
;;
;
;
;;
;;
BA0
;;
;;
;;
;;
;;
;;
;
;
;
;;
;;
;;
;;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;;
;;
;;
RAa
;
RDa
CAa
;
;
CDa CDb CDc CAb
;
;
;
;
;
;
;
CDd
;;
;;
;
;
;;
;
Activate
Command
for Bank A Activate
Command
for bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank A
Read
Command
for Bank D
Precharge
Command
for Bank A
Precharge
Command
for Bank D
Read
Command
for Bank A
Data Sheet E0031N30
64
µ
µµ
µ
PD45128441, 45128841, 45128163
Interleaved Column Read Cycle (2/2) (Burst Length = 4, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA1
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;;
;;
;;
;;
;
;
;
;
;
;
L
Hi-Z
;
;
;
;
;
;
;
;
Aa1 Aa2
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;
;
;
;
;
;
Aa3 Aa4 Da1 Da2 Dc1 Dc2 Ab3 Ab4
;
;
;
;
H
;;
;;
;;
;
;
;;
;;
;
;
;;
;;
;
;
;
;
;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
Ab1 Ab2Db1 Db2
;
;
;
;;
;;
;
;
;;
;;
RAa
;
;
RDa
;;
;;
;
;
;;
;;
;;
;
;
;
;;
;;
;;
BA0
;;
;;
;;
;;
;;
;;
;;
;
;
;
;;
;;
;;
;;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
RAa CAb
CDc
RDa CDaCAa
Activate
Command
for Bank A
Activate
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank A Precharge
Command
for Bank D
Precharge
Command
for Bank A
Read
Command
for Bank A
CDb
Data Sheet E0031N30 65
µ
µµ
µ
PD45128441, 45128841, 45128163
13.18 Interleaved Column Write Cycle (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
L
Hi-Z
;
;
;
;
;
;
;
;
Aa1 Aa2
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Aa3 Aa4 Ba1 Ba2 Bc1 Bc2 Bd1 Bd2 Bd3 Bd4
;
;
H
RAa RBa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Ab1 Ab2Bb1 Bb2
;
;
;
;
RAa
;
;
RBa
CAa
;
;
CBa CBb CBc CAb
;
;
;
;
;
;
;
;
CBd
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BA1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank A
Precharge
Command
for Bank A Precharge
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
Data Sheet E0031N30
66
µ
µµ
µ
PD45128441, 45128841, 45128163
Interleaved Column Write Cycle (2/2) (Burst Length = 4, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;;
;;
;;
;;
;
;
;
;
;
L
Hi-Z
;
;
Aa1 Aa2
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
;
;
Aa3 Aa4 Ba1 Ba2 Bc1 Bc2 Bd1 Bd2
;
;
H
;;
;;
;;
;;
;
;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;;
;;
;
;
;;
;;
;
;
;
;
Ab1 Ab2Bb1 Bb2
;;
;;
;;
;;
;;
RAa
;
;
;
RBa
;;
;;
;;
;
;
;
;;
;;
;;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
RAa CAb
CBc
RBa CBa CBbCAa
;;
;;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
CBd
Bd3 Bd4
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank A Precharge
Command
for Bank A
Precharge
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
Write
Command
for Bank B
;;
;;
BA1
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;;
;;
;;
;
;
;
;
;
;
Data Sheet E0031N30 67
µ
µµ
µ
PD45128441, 45128841, 45128163
13.19 Auto Precharge after Read Burst (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;;
;;
;
;
;
;
;
;
;
;
;
;
;
L
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
H
;;
;
;;
;;
;;
;;
;
;
;
;;
;;
;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
;
;;
;;
;
;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;;
;;
;;
;
;
BA1
;;
;;
;
;
;
;;
;;
;;
;;
;;
;
;
;
;;
;;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RDb
;
;
;
RAc
;
;
;
;
;
;
RDa
;
;
;
RAa
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
RAa CAbCAa RDbCDaRDa CAcCDb RAc
Hi-Z
Activate
Command
for Bank A
Activate
Command
for Bank D
Read
Command
for Bank A
Read with
Auto Precharge
Command
for Bank D
Read with
Auto Precharge
Command
for Bank AAuto Precharge
Start for Bank D
Read with
Auto Precharge
Command
for Bank D
Auto Precharge
Start for Bank A Auto Precharge
Start for Bank D
Activate
Command
for Bank A Read with
Auto Precharge
Command
for Bank A
Activate
Command
for Bank D
Data Sheet E0031N30
68
µ
µµ
µ
PD45128441, 45128841, 45128163
Auto Precharge after Read Burst (2/2) (Burst Length = 4, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
;;
;;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
L
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
H
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RDb
;
;
;
;
;
;
;
;
;
;
;
;
RAa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa CAbCAa RDbCDaRDa CDb
Hi-Z
;
;
;
;
;
BA1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RDa
Activate
Command
for Bank A
Activate
Command
for Bank D
Read
Command
for Bank A
Read with
Auto Precharge
Command
for Bank D
Read with
Auto Precharge
Command
for Bank A
Read with
Auto Precharge
Command
for Bank D
Auto Precharge
Start for Bank D
Activate
Command
for Bank D
Auto Precharge
Start for Bank A
Data Sheet E0031N30 69
µ
µµ
µ
PD45128441, 45128841, 45128163
13.20 Auto Precharge after Write Burst (1/2) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
Activate
Command
for Bank A Write
Command
for Bank A
Activate
Command
for Bank D
Activate
Command
for Bank D
Write with
Auto Precharge
Command
for Bank D
Write with
Auto Precharge
Command
for Bank D
Write with
Auto Precharge
Command
for Bank A Auto Precharge
Start for Bank D Auto Precharge
Start for Bank A Auto Precharge
Start for Bank D
Activate
Command
for Bank A Write with
Auto Precharge
Command
for Bank A
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;;
;;
;
;
;
;
L
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
H
;;
;
;;
;;
;;
;;
;
;
;
;;
;;
;
;
;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RDb
;
;
;
RAc
;
;
;
;
;
;
RDa
;
;
;
RAa
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
RAa CAbCAa RDbCDaRDa CAcCDb RAc
;
;
BA1
;;
;;
;
;
;
;
;;
;;
;;
;;
;;
;
;
;
;;
;;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Hi-Z
Data Sheet E0031N30
70
µ
µµ
µ
PD45128441, 45128841, 45128163
Auto Precharge after Write Burst (2/2) (Burst Length = 4, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;;
;;
L
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
H
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RDb
;
;
;
;
;
;
;
;
;
;
RAa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa CAbCAa RDbCDaRDa CDb
;;
;;
;;
;
RDa
;
;
BA1
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Hi-Z
Activate
Command
for Bank A Write
Command
for Bank A
Activate
Command
for Bank D Write with
Auto Precharge
Command
for Bank D
Write with
Auto Precharge
Command
for Bank A
Auto Precharge
Start for Bank D Auto Precharge
Start for Bank A
Activate
Command
for bank D Write with
Auto Precharge
Command
for Bank D
Data Sheet E0031N30 71
µ
µµ
µ
PD45128441, 45128841, 45128163
13.21 Full Page Read Cycle (1/2) (/CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 T7 Tn Tn
+
1Tn
+
2Tn
+
3Tn
+
4Tn
+
5Tn
+
6Tn
+
7Tn
+
8Tn
+
9Tn
+
10 Tn
+
11 Tn
+
12 Tn
+
13
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
H
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa RDa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RDb
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa
RDa
CDaCAa RDb
Aa Aa+1 Aa+2 Aa-2 Aa-1 Aa Aa+1 Da Da+1 Da+2 Da+3 Da+4 Da+5 Da+6
Activate
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank D
Read
Command
for Bank D Burst Stop Command
Precharge
Command
for Bank D
Activate
Command
for Bank D
T6
BA1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
L
Hi-Z
Data Sheet E0031N30
72
µ
µµ
µ
PD45128441, 45128841, 45128163
Full Page Read Cycle (2/2) (/CAS latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 Tn Tn
+
1Tn
+
2Tn
+
3Tn
+
4Tn
+
5Tn
+
6Tn
+
7Tn
+
8Tn
+
9Tn
+
10 Tn
+
11 Tn
+
12
;
;
;
;
;
;
L
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
H
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa RDa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RDb
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa RDa CDaCAa RDb
Aa Aa+1 Aa-3 Aa-2 Aa-1 Aa Aa+1 Da Da+1 Da+2 Da+3 Da+4 Da+5
Precharge
Command
for Bank D
Activate
Command
for Bank A
Read
Command
for Bank A
Activate
Command
for Bank D
Read
Command
for Bank D Burst Stop Command
Activate
Command
for Bank D
Hi-Z
BA1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Data Sheet E0031N30 73
µ
µµ
µ
PD45128441, 45128841, 45128163
13.22 Full Page Write Cycle (1/2) (/CAS latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 Tn Tn
+
1Tn
+
2Tn
+
3Tn
+
4Tn
+
5Tn
+
6Tn
+
7Tn
+
8Tn
+
9Tn
+
10 Tn
+
11 Tn
+
12 Tn
+
13 Tn
+
14 Tn
+
15
;;
;;
;
;
;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
H
;;
;;
;;
;;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
RAa RDa
;;
;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
RDb
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
RAa RDa CDaCAa RDb
Aa Aa+1 Aa+2 Aa-2 Aa-1 Aa Aa+1 Da Da+1 Da+2 Da+3 Da+4 Da+5
;
;
;
;
;
;
;
BA1
;;
;;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;;
;;
Precharge
Command
for Bank D
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank D
Write
Command
for Bank D
Burst Stop Command Activate
Command
for Bank D
L
Hi-Z
Data Sheet E0031N30
74
µ
µµ
µ
PD45128441, 45128841, 45128163
Full Page Write Cycle (2/2) (/CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 Tn Tn
+
1Tn
+
2Tn
+
3Tn
+
4Tn
+
5Tn
+
6Tn
+
7Tn
+
8Tn
+
9Tn
+
10 Tn
+
11 Tn
+
12 Tn
+
13
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
H
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa RDa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RDb
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa
RDa
CDaCAa RDb
Aa Aa+1 Aa+2 Aa+3 Aa-1 Aa Aa+1 Da Da+1 Da+2 Da+3 Da+4 Da+5
;
;
;
;
;
;
;
;
;
Precharge
Command
for Bank D
Activate
Command
for Bank A
Write
Command
for Bank A
Activate
Command
for Bank D Burst is not completed
in the Full Page Mode
Write
Command
for Bank D
Burst Stop Command
Activate
Command
for Bank D
BA1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
L
Hi-Z
Data Sheet E0031N30 75
µ
µµ
µ
PD45128441, 45128841, 45128163
13.23 Byte Write Operation (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
LDQM
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
;
;
;
;
UDQM
;
;
;
;
;
;
;
BA1
DQ
(lower)
DQ
(upper)
Activate
Command
for Bank D
Read
Command
for Bank D
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Upper Byte
not Read Lower Byte
not Write Upper Byte
not Write Lower Byte
not Write
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Data Sheet E0031N30
76
µ
µµ
µ
PD45128441, 45128841, 45128163
Byte Write Operation (Burst Length = 4, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
LDQM
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
;
;
;
;
;
UDQM
;
;
;
;
;
;
BA1
DQ
(lower)
DQ
(upper)
Activate
Command
for Bank D
Read
Command
for Bank D
Read
Command
for Bank D
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Upper
Byte
not Read
Lower
Byte
not Read
Lower
Byte
not Read
Lower
Byte
not Read
Lower
Byte
not Write
Upper
Byte
not Write
Lower
Byte
not Write
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Data Sheet E0031N30 77
µ
µµ
µ
PD45128441, 45128841, 45128163
13.24 Burst Read and Single Write (Option) (Burst Length = 4, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
H
Hi-Z
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
DQ
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BA1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Activate
Command
for Bank D
Read
Command
for Bank D
Single
Write
Command
for Bank D
Single
Write
Command
for Bank D
Read
Command
for Bank D
Single
Write
Command
for Bank D
;
;
Qa1 Qa2 Qa3 Qa4 D1 Qb1 Qb2 Qb4 D2
Data Sheet E0031N30
78
µ
µµ
µ
PD45128441, 45128841, 45128163
Burst Read and Single Write (Option) (Burst Length = 4, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
H
Hi-Z
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
DQ
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BA1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Activate
Command
for Bank D
Read
Command
for Bank D
Single
Write
Command
for Bank D
Single
Write
Command
for Bank D
Read
Command
for Bank D
Qa1 Qa2 Qa3 Qa4 D1 Qb1 Qb2 Qb4
Data Sheet E0031N30 79
µ
µµ
µ
PD45128441, 45128841, 45128163
13.25 Full Page Random Column Read (Burst Length = Full Page, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
L
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
H
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Hi-Z
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa CAc
CDbCAbRDa
;
;
RDa
CDc
RAa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BA1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
CAa CDa
QAa1 QDa1 QAb1 QAb2 QDb1 QDb2 QAc1 QAc2 QAc3 QDc1 QDc2 QDc3
Activate
Command
for Bank A
Activate
Command
for Bank DRead
Command
for Bank ARead
Command
for Bank D
Read
Command
for Bank A
Read
Command
for Bank D
Read
Command
for Bank A
Read
Command
for Bank D
Precharge
Command
for Bank D
(PRE Termination of Burst)
Data Sheet E0031N30
80
µ
µµ
µ
PD45128441, 45128841, 45128163
Full Page Random Column Read (Burst Length = Full Page, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
;
;
;
;
L
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
H
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Hi-Z
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa CAc
CDbCAbRDa
;
;
RDa
CDc
RAa
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BA1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
CAa CDa
QAa1 QDa1 QAb1 QAb2 QDb1 QDb2 QAc1 QAc2 QAc3 QDc1 QDc2 QDc3
Activate
Command
for Bank A
Activate
Command
for Bank DRead
Command
for Bank ARead
Command
for Bank D
Read
Command
for Bank A
Read
Command
for Bank D
Read
Command
for Bank A
Read
Command
for Bank D
Precharge
Command
for Bank D
(PRE Termination of Burst)
Hi-Z
Data Sheet E0031N30 81
µ
µµ
µ
PD45128441, 45128841, 45128163
13.26 Full Page Random Column Write (Burst Length = Full Page, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
L
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
H
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Hi-Z
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa CAc
CDbCAbRDa
;
RDa
CDc
RAa
;
;
;
;
;
;
;
;
;
;
;
;
BA1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
CAa CDa
DAa1 DDa1 DAb1 DAb2 DDb1 DDb2 DAc1 DAc2 DAc3 DDc1 DDc2 DDc3
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
DDc4
Precharge
Command
for Bank D
(PRE Termination of Burst)
Activate
Command
for Bank A
Activate
Command
for Bank DWrite
Command
for Bank AWrite
Command
for Bank D
Write
Command
for Bank A
Write
Command
for Bank D
Write
Command
for Bank A
Write
Command
for Bank D
Data Sheet E0031N30
82
µ
µµ
µ
PD45128441, 45128841, 45128163
Full Page Random Column Write (Burst Length = Full Page, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
;
;
L
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
H
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Hi-Z
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa CAc
CDbCAbRDa
;
RDa
CDc
RAa
;
;
;
;
;
;
;
;
;
;
;
;
BA1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
CAa CDa
DAa1 DDa1 DAb1 DAb2 DDb1 DDb2 DAc1 DAc2 DAc3 DDc1 DDc2 DDc3
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
DDc4
Precharge
Command
for Bank D
(PRE Termination of Burst)
Activate
Command
for Bank A
Activate
Command
for Bank DWrite
Command
for Bank AWrite
Command
for Bank D
Write
Command
for Bank A
Write
Command
for Bank D
Write
Command
for Bank A
Write
Command
for Bank D
Data Sheet E0031N30 83
µ
µµ
µ
PD45128441, 45128841, 45128163
13.27 PRE (Precharge) Termination of Burst (1/2) (Burst Length = 8, /CAS Latency = 2)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
;
;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
L
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
H
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
BA1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
Hi-Z
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa RAb
CAa
;
;
;
;
;
RAa RAb
CAb
DAa1 DAa2 DAa3 DAa4 DAa5 QAb1 QAb2 QAb3 QAb4 QAb5
Activate
Command
for Bank A
Activate
Command
for Bank A
Write
Command
for Bank A
PRE Termination
of Burst PRE Termination
of Burst
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A Precharge
Command
for Bank A
Hi-Z
Write
Masking
;
;
;
;
;
RAc
RAc
tRCD tDPL tRP tRAS
tRAS
Data Sheet E0031N30
84
µ
µµ
µ
PD45128441, 45128841, 45128163
PRE (Precharge) Termination of Burst (2/2) (Burst Length = 8, /CAS Latency = 3)
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0
A10
ADD
DQM
DQ
;;
;;
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21
;
;
L
Hi-Z
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
H
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;
;
;
;
;
BA1
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
;
RAa RAb
CAa
;;
;;
;;
;;
;;
;;
RAa RAb
CAb
DAa1 DAa2 DAa3 QAb1 QAb2 QAb3 QAb4
Hi-Z
Activate
Command
for Bank A
Activate
Command
for Bank A
Write
Command
for Bank A
PRE Termination
of Burst
Precharge
Command
for Bank A
Precharge
Command
for Bank A
Activate
Command
for Bank A
Read
Command
for Bank A
PRE Termination
of Burst
;;
;;
;;
;;
;;
;;
DAa4 DAa5
Write
Masking
;;
;;
;;
;;
;
;
;
;
;;
;;
;;
;
;
;
;
;
;
;
;
RAc
RAc
;;
;;
tRCD tRP tRAStDPL
tRAS
Data Sheet E0031N30 85
µ
µµ
µ
PD45128441, 45128841, 45128163
14. Package Drawing
NOTES
1. Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
2. Dimension "A" does not include mold fiash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15 mm per side.
M
P
A
G
CNB
M
D
L
K
J
H
I
E
F
detail of lead end
S
54 28
127
S
ITEM
B
C
I
L
M
N
54-PIN PLASTIC TSOP (II) (10.16 mm (400))
A
D
E
F
G
H
J
P
MILLIMETERS
0.80 (T.P.)
0.91 MAX.
0.13
0.50±0.10
10.16±0.10
0.10
22.22±0.05
0.10±0.05
0.32
1.1±0.1
11.76±0.20
1.00
+0.08
−0.07
0.80±0.20
3°+7°
−3°
K0.145+0.025
−0.015
S54G5-80-9JF-2
Data Sheet E0031N30
86
µ
µµ
µ
PD45128441, 45128841, 45128163
15. Recommended Soldering Conditions
Please consult with our sales offices for soldering conditions of the
µ
PD45128xxx.
Type of Surface Mount Device
µ
PD45128xxxG5 : 54-pin Plastic TSOP (II) (10.16mm (400))
Data Sheet E0031N30 87
µ
µµ
µ
PD45128441, 45128841, 45128163
16. Revision History
Edition / Page Description
Date
This
edition
Previous
edition
Type of
revision
Location
NEC Corporation (M12650E)
9th edition /
Mar. 1999
p.15 p.15 Modification,
Addition
CKE Truth Table - Power down
p.19 p.19 Modification,
Addition
Command Truth Table for CKE - Power down
p.35 p.35 Modification ICC1 (spec), ICC2NS (spec), ICC3N (spec), ICC4 (spec), ICC5 (spec)
p.37 p.37 Modification Output load
p.50 p.50 Modification Timing Chart (Power Down Mode and Clock Mask)
p.77 p.77 Modification Timing Chart (Full Page Random Column Read)
10th edition / Throughout Throughout Modification A13
→ BA0, A12 → BA1
Jan. 2000 p.2, 3 p.2, 3 Addition -A75
Deletion -AxxL (Low power)
p.34 p.34 Addition Pin Capacitance (MAX.)
p.35 p.35 Addition -A75 specs
Modification ICC5
Deletion ICC6 -AxxL (Low power)
p.36 p.36 Modification AC Characteristics Test Conditions
p.37, 38,
42
p.37, 38,
42
Addition -A75 specs
p.76, 78,
80, 82
– Addition Timing chart (/CAS latency = 3)
p.85 p.81 Modification Package Drawing
11th edition / p.38 p.38 Modification tRC1 spec (-A10)
Apr. 2000
Elpida Memory, Inc. (E0031N)
1st edition /
Jan. 2001
– – – Republished by Elpida Memory, Inc.
Ver. 2.0 /
June 2001
p.2, 3 p.2, 3 Addition -AxxL (Low power)
p.2, 3, 35,
37, 38, 42
p.2, 3, 35,
37, 38, 42
Deletion -10B specs
p.35 p.35 Addition ICC6 -AxxL (Low power)
Ver. 3.0 / p.2, 3 p.2, 3 Addition -A75A and -A75AL (Low power)
August 2001 p.35, 37,
38
p.35, 37,
38
Addition -A75A specs
Data Sheet E0031N30
88
µ
µµ
µ
PD45128441, 45128841, 45128163
[MEMO]
Data Sheet E0031N30 89
µ
µµ
µ
PD45128441, 45128841, 45128163
[MEMO]
Data Sheet E0031N30
90
µ
µµ
µ
PD45128441, 45128841, 45128163
[MEMO]
Data Sheet E0031N30 91
µ
µµ
µ
PD45128441, 45128841, 45128163
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR MOS DEVICES
Exposing the MOS devices to a strong electric field can cause destruction of the gate
oxide and ultimately degrade the MOS devices operation. Steps must be taken to stop
generation of static electricity as much as possible, and quickly dissipate it, when once
it has occurred. Environmental control must be adequate. When it is dry, humidifier
should be used. It is recommended to avoid using insulators that easily build static
electricity. MOS devices must be stored and transported in an anti-static container,
static shielding bag or conductive material. All test and measurement tools including
work bench and floor should be grounded. The operator should be grounded using
wrist strap. MOS devices must not be touched with bare hands. Similar precautions
need to be taken for PW boards with semiconductor MOS devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS DEVICES
No connection for CMOS devices input pins can be a cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level may be
generated due to noise, etc., hence causing malfunction. CMOS devices behave
differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected
to VDD or GND with a resistor, if it is considered to have a possibility of being an output
pin. The unused pins must be handled in accordance with the related specifications.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS devices. Production process
of MOS does not define the initial operation status of the device. Immediately after the
power source is turned ON, the MOS devices with reset function have not yet been
initialized. Hence, power-on does not guarantee output pin levels, I/O settings or
contents of registers. MOS devices are not initialized until the reset signal is received.
Reset operation must be executed immediately after power-on for MOS devices having
reset function.
CME0107
µ
µµ
µ
PD45128441, 45128841, 45128163
M01E0107
No part of this document may be copied or reproduced in any form or by any means without the prior
written consent of Elpida Memory, Inc.
Elpida Memory, Inc. does not assume any liability for infringement of any intellectual property rights
(including but not limited to patents, copyrights, and circuit layout licenses) of Elpida Memory, Inc. or
third parties by or arising from the use of the products or information listed in this document. No license,
express, implied or otherwise, is granted under any patents, copyrights or other intellectual property
rights of Elpida Memory, Inc. or others.
Descriptions of circuits, software and other related information in this document are provided for
illustrative purposes in semiconductor product operation and application examples. The incorporation of
these circuits, software and information in the design of the customer's equipment shall be done under
the full responsibility of the customer. Elpida Memory, Inc. assumes no responsibility for any losses
incurred by customers or third parties arising from the use of these circuits, software and information.
[Product applications]
Elpida Memory, Inc. makes every attempt to ensure that its products are of high quality and reliability.
However, users are instructed to contact Elpida Memory's sales office before using the product in
aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment,
medical equipment for life support, or other such application in which especially high quality and
reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk
of bodily injury.
[Product usage]
Design your application so that the product is used within the ranges and conditions guaranteed by
Elpida Memory, Inc., including the maximum ratings, operating supply voltage range, heat radiation
characteristics, installation conditions and other related characteristics. Elpida Memory, Inc. bears no
responsibility for failure or damage when the product is used beyond the guaranteed ranges and
conditions. Even within the guaranteed ranges and conditions, consider normally foreseeable failure
rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so
that the equipment incorporating Elpida Memory, Inc. products does not cause bodily injury, fire or other
consequential damage due to the operation of the Elpida Memory, Inc. product.
[Usage environment]
This product is not designed to be resistant to electromagnetic waves or radiation. This product must be
used in a non-condensing environment.
If you export the products or technology described in this document that are controlled by the Foreign
Exchange and Foreign Trade Law of Japan, you must follow the necessary procedures in accordance
with the relevant laws and regulations of Japan. Also, if you export products/technology controlled by
U.S. export control regulations, or another country's export control laws or regulations, you must follow
the necessary procedures in accordance with such laws or regulations.
If these products/technology are sold, leased, or transferred to a third party, or a third party is granted
license to use these products, that third party must be made aware that they are responsible for
compliance with the relevant laws and regulations.
The information in this document is subject to change without notice. Before using this document, confirm that this is the latest version.
