A80960CA-25 - Intel - Datasheet.Live

Intel Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in an Intel product. No other circuit patent

licenses are implied. Information contained herein supersedes previously published specifications on these devices from Intel.

80960CA-33, -25, -16

32-BIT HIGH-PERFORMANCE EMBEDDEDPROCESSOR

• Two Instructions/Clock Sustained Execution

• Four 59 Mbytes/s DMA Channels with Data Chaining

• Demultiplexed 32-bit Burst Bus with Pipelining

■32-bit Parallel Architecture

—Two Instructions/clock Execution

—Load/Store Architecture

—Sixteen 32-bit Global Registers

—Sixteen 32-bit Local Registers

—Manipulates 64-bit Bit Fields

—11 Addressing Modes

—Full Parallel Fault Model

—Supervisor Protection Model

■Fast Procedure Call/Return Model

—Full Procedure Call in 4 Clocks

■On-Chip Register Cache

—Caches Registers on Call/Ret

—Minimum of 6 Frames Provided

—Up to 15 Programmable Frames

■On-Chip Instruction Cache

—1 Kbyte Two-Way Set Associative

—128-bit Path to Instruction Sequencer

—Cache-Lock Modes

—Cache-Off Mode

■High Bandwidth On-Chip Data RAM

—1 Kbyte On-Chip Data RAM

—Sustains 128 bits per Clock Access

■Four On-Chip DMA Channels

—59 Mbytes/s Fly-by Transfers

—32 Mbytes/s Two-Cycle Transfers

—Data Chaining

—Data Packing/Unpacking

—Programmable Priority Method

■32-Bit Demultiplexed Burst Bus

—128-bit Internal Data Paths to and

from Registers

—Burst Bus for DRAM Interfacing

—Address Pipelining Option

—Fully Programmable Wait States

—Supports 8-, 16- or 32-bit Bus Widths

—Supports Unaligned Accesses

—Supervisor Protection Pin

■Selectable Big or Little Endian Byte

Ordering

■High-Speed Interrupt Controller

—Up to 248 External Interrupts

—32 Fully Programmable Priorities

—Multi-mode 8-bit Interrupt Port

—Four Internal DMA Interrupts

—Separate, Non-maskable Interrupt Pin

—Context Switch in 750 ns Typical

CONTENTS PAGE

1.0 PURPOSE..................................................................................................................................................1

2.0 80960CA OVERVIEW.................................................................................................................................1

2.1 The C-Series Core ..............................................................................................................................2

2.2 Pipelined, Burst Bus ...........................................................................................................................2

2.3 Flexible DMA Controller ......................................................................................................................2

2.4 Priority Interrupt Controller ..................................................................................................................2

2.5 Instruction Set Summary ....................................................................................................................3

3.0 PACKAGE INFORMATION.........................................................................................................................4

3.1 Package Introduction ..........................................................................................................................4

3.2 Pin Descriptions ..................................................................................................................................4

3.3 80960CA Mechanical Data ...............................................................................................................11

3.3.1 80960CA PGA Pinout ............................................................................................................11

3.3.2 80960CA PQFP Pinout ..........................................................................................................15

3.4 Package Thermal Specifications ......................................................................................................18

3.5 Stepping Register Information ..........................................................................................................20

3.6 Suggested Sources for 80960CA Accessories..................................................................................20

4.0 ELECTRICAL SPECIFICATIONS.............................................................................................................21

4.1 Absolute Maximum Ratings ..............................................................................................................21

4.2 Operating Conditions ........................................................................................................................21

4.3 Recommended Connections ............................................................................................................21

4.4 DC Specifications .............................................................................................................................22

4.5 AC Specifications ..............................................................................................................................23

4.5.1 AC Test Conditions ................................................................................................................29

4.5.2 AC Timing Waveforms ...........................................................................................................29

4.5.3 Derating Curves .....................................................................................................................33

5.0 RESET, BACKOFF AND HOLD ACKNOWLEDGE.................................................................................35

6.0 BUS WAVEFORMS .................................................................................................................................36

7.0 REVISION HISTORY................................................................................................................................64

80960CA-33, -25, -16

32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

iii

CONTENTS PAGE

LIST OF FIGURES

Figure 1 80960CA Block Diagram ..............................................................................................................1

Figure 2 80960CA PGA Pinout—View from Top (Pins Facing Down) ......................................................13

Figure 3 80960CA PGA Pinout —View from Bottom (Pins Facing Up) ....................................................14

Figure 4 80960CA PQFP Pinout (View from Top Side) ............................................................................17

Figure 5 Measuring 80960CA PGA and PQFP Case Temperature ..........................................................18

Figure 6 Register g0 .................................................................................................................................20

Figure 7 AC Test Load ..............................................................................................................................29

Figure 8 Input and Output Clocks Waveform ............................................................................................29

Figure 9 CLKIN Waveform ........................................................................................................................29

Figure 10 Output Delay and Float Waveform .............................................................................................30

Figure 11 Input Setup and Hold Waveform ................................................................................................30

Figure 12 NMI,XINT7:0 Input Setup and Hold Waveform ..........................................................................31

Figure 13 Hold Acknowledge Timings ........................................................................................................31

Figure 14 Bus Backoff (BOFF) Timings ......................................................................................................32

Figure 15 Relative Timings Waveforms ......................................................................................................33

Figure 16 Output Delay or Hold vs. Load Capacitance ..............................................................................33

Figure 17 Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC ..................34

Figure 18 ICC vs. Frequency and Temperature ...........................................................................................34

Figure 19 Cold Reset Waveform ................................................................................................................36

Figure 20 Warm Reset Waveform ..............................................................................................................37

Figure 21 Entering the ONCE State ...........................................................................................................38

Figure 22 Clock Synchronization in the 2-x Clock Mode ............................................................................39

Figure 23 Clock Synchronization in the 1-x Clock Mode ............................................................................39

Figure 24 Non-Burst, Non-Pipelined Requests Without Wait States ..........................................................40

Figure 25 Non-Burst, Non-Pipelined Read Request With Wait States .......................................................41

Figure 26 Non-Burst, Non-Pipelined Write Request With Wait States .......................................................42

Figure 27 Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus ........................................43

Figure 28 Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus .............................................44

Figure 29 Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus .......................................45

Figure 30 Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus .............................................46

Figure 31 Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus ............................................47

Figure 32 Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus ...............................................48

Figure 33 Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus .......................................49

Figure 34 Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus ............................................50

Figure 35 Burst, Pipelined Read Request Without Wait States, 32-Bit Bus ...............................................51

Figure 36 Burst, Pipelined Read Request With Wait States, 32-Bit Bus.....................................................52

Figure 37 Burst, Pipelined Read Request With Wait States, 16-Bit Bus.....................................................53

Figure 38 Burst, Pipelined Read Request With Wait States, 8-Bit Bus.......................................................54

CONTENTS PAGE

LIST OF FIGURES (continued)

Figure 39 Using External READY...............................................................................................................55

Figure 40 Terminating a Burst with BTERM...............................................................................................56

Figure 41 BOFF Functional Timing ............................................................................................................57

Figure 42 HOLD Functional Timing ............................................................................................................58

Figure 43 DREQ and DACK Functional Timing ..........................................................................................59

Figure 44 EOP Functional Timing ..............................................................................................................59

Figure 45 Terminal Count Functional Timing ..............................................................................................60

Figure 46 FAIL Functional Timing ...............................................................................................................60

Figure 47 A Summary of Aligned and Unaligned Transfers for Little Endian Regions ................................61

Figure 48 A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued) ............62

Figure 49 Idle Bus Operation ......................................................................................................................63

LIST OF TABLES

Table 1 80960CA Instruction Set ..............................................................................................................3

Table 2 Pin Description Nomenclature ......................................................................................................4

Table 3 80960CA Pin Description — External Bus Signals ......................................................................5

Table 4 80960CA Pin Description — Processor Control Signals ..............................................................8

Table 5 80960CA Pin Description — DMA and Interrupt Unit Control Signals .......................................10

Table 6 80960CA PGA Pinout — In Signal Order ...................................................................................11

Table 7 80960CA PGA Pinout — In Pin Order ........................................................................................12

Table 8 80960CA PQFP Pinout — In Signal Order .................................................................................15

Table 9 80960CA PQFP Pinout — In Pin Order .....................................................................................16

Table 10 Maximum TA at Various Airflows in oC (PGA Package Only) .....................................................18

Table 11 80960CA PGA Package Thermal Characteristics ......................................................................19

Table 12 80960CA PQFP Package Thermal Characteristics ....................................................................19

Table 13 Die Stepping Cross Reference ...................................................................................................20

Table 14 Operating Conditions (80960CA-33, -25, -16) ............................................................................21

Table 15 DC Characteristics .....................................................................................................................22

Table 16 80960CA AC Characteristics (33 MHz) ......................................................................................23

Table 17 80960CA AC Characteristics (25 MHz) ......................................................................................25

Table 18 80960CA AC Characteristics (16 MHz) ......................................................................................27

Table 19 Reset Conditions ........................................................................................................................35

Table 20 Hold Acknowledge and Backoff Conditions ................................................................................35

80960CA-33, -25, -16

1.0 PURPOSE

This document provides electrical characteristics for

the 33, 25 and 16 MHz versions of the 80960CA. For

a detailed description of any 80960CA functional

topic—other than parametric performance—consult

the 80960CA Product Overview (Order No. 270669)

or the i960 CA Microprocessor User’s Manual

(Order No. 270710). To obtain data sheet updates

and errata, please call Intel’s FaxBACK data-on-

demand system (1-800-628-2283 or 916-356-3105).

Other information can be obtained from Intel’s tech-

nical BBS (916-356-3600).

2.0 80960CA OVERVIEW

The 80960CA is the second-generation member of

the 80960 family of embedded processors. The

80960CA is object code compatible with the 32-bit

80960 Core Architecture while including Special

Function Register extensions to control on-chip

peripherals and instruction set extensions to shift 64-

bit operands and configure on-chip hardware.

Multiple 128-bit internal buses, on-chip instruction

caching and a sophisticated instruction scheduler

allow the processor to sustain execution of two

instructions every clock and peak at execution of

three instructions per clock.

A 32-bit demultiplexed and pipelined burst bus

provides a 132Mbyte/s bandwidth to a system’s

high-speed external memory sub-system. In

addition, the 80960CA’s on-chip caching of instruc-

tions, procedure context and critical program data

substantially decouple system performance from the

wait states associated with accesses to the system’s

slower, cost sensitive, main memory subsystem.

The 80960CA bus controller integrates full wait state

and bus width control for highest system perfor-

mance with minimal system design complexity.

Unaligned access and Big Endian byte order support

reduces the cost of porting existing applications to

the 80960CA.

The processor also integrates four complete data-

chaining DMA channels and a high-speed interrupt

controller on-chip. DMA channels perform: single-

cycle or two-cycle transfers, data packing and

unpacking and data chaining. Block transfers—in

addition to source or destination synchronized trans-

fers—are provided.

The interrupt controller provides full programmability

of 248 interrupt sources into 32 priority levels with a

typical interrupt task switch (”latency”) time of

750ns.

Figure 1. 80960CA Block Diagra m

Execution

Unit

Programmable Bus

Controller

Bus Request

Queues

Six-port

64-Bit

SRC1 Bus

64-Bit

SRC2 Bus

64-Bit

DST Bus

32-Bit

Base Bus

128-Bit

Load Bus

128-Bit

Store Bus

Instruction Prefetch Queue

Instruction Cache

(1 KByte, Two-way

Set Associative)

128-BIT CACHE BUS

Interrupt Controller

Control

Address

Data

Memory-side

Machine Bus

Parallel

Instruction

Scheduler

Memory Region

Configuration

Multiply/Divide

Unit

Four-Channel

DMA Controller

Interrupt

Port

1 KByte

5 to 15 Sets

Data RAM

Address

Generation Unit

F_CX001A

DMA

Port

80960CA-33, -25, -16

2.1 The C-Series Core

The C-Series core is a very high performance

microarchitectural implementation of the 80960 Core

Architecture. The C-Series core can sustain execu-

tion of two instructions per clock (66MIPs at

33MHz). To achieve this level of performance, Intel

has incorporated state-of-the-art silicon technology

and innovative microarchitectural constructs into the

implementation of the C-Series core. Factors that

contribute to the core’s performance include:

•Parallel instruction decoding allows issuance of

up to three instructions per clock

•Single-clock execution of most instructions

•Parallel instruction decode allows sustained,

simultaneous execution of two single-clock

instructions every clock cycle

•Efficient instruction pipeline minimizes pipeline

break losses

•Register and resource scoreboarding allow simul-

taneous multi-clock instruction execution

•Branch look-ahead and prediction allows many

branches to execute with no pipeline break

•Local Register Cache integrated on-chip caches

Call/Return context

•Two-way set associative, 1Kbyte integrated

instruction cache

•1Kbyte integrated Data RAM sustains a four-

word (128-bit) access every clock cycle

2.2 Pipelined, Burst Bus

A 32-bit high performance bus controller interfaces

the 80960CA to external memory and peripherals.

The Bus Control Unit features a maximum transfer

rate of 132Mbytes per second (at 33MHz). Inter-

nally programmable wait states and 16 separately

configurable memory regions allow the processor to

interface with a variety of memory subsystems with a

minimum of system complexity and a maximum of

performance. The Bus Controller’s main features

include:

•Demultiplexed, Burst Bus to exploit most efficient

DRAM access modes

•Address Pipelining to reduce memory cost while

maintaining performance

•32-, 16- and 8-bit modes for I/O interfacing ease

•Full internal wait state generation to reduce

system cost

•Little and Big Endian support to ease application

development

•Unaligned access support for code portability

•Three-deep request queue to decouple the bus

from the core

2.3 Flexible DMA Controller

A four-channel DMA controller provides high speed

DMA control for data transfers involving peripherals

and memory. The DMA provides advanced features

such as data chaining, byte assembly and disas-

sembly and a high performance fly-by mode capable

of transfer speeds of up to 59Mbytes per second at

33 MHz. The DMA controller features a performance

and flexibility which is only possible by integrating the

DMA controller and the 80960CA core.

2.4 Priority Interrupt Controller

A programmable-priority interrupt controller

manages up to 248 external sources through the 8-

bit external interrupt port. The Interrupt Unit also

handles the four internal sources from the DMA

controller and a single non-maskable interrupt input.

The 8-bit interrupt port can also be configured to

provide individual interrupt sources that are level or

edge triggered.

Interrupts in the 80960CA are prioritized and

signaled within 270ns of the request. If the interrupt

is of higher priority than the processor priority, the

context switch to the interrupt routine typically is

complete in another 480ns. The interrupt unit

provides the mechanism for the low latency and high

throughput interrupt service which is essential for

embedded applications.

80960CA-33, -25, -16

2.5 Instruction Set Summary

Table 1 summarizes the 80960CA instruction set by logical groupings. See the i960 CA Microprocessor User’s

Manual for a complete description of the instruction set.

Table 1. 80960CA Instruction Set

Data

MovementArithmeticLogicalBit and Bit Field

and Byte

Load

Store

Move

Load Address

Add

Subtract

Multiply

Divide

Remainder

Modulo

Shift

*Extended Shift

Extended Multiply

Extended Divide

Add with Carry

Subtract with Carry

Rotate

And

Not And

And Not

Exclusive Or

Not Or

Or Not

Nor

Exclusive Nor

Not

Nand

Set Bit

Clear Bit

Not Bit

Alter Bit

Scan For Bit

Span Over Bit

Extract

Modify

Scan Byte for Equal

ComparisonBranchCall/ReturnFault

Compare

Conditional Compare

Compare and

Increment

Compare and

Decrement

Test Condition Code

Check Bit

Unconditional Branch

Conditional Branch

Compare and Branch

Call

Call Extended

Call System

Return

Branch and Link

Conditional Fault

Synchronize Faults

DebugProcessor

ManagementAtomic

Modify Trace Controls

Mark

Force Mark

Flush Local Registers

Modify Arithmetic

Controls

Modify Process

Controls

*System Control

*DMA Control

Atomic Add

Atomic Modify

NOTES:

Instructions marked by (*) are 80960CA extensions to the 80960 instruction set.

80960CA-33, -25, -16

3.0 PACKAGE INFORMATION

3.1 Package Introduction

This section describes the pins, pinouts and thermal

characteristics for the 80960CA in the 168-pin

Ceramic Pin Grid Array (PGA) package and the 196-

pin Plastic Quad Flat Package (PQFP). For complete

package specifications and information, see the

Packaging Handbook (Order No. 240800).

3.2 Pin Descriptions

The 80960CA pins are described in this section.

Table 2 presents the legend for interpreting the pin

descriptions in the following tables. Pins associated

with the 32-bit demultiplexed processor bus are

described in Table 3. Pins associated with basic

processor configuration and control are described in

Table 4. Pins associated with the 80960CA DMA

Controller and Interrupt Unit are described in Table

All pins float while the processor is in the ONCE

mode.

Table 2. Pin Description Nomenclature

SymbolDescription

IInput only pin

OOutput only pin

I/OPin can be either an input or output

–Pins “must be” connected as described

S(...)Synchronous. Inputs must meet setup

and hold times relative to PCLK2:1 for

proper operation. All outputs are

synchronous to PCLK2:1.

S(E) Edge sensitive input

S(L) Level sensitive input

A(...)Asynchronous. Inputs may be

asynchronous to PCLK2:1.

A(E) Edge sensitive input

A(L) Level sensitive input

H(...)While the processor’s bus is in the

Hold Acknowledge or Bus Backoff state,

the pin:

H(1) is driven to VCC

H(0) is driven to VSS

H(Z) floats

H(Q) continues to be a valid input

R(...)While the processor’s RESET pin is low,

the pin:

R(1) is driven to VCC

R(0) is driven to VSS

R(Z) floats

R(Q) continues to be a valid output

80960CA-33, -25, -16

Table 3. 80960CA Pin Description — External Bus Signals (Sheet 1 of 3)

NameTypeDescription

A31:2O

H(Z)

R(Z)

ADDRESS BUS carries the physical address’ upper 30 bits. A31 is the most

significant address bit; A2 is the least significant. During a bus access, A31:2 identify

all external addresses to word (4-byte) boundaries. The byte enable signals indicate

the selected byte in each word. During burst accesses, A3:2 increment to indicate

successive data cycles.

D31:0I/O

S(L)

H(Z)

R(Z)

DATA BUS carries 32-, 16- or 8-bit data quantities depending on bus width configu-

ration. The least significant bit of the data is carried on D0 and the most significant on

D31. When the bus is configured for 8-bit data, the lower 8 data lines, D7:0 are used.

For 16-bit data bus widths, D15:0 are used. For 32-bit bus widths the full data bus is

used.

BE3:0O

H(Z)

R(1)

BYTE ENABLES select which of the four bytes addressed by A31:2 are active during

an access to a memory region configured for a 32-bit data-bus width. BE3 applies to

D31:24; BE2 applies to D23:16; BE1 applies to D15:8 BE0 applies to D7:0.

32-bit bus: BE3–Byte Enable 3 –enable D31:24

BE2–Byte Enable 2 –enable D23:16

BE1–Byte Enable 1 –enable D15:8

BE0–Byte Enable 0 –enable D7:0

For accesses to a memory region configured for a 16-bit data-bus width, the

processor uses the BE3,BE1 and BE0 pins as BHE, A1 and BLE respectively.

16-bit bus: BE3–Byte High Enable (BHE)–enable D15:8

BE2–Not used (driven high or low)

BE1–Address Bit 1 (A1)

BE0–Byte Low Enable (BLE)–enable D7:0

For accesses to a memory region configured for an 8-bit data-bus width, the

processor uses the BE1 and BE0 pins as A1 and A0 respectively.

8-bit bus: BE3–Not used (driven high or low)

BE2–Not used (driven high or low)

BE1–Address Bit 1 (A1)

BE0–Address Bit 0 (A0)

W/RO

H(Z)

R(0)

WRITE/READ is asserted for read requests and deasserted for write requests. The

W/R signal changes in the same clock cycle as ADS. It remains valid for the entire

access in non-pipelined regions. In pipelined regions, W/R is not guaranteed to be

valid in the last cycle of a read access.

ADSO

H(Z)

R(1)

ADDRESS STROBE indicates a valid address and the start of a new bus access.

ADS is asserted for the first clock of a bus access.

80960CA-33, -25, -16

READYI

S(L)

H(Z)

R(Z)

READY is an input which signals the termination of a data transfer. READY is used to

indicate that read data on the bus is valid or that a write-data transfer has completed.

The READY signal works in conjunction with the internally programmed wait-state

generator. If READY is enabled in a region, the pin is sampled after the programmed

number of wait-states has expired. If the READY pin is deasserted, wait states

continue to be inserted until READY becomes asserted. This is true for the NRAD,

NRDD, NWAD and NWDD wait states. The NXDA wait states cannot be extended.

BTERMI

S(L)

H(Z)

R(Z)

BURST TERMINATE is an input which breaks up a burst access and causes another

address cycle to occur. The BTERM signal works in conjunction with the internally

programmed wait-state generator. If READY and BTERM are enabled in a region, the

BTERM pin is sampled after the programmed number of wait states has expired.

When BTERM is asserted, a new ADS signal is generated and the access is

completed. The READY input is ignored when BTERM is asserted. BTERM must be

externally synchronized to satisfy BTERM setup and hold times.

WAITO

H(Z)

R(1)

WAIT indicates internal wait state generator status. WAIT is asserted when wait

states are being caused by the internal wait state generator and not by the READY or

BTERM inputs. WAIT can be used to derive a write-data strobe. WAIT can also be

thought of as a READY output that the processor provides when it is inserting wait

states.

BLASTO

H(Z)

R(0)

BURST LAST indicates the last transfer in a bus access. BLAST is asserted in the

last data transfer of burst and non-burst accesses after the wait state counter reaches

zero. BLAST remains asserted until the clock following the last cycle of the last data

transfer of a bus access. If the READY or BTERM input is used to extend wait states,

the BLAST signal remains asserted until READY or BTERM terminates the access.

DT/RO

H(Z)

R(0)

DATA TRANSMIT/RECEIVE indicates direction for data transceivers. DT/R is used in

conjunction with DEN to provide control for data transceivers attached to the external

bus. When DT/R is asserted, the signal indicates that the processor receives data.

Conversely, when deasserted, the processor sends data. DT/R changes only while

DEN is high.

DENO

H(Z)

R(1)

DATA ENABLE indicates data cycles in a bus request. DEN is asserted at the start of

the bus request first data cycle and is deasserted at the end of the last data cycle.

DEN is used in conjunction with DT/R to provide control for data transceivers attached

to the external bus. DEN remains asserted for sequential reads from pipelined

memory regions. DEN is deasserted when DT /R changes.

LOCKO

H(Z)

R(1)

BUS LOCK indicates that an atomic read-modify-write operation is in progress. LOCK

may be used to prevent external agents from accessing memory which is currently

involved in an atomic operation. LOCK is asserted in the first clock of an atomic

operation and deasserted in the clock cycle following the last bus access for the

atomic operation. To allow the most flexibility for memory system enforcement of

locked accesses, the processor acknowledges a bus hold request when LOCK is

asserted. The processor performs DMA transfers while LOCK is active.

HOLDI

S(L)

H(Z)

R(Z)

HOLD REQUEST signals that an external agent requests access to the external bus.

The processor asserts HOLDA after completing the current bus request. HOLD,

HOLDA and BREQ are used together to arbitrate access to the processor’s external

bus by external bus agents.

Table 3. 80960CA Pin Description — External Bus Signals (Sheet 2 of 3)

NameTypeDescription

80960CA-33, -25, -16

BOFFI

S(L)

H(Z)

R(Z)

BUS BACKOFF, when asserted, suspends the current access and causes the bus

pins to float. When BOFF is deasserted, the ADS signal is asserted on the next clock

cycle and the access is resumed.

HOLDAO

H(1)

R(Q)

HOLD ACKNOWLEDGE indicates to a bus requestor that the processor has relin-

quished control of the external bus. When HOLDA is asserted, the external address

bus, data bus and bus control signals are floated. HOLD, BOFF, HOLDA and BREQ

are used together to arbitrate access to the processor’s external bus by external bus

agents. Since the processor grants HOLD requests and enters the Hold Acknowledge

state even while RESET is asserted, the state of the HOLDA pin is independent of the

RESET pin.

BREQ O

H(Q)

R(0)

BUS REQUEST is asserted when the bus controller has a request pending. BREQ

can be used by external bus arbitration logic in conjunction with HOLD and HOLDA to

determine when to return mastership of the external bus to the processor.

D/CO

H(Z)

R(Z)

DATA OR CODE is asserted for a data request and deasserted for instruction

requests. D/C has the same timing as W/R.

DMAO

H(Z)

R(Z)

DMA ACCESS indicates whether the bus request was initiated by the DMA controller.

DMA is asserted for any DMA request. DMA is deasserted for all other requests.

SUPO

H(Z)

R(Z)

SUPERVISOR ACCESS indicates whether the bus request is issued while in

supervisor mode. SUP is asserted when the request has supervisor privileges and is

deasserted otherwise. SUP can be used to isolate supervisor code and data

structures from non-supervisor requests.

Table 3. 80960CA Pin Description — External Bus Signals (Sheet 3 of 3)

NameTypeDescription

80960CA-33, -25, -16

Table 4. 80960CA Pin Description — Processor Control Signals (Sheet 1 of 2)

NameTypeDescription

RESETI

A(L)

H(Z)

R(Z)

RESET causes the chip to reset. When RESET is asserted, all external signals

return to the reset state. When RESET is deasserted, initialization begins. When

the 2-x clock mode is selected, RESET must remain asserted for 32 CLKIN cycles

before being deasserted to guarantee correct processor initialization. When the 1-x

clock mode is selected, RESET must remain asserted for 10,000 CLKIN cycles

before being deasserted to guarantee correct processor initialization. The

CLKMODE pin selects 1-x or 2-x input clock division of the CLKIN pin.

The processor’s Hold Acknowledge bus state functions while the chip is reset. If the

processor’s bus is in the Hold Acknowledge state when RESET is asserted, the

processor will internally reset, but maintains the Hold Acknowledge state on

external pins until the Hold request is removed. If a Hold request is made while the

processor is in the reset state, the processor bus will grant HOLDA and enter the

Hold Acknowledge state.

FAILO

H(Q)

R(0)

FAIL indicates failure of the processor’s self-test performed at initialization. When

RESET is deasserted and the processor begins initialization, the FAIL pin is

asserted. An internal self-test is performed as part of the initialization process. If

this self-test passes, the FAIL pin is deasserted; otherwise it remains asserted. The

FAIL pin is reasserted while the processor performs an external bus self-confidence

test. If this self-test passes, the processor deasserts the FAIL pin and branches to

the user’s initialization routine; otherwise the FAIL pin remains asserted. Internal

self-test and the use of the FAIL pin can be disabled with the STEST pin.

STESTI

S(L)

H(Z)

R(Z)

SELF TEST causes the processor’s internal self-test feature to be enabled or

disabled at initialization. STEST is read on the rising edge of RESET. When

asserted, the processor’s internal self-test and external bus confidence tests are

performed during processor initialization. When deasserted, only the bus

confidence tests are performed during initialization.

ONCEI

A(L)

H(Z)

R(Z)

ON CIRCUIT EMULATION, when asserted, causes all outputs to be floated. ONCE

is continuously sampled while RESET is low and is latched on the rising edge of

RESET. To place the processor in the ONCE state:

(1) assert RESET and ONCE (order does not matter )

(2) wait for at least 16 CLKIN periods in 2-x mode—or 10,000 CLKIN periods in

1-x mode—after VCC and CLKIN are within operating specifications

(3) deassert RESET

(4) wait at least 32 CLKIN periods

(The processor will now be latched in the ONCE state as long as RESET is high.)

To exit the ONCE state, bring VCC and CLKIN to operating conditions, then assert

RESET and bring ONCE high prior to deasserting RESET.

CLKIN must operate within the specified operating conditions of the processor until

Step 4 above has been completed. CLKIN may then be changed to DC to achieve

the lowest possible ONCE mode leakage current.

ONCE can be used by emulator products or for board testers to effectively make an

installed processor transparent in the board.

80960CA-33, -25, -16

CLKINI

A(E)

H(Z)

R(Z)

CLOCK INPUT is an input for the external clock needed to run the processor. The

external clock is internally divided as prescribed by the CLKMODE pin to produce

PCLK2:1.

CLKMODEI

A(L)

H(Z)

R(Z)

CLOCK MODE selects the division factor applied to the external clock input

(CLKIN). When CLKMODE is high, CLKIN is divided by one to create PCLK2:1 and

the processor’s internal clock. When CLKMODE is low, CLKIN is divided by two to

create PCLK2:1 and the processor’s internal clock. CLKMODE should be tied high

or low in a system as the clock mode is not latched by the processor. If left

unconnected, the processor will internally pull the CLKMODE pin low, enabling the

2-x clock mode.

PCLK2:1O

H(Q)

R(Q)

PROCESSOR OUTPUT CLOCKS provide a timing reference for all processor

inputs and outputs. All input and output timings are specified in relation to PCLK2

and PCLK1. PCLK2 and PCLK1 are identical signals. Two output pins are provided

to allow flexibility in the system’s allocation of capacitive loading on the clock.

PCLK2:1 may also be connected at the processor to form a single clock signal.

VSS–GROUND connections must be connected externally to a VSS board plane.

VCC –POWER connections must be connected externally to a VCC board plane.

VCCPLL–VCCPLL is a separate VCC supply pin for the phase lock loop used in 1-x clock mode.

Connecting a simple lowpass filter to VCCPLL may help reduce clock jitter (TCP) in

noisy environments. Otherwise, VCCPLL should be connected to VCC.This pin is

implemented starting with the D-stepping. See Table 13 for die stepping

information.

NC –NO CONNECT pins must not be connected in a system.

Table 4. 80960CA Pin Description — Processor Control Signals (Sheet 2 of 2)

NameTypeDescription

80960CA-33, -25, -16

Table 5. 80960CA Pin Description — DMA and Interrupt Unit Control Signals

NameTypeDescription

DREQ3:0I

A(L)

H(Z)

R(Z)

DMA REQUEST causes a DMA transfer to be requested. Each of the four signals

requests a transfer on a single channel. DREQ0 requests channel 0, DREQ1

requests channel 1, etc. When two or more channels are requested simulta-

neously, the channel with the highest priority is serviced first. The channel priority

mode is programmable.

DACK3:0O

H(1)

R(1)

DMA ACKNOWLEDGE indicates that a DMA transfer is being executed. Each of

the four signals acknowledges a transfer for a single channel. DACK0 acknowl-

edges channel 0, DACK1 acknowledges channel 1, etc. DACK3:0 are asserted

when the requesting device of a DMA is accessed.

EOP/TC3:0I/O

A(L)

H(Z/Q)

R(Z)

END OF PROCESS/TERMINAL COUNT can be programmed as either an input

(EOP3:0) or as an output (TC3:0), but not both. Each pin is individually program-

mable. When programmed as an input, EOPx causes the termination of a current

DMA transfer for the channel corresponding to the EOPx pin. EOP0 corresponds

to channel 0, EOP1 corresponds to channel 1, etc. When a channel is configured

for source and destination chaining, the EOP pin for that channel causes

termination of only the current buffer transferred and causes the next buffer to be

transferred. EOP3:0 are asynchronous inputs.

When programmed as an output, the channel’s TCx pin indicates that the channel

byte count has reached 0 and a DMA has terminated. TCx is driven with the same

timing as DACKx during the last DMA transfer for a buffer. If the last bus request is

executed as multiple bus accesses, TCx will stay asserted for the entire bus

request.

XINT7:0I

A(E/L)

H(Z)

R(Z)

EXTERNAL INTERRUPT PINS cause interrupts to be requested. These pins can

be configured in three modes:

Dedicated Mode:each pin is a dedicated external interrupt source. Dedicated

inputs can be individually programmed to be level (low) or

edge (falling) activated.

Expanded Mode:the eight pins act together as an 8-bit vectored interrupt

source. The interrupt pins in this mode are level activat-

ed.Since the interrupt pins are active low, the vector number

requested is the one’s complement of the positive logic

value place on the port. This eliminates glue logic to

interface to combinational priority encoders which output

negative logic.

Mixed Mode:XINT7:5 are dedicated sources and XINT4:0 act as the five

most significant bits of an expanded mode vector. The least

significant bits are set to 010 internally.

NMII

A(E)

H(Z)

R(Z)

NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to occur.

NMI is the highest priority interrupt recognized. NMI is an edge (falling) activated

source.

80960CA-33, -25, -16

3.3 80960CA Mechanical Data

3.3.1 80960CA PGA Pinout

Tables 6 and 7 list the 80960CA pin names with

package location. Figure 2 depicts the complete

80960CA PGA pinout as viewed from the top side of

the component (i.e., pins facing down). Figure 3

shows the complete 80960CA PGA pinout as viewed

from the pin-side of the package (i.e., pins facing up).

See Section 4.0, ELECTRICAL SPECIFICATIONS

for specifications and recommended connections.

Table 6. 80960CA PGA Pinout — In Signal Order

Address BusData BusBus ControlProcessor ControlI/O

SignalPinSignalPinSignalPinSignalPinSignalPin

A31S15D31R3BE3S5RESETA16DREQ3A7

A30Q13D30Q5BE2S6DREQ2B6

A29R14D29S2BE1S7FAILA2DREQ1A6

A28Q14D28Q4BE0R9DREQ0B5

A27S16D27R2STESTB2

A26R15D26Q3W/RS10DACK3A10

A25S17D25S1ONCEC3DACK2A9

A24Q15D24R1ADSR6DACK1A8

A23R16D23Q2CLKINC13DACK0B8

A22R17D22P3READYS3CLKMODEC14

A21Q16D21Q1BTERMR4PLCK1B14EOP/TC3A14

A20P15D20P2PLCK2B13EOP/TC2A13

A19P16D19P1WAITS12EOP/TC1A12

A18Q17D18N2BLASTS8VSS EOP/TC0A11

A17P17D17N1Location

A16N16D16M1DT/RS11C7, C8, C9, C10,

C11, C12, F15, G3,

G15, H3, H15, J3,

J15, K3, K15, L3,

L15, M3, M15, Q7,

Q8, Q9, Q10, Q11

XINT7C17

A15N17D15 L1 DENS9XINT6C16

A14M17D14 L2 XINT5B17

A13L16D13K1LOCKS14XINT4C15

A12L17D12J1XINT3B16

A11K17D11H1VCCXINT2A17

A10J17D10H2HOLD R5LocationXINT1A15

A9H17D9G1HOLDA S4B7, B9, B11, B12,

C6, E15, F3, F16,

G2, H16, J2, J16, K2,

K16, M2, M16, N3,

N15, Q6, R7, R8,

R10, R11

XINT0B15

A8G17D8F1BREQR13

A7G16D7E1NMID15

A6F17D6F2D/CS13

A5E17D5D1DMAR12

A4E16D4E2SUPQ12VCCPLLB10

A3D17D3C1No Connect

A2D16D2D2BOFFB1Location

D1C2A1, A3, A4, A5, B3,

B4, C4, C5, D3

D0E3

80960CA-33, -25, -16

Table 7. 80960CA PGA Pinout — In Pin Order

PinSignalPinSignalPinSignalPinSignalPinSignal

A1NC C1D3G1D9M1D16R1D24

A2FAILC2D1G2VCC M2VCC R2D27

A3NC C3ONCEG3VSS M3VSSR3D31

A4NC C4NC G15VSS M15VSSR4BTERM

A5NC C5NC G16A7M16VCC R5HOLD

A6DREQ1C6VCC G17A8M17A14R6ADS

A7DREQ3C7VSS R7VCC

A8DACK1C8VSS H1D11N1D17R8VCC

A9DACK2C9VSS H2D10N2D18R9BE0

A10DACK3C10VSS H3VSS N3VCC R10VCC

A11EOP/TC0C11VSS H15VSS N15VCC R11VCC

A12EOP/TC1C12VSS H16VCC N16A16R12DMA

A13EOP/TC2C13CLKINH17A9N17A15R13BREQ

A14EOP/TC3C14CLKMODER14A29

A15XINT1C15XINT4J1D12P1D19R15A26

A16RESETC16XINT6J2VCC P2D20R16A23

A17XINT2C17XINT7J3VSS P3D22R17A22

J15VSS P15A20

B1BOFFD1D5J16VCC P16A19S1D25

B2STESTD2D2J17A10P17A17S2D29

B3NC D3NC S3READY

B4NC D15NMIK1D13Q1D21S4HOLDA

B5DREQ0D16A2K2VCC Q2D23S5BE3

B6DREQ2D17A3K3VSS Q3D26S6BE2

B7VCC K15VSS Q4D28S7BE1

B8DACK0E1D7K16VCC Q5D30S8BLAST

B9VCC E2D4K17A11Q6VCC S9DEN

B10VCCPLLE3D0Q7VSSS10W/R

B11VCC E15VCC L1D15Q8VSSS11DT/R

B12VCC E16A4L2D14Q9VSSS12WAIT

B13PCLK2E17A5L3VSS Q10VSSS13D/C

B14PCLK1L15VSS Q11VSSS14LOCK

B15XINT0F1D8L16A13Q12SUPS15A31

B16XINT3F2D6L17A12Q13A30S16A27

B17XINT5F3VCC Q14A28S17A25

F15VSS Q15A24

F16VCC Q16A21

F17A6Q17A18

80960CA-33, -25, -16

Figure 2. 80960CA PGA Pinout — View from Top (Pins Facing Down)

D5D7D8D9D11D12D13D15D16D17D19D21D24D25

D2D4D6VCC

D10VCC

VCC

D14VCC

D18D20D23D27D29

NCD0VCC

VSS

VCC

D22D31READY D26

D28BTERM

HOLDA

D30HOLDBE3

VCC

ADSBE2

VSS

VCC

BE1

VSS

VCC

BLAST

VSS

BE0DEN

VSS

VCC

W/R

VSS

VCC

DT/R

A29LOCK

SUPWAIT DMA

A28

A30BREQD/C

ONCE

VCC

VSS

CLKIN

CLK MODE

VSS

BOFF

STEST

DREQ0

DREQ2

VCC

DACK0

VCC

VCCPLL

VCC

PCLK2

PCLK1

VCC

FAIL

DREQ1

DREQ3

DACK1

DACK2

DACK3

EOP/TC0

EOP/TC2

EOP/TC3

EOP/TC1

VSS

VCC

A22A25

A20 VSS

A3A5

NMI

VCC

VSS

VSS VSS

A24A31 A26

A4VCC

A6A8A9A10A11A12A14A15A17A18

VCC

A13VCC

A16A19A21A23A27 A7 XINT6

XINT7

XINT4

XINT3

XINT5

XINT0

RESET

XINT2

XINT1

ABCDEFGHJKLMNPQRS

F_CA002A

ABCDEFGHJKLMNPQRS

80960CA-33, -25, -16

Figure 3. 80960CA PGA Pinout — View from Bottom (Pins Facing Up)

D5 D7 D8 D9 D11 D12 D13 D15 D16 D17 D19 D21 D24 D25

D2 D4 D6 VCC D10 VCC VCC D14 VCC D18 D20 D23 D27 D29

NC D0 VCC VSS VSS VSS VSS VSS VSS VCC D22 D31 READYD26

D28 BTERM HOLDA

D30 HOLD BE3

VCC ADS BE2

VSS VCC BE1

VSS VCC BLAST

VSS BE0 DEN

VSS VCC W/R

VSS VCC DT/R

A29 LOCK

SUP WAITDMA

A28

A30 BREQ D/C

ONCE

VCC

VSS

CLKIN

CLK MODE

VSS

BOFF

STEST

DREQ0

DREQ2

VCC

DACK0

VCC

VCCPLL

VCC

PCLK2

PCLK1

VCC

FAIL

DREQ1

DREQ3

DACK1

DACK2

DACK3

EOP/TC0

EOP/TC2

EOP/TC3

EOP/TC1

VSS

VCC

A22 A25

A20VSS

A3 A5

NMI VCC VSS VSS VSS VSS

VSS A24 A31A26

A4 VCC

A6 A8 A9 A10 A11 A12 A14 A15 A17 A18

VCC VCC VCC A13 VCC A16 A19 A21 A23 A27A7XINT6

XINT7

XINT4

XINT3

XINT5

XINT0

RESET

XINT2

XINT1

F_CA003A

A B C D EFGHJKLMNPQRS

Metal Lid

80960CA-33, -25, -16

3.3.2 80960CA PQFP Pinout

Tables 8 and 9 list the 80960CA pin names with

package location. Figure 4 shows the 80960CA

PQFP pinout as viewed from the top side.

See Section 4.0, ELECTRICAL SPECIFICATIONS

for specifications and recommended connections.

Table 8. 80960CA PQFP Pinout — In Signal Order

Address BusData BusBus ControlProcessor Control I/O

SignalPinSignalPinSignalPinSignalPinSignalPin

A31153D31186BE3176RESET91 DREQ360

A30152D30187BE2175FAIL 45 DREQ259

A29151D29188BE1172STEST46 DREQ158

A28145D28189BE0170ONCE43 DREQ057

A27144D27191CLKIN87

A26143D26192W/R164CLKMODE85 DACK365

A25142D25194PCLK2 74 DACK264

A24141D24195ADS178PCLK1 78 DACK163

A23139D23 3 VSSDACK062

A22138D22 4 READY182Location

A21137D21 5 BTERM1842, 7, 16, 24, 30, 38,

39, 49, 56, 70, 75,

77, 81, 83, 88, 89,

92, 98, 105, 109,

110, 121, 125, 131,

135, 147, 150, 161,

165, 173, 174, 185,

196

EOP/TC369

A20136D20 6 EOP/TC268

A19134D19 8 WAIT162EOP/TC167

A18133D18 9 BLAST169EOP/TC066

A17132D17 10

A16130D16 11 DT/R163XINT7107

A15129D15 13 DEN167VCC XINT6106

A14128D14 14 LocationXINT5102

A13124D13 15 LOCK1561, 12, 20, 28, 32, 37,

44, 50, 61, 71, 79,

82, 96, 99, 103, 115,

127, 140, 148, 154,

168, 171, 180, 190

XINT4101

A12123D12 17 XINT3100

A11122D11 18 HOLD181XINT295

A10120D10 19 HOLDA179XINT194

A9119D9 21 BREQ155XINT093

A8118D8 22 VCCPLL72

A7117D7 23 D/C159No ConnectNMI108

A6116D6 25 DMA160Location

A5114D5 26 SUP15829, 31, 41, 42, 47,

48, 51, 52, 53, 54,

55, 73, 76, 80, 84,

86, 90, 97, 104, 126,

146, 149, 157, 166,

177, 183, 193

A4113D4 27

A3112D3 33 BOFF40

A2111D2 34

D1 35

D0 36

80960CA-33, -25, -16

Table 9. 80960CA PQFP Pinout — In Pin Order

PinSignalPinSignalPinSignalPinSignalPinSignalPinSignal

1VCC 34 D2 67 EOP/TC1100XINT3133A18166NC

2VSS 35 D1 68 EOP/TC2101XINT4134A19167DEN

3D23 36 D0 69 EOP/TC3102XINT5135VSS168VCC

4D22 37 VCC 70 VSS 103VCC 136A20169BLAST

5D21 38 VSS71 VCC 104NC 137A21170BE0

6D20 39 VSS72 VCCPLL105VSS 138A22171VCC

7VSS 40 BOFF73 NC 106XINT6139A23172BE1

8D19 41 NC 74 PCLK2107XINT7140VCC 173VSS

9D18 42 NC 75 VSS 108NMI141A24174VSS

10 D17 43 ONCE76 NC 109VSS 142A25175BE2

11 D16 44 VCC 77 VSS 110VSS 143A26176BE3

12 VCC 45 FAIL 78 PCLK1111A2144A27177NC

13 D15 46 STEST79 VCC 112A3145A28178ADS

14 D14 47 NC 80 NC 113A4146NC 179HOLDA

15 D13 48 NC 81 VSS 114A5147VSS180VCC

16 VSS 49 VSS82 VCC 115VCC 148VCC 181HOLD

17 D12 50 VCC 83 VSS 116A6149NC 182READY

18 D11 51 NC 84 NC 117A7150VSS183NC

19 D10 52 NC 85 CLKMODE118A8151A29184BTERM

20 VCC 53 NC 86 NC 119A9152A30185VSS

21 D9 54 NC 87 CLKIN120A10153A31186D31

22 D8 55 NC 88 VSS 121VSS 154VCC 187D30

23 D7 56 VSS89 VSS 122A11155BREQ188D29

24 VSS 57 DREQ0 90 NC 123A12156LOCK189D28

25 D6 58 DREQ191 RESET124A13157NC 190VCC

26 D5 59 DREQ2 92 VSS 125VSS 158SUP191D27

27 D4 60 DREQ393 XINT0126NC 159D/C192D26

28 VCC 61 VCC 94 XINT1127VCC 160DMA193NC

29 NC 62 DACK095 XINT2128A14161VSS194D25

30 VSS 63 DACK1 96 VCC 129A15162WAIT195D24

31 NC 64 DACK297 NC 130A16163DT/R196VSS

32 VCC 65 DACK3 98 VSS 131VSS 164W/R

33 D3 66 EOP/TC0 99 VCC 132A17165VSS

80960CA-33, -25, -16

Figure 4. 80960CA PQFP Pinout (View from Top Side)

5098

147

148 196

Pin 1

F_CA004A

80960CA-33, -25, -16

3.4 Package Thermal Specifications

The 80960CA is specified for operation when TC

(case temperature) is within the range of 0oC–100oC.

TC may be measured in any environment to deter-

mine whether the 80960CA is within specified oper-

ating range. Case temperature should be measured

at the center of the top surface, opposite the pins.

Refer to Figure 5.

TA (ambient temperature) can be calculated from θCA

(thermal resistance from case to ambient) using the

following equation:

TA = TC – P*θCA

Table 10 shows the maximum TA allowable (without

exceeding TC) at various airflows and operating

frequencies (fPCLK).

Note that TA is greatly improved by attaching fins or a

heatsink to the package. P (maximum power

consumption) is calculated by using the typical ICC

as tabulated in Section 4.4, DC Specifications and

VCC of 5V.

Figure 5. Measuring 80960CA PGA and PQFP Case Temperature

Table 10. Maximum TA at Various Airflows in oC (PGA Package Only)

Airflow-ft/min (m/sec)

fPCLK

(MHz)0

(0)200

(1.01)400

(2.03)600

(3.04)800

(4.06)1000

(5.07)

TA with

Heatsink*

TA without

Heatsink*

NOTES:

*0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).

Measure PQFP case temperature

at center of top surface.

Measure PGA temperature at

center of top surface

168 - Pin PGA

Pin 196 Pin 1 F_CX007A

80960CA-33, -25, -16

Table 11. 80960CA PGA Package Thermal Characteristics

Thermal Resistance — °C/Watt

ParameterAirflow — ft./min (m/sec)

(0)200

(1.01)400

(2.03)600

(3.07)800

(4.06)1000

(5.07)

θ Junction-to-Case

(Case measured as

shown in Figure 5)1.51.51.51.51.51.5

θ Case-to-Ambient

(No Heatsink)17 14 11 9 7.16.6

θ Case-to-Ambient

(With Heatsink)*13 9 5.5 5 3.93.4

NOTES:

1. This table applies to 80960CA PGA plugged into socket or soldered directly to board.

2. θJA = θJC + θCA

*0.285” high unidirectional heatsink (AI alloy 6061, 50 mil fin width, 150 mil center-to-center fin spacing).

Table 12. 80960CA PQFP Package Thermal Characteristics

Thermal Resistance — °C/Watt

Parameter

Airflow — ft./min (m/sec)

(0)50

(0.25)100

(0.50)200

(1.01)400

(2.03)600

(3.04)800

(4.06)

θ Junction-to-Case (Case Measured

as shown in Figure 5)5555555

θ Case-to-Ambient (No Heatsink)19 18 171512 10 9

NOTES:

1. This table applies to 80960CA PQFP soldered directly to board.

2. θJA = θJC + θCA

θJC

80960CA-33, -25, -16

3.5 Stepping Register Information

Upon reset, register g0 contains die stepping infor-

mation. Figure 6 shows how g0 is configured. The

most significant byte contains an ASCII 0. The upper

middle byte contains an ASCII C. The lower middle

byte contains an ASCII A. The least significant byte

contains the stepping number in ASCII. g0 retains

this information until it is overwritten by the user

program.

Figure 6. Register g0

Table 13 contains a cross reference of the number in

the least significant byte of register g0 to the die

stepping number.

Table 13. Die Stepping Cross Reference

g0 Least Significant

ByteDie Stepping

01B

02C-1

03C-2,C-3

04D

ASCII 00 43 41 Stepping Number

DECIMAL 0CAStepping Number

MSBLSB

3.6 Suggested Sources for 80960CA

Accessories

The following is a list of suggested sources for

80960CA accessories. This is not an endorsement of

any kind, nor is it a warranty of the performance of

any of the listed products and/or companies.

Sockets

1. 3M Textool Test and Interconnection

Products Department

P.O. Box 2963

Austin, TX 78769-2963

2. Augat, Inc.

Interconnection Products Group

33 Perry Avenue

P.O. box 779

Attleboro, MA 02703

(508) 699-7646

3. Concept Manufacturing, Inc.

(Decoupling Sockets)

41484 Christy Street

Fremont, CA 94538

(415) 651-3804

Heatsinks/Fins

1. Thermalloy, Inc.

2021 West Valley View Lane

Dallas, TX 75234-8993

(214) 243-4321

FAX: (214) 241-4656

2. E G & G Division

60 Audubon Road

Wakefield, MA 01880

(617) 245-5900

80960CA-33, -25, -16

4.0 ELECTRICAL SPECIFICATIONS

4.1 Absolute Maximum Ratings

ParameterMaximum Rating

Storage Temperature................................–65oC to +150oC

Case Temperature Under Bias .................–65oC to +110oC

Supply Voltage wrt. VSS ............................. –0.5V to + 6.5V

Voltage on Other Pins wrt. VSS ...........–0.5V to VCC + 0.5V

NOTICE: This is a production data sheet. The

specifications are subject to change without notice.

*WARNING: Stressing the device beyond the

“Absolute Maximum Ratings” may cause perma-

nent damage. These are stress ratings only. Opera-

tion beyond the “Operating Conditions” is not

recommended and extended exposure beyond the

“Operating Conditions” may affect device reliability.

4.2 Operating Conditions

Table 14. Operating Conditions (80960 CA-33, -25, -16)

SymbolParameterMinMaxUnitsNotes

VCC Supply Voltage 80960CA-33

80960CA-25

80960CA-16

4.75

4.50

5.25

5.50

fCLK2xInput Clock Frequency (2-x Mode) 80960CA-33

80960CA-25

80960CA-16

66.66

MHz

fCLK1xInput Clock Frequency (1-x Mode) 80960CA-33

80960CA-25

80960CA-16

33.33

MHz

MHz(1)

TCCase Temperature Under Bias PGA Package

80960CA-33, -25, -16 196-Pin PQFP0

0100

100oC

NOTES:

1. When in the 1-x input clock mode, CLKIN is an input to an internal phase-locked loop and must maintain a minimum fre-

quency of 8MHz for proper processor operation. However, in the 1-x mode, CLKIN may still be stopped when the pro-

cessor either is in a reset condition or is reset. If CLKIN is stopped, the specified RESET low time must be provided once

CLKIN restarts and has stabilized.

4.3 Recommended Connections

Power and ground connections must be made to

multiple VCC and VSS (GND) pins. Every 80960CA-

based circuit board should include power (VCC) and

ground (VSS) planes for power distribution. Every

VCC pin must be connected to the power plane, and

every VSS pin must be connected to the ground

plane. Pins identified as “NC” must not be

connected in the system.

Liberal decoupling capacitance should be placed

near the 80960CA. The processor can cause tran-

sient power surges when its numerous output buffers

transition, particularly when connected to large

capacitive loads.

Low inductance capacitors and interconnects are

recommended for best high frequency electrical

performance. Inductance can be reduced by short-

ening the board traces between the processor and

decoupling capacitors as much as possible. Capaci-

tors specifically designed for PGA packages will offer

the lowest possible inductance.

For reliable operation, always connect unused inputs

to an appropriate signal level. In particular, any

unused interrupt (XINT,NMI) or DMA (DREQ) input

should be connected to VCC through a pull-up

resistor, as should BTERM if not used. Pull-up resis-

tors should be in the in the range of 20KΩfor each

pin tied high. If READY or HOLD are not used, the

unused input should be connected to ground. N.C.

pins must always remain unconnected. Refer to

the i960 Cx Microprocessor User’s Manual (Order

Number 270710) for more information.

80960CA-33, -25, -16

4.4 DC Specifications

Table 15. DC Characteristic s

(80960CA-33, -25, -16 under the conditions described in Section 4.2, Operating Condition s.)

SymbolParameterMinMaxUnitsNotes

VILInput Low Voltage for all pins except RESET– 0.3+0.8V

VIHInput High Voltage for all pins except RESET2.0VCC + 0.3V

VOLOutput Low Voltage0.45VIOL = 5 mA

VOHOutput High Voltage IOH = –1 mA

IOH = – 200 µA2.4

VCC – 0.5V

VILRInput Low Voltage for RESET– 0.31.5V

VIHRInput High Voltage for RESET3.5VCC + 0.3V

ILI1Input Leakage Current for each pin except:

BTERM,ONCE,DREQ3:0, STEST,

EOP3:0/TC3:0,NMI, XINT7:0,BOFF,READY,

HOLD, CLKMODE±15 µA0≤ VIN≤VCC (1)

ILI2Input Leakage Current for:

BTERM,ONCE,DREQ3:0, STEST,

EOP3:0/TC3:0,NMI, XINT7:0,BOFF0– 300 µA VIN=0.45V(2)

ILI3Input Leakage Current for:

READY, HOLD, CLKMODE0500 µA VIN=2.4V (3,7)

ILOOutput Leakage Current±15 µA0.45 ≤ VOUT≤VCC

ICC Supply Current (80960CA-33): ICC Max

ICCTyp900

750mA

mA(4)

(5)

ICC Supply Current (80960CA-25): ICC Max

ICCTyp750

600mA

mA(4)

(5)

ICC Supply Current (80960CA-16): ICC Max

ICCTyp550

400mA

mA(4)

(5)

IONCEONCE-mode Supply Current100mA

CINInput Capacitance for:

CLKIN, RESET,ONCE,

READY, HOLD, DREQ3:0,BOFF,

XINT7:0,NMI,BTERM, CLKMODE012 pF FC = 1 MHz

COUTOutput Capacitance of each output pin12 pF FC = 1 MHz (6)

CI/OI/O Pin Capacitance12 pF FC = 1 MHz

NOTES:

1. No pullup or pulldown.

2. These pins have internal pullup resistors.

3. These pins have internal pulldown resistors.

4. Measured at worst case frequency, VCC and temperature, with device operating and outputs loaded to the test conditions described in Sec-

tion 4.5.1, AC Test Conditions.

5. ICC Typical is not tested.

6. Output Capacitance is the capacitive load of a floating output.

7. CLKMODE pin has a pulldown resistor only when ONCE pin is deasserted.

80960CA-33, -25, -16

4.5 AC Specifications

Table 16. 80960CA AC Characteristics (33 MHz)

(80960CA-33 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test

Conditions.)

SymbolParameterMinMaxUnitsNotes

Input Clock (1,9)

TFCLKIN Frequency066.66MHz

TCCLKIN Period In 1-x Mode (f CLK1x)

In 2-x Mode (f CLK2x)30

15 125

∞ns

ns(11)

TCSCLKIN Period Stability In 1-x Mode (f CLK1x)±0.1%∆(12)

TCH CLKIN High Time In 1-x Mode (f CLK1x)

In 2-x Mode (f CLK2x)6

662.5

∞ns

ns(11)

TCLCLKIN Low Time In 1-x Mode (f CLK1x)

In 2-x Mode (f CLK2x)6

662.5

∞ns

ns(11)

TCR CLKIN Rise Time 0 6 ns

TCFCLKIN Fall Time 0 6 ns

Output Clocks (1,8)

TCPCLKIN to PCLK2:1 Delay In 1-x Mode (f CLK1x)

In 2-x Mode (f CLK2x)– 2

25 ns

ns(3,12)

(3)

TPCLK2:1 Period In 1-x Mode (f CLK1x)

In 2-x Mode (f CLK2x)TC

2TCns

ns(12)

(3)

TPHPCLK2:1 High Time(T/2) – 2T/2 ns(12)

TPLPCLK2:1 Low Time(T/2) – 2T/2 ns(12)

TPRPCLK2:1 Rise Time 1 4 ns(3)

TPFPCLK2:1 Fall Time 1 4 ns(3)

Synchronous Outputs (8)

TOH

TOVOutput Valid Delay, Output Hold

TOH1, TOV1 A31:2

TOH2, TOV2 BE3:0

TOH3, TOV3 ADS

TOH4, TOV4 W/R

TOH5, TOV5 D/C,SUP,DMA

TOH6, TOV6 BLAST,WAIT

TOH7, TOV7 DEN

TOH8, TOV8 HOLDA, BREQ

TOH9, TOV9 LOCK

TOH10, TOV10 DACK3:0

TOH11, TOV11 D31:0

TOH12, TOV12 DT/R

TOH13, TOV13 FAIL

TOH14, TOV14 EOP3:0/TC3:0

T/2 + 3

T/2 + 14

(6,10)

TOFOutput Float for all outputs3 22 ns(6)

Synchronous Inputs (1,9,10)

TISInput Setup

TIS1D31:0

TIS2BOFF

TIS3BTERM/READY

TIS4HOLD

TIHInput Hold

TIH1D31:0

TIH2BOFF

TIH3BTERM/READY

TIH4HOLD

80960CA-33, -25, -16

Relative Output Timings (1,2,3,8)

TAVSH1A31:2 Valid to ADS RisingT – 4T + 4 ns

TAVSH2BE3:0, W/R,SUP, D/C,

DMA,DACK3:0 Valid to ADS RisingT – 6T + 6 ns

TAVEL1A31:2 Valid to DEN FallingT – 4T + 4 ns

TAVEL2BE3:0, W/R,SUP,INST,

DMA,DACK3:0 Valid to DEN FallingT – 6T + 6 ns

TNLQVWAIT Falling to Output Data Valid±4 ns

TDVNHOutput Data Valid to WAIT RisingN*T – 4N*T + 4 ns(4)

TNLNHWAIT Falling to WAIT RisingN*T ± 4 ns(4)

TNHQXOutput Data Hold after WAIT Rising(N+1)*T–8(N+1)*T+6 ns(5)

TEHTVDT/R Hold after DEN HighT/2 – 7∞ns(6)

TTVELDT/R Valid to DEN FallingT/2 – 4 ns

Relative Input Timings (1,2,3)

TIS5RESET Input Setup (2-x Clock Mode)6 ns(13)

TIH5RESET Input Hold (2-x Clock Mode)5 ns(13)

TIS6DREQ3:0 Input Setup 12 ns(7)

TIH6DREQ3:0 Input Hold 7 ns(7)

TIS7XINT7:0,NMI Input Setup 7 ns(15)

TIH7XINT7:0,NMI Input Hold 3 ns(15)

TIS8RESET Input Setup (1-x Clock Mode)3 ns(14)

TIH8RESET Input Hold (1-x Clock Mode)T/4 + 1 ns(14)

NOTES:

1. See Section 4.5.2, AC Timing Waveforms for waveforms and definitions.

2. See Figure 16 for capacitive derating information for output delays and hold times.

3. See Figure 17 for capacitive derating information for rise and fall times .

4. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus Controller Region Table.WAIT never goes

active when there are no wait states in an access.

5. N = Number of wait states inserted with READY.

6. Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity.

7. Since asynchronous inputs are synchronized internally by the 80960CA, they have no required setup or hold times to be recognized and for

proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1, the setup times shown must be met. Asyn-

chronous inputs must be active for at least two consecutive PCLK2:1 rising edges to be seen by the processor.

8. These specifications are guaranteed by the processor.

9. These specifications must be met by the system for proper operation of the processor.

10. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating Curves to adjust the timing for

PCLK2:1 loading.

11. In the 1-x input clock mode, the maximum input clock period is limited to 125ns while the processor is operating. When the processor is in

reset, the input clock may stop even in 1-x mode.

12. When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than ± 0.1% between adja-

cent cycles.

13. In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee

the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the falling edge of the

CLKIN. (See Figure 22.)

14. In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee

the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the rising edge of the CLKIN.

(See Figure 23.)

15. The interrupt pins are synchronized internally by the 80960CA. They have no required setup or hold times for proper operation. These pins

are sampled by the interrupt controller every other clock and must be active for at least three consecutive PCLK2:1 rising edges when assert-

ing them asynchronously. To guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consecu-

tive PCLK2:1 rising edges.

Table 16. 80960CA AC Characteristics (33 MHz) (Continued)

(80960CA-33 only, under the conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test

Conditions.)

SymbolParameterMinMaxUnitsNotes

80960CA-33, -25, -16

Table 17. 80960CA AC Characteristics (25 MHz)

(80960CA-25 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test

Conditions.)

SymbolParameterMinMaxUnitsNotes

Input Clock (1,9)

TFCLKIN Frequency050MHz

TCCLKIN Period In 1-x Mode (f CLK1x)

In 2-x Mode (f CLK2x)40

20 125

∞ns

ns(11)

TCSCLKIN Period Stability In 1-x Mode (f CLK1x)±0.1%∆(12)

TCH CLKIN High Time In 1-x Mode (f CLK1x)

In 2-x Mode (f CLK2x)8

862.5

∞ns

ns(11)

TCLCLKIN Low Time In 1-x Mode (f CLK1x)

In 2-x Mode (f CLK2x)8

862.5

∞ns

ns(11)

TCR CLKIN Rise Time 0 6 ns

TCFCLKIN Fall Time 0 6 ns

Output Clocks (1,8)

TCPCLKIN to PCLK2:1 Delay In 1-x Mode (f CLK1x)

In 2-x Mode (f CLK2x)– 2

25ns

ns(3,12)

(3)

TPCLK2:1 Period In 1-x Mode (f CLK1x)

In 2-x Mode (f CLK2x)TC

2TCns

ns(12)

(3)

TPHPCLK2:1 High Time(T/2) – 3T/2 ns(12)

TPLPCLK2:1 Low Time(T/2) – 3T/2 ns(12)

TPRPCLK2:1 Rise Time 1 4 ns(3)

TPFPCLK2:1 Fall Time 1 4 ns(3)

Synchronous Outputs (8)

TOH

TOVOutput Valid Delay, Output Hold

TOH1, TOV1 A31:2

TOH2, TOV2 BE3:0

TOH3, TOV3 ADS

TOH4, TOV4 W/R

TOH5, TOV5 D/C,SUP,DMA

TOH6, TOV6 BLAST,WAIT

TOH7, TOV7 DEN

TOH8, TOV8 HOLDA, BREQ

TOH9, TOV9 LOCK

TOH10, TOV10 DACK3:0

TOH11, TOV11 D31:0

TOH12, TOV12 DT/R

TOH13, TOV13 FAIL

TOH14, TOV14 EOP3:0/TC3:0

T/2 + 3

T/2 + 16

(6,10)

TOFOutput Float for all outputs322 ns(6)

Synchronous Inputs (1,9,10)

TISInput Setup

TIS1D31:0

TIS2BOFF

TIS3BTERM/READY

TIS4HOLD

TIHInput Hold

TIH1D31:0

TIH2BOFF

TIH3BTERM/READY

TIH4HOLD

80960CA-33, -25, -16

Relative Output Timings (1,2,3,8)

TAVSH1A31:2 Valid to ADS RisingT – 4T + 4 ns

TAVSH2BE3:0, W/R,SUP, D/C,

DMA,DACK3:0 Valid to ADS RisingT – 6T + 6 ns

TAVEL1A31:2 Valid to DEN FallingT – 4T + 4 ns

TAVEL2BE3:0, W/R,SUP,INST,

DMA,DACK3:0 Valid to DEN FallingT – 6T + 6 ns

TNLQVWAIT Falling to Output Data Valid±4 ns

TDVNHOutput Data Valid to WAIT RisingN*T – 4N*T + 4 ns(4)

TNLNHWAIT Falling to WAIT RisingN*T ± 4 ns(4)

TNHQXOutput Data Hold after WAIT Rising(N+1)*T–8(N+1)*T+6 ns(5)

TEHTVDT/R Hold after DEN HighT/2 – 7∞ns(6)

TTVELDT/R Valid to DEN FallingT/2 – 4 ns

Relative Input Timings (1,2,3)

TIS5RESET Input Setup (2-x Clock Mode)8 ns(13)

TIH5RESET Input Hold (2-x Clock Mode)7 ns(13)

TIS6DREQ3:0 Input Setup 14 ns(7)

TIH6DREQ3:0 Input Hold 9 ns(7)

TIS7XINT7:0,NMI Input Setup 9 ns(15)

TIH7XINT7:0,NMI Input Hold 5 ns(15)

TIS8RESET Input Setup (1-x Clock Mode)3 ns(14)

TIH8RESET Input Hold (1-x Clock Mode)T/4 + 1 ns(14)

NOTES:

1. See Section 4.5.2, AC Timing Waveforms for waveforms and definitions.

2. See Figure 16 for capacitive derating information for output delays and hold times.

3. See Figure 17 for capacitive derating information for rise and fall times .

4. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus Controller Region Table.WAIT never goes

active when there are no wait states in an access.

5. N = Number of wait states inserted with READY.

6. Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity.

7. Since asynchronous inputs are synchronized internally by the 80960CA, they have no required setup or hold times to be recognized and for

proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1, the setup times shown must be met. Asyn-

chronous inputs must be active for at least two consecutive PCLK2:1 rising edges to be seen by the processor.

8. These specifications are guaranteed by the processor.

9. These specifications must be met by the system for proper operation of the processor.

10. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating Curves to adjust the timing for

PCLK2:1 loading.

11. In the 1-x input clock mode, the maximum input clock period is limited to 125ns while the processor is operating. When the processor is in

reset, the input clock may stop even in 1-x mode.

12. When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than ± 0.1% between adja-

cent cycles.

13. In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee

the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the falling edge of the

CLKIN. (See Figure 22.)

14. In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee

the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the rising edge of the CLKIN.

(See Figure 23.)

15. The interrupt pins are synchronized internally by the 80960CA. They have no required setup or hold times for proper operation. These pins

are sampled by the interrupt controller every other clock and must be active for at least three consecutive PCLK2:1 rising edges when assert-

ing them asynchronously. To guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consecu-

tive PCLK2:1 rising edges.

Table 17. 80960CA AC Characteristics (25 MHz) (Continued)

(80960CA-25 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test

Conditions.)

SymbolParameterMinMaxUnitsNotes

80960CA-33, -25, -16

Table 18. 80960CA AC Characteristics (16 MHz)

(80960CA-16 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.)

SymbolParameterMinMaxUnitsNotes

Input Clock (1,9)

TFCLKIN Frequency0 32 MHz

TCCLKIN Period In 1-x Mode (f CLK1x)

In 2-x Mode (f CLK2x)62.5

31.25125

∞ns

ns(11)

TCSCLKIN Period Stability In 1-x Mode (f CLK1x)±0.1%∆(12)

TCH CLKIN High Time In 1-x Mode (f CLK1x)

In 2-x Mode (f CLK2x)10

10 62.5

∞ns

ns(11)

TCLCLKIN Low Time In 1-x Mode (f CLK1x)

In 2-x Mode (f CLK2x)10

10 62.5

∞ns

ns(11)

TCR CLKIN Rise Time 0 6 ns

TCFCLKIN Fall Time 0 6 ns

Output Clocks (1,8)

TCPCLKIN to PCLK2:1 Delay In 1-x Mode (f CLK1x)

In 2-x Mode (f CLK2x)– 2

25 ns

ns(3,12)

(3)

TPCLK2:1 Period In 1-x Mode (f CLK1x)

In 2-x Mode (f CLK2x)TC

2TCns

ns(12)

(3)

TPHPCLK2:1 High Time(T/2) – 4T/2 ns(12)

TPLPCLK2:1 Low Time(T/2) – 4T/2 ns(12)

TPRPCLK2:1 Rise Time 1 4 ns(3)

TPFPCLK2:1 Fall Time 1 4 ns(3)

Synchronous Outputs (8)

TOH

TOVOutput Valid Delay, Output Hold

TOH1, TOV1 A31:2

TOH2, TOV2 BE3:0

TOH3, TOV3 ADS

TOH4, TOV4 W/R

TOH5, TOV5 D/C,SUP,DMA

TOH6, TOV6 BLAST,WAIT

TOH7, TOV7 DEN

TOH8, TOV8 HOLDA, BREQ

TOH9, TOV9 LOCK

TOH10, TOV10 DACK3:0

TOH11, TOV11 D31:0

TOH12, TOV12 DT/R

TOH13, TOV13 FAIL

TOH14, TOV14 EOP3:0/TC3:0

T/2 + 3

T/2 + 18

(6,10)

TOFOutput Float for all outputs3 22 ns(6)

Synchronous Inputs (1,9,10)

TISInput Setup

TIS1D31:0

TIS2BOFF

TIS3BTERM/READY

TIS4HOLD

TIHInput Hold

TIH1D31:0

TIH2BOFF

TIH3BTERM/READY

TIH4HOLD

80960CA-33, -25, -16

Relative Output Timings (1,2,3,8)

TAVSH1A31:2 Valid to ADS RisingT – 4T + 4 ns

TAVSH2BE3:0, W/R,SUP, D/C,

DMA,DACK3:0 Valid to ADS RisingT – 6T + 6 ns

TAVEL1A31:2 Valid to DEN FallingT – 6T + 6 ns

TAVEL2BE3:0, W/R,SUP,INST,

DMA,DACK3:0 Valid to DEN FallingT – 6T + 6 ns

TNLQVWAIT Falling to Output Data Valid±4 ns

TDVNHOutput Data Valid to WAIT RisingN*T – 4N*T + 4 ns(4)

TNLNHWAIT Falling to WAIT RisingN*T ± 4 ns(4)

TNHQXOutput Data Hold after WAIT Rising(N+1)*T–8(N+1)*T+6 ns(5)

TEHTVDT/R Hold after DEN HighT/2 – 7∞ns(6)

TTVELDT/R Valid to DEN FallingT/2 – 4 ns

Relative Input Timings (1,2,3)

TIS5RESET Input Setup (2-x Clock Mode)10 ns(13)

TIH5RESET Input Hold (2-x Clock Mode)9 ns(13)

TIS6DREQ3:0 Input Setup 16 ns(7)

TIH6DREQ3:0 Input Hold 11 ns(7)

TIS7XINT7:0,NMI Input Setup 9 ns(15)

TIH7XINT7:0,NMI Input Hold 5 ns(15)

TIS8RESET Input Setup (1-x Clock Mode)3 ns(14)

TIH8RESET Input Hold (1-x Clock Mode)T/4 + 1 ns(14)

NOTES:

1. See Section 4.5.2, AC Timing Waveforms for waveforms and definitions.

2. See Figure 16 for capacitive derating information for output delays and hold times.

3. See Figure 17 for capacitive derating information for rise and fall times .

4. Where N is the number of NRAD, NRDD, NWAD or NWDD wait states that are programmed in the Bus Controller Region Table.WAIT never goes

active when there are no wait states in an access.

5. N = Number of wait states inserted with READY.

6. Output Data and/or DT/R may be driven indefinitely following a cycle if there is no subsequent bus activity.

7. Since asynchronous inputs are synchronized internally by the 80960CA, they have no required setup or hold times to be recognized and for

proper operation. However, to guarantee recognition of the input at a particular edge of PCLK2:1, the setup times shown must be met. Asyn-

chronous inputs must be active for at least two consecutive PCLK2:1 rising edges to be seen by the processor.

8. These specifications are guaranteed by the processor.

9. These specifications must be met by the system for proper operation of the processor.

10. This timing is dependent upon the loading of PCLK2:1. Use the derating curves of Section 4.5.3, Derating Curves to adjust the timing for

PCLK2:1 loading.

11. In the 1-x input clock mode, the maximum input clock period is limited to 125ns while the processor is operating. When the processor is in

reset, the input clock may stop even in 1-x mode.

12. When in the 1-x input clock mode, these specifications assume a stable input clock with a period variation of less than ± 0.1% between adja-

cent cycles.

13. In 2-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee

the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the falling edge of the CLKIN.

(See Figure 22.)

14. In 1-x clock mode, RESET is an asynchronous input which has no required setup and hold time for proper operation. However, to guarantee

the device exits reset synchronized to a particular clock edge, the RESET pin must meet setup and hold times to the rising edge of the CLKIN.

(See Figure 23.)

15. The interrupt pins are synchronized internally by the 80960CA. They have no required setup or hold times for proper operation. These pins are

sampled by the interrupt controller every other clock and must be active for at least three consecutive PCLK2:1 rising edges when asserting

them asynchronously. To guarantee recognition at a particular clock edge, the setup and hold times shown must be met for two consecutive

PCLK2:1 rising edges.

Table 18. 80960CA AC Characteristics (16 MHz) (Continued)

(80960CA-16 only, under conditions described in Section 4.2, Operating Conditions and Section 4.5.1, AC Test Conditions.)

SymbolParameterMinMaxUnitsNotes

80960CA-33, -25, -16

4.5.1 AC Test Conditions

The AC Specifications in Section4.5 are tested with

the 50 pF load shown in Figure 7.Figure 16 shows

how timings vary with load capacitance.

Specifications are measured at the 1.5V crossing

point, unless otherwise indicated. Input waveforms

are assumed to have a rise and fall time of ≤2ns

from 0.8V to 2.0V. See Section 4.5.2, AC Timing

Waveforms for AC spec definitions, test points and

illustrations.Figure 7. AC Test Load

Output Pin

CL = 50 pF for all signals

F_CX008A

4.5.2 AC Timing Waveforms

Figure 8. Input and Output Clocks Waveform

Figure 9. CLKIN Waveform

PCLK2:1 2.4V

1.5V

1.5V 1.5V

0.45V

TCP

TPH TPL

TPR TPF

F_CX009A

CLKIN

2.0V

1.5V

0.8V

TCF

TCH TCL

TCR

F_CX010A

80960CA-33, -25, -16

Figure 10. Output Delay and Float Waveform

Figure 11. Input Setup and Hold Wavefor m

PCLK2:1

Outputs

1.5V

TOV

Min Max

TOH

Min Max

TOF

1.5V 1.5V

1.5V

Outputs

F_CX011A

PCLK2:1

Inputs:

1.5V1.5V1.5V

Valid

TIS TIH

(READY, HOLD, BTERM,

BOFF,DREQ3:0,

D31:0 on reads)

F_CX012A

Min Max

TOV TOH - OUTPUT DELAY - The maximum output delay is referred to

as the Output Valid Delay (TOV). The minimum output delay is

referred to as the Output Hold (TOH).

TOF- OUTPUT FLOAT DELAY - The output float condition occurs

when the maximum output current becomes less that ILO in magnitude.

TIS TIH- INPUT SETUP AND HOLD - The input setup and hold requirements

specify the sampling window during which synchronous inputs must be

stable for correct processor operation.

80960CA-33, -25, -16

Figure 12. NMI, XINT7:0 Input Setup and Hold Waveform

Figure 13. Hold Acknowledge Timings

PCLK2:1 1.5V1.5V1.5V

Valid

TIS TIH

NMI, XINT7:0

Min Min

F_CX013A

1.5V

PCLK2:1 1.5V

1.5V 1.5V

Outputs:

A31:2, D31:0, BE3:0,

ADS,BLAST,WAIT, W/R,

DT/R,DEN,LOCK,

D/C,SUP,DMA

Min Max Min Max

Valid 1.5V Valid

TOF TOV

HOLD

TIS

TIH

1.5V 1.5V 1.5V

TIH TIS

HOLDA

TOV

Min

Min Min

Min

TOV

MaxMin MaxMin

TOV TOH - OUTPUT DELAY - The maximum output delay is referred to

as the Output Valid Delay (TOV). The minimum output delay is

referred to as the Output Hold (TOH).

TOF- OUTPUT FLOAT DELAY - The output float condition occurs

when the maximum output current becomes less that ILO in magnitude.

TIS TIH- INPUT SETUP AND HOLD - The input setup and hold requirements

specify the sampling window during which synchronous inputs must be

stable for correct processor operation.

F_CX014A

1.5V 1.5V 1.5V

80960CA-33, -25, -16

Figure 14. Bus Backoff (BOFF) Timings

PCLK2:1 1.5V

1.5V 1.5V

Outputs:

A31:2, D31:0, BE3:0,

ADS,BLAST,WAIT, W/R,

DT/R,DEN,LOCK,

D/C,SUP,DMA

Min

Max

Min

Max

Valid 1.5V Valid

TOF TOV

BOFF

TIS

TIH

1.5V 1.5V 1.5V

TIH TIS

F_CX015A

1.5V

80960CA-33, -25, -16

Figure 15. Relative Timings Waveforms

4.5.3 Derating Curves

Figure 16. Output Delay or Hold vs. Load Capacitance

PCLK2:1 1.5V

1.5V 1.5V

1.5V

1.5V 1.5V

1.5V

TAVSH

TDVHN TNHQX

TNLNH

TAVEL

TVEL

TEHTV

TNLQV

ADS

A31:2, BE3:0,

W/R,LOCK,

SUP, D/C,DMA

D31:0

WAIT

DT/R

DEN

D31:0

F_CX016A

1.5V

In VIH

VIL

Out

50 100 150

CL(pF)

nom + 10

nom + 5

nom

All outputs except: LOCK,

EOP3:0/TC3:0,FAIL

F_CX017A

DMA,SUP, BREQ, DACK3:0,

Note: PCLK Load = 50pF

Output Valid Delays (ns) @ 1.5V

LOCK,DMA,SUP, BREQ,

DACK3:0,EOP3:0/TC3:0,FAIL

80960CA-33, -25, -16

Figure 17. Rise and Fall Time Derating at Highest Operating Temperature and Minimum VCC

Figure 18. ICC vs. Frequency and Temperature

50 100 150

Time (ns)

CL(pF)

50 100 150

Time (ns)

CL(pF)

a) All outputs except: LOCK,DMA,SUP, HOLDA, BREQ

DACK3:0,EOP3:0/TC3:0,FAIL b) LOCK,DMA,SUP, HOLDA, BREQ, DACK3:0,

EOP3:0/TC3:0,FAIL

0.8V to 2.0V

F_CX019A

900

0033

TC = 100° C

TC = 0° C

fPCLK (MHz)

ICC (mA)

ICC - ICC under test conditions

F_CX020A

80960CA-33, -25, -16

5.0 RESET, BACKOFF AND HOLD

ACKNOWLEDGE

Table 19 lists the condition of each processor output

pin while RESET is asserted (low) .

Table 19. Reset Conditions

PinsState During Reset

(HOLDA inactive)1

A31:2Floating

D31:0Floating

BE3:0Driven high (Inactive)

W/RDriven low (Read)

ADSDriven high (Inactive)

WAITDriven high (Inactive)

BLASTDriven low (Active)

DT/RDriven low (Receive)

DENDriven high (Inactive)

LOCKDriven high (Inactive)

BREQDriven low (Inactive)

D/CFloating

DMAFloating

SUPFloating

FAILDriven low (Active)

DACK3:0Driven high (Inactive)

EOP3:0/TC3:0Floating (Set to input mode)

NOTES:

1. With regard to bus output pin state only, the Hold

Acknowledge state takes precedence over the reset

state. Although asserting the RESET pin will internally

reset the processor, the processor’s bus output pins

will not enter the reset state if it has granted Hold

Acknowledge to a previous HOLD request (HOLDA is

active). Furthermore, the processor will grant new

HOLD requests and enter the Hold Acknowledge state

even while in reset.

For example, if HOLDA is inactive and the processor is

in the reset state, then HOLD is asserted, the proces-

sor’s bus pins enter the Hold Acknowledge state and

HOLDA is granted. The processor will not be able to

perform memory accesses until the HOLD request is

removed, even if the RESET pin is brought high. This

operation is provided to simplify boot-up synchroniza-

tion among multiple processors sharing the same bus.

Table 20 lists the condition of each processor output

pin while HOLDA is asserted (low).

Table 20. Hold Acknowledge

and Backoff Conditions

PinsState During HOLDA

A31:2Floating

D31:0Floating

BE3:0Floating

W/RFloating

ADSFloating

WAITFloating

BLASTFloating

DT/RFloating

DENFloating

LOCKFloating

BREQDriven (High or low)

D/CFloating

DMAFloating

SUPFloating

FAILDriven high (Inactive)

DACK3:0Driven high (Inactive)

EOP3:0/TC3:0Driven (If output)

80960CA-33, -25, -16

6.0 BUS WAVEFORMS

Figure 19. Cold Reset Waveform

CLKIN

PCLK2:1

ADS,

W/R, DT/R,

INST, SUP,

D31:0,

STEST

RESET

VCC - ONCE

BLAST

LOCK, WAIT,

DEN, DACK3:0

BREQ, FAIL

DMA, A31:2,

D/C, BE3:0

EOP/TC3:0

∼

∼∼

∼

∼∼

∼

∼∼

∼

Invalid

Valid

∼

∼∼

∼

CLKIN and VCC Stable to RESET high,

32 CLKIN Periods in 2x Mode,

periods in 1x Mode.

∼

Inputs

Tdelay

1 PCLK

Tsetup

1PCLK Thold

1 PCLK

∼

∼∼

∼

∼∼

∼

minimum

10,000 CLKIN

F_CX021A

∼

RESET high to First Bus

activity, approximately

32 PCLK periods.

VCC and CLKIN Stable

to Outputs Valid, maximum

32 CLKIN Periods.

80960CA-33, -25, -16

Figure 20. Warm Reset Wavefor m

Tdelay

1PCLK

∼

∼∼

∼

∼∼

∼

Maximum RESET Low to RESET State

4 PCLK Periods 1 PCLK

∼

∼∼

∼

∼∼

∼

F_CX022A

PCLK2:1

ADS,

W/R, DT/R,

SUP,

D31:0,

STEST

RESET

BLAST

LOCK, WAIT,

DEN, DACK3:0

BREQ, FAIL

DMA, A31:2,

D/C, BE3:0

EOP/TC3:0

Valid

∼

∼∼

∼

Thold

Tsetup

1 PCLK

RESET High to First Bus Activity,

Approximately 32 PCLK Periods

Minimum RESET Low Time

16 PCLK Periods

∼

80960CA-33, -25, -16

Figure 21. Entering the ONCE Stat e

CLKIN

PCLK2:1

ADS, BE3:0, A31:2,

RESET

ONCE

∼

∼∼

∼

VCC and CLKIN Stable

to Outputs Valid, maximum

32 CLKIN Periods.

∼

CLKIN and VCC Stable and RESET low and ONCE low to

RESET high, minimum 32 CLKIN Periods in 2x Mode,

10,000 CLKIN Periods in 1x Mode.

∼

D31:0, LOCK, WAIT,

BLAST,W/R, D/C, DEN,

DT/R, HOLD, HOLDA,

DMA, EOP3:0/TC3:0,

STEST, XINT7:0, NMI,

DACK3:0, DREQ3:0

READY, BTERM

BLAST, FAIL, SUP,BREQ,

∼

∼∼

∼

∼∼

∼

Maximum 32 CLKIN Periods

Required after ONCE Mode entered

VCC

∼

∼∼

∼

F_CX023A

∼

CLKIN may not float. It must be

driven high or low or continue to run

80960CA-33, -25, -16

Figure 22. Clock Synchronization in the 2-x Clock Mode

Figure 23. Clock Synchronization in the 1-x Clock Mode

CLKIN

RESET

PCLK2:1

(Case 1)

PCLK2:1

(Case 2)

1.5V

TIH TIS

1.5V

1.5V1.5V

1.5V 1.5V

TCP

Max

Min TCP

Max

Min TCP

SYNC

Note: Case 1 and Case 2 show two possible polarities of PCLK2:1

Min

1.5V

F_CX024A

Max

CLKIN 1.5V1.5V

RESET

TIH TIS

1.5V

2x CLK

Note: In 1x clock mode, the RESET pin is actually sampled on the falling edge of 2xCLK. 2xCLK is an internal signal

generated by the PLL and is not available on an external pin. Therefore, RESET is specified relative to the rising

edge of CLKIN. The RESET pin is sampled when PCLK is high.

F_CX025A

80960CA-33, -25, -16

Figure 24. Non-Burst, Non-Pipelined Requests Without Wait State s

ADS

A31:4, SUP,

DMA, D/C,

BE3:0,LOCK

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

ADADAD

Valid Valid Valid

Valid Valid

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 210

xx X

xx 0

00000 X

xx 0

00000 OFF

0Disabled

0..0 Disabled

Valid

F_CX026A

Out

Function

Bit

Value

80960CA-33, -25, -16

Figure 25. Non-Burst, Non-Pipelined Read Request With Wait States

ADS

A31:2,BE3:0

DMA, D/C,

SUP,LOCK

W/R

BLAST

DT/R

DEN

WAIT

D31:0

PCLK

A32 1 D1

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

xx X

xxxxx X

xx 3

00011 OFF

0Disabled

0..0 Disabled

Function

Bit

Value

Valid

F_CX027A

80960CA-33, -25, -16

Figure 26. Non-Burst, Non-Pipelined Write Request With Wait States

ADS

A31:2,

W/R

BLAST

DT/R

DEN

SUP,DMA,

WAIT

D31:0

PCLK

A3 2 1 D1

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

xx X

xx 3

00011 X

xx X

xxxxxx OFF

0Disabled

0..0 Disabled

Out

Function

Bit

Value

Valid

D/C,LOCK

F_CX028A

BE3:0

80960CA-33, -25, -16

Figure 27. Burst, Non-Pipelined Read Request Without Wait States, 32-Bit Bus

In0

ADS

A31:4, SUP,

DMA, D/C,

BE3:0,LOCK

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

ADD D DA

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

32-Bit

10 X

xx X

xxxxx 0

00 0

00000 OFF

0Enabled

0..0 Disabled

F_CX029A

Function

Bit

Value

In3In2In1

Valid

00 01 10 11

80960CA-33, -25, -16

Figure 28. Burst, Non-Pipelined Read Request With Wait States, 32-Bit Bus

ADS

A31:4, SUP,

DMA, D/C,

BE3:0,LOCK

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

32-bit

10 X

xx X

xxxxx 1

01 2

00010 OFF

0Enabled

0..0 Disabled

A2 1 D1D1D1D1A

In1 In2 In3

In0

Valid

00 1101 10

Function

Bit

Value

F_CX030A

80960CA-33, -25, -16

Figure 29. Burst, Non-Pipelined Write Request Without Wait States, 32-Bit Bus

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 210

32-bit

10 0

00 0

00000 X

xx X

xxxxx OFF

0Enabled

0..0 Disabled

ADS

A31:4, SUP,

DMA, D/C,

BE3:0,LOCK

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

ADD D D A

Function

Bit

Value

00 01 10 11

Out0

Valid

Out3Out2Out1

F_CX031A

80960CA-33, -25, -16

Figure 30. Burst, Non-Pipelined Write Request With Wait States, 32-Bit Bus

ADS

A31:4, SUP,

DMA, D/C,

BE3:0,LOCK

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

32-bit

10 1

01 2

00010 X

xx X

xxxxx OFF

0Enabled

0..0 Disabled

A2 1 D1D1D1D1A

Out0

Valid

00 1101 10

Function

Bit

Value

Out1 Out2 Out3

F_CX032A

80960CA-33, -25, -16

Figure 31. Burst, Non-Pipelined Read Request With Wait States, 16-Bit Bus

ADS

SUP,DMA,

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

16-bit

01 X

xx X

xxxxx 1

01 2

00010 OFF

0Enabled

0..0 Disabled

A2 1 D1D1D1D1A

Function

Bit

Value

Valid

A3:2 = 00 or 10 A3:2 = 01 or 11

D15:0

A1=0 D15:0

A1=1 D15:0

A1=0 D15:0

A1=1

D/C,LOCK,

A31:4, BE3/BHE,

BE1/A1

BE0/BLE

F_CX033A

80960CA-33, -25, -16

Figure 32. Burst, Non-Pipelined Read Request With Wait States, 8-Bit Bus

ADS

SUP,DMA,

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

8-bit

00 X

xx X

xxxxx 1

01 2

00010 OFF

0Enabled

0..0 Disabled

A2 1 D1D1D1D1A

Function

Bit

Value

Valid

A3:2 = 00, 01, 10 or 11

D7:0

Byte 0 D7:0

Byte 1 D7:0

Byte 2 D7:0

Byte 3

D/C,LOCK,

A31:4

BE1/A1, A1:0 = 00 A1:0 = 01 A1:0 = 10 A1:0 =11

BE0/A0

F_CX034A

80960CA-33, -25, -16

Figure 33. Non-Burst, Pipelined Read Request Without Wait States, 32-Bit Bus

Non-Pipelined Request Concludes

Pipelined Reads Begin. Pipelined Reads Conclude,

Non-Pipelined Requests Begin.

ADS

A31:4, SUP,

DMA, D/C,

LOCK

BLAST

WAIT

D31:0

PCLK

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 210

xx X

xxxxx X

xx 0

00000 ON

1Disabled

0..0 X

Function

Bit

Value

DIN

D' IN

D'' IN

D''' IN

D''''

AA'

DA''

D' A'''

D'' A''''

D''' D''''

Valid Valid Valid Valid Valid Invalid

Invalid

DT/R

DEN

A3:2

BE3:0 Valid Valid Valid Valid Valid Invalid

W/R

F_CX035A

80960CA-33, -25, -16

Figure 34. Non-Burst, Pipelined Read Request With Wait States, 32-Bit Bus

Non-Pipelined Request Concludes

Pipelined Reads Begin. Pipelined Reads Conclude,

Non-Pipelined Requests Begin.

ADS

A31:4, SUP,

DMA, D/C,

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

BE3:0

A1A'

D1D'

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 210

xx X

xxxxx X

xx 1

00001 ON

1Disabled

0..0 X

Invalid

Valid Valid Invalid

LOCK Valid Valid Invalid

Function

Bit

Value

F_CX036A

80960CA-33, -25, -16

Figure 35. Burst, Pipelined Read Request Without Wait States, 32-Bit Bus

Pipelined Reads

Conclude, Non-Pipelined

Requests Begin

ADS

A31:4, SUP,

DMA, D/C,

BE3:0,LOCK

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

PCLK

Non-pipelined Request

Concludes, Pipelined

Reads Begin

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

32-bit

10 X

xx X

xxxxx 0

00 0

00000 ON

1Enabled

0..0 Disabled

ADDDA' D'D'

Valid Valid

In-

ValidValid01 10 1100

DIN

Valid

Function

Bit

Value

In-

Valid

In-

Valid

F_CX037A

80960CA-33, -25, -16

Figure 36. Burst, Pipelined Read Request With Wait States, 32-Bit Bus

ADS

A31:4, SUP,

DMA, D/C,

BE3:0,LOCK

W/R

A3:2

D31:0

WAIT

BLAST

DT/R

DEN

PCLK

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

32-bit

10 X

xx X

xxxxx 1

01 2

00010 ON

1Enabled

0..0 Disabled

Function

Bit

Value

DIN

A2 1 D1D1D1A' 2 1

Valid

DD'

Valid In-

valid

In-

valid

00 01 10 11 Valid In-

valid

Non-pipelined request concludes,

pipelined reads begin. Pipelined reads conclude,

Non-pipelined requests begin.

F_CX038A

80960CA-33, -25, -16

Figure 37. Burst, Pipelined Read Request With Wait States, 16-Bit Bus

ADS

A31:4, SUP,

DMA, D/C,

BE0/BLE,

W/R

A3:2

BE1/A1

WAIT

BLAST

DT/R

DEN

PCLK

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 210

16-bit

10 X

xx X

xxxxx 1

01 2

00010 ON

1Enabled

0..0 Disabled

Function

Bit

Value

D15:0

A1=0 D15:0

A1=1 D15:0

A1=0 D15:0

A1=1 D15:0

A2 1 D1D1D1A' 2 1

DD'

In-

valid

Non-pipelined request concludes,

pipelined reads begin. Pipelined reads conclude,

Non-pipelined requests begin.

A3:2 = 00 or 10 A3:2 = 01 or 11 Valid In-

valid

Valid In-

valid

BE3/BHE,

D31:0

F_CX040A

LOCK

Valid Valid In-

valid

80960CA-33, -25, -16

Figure 38. Burst, Pipelined Read Request With Wait States, 8-Bit Bus

ADS

A31:4, SUP,

DMA, D/C,

LOCK

W/R

A3:2

BE1/A1,

WAIT

BLAST

DT/R

DEN

PCLK

reserved

Byte

Order Bus

Width NWDD NWAD NXDA NRDD NRAD Pipe-

Lining External

Ready

Control Burst

reserved

31-23 22 18-1721 20-19 16-12 7-311-10 9-8 2 1 0

8-bit

10 X

xx X

xxxxx 1

01 2

00010 ON

1Enabled

0..0 Disabled

Function

Bit

Value

D7:0

Byte 0 D7:0

Byte 1 D7:0

Byte 2 D7:0

Byte 3 D7:0

A2 1 D1D1D1A' 2 1

DD'

In-

valid

Non-pipelined request concludes,

pipelined reads begin. Pipelined reads conclude,

Non-pipelined requests begin.

Valid In-

valid

BE0/A0

D31:0

A3:2 = 00, 01, 10, or 11 Valid In-

valid

A1:0 = 00 A1:0 = 01 A1:0 = 10 A1:0 = 11

Valid Valid In-

valid

F_CX039A

80960CA-33, -25, -16

Figure 39. Using External READY

PCLK

ADS

A31:4, SUP,

DT/R

DEN

READY

W/R

DMA,INST,

BLAST

BTERM

A3:2

WAIT

D31:0

D/C,BE3:0,

LOCK

D0 D1 D2 D3 D0 D1 D2 D3

00 01 10 11 00 01 10 11

ValidValid

Quad-Word Read Request

NRAD = 0, NRDD = 0, NXDA = 0

Ready Enabled

Quad-Word Write Request

NWAD = 1, NWDD = 0, NWDA = 0

Ready Enabled

F_CX041A

80960CA-33, -25, -16

Figure 40. Terminating a Burst with BTERM

PCLK

ADS

A31:4, SUP,

DT/R

DEN

READY

W/R

DMA, INST,

BLAST

BTERM

A3:2

WAIT

D31:0

D/C,BE3:0,

LOCK

D0 D1 D2 D3

Valid

Quad-Word Write Request

NWAD = 0, NWDD = 0, NWDA = 0

Ready Enabled

00 01 10 11

Note:READY adds memory access time to data transfers, whether or not the

bus access is a burst access. BTERM interrupts a bus access, whether or not

the bus access has more data transfers pending. Either the READY signal or

the BTERM signal will terminate a bus access if the signal is asserted during

the last (or only) data transfer of the bus access.

See Note

F_CX042A

80960CA-33, -25, -16

Figure 41. BOFF Functional Timing

ADS

BLAST

READY

BOFF

A31:2, SUP,

D31:0,

BOFF may not

be asserted

BOFF may not

be asserted

BOFF May be asserted to suspend request

Begin Request End Request

SUSPEND REQUEST

NON-BURST

Regenerate ADS

DMA, D/C,

BE3:0,WAIT,

DEN, DT/R

(WRITES)

BURST

MAY CHANGE

RESUME REQUEST

BURST

∼

Note:READY/

BTERM must be enabled;

NRAD

NRDD

NWAD

NWDD

= 0

∼

F_CX043A

80960CA-33, -25, -16

Figure 42. HOLD Functional Timing

Word Read Request

NRAD=1, NXDA=1

Word Read

Request

NRAD=0,

NXDA=0

Hold State Hold State

PCLK2:1

ADS

A31:2, SUP,

DMA, D/C,

BE3:0,WAIT,

DEN, DT/R

BLAST

HOLD

HOLDA

ValidValid

F_CX044A

80960CA-33, -25, -16

Figure 43. DREQ and DACK Functional Timing

Figure 44. EOP Functional Timing

PCLK2:1

ADS

! (BLAST

&READY

DACKx

(All Modes)

DREQx

(Case 1)

DREQx

(Case 2)

Note:

F_CX018A

&!WAIT)

∼

High To Prevent

Next Bus Cycle

High To Prevent

Next Bus Cycle

System

Clock

Start DMA

Bus Request

End of DMA

Bus Request

DMA

Acknowledge

DMA

Request

tIS5 tIH5

(See Note)

1. Case 1: DREQ must deassert before DACK deasserts. Applications are Fly-By and some packing and

unpacking modes in which loads are followed by loads or stores are followed by stores.

2. Case 2: DREQ must be deasserted by the second clock (rising edge) after DACK is driven high.

Applications are non Fly-By transfers and adjacent load-stores or store-loads.

3. DACKx is asserted for the duration of a DMA bus request. The request may consist of multiple bus

accesses (defined by ADS and BLAST. Refer to i960 Cx Microprocessor User’s Manual for “access”,

“request” definitions.

∼

PCLK2:1

EOP

F_CX045A

∼

Note:EOP has the same AC Timing Requirements as DREQ to prevent unwanted DMA requests. EOP is NOT edge

held for a minimum of 2 clock cycles then deasserted within 15 clock cycles.

triggered. EOP must be

15 CLKs Max

2 CLKs Min

80960CA-33, -25, -16

Figure 45. Terminal Count Functional Timing

Figure 46. FAIL Functional Timin g

Note: Terminal Count becomes active during the last bus request of a buffer transfer. If the

last LOAD/STORE bus request is executed as multiple bus accesses, the TC will be active

for the entire bus request. Refer to the i960® Cx Microprocessor User’s Manual for

further information.

PCLK2

DREQ

ADS

DACK

F_CX046A

RESET

FAIL

~65,000 Cycles 5 Cycles 102 Cycles

(Bus Test)

Pass

(Internal Self-Test)

Pass

∼

Fail Fail

F_CX047A

80960CA-33, -25, -16

Figure 47. A Summary of Aligned and Unaligned Transfers for Little Endian Region s

0 4 8 12 16 20 24

0 1 2 3 4 5 6

One Double-Word

Short-Word

Load/Store

Word

Load/Store

Double-Word

Load/Store

Byte, Byte Requests

Short Request (Aligned)

Byte, Byte Requests

Word Request (Aligned)

Byte, Short, Byte, Requests

Short, Short Requests

Byte, Short, Byte Requests

Byte Offset

Word Offset

F_CX048A

One Double-Word Burst (Aligned)

Byte, Short, Word, Byte Requests

Short, Word, Short Requests

Byte, Word, Short, Byte Requests

Word, Word Requests

Request (Aligned)

80960CA-33, -25, -16

Figure 48. A Summary of Aligned and Unaligned Transfers for Little Endian Regions (Continued)

0 4 8 12 16 20 24

0 1 2 3 4 5 6

Triple-Word

Load/Store

Quad-Word

Load/Store

Word, Word,

Word Requests

Requests

Double-

Word, Word, Word,

Word Requests

Byte Offset

Word Offset

One Three-Word

Request (Aligned)

Byte, Short, Word,

Word, Byte Requests

Short Requests

Short, Word, Word,

Byte, Word, Word,

Short, Byte Requests

Word, Word,

Word Requests

One Four-Word

Request (Aligned)

Byte, Short, Word, Word,

Word, Byte Requests

Short, Word, Word, Word,

Short Requests

Byte, Word, Word, Word,

Short, Byte Requests

F_CX049A

Requests

Word,

Word

Word,

80960CA-33, -25, -16

Figure 49. Idle Bus Operation

PCLK

ADS

A31:4, SUP,

DMA, INST,

D/C,BE3:0

LOCK

W/R

BLAST

DT/R

DEN

A3:2

WAIT

D31:0

READY,

BTERM

Write Request

NWAD=2, NXDA = 0

Ready Disabled Idle Bus

(not in Hold Acknowledge state) Read Request

NWAD=2, NXDA = 0

Ready Disabled

Out

Valid

Valid Valid

F_CX050A

80960CA-33, -25, -16

7.0 REVISION HISTORY

This data sheet supersedes data sheet 270727-005. Specification changes in the 80960CA data sheet are a

result of design changes. The sections significantly changed since the previous revision are:

SectionLast

Rev.Description

Table 11. 80960CA PGA Package Thermal

Characteristics-005Removed references and notes pertaining to

θJ-CAP and θJ-PIN.

Table 12. 80960CA PQFP package Thermal

Characteristics-005Removed references and notes pertaining to θJL

and θJB.

3.3 80960CA Mechanical Data-005Removed section containing information on

Package Dimensions. Moved section header to

encompass Pinout tables and diagrams.

3.7 Suggested Sources for 80960CA

Accessories-005Removed entire section containing information

about 80960CA accessories.

Tables 16,17 and18 80960CA AC Charac-

teristics (33-, 25- and 16MHz, respectively)-005TTVEL maximum deleted.

TNHQX and TEHTV minimums changed:

WAS: IS:

TNHQX(N+1)*T-6 (N+1)*T-8

TEHTVT/2 - 6 T/2 - 7

All-005All timing diagrams and waveforms have been

redrawn to conform to consistent format.

Data sheet formatting has been changed to

conform to corporate standards. Specific

formatting changes are not itemized in this revision

history.