SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUAR Y 1990 – REVISED MAY 1999
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Meet or Exceed the Requirements of ANSI
Standards TIA/EIA-422-B and TIA/EIA-485-A
and ITU Recommendations V.10 and V.11
D
Designed for Multipoint Bus Transmission
on Long Bus Lines in Noise Environments
D
Driver Positive- and Negative-Current
Limiting
D
Thermal Shutdown Protection
D
Driver 3-State Outputs
D
Receiver Common-Mode Input Voltage
Range of –12 V to 12 V
D
Receiver Input Sensitivity...±200 mV
D
Receiver Hysteresis...50 mV Typ
D
Receiver Input Impedance...12kΩ Min
D
Receiver 3-State Outputs (SN751177 Only)
D
Operate From Single 5-V Supply
description
The SN751177 and SN751178 dual differential
drivers and receivers are monolithic integrated
circuits that are designed for balanced multipoint
bus transmission at rates up to 10 Mbit/s. They are
designed to improve the performance of
full-duplex data communications over long bus
lines and meet ANSI Standards TIA/EIA-422-B
and TIA/EIA-485-A and ITU Recommendations
V.10 and V.11.
The SN751177 and SN751178 driver outputs provide limiting for both positive and negative currents and
thermal-shutdown protection from line-fault conditions on the transmission bus line.
The receiver features high input impedance of at least 12 kΩ, an input sensitivity of ±200 mV over a
common-mode input voltage range of –12 V to 12 V, and typical input hysteresis of 50 mV. Fail-safe design
ensures that if the receiver inputs are open, the receiver outputs always will be high.
The SN751177 and SN751178 are characterized for operation from –20°C to 85°C.
Copyright 1999, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1R
RE
2R
2A
2B
GND
VCC
1D
1Y
1Z
DE
2Z
2Y
2D
SN751177 ...N OR NS
†
PACKAGE
(TOP VIEW)
†The NS package is only available taped and reeled.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1B
1A
1R
1DE
2R
2A
2B
GND
VCC
1D
1Y
1Z
2DE
2Z
2Y
2D
SN751178 ...N OR NS
†
PACKAGE
(TOP VIEW)
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUAR Y 1990 – REVISED MAY 1999
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Function Tables
SN751177, SN751178
(each driver)
INPUT ENABLE OUTPUTS
D DE Y Z
H H H L
L H L H
X L Z Z
H = high level, L = low level, X = irrelevant,
Z = high impedance (off)
SN751177
(each receiver)
DIFFERENTIAL INPUTS
A – B ENABLE
RE OUTPUT
R
VID ≥ 0.2 V L H
–0.2 V < VID < 0.2 V L ?
VID ≤ –0.2 V L L
X H Z
Open L H
H = high level, L = low level, ? = indeterminate,
X = irrelevant, Z = high impedance (off)
SN751178
(each receiver)
DIFFERENTIAL INPUTS
A – B OUTPUT
R
VID ≥ 0.2 V H
–0.2 V < VID < 0.2 V ?
VID ≤ –0.2 V L
H = high level, L = low level,
? = indeterminate
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUAR Y 1990 – REVISED MAY 1999
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
logic symbols†
SN751177
SN751178
1
1
1
1
†These symbols are in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
EN1
12
DE
EN2
4
15
1D
1R 3
9
2D
2R 5
2
2
1Y
14
1Z
13
1A
2
1B
1
2Y
10
2Z
11
2A
6
2B
7
EN
4
1DE 15
1D
1R 3
EN
12
2DE 9
2D
2R 5
1Y
14
1Z
13
1A
2
1B
1
2Y
10
2Z
11
2A
6
2B
7
RE
logic diagrams (positive logic)
RE
DE
SN751177
SN751178
12
4
15 14
13
2
1
3
910
11
6
7
5
1D
1R
2D
2R 2B
2A
2Z
2Y
1B
1A
1Z
1Y
15 14
13
1D 1Z
1Y
4
1DE
2
1
3
1R 1B
1A
910
11
2D 2Z
2Y
12
2DE
6
7
5
2R 2B
2A
schematics of inputs
EQUIVALENT OF RECEIVER INPUTEQUIVALENT OF DRIVER OR ENABLE INPUT
Input
VCC
Driver Input: R(eq) = 6 kΩ NOM
Enable Input: R(eq) = 4 kΩ NOM
R(eq) = Equivalent Resistor
Input
VCC
R(eq)
All resistor values are nominal.
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUAR Y 1990 – REVISED MAY 1999
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
schematics of outputs
TYPICAL OF ALL RECEIVER OUTPUTSTYPICAL OF ALL DRIVER OUTPUTS
Output
85 Ω
NOM
VCC
GND
Output
VCC
All resistor values are nominal.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage, VCC (see Note 1) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI (DE, RE, and D inputs) 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver input voltage range, VI (A or B inputs) –25 V to 25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver differential input voltage range, V ID (see Note 2) –25 V to 25 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Driver output voltage range, VO –10 V to 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Receiver low-level output current, IOL 50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Package thermal impedance, θJA (see Note 3): N package 78°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
NS package 111°C/W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTES: 1. All voltage values, except differential input voltage, are with respect to the network ground terminal.
2. Differential input voltage is measured at the noninverting terminal with respect to the inverting terminal.
3. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace
length of zero.
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUAR Y 1990 – REVISED MAY 1999
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, VCC 4.75 5 5.25 V
High-level input voltage, VIH
DE RE and D inp ts
2 V
Low-level input voltage, VIL
DE
,
RE
, an
d
D
i
nputs 0.8 V
Common-mode output voltage, VOC –7†12 V
High-level output current, IOH Driver –60 mA
Low-level output current, IOL 60 mA
Common-mode input voltage, VIC ±12 V
Differential input voltage, VID
Receiver
±12 V
High-level output current, IOH
Recei
v
er
–400 µA
Low-level output current, IOL 16 mA
Operating free-air temperature, TA–20 85 °C
†The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode
output and threshold voltage levels only.
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUAR Y 1990 – REVISED MAY 1999
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DRIVER SECTIONS
electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIK Input clamp voltage II = –18 mA –1.5 V
VOH High-level output voltage VIH = 2 V, VIL = 0.8 V, IOH = –33 mA 3.7 V
VOL Low-level output voltage VIH = 2 V, VIL = 0.8 V, IOH = 33 mA 1.1 V
|VOD1|Differential output voltage IO = 0 1.5 6 V
RL= 100 Ω
See Figure 1
2 or
|VOD2|Differential output voltage
R
L =
100
Ω
,
See
Fig
u
re
1
1/2 VOD1‡V
OD2
g
RL = 54 Ω,See Figure 1 1.5 5
VOD3 Differential output voltage See Note 4 1.5 5 V
∆|VOD|Change in magnitude of
differential output voltage (see Note 5) ±0.2 V
VOC Common-mode output voltage RL = 54 Ω or 100 Ω,See Figure 1 –1§3 V
∆|VOC|Change in magnitude of
common-mode output voltage (see Note 5) ±0.2 V
IOOutput current with power off VCC = 0, VO = –7 V to 12 V ±100 µA
IOZ High-impedance-state output current VO = –7 V to 12 V ±100 µA
IIH High-level input current VIH = 2.7 V 20 µA
IIL Low-level input current VIL = 0.4 V –100 µA
VO = –7 V –250
IOS Short-circuit output current (see Note 6) VO = VCC 250 mA
VO = 12 V 250
ICC
Su
pp
ly current
No load
Outputs enabled 80 110
mA
I
CC
S
u
ppl
y
c
u
rrent
No
load
Outputs disabled 50 80
mA
†All typical values are at VCC = 5 V and TA = 25°C.
‡The minimum VOD2 with a 100-Ω load is either 1/2 VOD1 or 2 V, whichever is greater.
§The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode
output and threshold voltage levels only.
NOTES: 4. See TIA/EIA-485-A Figure 3.5, Test Termination Measurement 2
5. ∆|VOD| and ∆|VOC| are the changes in magnitude of VOD and VOC, respectively , that occur when the input is changed from a high
level to a low level.
6. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
switching characteristics at VCC = 5 V, CL = 50 pF, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
td(OD) Differential output delay time
RL=54Ω
See Figure 3
20 25 ns
tt(OD) Differential output transition time
R
L =
54
Ω
,
See
Fig
u
re
3
27 35 ns
tPLH Propagation delay time, low- to high-level output
RL=27Ω
See Figure 4
20 25 ns
tPHL Propagation delay time, high- to low-level output
R
L =
27
Ω
,
See
Fig
u
re
4
20 25 ns
tPZH Output enable time to high level RL = 110 Ω,See Figure 5 80 120 ns
tPZL Output enable time to low level RL = 110 Ω,See Figure 6 40 60 ns
tPHZ Output disable time from high level RL = 110 Ω,See Figure 5 90 120 ns
tPLZ Output disable time from low level RL = 110 Ω,See Figure 6 30 45 ns
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUAR Y 1990 – REVISED MAY 1999
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SYMBOL EQUIVALENTS
DATA-SHEET
PARAMETER TIA/EIA-422-B TIA/EIA-485-A
|VOD1| VOVO
|VOD2| Vt (RL = 100 Ω) Vt (RL = 54 Ω)
|VOD3|Vt (Test Termination
Measurement 2)
∆|VOD|| |Vt| – |Vt| | | |Vt| – |Vt| |
VOC |VOS||VOS|
∆|VOC||VOS – VOS||VOS – VOS|
IOS |Isa|, |Isb|
IO|Ixa|, |Ixb| Iia, Iib
RECEIVER SECTIONS
electrical characteristics over recommended ranges of common-mode input voltage, supply
voltage, and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
VIT+ Positive-going input threshold voltage VO = 2.7 V, IO = –0.4 mA 0.2 V
VIT– Negative-going input threshold voltage VO = 0.5 V, IO = 16 mA –0.2‡V
Vhys Input hysteresis voltage (VIT+ – VIT–)50 mV
VIK Enable clamp voltage SN751177 II = –18 mA –1.5 V
VOH High-level output voltage VID = 200 mV, IOH = –400 µA 2.7 V
VOL
Low level out
p
ut voltage
IOL = 8 mA 0.45
V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
ID = –
IOL = 16 mA 0.5
V
IOZ High-impedance-state output current SN751177 VO = 0.4 V to 2.4 V ±20 µA
II
Line in
p
ut current (see Note 7)
p
VI = 12 V 1
mA
I
I
Line
inp
u
t
c
u
rrent
(see
Note
7)
u
VI = –7 V –0.8
mA
IIH High-level enable input current SN751177 VIH = 2.7 V 20 µA
IIL Low-level enable input current SN751177 VIL = 0.4 V –100 µA
IOS Short-circuit output current (see Note 6) –15 –85 µA
ICC Supply current No load, Outputs enabled 80 110 mA
riInput resistance 12 kΩ
†All typical values are at VCC = 5 V and TA = 25°C.
‡The algebraic convention, where the less positive (more negative) limit is designated as minimum, is used in this data sheet for common-mode
output and threshold voltage levels only.
NOTES: 6. Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
7. Refer to ANSI Standards TIA/EIA-422-B, TIA/EIA-423-A, and TIA/EIA-485-A for exact conditions.
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUAR Y 1990 – REVISED MAY 1999
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
switching characteristics at VCC = 5 V, CL = 15 pF, TA = 25°C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tPLH Propagation delay time, low- to high-level output
VID = 15Vto15V
See Figure 7
20 35 ns
tPHL Propagation delay time, high- to low-level output
V
ID = –
1
.
5
V
to
1
.
5
V
,
See
Fig
u
re
7
22 35 ns
tPZH Output enable time to high level 17 25 ns
tPZL Output enable time to low level
SN751177
See Figure 8
20 27 ns
tPHZ Output disable time from high level
SN751177
See
Fig
u
re
8
25 40 ns
tPLZ Output disable time from low level 30 40 ns
PARAMETER MEASUREMENT INFORMATION
VOC
VOD2
RL
2
RL
2
Figure 1. Driver Test Circuit, VOD and VOC
VOL
VOH –IOH
+IOL
VID
Figure 2. Receiver Test Circuit, VOH and VOL
TEST CIRCUIT
50 Ω
3 V
Output
RL = 54 Ω
Generator
(see Note B)
CL = 50 pF
(see Note A)
VOLTAGE WAVEFORMS
Output
Input
td(OD)
td(OD)
tt(OD) tt(OD)
≈ 2.5 V
0 V
3 V
≈ –2.5 V
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns.
1.5 V 1.5 V
90% 90% 50%
10%
50%
10%
Figure 3. Driver Differential Output-Delay and Transition-Time Test Circuit and Voltage Waveforms
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUAR Y 1990 – REVISED MAY 1999
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
Y
Output
VOL
VOH
VOL
VOH
tPLH
tPHL
tPHL
tPLH
Output
RL = 27 Ω
VOLTAGE WAVEFORMSTEST CIRCUIT
50 Ω
Input 0 V
3 V
Generator
(see Note B) CL = 15 pF
(see Note A) Z
Output
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns.
1.5 V 1.5 V
2.3 V 2.3 V
2.3 V 2.3 V
3 V
2.3 V
S1
Figure 4. Driver Propagation-Time Test Circuit and Voltage Waveforms
tPHZ
Voff ≈0 V
Output VOH
VOLTAGE WAVEFORMSTEST CIRCUIT
Input 0 V
3 V
tPZH
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns.
RL = 110 Ω
50 Ω
Generator
(see Note B)
CL = 15 pF
(see Note A)
0 V or 3 V
Output
1.5 V 1.5 V
0.5 V
2.3 V
S1
Figure 5. Driver Enable- and Disable-Time Test Circuit and Voltage Waveforms
VOL
5 V
tPLZ
tPZL
Output
VOLTAGE WAVEFORMSTEST CIRCUIT
Input 0 V
3 V
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns.
RL = 110 Ω
50 Ω
Generator
(see Note B)
CL = 15 pF
(see Note A)
0 V or 3 V S1 Output
5 V
0.5 V
1.5 V
2.3 V
1.5 V
Figure 6. Driver Enable- and Disable-Time Test Circuit and Voltage Waveforms
SN751177, SN751178
DUAL DIFFERENTIAL DRIVERS AND RECEIVERS
SLLS059D – FEBRUAR Y 1990 – REVISED MAY 1999
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOL
VOH
tPHL
tPLH
Output
VOLTAGE WAVEFORMSTEST CIRCUIT
50 Ω
Output
Input 0 V
3 V
Generator
(see Note B) CL = 15 pF
(see Note A)
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns.
1.5 V 0 V
1.5 V 1.5 V
1.3 V 1.3 V
Figure 7. Receiver Propagation-Time Test Circuit and Voltage Waveforms
VOLTAGE WAVEFORMS
≈1.3 V
0.5 V
tPHZ
3 V
0 V
VOH
Input
Output
0 V
3 V
VOL
S1 to –1.5 V
S2 Closed
S3 Open
VOL
1.5 V
≈4.5 V
tPZL
3 V
1.5 V
0 V
Output
Input
tPZH
0 V
VOH
0 V
1.5 V
3 V
1.5 V
TEST CIRCUIT
1N916 or Equivalent
2 kΩ
5 kΩ
50 Ω
≈1.3 V
tPLZ S1 to –1.5 V
S2 Closed
S3 Closed
S1 to 1.5 V
S2 Closed
S3 Closed
Generator
(see Note B)
CL = 15 pF
(see Note A)
Input
Output
Output
Input
S1 to 1.5 V
S3 Closed
S2 Open
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR ≤ 1 MHz, 50% duty cycle, ZO = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns.
5 V
S3
1.5 V
–1.5 V
S1 S2
0.5 V
1.5 V 1.5 V
Figure 8. Receiver Output Enable- and Disable-Time Test Circuit and Voltage Waveforms
PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
SN751177N ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN751177NE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN751177NSR ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN751177NSRE4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN751177NSRG4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN751178N ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN751178NE4 ACTIVE PDIP N 16 25 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type
SN751178NSR ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN751178NSRE4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
SN751178NSRG4 ACTIVE SO NS 16 2000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-1-260C-UNLIM
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
PACKAGE OPTION ADDENDUM
www.ti.com 4-Jun-2007
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
SN751177NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
SN751178NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
SN751177NSR SO NS 16 2000 346.0 346.0 33.0
SN751178NSR SO NS 16 2000 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Mar-2008
Pack Materials-Page 2
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