NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green) NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green) 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM 240pin Unbuffered DDR2 SDRAM MODULE Based on 64Mx8 DDR2 SDRAM Features * JEDEC Standard 240-pin Dual In-Line Memory Module * 64Mx64 and 128Mx64 DDR2 Unbuffered DIMM based on 64Mx8 DDR2 SDRAM * Performance: * Address and control signals are fully synchronous to positive clock edge * Programmable Operation: - Device Latency: 3, 4, 5 - Burst Type: Sequential or Interleave - Burst Length: 4, 8 - Operation: Burst Read and Write * Auto Refresh (CBR) and Self Refresh Modes * Automatic and controlled precharge commands * 14/10/1 Addressing (row/column/bank) - NT512T64U88A0F * 14/10/2 Addressing (row/column/bank) - NT1GT64U8HA0F * 7.8 s Max. Average Periodic Refresh Interval * Serial Presence Detect * Gold contacts * SDRAMs in 84-ball FBGA Package PC2-3200 PC2-4200 Speed Sort DIMM Latency* f CK Clock Frequency t CK Clock Cycle f DQ DQ Burst Frequency Unit 5A 37B 3 4 200 266 5 3.7 ns 400 533 MHz MHz * Intended for 200 MHz and 266MHz applications * Inputs and outputs are SSTL-18 compatible * VDD = VDDQ = 1.8Volt 0.1 * SDRAMs have 4 internal banks for concurrent operation * Differential clock inputs * Data is read or written on both clock edges * Bi-directional data strobe with one clock cycle preamble and one-half clock post-amble Description NT512T64U88A0F, NT512T64U88A0B, NT512T64U88A0BY, NT1GT64U8HA0F, NT1GT64U8HA0B and NT1GT64U8HA0BY are 240-Pin Double Data Rate 2 (DDR2) Synchronous DRAM Unbuffered Dual In-Line Memory Module (UDIMM), organized as a one-rank 64Mx64 and two ranks 128Mx64 high-speed memory array. Modules use eight 64Mx8 (NT512T64U88A0F) and sixteen 64Mx8 (NT1GT64U8HA0F) DDR2 SDRAMs in FBGA packages. These DIMMs are manufactured using raw cards developed for broad industry use as reference designs. The use of these common design files minimizes electrical variation between suppliers. All NANYA DDR2 SDRAM DIMMs provide a high-performance, flexible 8-byte interface in a 5.25" long space-saving footprint. The DIMM is intended for use in applications operating up to 200 MHz (266MHz) clock speeds and achieves high-speed data transfer rates of up to 400 MHz (533MHz). Prior to any access operation, the device latency and burst / length / operation type must be programmed into the DIMM by address inputs A0-A13 and I/O inputs BA0 and BA1 using the mode register set cycle. The DIMM uses serial presence-detect implemented via a serial 2,048-bit EEPROM using a standard IIC protocol. The first 128 bytes of serial PD data are programmed and locked during module assembly. The remaining 128 bytes are available for use by the customer. REV 1.5 08/2006 1 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green) NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green) 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Ordering Information Part Number Speed Organization Leads Power NT512T64U88A0F-5A NT512T64U88A0B-5A 84-ball 200MHz (5ns @ CL = 3) DDR2-400 PC2-3200 NT512T64U88A0BY-5A 60-ball 64Mx64 NT512T64U88A0F-37B NT512T64U88A0B-37B Note 266MHz (3.7ns @ CL = 4) DDR2-533 Gold 1.8V PC2-4200 Green 84-ball 60-ball NT512T64U88A0BY-37B Green NT1GT64U8HA0F-5A 84-ball NT1GT64U8HA0B-5A 200MHz (5ns @ CL = 3) DDR2-400 PC2-3200 NT1GT64U8HA0BY-5A 128Mx64 NT1GT64U8HA0F-37B NT1GT64U8HA0B-37B 266MHz (3.7ns @ CL = 4) DDR2-533 NT1GT64U8HA0BY-37B REV 1.5 08/2006 60-ball PC2-4200 Gold 1.8V Green 84-ball 60-ball Green 2 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green) NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green) 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Pin Description CK0, CKE0, CKE1 Differential Clock Inputs DQ0-DQ63 Clock Enable CB0-CB7 Row Address Strobe DQS0-DQS8 Column Address Strobe , A0-A9, A11-A13 A10/AP BA0, BA1 ODT0, ODT1 NC REV 1.5 08/2006 Data input/output ECC Check Bit Data Input/Output Bidirectional data strobes DM0-DM8/DQS9-17 Input Data Mask/High Data Strobes Write Enable - Chip Selects VDD Power (1.8V) VREF Ref. Voltage for SSTL_18 inputs Address Inputs Column Address Input/Auto-precharge VDDSPD Differential data strobes Serial EEPROM positive power supply SDRAM Bank Address Inputs VSS Ground Reset pin SCL Serial Presence Detect Clock Input Active termination control lines SDA No Connect SA0-2 Serial Presence Detect Data input/output Serial Presence Detect Address Inputs 3 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green) NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green) 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Pinout Pin Front Pin Front Pin Front Pin 1 VREF 42 NC 82 VSS 121 VSS 2 VSS 43 NC 83 122 DQ4 3 DQ0 44 VSS 84 DQS4 123 DQ5 164 4 DQ1 45 NC 85 VSS 124 VSS 5 VSS 46 NC 86 DQ34 125 DM0, DQS9 47 VSS 87 DQ35 126 6 Back Pin Back Pin Back 162 NC 202 DM4 163 VSS 203 NC NC 204 VSS 165 NC 205 DQ38 166 VSS 206 DQ39 167 NC 207 VSS 7 DQS0 48 NC 88 VSS 127 VSS 168 NC 208 DQ44 8 VSS 49 NC 89 DQ40 128 DQ6 169 VSS 209 DQ45 9 DQ2 50 VSS 90 DQ41 129 DQ7 170 VDDQ 210 VSS 10 DQ3 51 VDDQ 91 VSS 130 VSS 171 CKE1 211 DM5 11 VSS 52 CKE0 92 131 DQ12 172 VDD 212 NC 12 DQ8 53 VDD 93 DQS5 132 DQ13 173 NC 213 VSS 13 DQ9 54 NC 94 VSS 133 VSS 174 NC 214 DQ46 14 VSS 55 NC 95 DQ42 134 DM1, DQS10 175 VDDQ 215 DQ47 56 VDDQ 96 DQ43 135 176 A12 216 VSS 15 16 DQS1 57 A11 97 VSS 136 VSS 177 A9 217 DQ52 17 VSS 58 A7 98 DQ48 137 CK1 178 VDD 218 DQ53 18 NC 59 VDD 99 DQ49 138 179 A8 219 VSS 19 NC 60 A5 100 VSS 139 VSS 180 A6 220 CK2 20 VSS 61 A4 101 SA2 140 DQ14 181 VDDQ 221 21 DQ10 62 VDDQ 102 NC 141 DQ15 182 A3 222 VSS 22 DQ11 63 A2 103 VSS DM6 23 VSS 64 VDD 104 24 DQ16 25 DQ17 65 VSS 106 VSS 145 VSS 185 26 VSS 66 VSS 107 DQ50 146 DM2 186 27 KEY 105 DQS6 142 VSS 183 A1 223 143 DQ20 184 VDD 224 NC 144 DQ21 225 VSS 226 DQ54 227 DQ55 KEY CK0 67 VDD 108 DQ51 147 NC 187 VDD 228 VSS DQS2 68 NC 109 VSS 148 VSS 188 A0 229 DQ60 29 VSS 69 VDD 110 DQ56 149 DQ22 189 VDD 230 DQ61 30 DQ18 70 A10/AP 111 DQ57 150 DQ23 190 BA1 231 VSS 31 DQ19 71 BA0 112 VSS VDDQ 232 DM7 32 VSS 72 VDDQ 113 33 DQ24 73 34 DQ25 74 35 VSS 75 28 36 114 VDDQ VSS 191 DQ28 192 233 NC 153 DQ29 193 234 VSS 115 VSS 154 VSS 194 VDDQ 235 DQ62 116 DQ58 155 DM3 195 ODT0 236 DQ63 117 DQ59 156 NC 196 A13 237 VSS DQS3 77 ODT1 118 VSS 157 VSS 197 VDD 238 VDDSPD 38 VSS 78 VDDQ 119 SDA 158 DQ30 198 VSS 239 SA0 39 DQ26 79 VSS 120 SCL 159 DQ31 199 DQ36 240 SA1 40 DQ27 80 DQ32 160 VSS 200 DQ37 41 VSS 81 DQ33 161 NC 201 VSS 37 76 DQS7 151 152 REV 1.5 08/2006 4 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green) NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green) 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Input/Output Functional Description Symbol Type CK0, CK1, CK2 (SSTL) The positive line of the differential pair of system clock inputs which drives the input to Positive the on-DIMM PLL. All the DDR2 SDRAM address and control inputs are sampled on the Edge rising edge of their associated clocks. (SSTL) Negative The negative line of the differential pair of system clock inputs which drives the input to Edge the on-DIMM PLL. , , Polarity Function CKE0, CKE1 (SSTL) Active High Activates the SDRAM CK signal when high and deactivates the CK signal when low. By deactivating the clocks, CKE low initiates the Power Down mode, or the Self Refresh mode. , (SSTL) Active Low Enables the associated SDRAM command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. (SSTL) Active Low When sampled at the positive rising edge of the clock, operation to be executed by the SDRAM. , , , , define the VREF Supply Reference voltage for SSTL-18 inputs VDDQ Supply Isolated power supply for the DDR SDRAM output buffers to provide improved noise immunity ODT0, ODT1 Input Active High BA0, BA1 (SSTL) - Selects which SDRAM bank is to be active. During a Bank Activate command cycle, A0-A12 defines the row address (RA0-RA12) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A9, A11 defines the column address (CA0-CA10) when sampled at the rising clock edge. In addition to the column address, AP is used to invoke Autoprecharge operation at the end of the Burst Read or Write cycle. If AP is high, autoprecharge is selected and BA0/BA1 define the bank to be precharged. If AP is low, autoprecharge is disabled. During a Precharge command cycle, AP is used in conjunction with BA0/BA1 to control which bank(s) to precharge. If AP is high all 4 banks will be precharged regardless of the state of BA0/BA1. If AP is low, then BA0/BA1 are used to define which bank to pre-charge. A0 - A9 A10/AP A11 - A13 (SSTL) - DQ0 - DQ63 CB0 - CB7 (SSTL) Active High VDD, VSS Supply DQS0 - DQS8 - (SSTL) DM0 - DM8 Input On-Die Termination control signals Data and Check Bit Input/Output pins. Check bits are only applicable on the x72 DIMM configurations. Power and ground for the DDR SDRAM input buffers and core logic Negative and Data strobe for input and output data Positive Edge Active High The data write masks, associated with one data byte. In Write mode, DM operates as a byte mask by allowing input data to be written if it is low but blocks the write operation if it is high. In Read mode, DM lines have no effect. DM8 is associated with check bits CB0-CB7, and is not used on x64 modules. SA0 - SA2 - Address inputs. Connected to either VDD or VSS on the system board to configure the Serial Presence Detect EEPROM address. SDA - This bi-directional pin is used to transfer data into or out of the SPD EEPROM. A resistor must be connected from the SDA bus line to V DD to act as a pull-up. SCL - This signal is used to clock data into and out of the SPD EEPROM. A resistor may be connected from the SCL bus time to V DD to act as a pull-up. VDDSPD REV 1.5 08/2006 Supply Serial EEPROM positive power supply. 5 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green) NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green) 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) DQS0 DQS4 DM0 DM4 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS D0 DQS1 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D1 DQS2 DQS D5 DQS6 DM6 DM2 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D2 DQS3 DQS D6 DQS7 DM3 DM7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQS CKE0 ODT0 1. 2. 3. 4. 5. DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D3 BA0-BA1 : SDRAMs D0-D8 A0-A13 : SDRAMs D0-D8 : SDRAMs D0-D8 : SDRAMs D0-D8 : SDRAMs D0-D8 CKE : SDRAMs D0-D8 ODT : SDRAMs D0-D8 BA0-BA1 A0-A13 08/2006 D4 DM5 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 REV 1.5 DQS DQS5 DM1 Notes : DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 VDDSPD VDDQ VDD VREF VSS VDDID DQ-to-I/O wiring may be changed within a byte. DQ/DQS/DM/CKE/CS relationships are maintained as shown. DQ/DQS/ resistors are 22 Ohms +/- 5% BAx, Ax, , , resistors are 5.1 Ohms +/- 5% Address and control resistors are 22 Ohms +/- 5% DQS D7 Serial PD D0-D8 D0-D8 D0-D8 D0-D8 Strap : see Note 4 Serial PD SCL WP A0 SA0 A1 A2 SA1 SA2 SDA 6 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green) NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green) 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Functional Block Diagram (1GB, 2 Rank, 64Mx8 DDR2 SDRAMs) DQS0 DQS4 DM0 DM4 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS D0 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 D8 DQS1 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D4 DQS D12 DQS5 DM1 DM5 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS D1 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 D9 DQS2 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS D5 DQS D13 DQS6 DM6 DM2 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS D2 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 D10 DQS3 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 D6 DQS D14 DQS7 DM3 DM7 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 BA0-BA1 A0-A13 Notes : REV 1.5 DQS D3 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 D11 BA0-BA1 : SDRAMs D0-D17 A0-A13 : SDRAMs D0-D17 : SDRAMs D0-D17 : SDRAMs D0-D17 : SDRAMs D0-D17 CKE : SDRAMs D0-D8 CKE : SDRAMs D9-D17 ODT : SDRAMs D0-D8 ODT : SDRAMs D9-D17 CKE0 CKE1 ODT0 ODT1 08/2006 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 1. 2. 3. 4. 5. DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS D7 VDDSPD VDDQ VDD VREF VSS VDDID DQ-to-I/O wiring may be changed within a byte. DQ/DQS/DM/CKE/CS relationships are maintained as shown. DQ/DQS/ resistors are 22 Ohms +/- 5% BAx, Ax, , , resistors are 5.1 Ohms +/- 5% Address and control resistors are 22 Ohms +/- 5% DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 DQS D15 Serial PD D0-D8 D0-D8 D0-D8 D0-D8 Strap : see Note 4 Serial PD SCL WP A0 SA0 SDA A1 A2 SA1 SA2 7 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green) NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green) 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect - Part 1 of 2 (512MB) 64Mx64 1 BANK UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD SPD Entry Value Byte Description DDR2-400 (-5A) DDR2-533 (-37B) Serial PD Data Entry (Hexadecimal) DDR2-400 (-5A) DDR2-533 (-37B) 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type DDR2-SDRAM 08 3 Number of Row Addresses on Assembly 14 0E 4 Number of Column Addresses on Assembly 10 0A 5 Number of DIMM Bank, Package, and Height 1 rank, Height=30mm 60 6 Data Width of this Assembly X64 40 7 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 05 9 DDR2 SDRAM Device Cycle Time at Maximum Support Latency CL=5 10 DDR2 SDRAM Device Access Time (tac) from Clock at CL=5 11 DIMM Configuration Type 12 Refresh Rate/Type 13 5ns 3.7ns 50 3D 0.6ns 0.5ns 60 50 Non - ECC 00 7.8 s/self 82 Primary DDRII SDRAM Width X8 08 14 Error Checking DDRII SDRAM Device Width N/A 00 15 Reserved 16 DDR2 SDRAM Device Attributes: Burst Length Supported 17 DDR2 SDRAM Device Attributes: Number of Device Banks 18 DDR2 SDRAM Device Attributes: 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 22 DDR2 SDRAM Device Attributes: General Support weak driver 01 01 23 Minimum Clock Cycle at CL=4 5ns 3.75ns 50 3D 24 Maximum Data Access Time (tac) from Clock at CL=4 0.5ns 60 25 Minimum Clock Cycle Time at CL=3 26 Maximum Data Access Time (tac) from Clock at CL=3 0.6ns 60 27 Minimum Row Precharge Time (tRP) 15ns 3C 28 Minimum Row Active to Row Active delay (tRRD) 7.5ns 1E 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 30 Minimum Active to Precharge Time (tRAS) 45ns 2D 31 Module Bank Density 32 Address and Command Input Setup Time Before Clock (tIS) 0.35ns 0.25ns 35 33 Address and Command Input Hold Time After Clock (tIH) 0.475ns 0.375ns 47 37 34 Data Input Setup Time Before Clock (tDS) 0.15ns 0.1ns 15 10 35 Data Input Hold Time After Clock (tDH) 0.275ns 0.225ns 27 36 Write Recovery Time (tWR) 37 Internal Write to Read Command delay (tWTR) 38 Internal Read to Precharge Command delay (tRTP) 39 Memory Analysis Probe Characteristics 40 08/2006 00 4,8 0C 4 04 3/4/5 38 X <= 4.1mm 01 Regular UDIMM (133.35mm) 02 Normal DIMM 0.6ns 00 5ns 80 15ns 10ns 50 50 512MB Extension of Byte 41 tRC and Byte 42 tRFC REV 1.5 Undefined Latencies Supported Note 25 22 3C 7.5ns 28 1E 7.5ns 1E Undefined 00 The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 8 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green) NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green) 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect - Part 2 of 2 (512MB) 64Mx64 1 BANK UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD SPD Entry Value Byte Description DDR2-400 (-5A) DDR2-533 (-37B) Serial PD Data Entry (Hexadecimal) DDR2-400 (-5A) DDR2-533 (-37B) 41 Minimum Core Cycle Time (tRC) 60ns 42 Min. Auto Refresh Command Cycle Time (tRFC) 105ns 69 43 Maximum Clock Cycle Time (tCK max) 8ns 80 44 Max. DQS-DQ Skew Factor (tQHS) 0.35ns 0.3ns 23 45 Read Data Hold Skew Factor (tQHS) 0.45ns 0.4ns 2D 46 PLL Relock Time 47 Tcasemax 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 16C 18C 43 4B 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 37C 47C 25 2E 51 DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) 39C 39C 27 27 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 27C 33C 1B 21 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3P fast) 30C 37C 1E 25 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) 23C 23C 17 17 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 23C 26C 2E 34 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) 30C 35C 1E 23 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) 35C 37C 23 25 58 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 61 Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 00 00 62 SPD Revision 63 Checksum Data 72 1C 28 51 51 7A 1.2 92-255 Reserved 12 50 F7 NANYA 7F7F7F0B00000000 Manufacturing code -- Module Part Number in ASCII -- Undefined -- 1 NT512T64U88A0F-5A 4E543531325436345538384130462D35412020 NT512T64U88A0F-37B 4E543531325436345538384130462D33374220 NT512T64U88A0B-5A 4E543531325436345538384130422D35412020 NT512T64U88A0B-37B 4E543531325436345538384130422D33374220 NT512T64U88A0BY-5A 4E54353132543634553838413042592D354120 NT512T64U88A0BY-37B 4E54353132543634553838413042592D3337420 REV 1.5 08/2006 1C Checksum Data Module Manufacturing Location 1E 00 122C/W 73-91 Module Part Number 1. 3C N/A 64-71 Manufacturer's JEDEC ID Code Note 9 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green) NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green) 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 1 of 2 (1GB) 128Mx64 2 BANKS UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD SPD Entry Value Byte Description DDR2-400 (-5A) DDR2-533 (-37B) Serial PD Data Entry (Hexadecimal) DDR2-400 (-5A) DDR2-533 (-37B) 0 Number of Serial PD Bytes Written during Production 128 80 1 Total Number of Bytes in Serial PD device 256 08 2 Fundamental Memory Type 3 Number of Row Addresses on Assembly 4 5 6 Data Width of this Assembly 7 DDR2-SDRAM 08 14 0E Number of Column Addresses on Assembly 10 0A Number of DIMM Bank, Package, and Height 2 rank, Height=30mm 61 X64 40 Reserved Undefined 00 8 Voltage Interface Level of this Assembly SSTL_1.8V 05 9 DDR2 SDRAM Device Cycle Time at Maximum Support Latency CL=5 10 DDR2 SDRAM Device Access Time (tac) from Clock at CL=5 11 DIMM Configuration Type Non - ECC 00 12 Refresh Rate/Type 7.8 s/self 82 13 Primary DDRII SDRAM Width X8 08 14 Error Checking DDRII SDRAM Device Width N/A 00 15 Reserved Undefined 00 16 DDR2 SDRAM Device Attributes: Burst Length Supported 4,8 0C 17 DDR2 SDRAM Device Attributes: Number of Device Banks 4 04 18 DDR2 SDRAM Device Attributes: 3/4/5 38 19 DIMM Mechanical Characteristics 20 DDR2 SDRAM DIMM Type Information 21 DDR2 SDRAM Module Attributes: 22 DDR2 SDRAM Device Attributes: General Support weak driver 01 01 23 Minimum Clock Cycle at CL=4 5ns 3.7ns 50 3D 24 Maximum Data Access Time (tac) from Clock at CL=4 0.6ns 0.5ns 60 50 25 Minimum Clock Cycle Time at CL=3 26 Maximum Data Access Time (tac) from Clock at CL=3 0.6ns 60 27 Minimum Row Precharge Time (tRP) 15ns 3C 28 Minimum Row Active to Row Active delay (tRRD) 7.5ns 1E 29 Minimum RAS to CAS delay (tRCD) 15ns 3C 30 Minimum Active to Precharge Time (tRAS) 45ns 2D 31 Module Bank Density 32 Address and Command Input Setup Time Before Clock (tIS) 0.35ns 0.25ns 35 25 33 Address and Command Input Hold Time After Clock (tIH) 0.475ns 0.375ns 47 37 34 Data Input Setup Time Before Clock (tDS) 0.15ns 0.1ns 15 10 35 Data Input Hold Time After Clock (tDH) 0.275ns 0.225ns 27 36 Write Recovery Time (tWR) 37 Internal Write to Read Command delay (tWTR) 38 Internal Read to Precharge Command delay (tRTP) 40 Extension of Byte 41 tRC and Byte 42 tRFC 39 Memory Analysis Probe Characteristics REV 1.5 08/2006 5ns 0.6ns Latencies Supported 3.75ns 50 0.5ns 60 3D 50 X < 4.1mm 01 Regular UDIMM (133.35mm) 02 Normal DIMM 00 5ns 50 512MB 80 15ns 10ns Note 22 3C 7.5ns 28 1E 7.5ns 1E The number below a decimal point of tRC and tRFC are 0, tRFC is less than 256ns 00 Undefined 00 10 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green) NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green) 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Serial Presence Detect -- Part 2 of 2 (1GB) 128Mx64 2 BANKS UNBUFFERED DDR2 SDRAM DIMM based on 64Mx8, 4Banks, 8K Refresh, 1.8V DDR2 SDRAMs with SPD SPD Entry Value Byte Description DDR2-400 (-5A) DDR2-533 (-37B) Serial PD Data Entry (Hexadecimal) DDR2-400 (-5A) DDR2-533 (-37B) 41 Minimum Core Cycle Time (tRC) 60ns 42 Min. Auto Refresh Command Cycle Time (tRFC) 105ns 69 43 Maximum Clock Cycle Time (tCK max) 8ns 80 44 Max. DQS-DQ Skew Factor (tDQs) 0.35ns 45 Read Data Hold Skew Factor (tQHS) 0.45ns 46 PLL Relock Time 47 Tcasemax 48 Thermal Resistance of DRAM Package from Top (Case) to Ambient (Psi T-A DRAM) 49 DRAM Case Temperature Rise from Ambient due to Activate-Precharge/Mode Bits (DT0/Mode Bits) 16C 18C 43 4B 50 DRAM Case Temperature Rise from Ambient due to Precharge/Quiet Standby (DT2N/DT2Q) 37C 47C 25 2E 51 DRAM Case Temperature Rise from Ambient due to precharge Power-Down (DT2P) 39C 39C 27 27 52 DRAM Case Temperature Rise from Ambient due to Active Standby (DT3N) 27C 33C 1B 21 53 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Fast PDN Exit (DT3P fast) 30C 37C 1E 25 54 DRAM Case Temperature Rise from Ambient due to Active Power-Down with Slow PDN Exit (DT3P slow) 23C 23C 17 17 55 DRAM Case Temperature Rise from Ambient due to Page Open Burst Read/DT4R4W Mode Bit (DT4R/DT4R4W Mode Bit) 23C 26C 2E 34 56 DRAM Case Temperature Rise from Ambient due to Burst Refresh (DT5B) 30C 35C 1E 23 57 DRAM Case Temperature Rise from Ambient due to Bank Interleave Reads with Auto-Precharge (DT7) 35C 37C 23 25 58 Thermal Resistance of PLL Package from Top (Case) to Ambient (Psi T-A PLL) 00 00 59 Thermal Resistance of Register Package from Top (Case) to Ambient (Psi T-A Register) 00 00 60 PLL Case Temperature Rise from Ambient due to PLL Active (DT PLL Active) 00 00 61 Resister Case Temperature Rise from Ambient due to Register Active/Mode Bit (DT Register Active/Mode Bit) 00 00 62 SPD Revision 63 Checksum Data 64-71 Manufacturer's JEDEC ID Code 72 Module Manufacturing Location 73-91 23 0.4ns 2D 1E 28 00 1C 51 122C/W 7A 1.2 Checksum data 51 12 51 F8 NANYA 7F7F7F0B00000000 Manufacturing code -- Module Part Number in ASCII -- Undefined -- 1 NT1GT64U8HA0F-5A 4E5431475436345538484130462D3541202020 NT1GT64U8HA0F-37B 4E5431475436345538484130462D3337422020 NT1GT64U8HA0B-5A 4E5431475436345538484130422D3541202020 NT1GT64U8HA0B-37B 4E5431475436345538484130422D3337422020 NT1GT64U8HA0BY-5A 4E543147543634553848413042592D35412020 NT1GT64U8HA0BY-37B 4E543147543634553848413042592D33374220 REV 1.5 08/2006 0.3ns 1C 92-255 Reserved 1. 3C N/A Module Part Number Note 11 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green) NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green) 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Absolute Maximum Ratings Symbol Rating Units Voltage on I/O pins relative to Vss -0.5 to +2.3 V Voltage on VDD pins relative to Vss -1.0 to +2.3 V VDDQ Voltage on VDDQ pins relative to Vss -0.5 to +2.3 V VDDL Voltage on VDDL pins relative to Vss -0.5 to +2.3 V TSTG Storage Temperature (Plastic) -55 to +100 C VIN, VOUT VDD Parameter Note: Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is stress rating only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating temperature Conditions Symbol TCASE Note: 1. 2. Parameter Operating Temperature (Ambient) Rating Units Note 0 to 95 C 1 Case temperature is measured at top and center side of any DRAMs. tCASE > 85C tREFI = 3.9 s DC Electrical Characteristics and Operating Conditions Symbol Min Max Units Notes VDD Supply Voltage 1.7 1.9 V 1 VDDL DLL Supply Voltage 1.7 1.9 V 1 VDDQ Output Supply Voltage 1.7 1.9 V 1 0 0 V VSS, VSSQ VREF Parameter Supply Voltage, I/O Supply Voltage Input Reference Voltage VTT Termination Voltage 0.49VDDQ 0.51VDDQ V 1, 2 VREF - 0.04 VREF + 0.04 V 3 Note: 1. Inputs are not recognized as valid until VREF stabilizes. 2. VREF is expected to be equal to 0.5 V DDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak noise on VREF may not exceed 2% of the DC value. 3. VTT of transmitting device must track VREF of receiving device. Input AC/DC logic level Symbol Min Max Units VIH (AC) Input High (Logic1) Voltage Parameter VREF + 0.250 - V Notes 1 VIL (AC) Input Low (Logic0) Voltage - VREF - 0.250 V 1 VIH (DC) Input High (Logic1) Voltage VREF + 0.125 VDDQ + 0.3 V VIL (DC) Input Low (Logic0) Voltage -0.3 VREF - 0.125 V 1 On Die Termination (ODT) Current Symbol Parameter IODTO Enabled ODT current per DQ ODT is HIGH; Data Bus inputs are FLOATING IODTT Active ODT current per DQ ODT is HIGH; worst case of Data Bus inputs are STABLE or SWITCHING REV 1.5 08/2006 Min Max Units EMRS(1) State 5 7.5 mA/DQ A6=0, A2=1 2.5 3.75 mA/DQ A6=1, A2=0 10 15 mA/DQ A6=0, A2=1 5 7.5 mA/DQ A6=1, A2=0 12 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green) NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green) 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) PC2-3200 (-5A) PC2-4200 (-37B) Unit I DD0 Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 520 560 mA I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 560 640 mA I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 40 40 mA I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 256 320 mA I DD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA 104 128 mA I DD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA 40 40 mA I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 280 336 mA I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 640 720 mA I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 600 760 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 1040 1200 mA I DD6 Self-Refresh Current: CKE 0.2V 40 40 mA I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1200 1280 mA Symbol Note: REV 1.5 08/2006 Parameter/Condition Notes Module IDD was calculated from component IDD. It may differ from the actual measurement. 13 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green) NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green) 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Operating, Standby, and Refresh Currents TCASE = 0 C ~ 85 C; VDDQ = VDD = 1.8V 0.1V (1GB, 2 Ranks, 64Mx8 DDR2 SDRAMs) Symbol Parameter/Condition PC2-3200 (-5A) PC2-4200 (-37B) Unit I DD0 (MIN); Operating Current: one bank; active/precharge; tRC = tRC (MIN); tCK = tCK DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 776 880 mA I DD1 Operating Current: one bank; active/read/precharge; Burst = 2; tRC = tRC (MIN); CL=2.5; tCK = tCK (MIN); IOUT = 0mA; address and control inputs changing once per clock cycle 816 960 mA I DD2P Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VIL (MAX); tCK = tCK (MIN) 80 80 mA I DD2N Idle Standby Current: CS VIH (MIN); all banks idle; CKE VIH (MIN); tCK = tCK (MIN); address and control inputs changing once per clock cycle 512 640 mA I DD3PF Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Fast PDN Exit MRS(12) = 0mA 208 256 mA I DD3PS Active Power-Down Standby Current: one bank active; power-down mode; CKE VIL (MAX); tCK = tCK (MIN); Slow PDN Exit MRS(12) = 1mA 80 80 mA I DD3N Active Standby Current: one bank; active/precharge; CS VIH (MIN); CKE VIH (MIN); tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; address and control inputs changing once per clock cycle 536 656 mA I DD4R Operating Current: one bank; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS outputs changing twice per clock cycle; CL = 2.5; tCK = tCK (MIN); IOUT = 0mA 896 1040 mA I DD4W Operating Current: one bank; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; DQ and DQS inputs changing twice per clock cycle; CL=2.5; tCK = tCK (MIN) 856 1080 mA I DD5 Auto-Refresh Current: tRC = tRFC (MIN) 1296 1520 mA I DD6 Self-Refresh Current: CKE 0.2V 80 80 mA I DD7 Operating Current: four bank; four bank interleaving with BL = 4, address and control inputs randomly changing; 50% of data changing at every transfer; tRC = tRC (min); IOUT = 0mA. 1456 1600 mA Note: REV 1.5 08/2006 Notes Module IDD was calculated from component IDD. It may differ from the actual measurement. 14 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green) NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green) 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE = 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 1 of 2) Symbol tAC tDQSCK -5A (DDR2-400) Parameter DQ output access time from CK/ -37B (DDR2-533) Min. Max. Min. Max. -0.6 0.6 -0.5 0.5 Unit ns DQS output access time from CK/ -0.5 0.5 -0.45 0.45 ns tCH CK high-level width 0.45 0.55 0.45 0.55 tCK tCL CK low-level width 0.45 0.55 0.45 0.55 tCK tHP Minimum half clk period for any given cycle; defined by clk high (tCH) or clk low (tCL) time Min(tCL, tCH) - Min(tCL, tCH) - tCK tCK Clock cycle time tDH DQ and DM input hold time(differential data strobe) 5 8 3.75 8 ns 0.275 - 0.225 - ns tDS DQ and DM input setup time(differential data strobe) 150 - 100 - ns tIPW Input pulse width 0.6 - 0.6 - tCK DQ and DM input pulse width (each input) 0.35 - 0.35 - tCK - tAC max - tAC max ns tDIPW tHZ Data-out high-impedance time from CK/ tLZ(DQ) Data-out low-impedance time from CK/ 2tAC min tAC max 2tAC min tAC max ns tLZ(DQS) DQS low-impedance time from CK/ tAC min tAC max tAC min tAC max ns DQS-DQ skew (DQS & associated DQ signals) - 0.35 - 0.3 ns tQHS Data hold Skew Factor - 0.45 - 0.4 ns tQH Data output hold time from DQS tHP tQHS - tHP tQHS - ns tDQSQ tDQSS Write command to 1st DQS latching transition -0.25 0.25 -0.25 0.25 tCK DQS input low (high) pulse width (write cycle) 0.35 - 0.35 - tCK tDSS DQS falling edge to CK setup time (write cycle) 0.2 - 0.2 - tCK tDSH DQS falling edge hold time from CK (write cycle) 0.2 - 0.2 - tCK tMRD Mode register set command cycle time 2 - 2 - tCK tWPST Write postamble 0.4 0.6 0.4 0.6 tCK tWPRE Write preamble 0.35 - 0.35 - tCK 0.475 - 0.375 - ns 0.35 - 0.35 - ns tDQSL,(H) tIH tIS Address and control input hold time Address and control input setup time tRPRE Read preamble 0.9 1.1 0.9 1.1 tCK tRPST Read postamble 0.4 0.6 0.4 0.6 tCK tRRD Active bank A to Active bank B command 7.5 - 7.5 - ns tDelay Minimum time clocks remains ON after CKE asynchronously drops Low tREFI 7.8 s Average Periodic Refresh Interval (0C TCASE 85C) 3.9 3.9 s tRFC Auto-Refresh to Active/Auto-Refresh command period 08/2006 ns 7.8 OCD drive mode output delay REV 1.5 tIS+tCK+ tIH Average Periodic Refresh Interval (85C < TCASE 95C) tOIT tCCD tIS+tCK+ tIH 0 12 0 105 to 2 12 105 - 2 ns ns - tCK 15 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green) NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green) 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM AC Timing Specifications for DDR2 SDRAM Devices Used on Module (TCASE= 0 C ~ 85 C; VDDQ = 1.8V 0.1V; VDD = 1.8V 0.1V, See AC Characteristics) (Part 2 of 2) Symbol -5A (DDR2-400) Parameter tWR Write recovery time without Auto-Precharge WR Write recovery time with Auto-Precharge -37B (DDR2-533) Unit Min. Max. Min. Max. 15 - 15 - ns tWR/tCK tWR/tCK WR + tRP - WR + tRP - tCK - 7.5 - ns tDAL Auto precharge write recovery + precharge time tWTR Internal write to read command delay 10 tRTP Internal read to precharge command delay 7.5 7.5 ns tRFC + 10 tRFC + 10 ns 200 200 tCK tXSNR Exit self refresh to a Non-read command tXSRD Exit self refresh to a Read command tXP Exit precharge power down to any Non- read command 2 - 2 - tCK 2 - tCK tXARD Exit active power down to read command 2 tXARDS Exit active power down to read command 6 - AL 6 - AL tCK 3 3 tCK tCKE CKE minimum pulse width ODT tAOND tAON tAONPD tAOFD ODT turn-on delay 2 2 2 2 tCK ODT turn-on t (max) t (max) tAC(min) AC tAC(min) AC +1 +1 ns ODT turn-on (Power down mode) 2tCK + 2tCK + tAC(min) tAC(min) tAC(max) tAC(max) +2 +2 +1 +1 ns ODT turn-off delay 2.5 2.5 2.5 2.5 tCK ODT turn-off t (max) t (max) tAC(min) AC tAC(min) AC +0.6 +0.6 ns tAOFPD ODT turn-off (Power down mode) 2.5tCK + 2.5tCK + tAC(min) tAC(min) t (max) t AC AC(max) +2 +2 +1 +1 ns tANPD ODT to power down entry latency 3 - 3 - tCK tAXPD ODT power down exit latency 8 - 8 - tCK ns tAOF Speed Grade Definition tRAS Row Active Time 40 70000 45 70000 tRC Row Cycle Time 55 - 60 - ns RAS to CAS delay 15 - 15 - ns Row Precharge Time 15 - 15 - ns tRCD tRP REV 1.5 08/2006 16 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green) NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green) 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Package Dimensions (512MB, 1 Rank, 64Mx8 DDR2 SDRAMs) " ! " 76 8 %"&' ! !! ! ! " ! ! " " "! 2 " ! ! " " " # $ ! ( ) * +,(+, - ./$ 0 4+ ,)5 * ( - +$ , (1 % 2' 3+ ,, ( -0 , , -,%6+$ ,' * Device position is only for reference. REV 1.5 08/2006 17 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green) NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green) 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Package Dimensions (1GB, 2 Rank, 64Mx8 DDR2 SDRAMs) " ! " 76 8 %"&' ! !! ! ! ! " " "! 2 " ! ! " " " # $ ! ( ) * +,(+, - ./$ 0 4+ ,)5 * ( - +$ ,(1 % 2' 3+ ,,( -0 , , -,%6+$ ,' * Device position is only for reference. REV 1.5 08/2006 18 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice. NT512T64U88A0F / NT512T64U88A0B / NT512T64U88A0BY (Green) NT1GT64U8HA0F / NT1GT64U8HA0B / NT1GT64U8HA0BY (Green) 512MB: 64M x 64 / 1GB: 128M x 64 Unbuffered DDR2 SDRAM DIMM Revision Log Rev Date 0.1 01/2004 Preliminary Release 1.0 01/2005 Added Idd values 1.1 03/2005 Added DDR2-667 spec. 1.2 09/2005 Remove DDR2-667 spec. update IDD & Timing data. 1.3 11/2005 Update SPD. 1.4 03/2006 Update Package Dimensions. 1.5 08/2006 Update Package Dimensions. REV 1.5 08/2006 Modification 19 (c) NANYA TECHNOLOGY CORP. NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.