HEF 4066B gates _- QUADRUPLE BILATERAL SWITCHES Le The HEF40668 has four independent bilateral analogue switches (transmission gates). Each switch has two input/output terminals (Y/Z) and an active HIGH enable input (E). When E is connected to Vpp a low impedance bidirectional path between Y and Z is established (ON condition). When E is connected to Vgg the switch is disabled and a high impedance between Y and Z is established (OFF condition). The HEF4OQ66B is pin compatible with the HEF4016B but exhibits a much lower ON resistance. In addition the ON resistance is relatively constant over the full input signal range. 13/1 ls 4 le 8 l12 11 aL S13] fiz] fi] fro] fo] fe Eo |Yo jE1 |1 jE2 |2 |E3 |3 Von Eo E3 Y3 23 Z2 Y2 - HEF4066B Yo 29 2: Y; E, E2 Vss Zo 21 22 23 2p BGP ele 2 3 9 10 7Z69712 7269571.2 Fig. 2 Pinning diagram. Fig. 1 Functional diagram. HEF4066BP : 14-lead DIL; plastic (SOT-27). HEF4066BD: 14-lead DIL; ceramic (cerdip) (SOT-73). PINNING HEF4066BT: 14-lead mini-pack; plastic Eg to E3 enable inputs (SO-14; SOT-108A). Yo to Y3 input/output terminals APPLICATION INFORMATION 29 to Z3 input/output terminals An example of application for the HEF4066B is: @ Analogue and digital switching Yn En >o- f>o Vss Zn -7274626.2 Fig. 3 Schematic diagram (one switch). S Products approved to CECC 90 104-042. | ( May 1983 389HEF 4066B gates RATINGS Limiting values in accordance with the Absolute Maximum System (IEC 134) Power dissipation per switch P max. 100 mW For other RATINGS see Family Specifications D.C. CHARACTERISTICS Tamb = 25 9C Vpp . woe Vv symbol | min. typ. max. conditions 5 - 350 2500 2 | E, at Vop ON resistance 10 | RON - 80 245 2 Vis = Vsg to Vpop 15 - 60 175 Q J see Fig. 4 5 - 115 340 2 | E, at Vpp ON resistance 10 | Ron _ 50 160 Q Vis= Vss 15 _ 40 115 2 J see Fig. 4 5 - 120 365 Q | En, at Vpp ON resistance 10 | Ron - 65 200 2 Vis=YVppb 15 _ 50 155 Q J see Fig. 4 A ON resistance 5 - 25 - 2 | En at Vpp between any two 10 | ARon |- 10 - Q Vis = Vss to Vpp channels 15 - 5 - Qa J see Fig. 4 OFF state leakage 5 - - - nA current, any 10 | loz _ _ _ nA E, at Vss channel OFF 15 - - 200 nA E, input voltage 5 _ 2,25 i sv - LOW 10 |v = |-))45000~CO2 | lis= JO BA 15 - 6,75 2 Vv 9 Vpp | symbol Tamb (OC) conditions Vv -40 +25 +85 max. max. max. Quiescent device 5 1,0 1,0 75 wA | Vgg = 0; all valid current 10 Ipp 2,0 2,0 150 pA input combinations; 15 4,0 4,0 30,0 yA J Vi =Vss 0rVpp Input leakage current at Ey, 15 itlin - 300 1000 nA En, at Vss or Vpp 390 May 1 see) (Quadruple bilateral switches HEF4066B gates En >o+ o- Yop Yn Zn Vis = Vss to Vop lig = 200 pA L Vssg 7 7Z74577.2 Fig. 4 Test set-up for measuring Ron. 7Z82373 400 Ron (22) 300 200 . : . : Fig. 5 Typical Ron asa function of input voltage. En at Vpp lig = 200 KA 100 Vsg = OV 0 0 5 10 vig(vy 15 NOTE To avoid drawing Vpp current out of terminal Z, when switch current flows into terminals Y, the voltage drop across the bidirectional switch must not exceed 0,4 V. If the switch current flows into terminal Z, no Vpp current will flow out of terminals Y, in this case there is no limit for the voltage drop across the switch, but the voltages at Y and Z may not exceed Vpp or Vgg. | (cesar 1980 391HEF 4066B gates A.C. CHARACTERISTICS Vss = 0V; Tamb = 25 C; input transition times < 20 ns dD symbol typ. max. Propagation delays Vis Vos 5 10 20 sons | HIGH to LOW 10 tPHL 5 10 ns note 1 15 5 10 ns J 5 10 20 ns LOW to HIGH 10 tpLH 5 10 ns note 1 15 5 10 ns Output disable times En Vos 5 80 160 ns | HIGH 10 tpHz 65 130 ns note 2 15 60 120 ns J 5 80 160 ns | LOW 10 tpLz 70 140 ons note 2 15 70 140 ~s ns J Output enable times En Vos 5 40 80 ons | HIGH 10 tpZH 20 40 ons note 2 15 15 30 ns J 5 45 90 ons ) LOW 10 tp2L 20 40 ons note 2 15 15 30 ~=ns Distortion, sine-wave 5 0,25 % response 10 0,04 % | note 3 15 0,04 % Crosstalk between 5 - MHz | any two channels 10 1 MHz note 4 15 - MHz | J Crosstalk; enable 5 _ mV input to output 10 50 mV note 5 15 _ mV OF F-state 5 - MHz | feed-through 10 1 MHz note 6 15 MHz | J ON-state frequency 5 _ MHz \ response 10 90 MHz note 7 15 - MHz J Vpp : where V typical formula for P (uW) f; = input freq. (MHz) ; fy = output freq. (MHz) Dynamic power 5 800 f+ Z(fgCL) x Vpp? C,_ = load capacitance (pF) dissipation per 10 3500 fj + E(fgCL) x Vpp? Z(fgC_) = sum of outputs package (P) 15 10 100 fj + Z(fyCL) x Vpp? VbbD = supply voltage (V) 392 October 1000 (Quadruple bilateral switches HEF4066B gates NOTES Vig is the input voltage at a Y or Z terminal, whichever is assigned as input. Vos is the output voltage at a Y or Z terminal, whichever is assigned as output. 1. RL = 10 k& to Vgg; CL = 50 pF to Vgs; En = Vop: Vis = Vpb (square-wave); see Figs 6 and 10. 2. RL = 10k; C_ = 50 pF to Vgs; En = Vpp (square-wave); Vis = Vpp and Ry, toVgg for tpyyz and tpzy; Vis = Vgg and R, to Vpp for tp_z and tpz_; see Figs 6 and 11. 3. Ri = = 10 kQ; CL = 15 pF; En = Vop: Vis= % Vppip-p) (sine wave, symmetrical about % Vpp); fis = 1 kHz; see Fig. 7. 4. RL =1kQ; Vis = % VpD{p-p) (sine-wave, symmetrical about % Vpp); g vos! Vig (A) 5. Ry = 10 k&2 to Vgg; CL = 15 pF to Veg; En = Vpp (square-wave); crosstalk is [Vos | (peak value); see Fig. 6. 6. Ry = 1k9; Cy) = 5 pF; Ey = Vgs; Vis=% Vopip-p) (sine-wave, symmetrical about % Vpp); 20 lo = 50 dB; E, (A) = Vgg; Ey (B) = Vpp;: see Fig. 8. Vos : 20 log vy. = 50 dB; see Fig. 7. is 7, RL = 1k, Cy = 5 pF; E_ = Vop: Vis = % VpD{(p-p} (sine-wave, symmetrical about % Vpp):; Vv 20 log OS 3 dB; see Fig. 7. Vis te E ope Rv CL 7274581.2 Fig. 6. Vv san En 4 7Z74579.1 Fig. 7. | Ce 1980 393HEF4066B gates E, (A) >o+> switch A RL (a) Vgs 9 Do Fig. 8. Fig. 9. switch B Vss 7274590.2 394 October 20 (Quadruple bilateral switches HEF4066B gates 20ns ~) ja Vss ~ tpye 7279897 Fig. 10 Waveforms showing propagation delays from Vjs to Vos. 20ns 20ns Vv f 20% 1 DD E, INPUT 50% 10% Vss 90% Vos (1) 10% _ tpZH >| tpHz |= 90% Vos (2) 10% _- UPZL ~l tpez i= 7279898 (1) Vig at Vpp; (2) Vis at Vss- Fig. 11 Waveforms showing output disable and enable times. | (coo 1980 395