_______________
General Description
The MAX1248/MAX1249 10-bit data-acquisition sys-
tems combine a 4-channel multiplexer, high-bandwidth
track/hold, and serial interface with high conversion
speed and low power consumption. They operate from
a single +2.7V to +5.25V supply, and their analog
inputs are software configurable for unipolar/bipolar
and single-ended/differential operation.
The 4-wire serial interface connects directly to SPI™/
QSPI™ and MICROWIRE™ devices without external
logic. A serial strobe output allows direct connection
to TMS320-family digital signal processors. The
MAX1248/MAX1249 use either the internal clock or an
external serial-interface clock to perform successive-
approximation analog-to-digital conversions.
The MAX1248 has an internal 2.5V reference, while the
MAX1249 requires an external reference. Both parts
have a reference-buffer amplifier with a ±1.5% voltage
adjustment range.
These devices provide a hard-wired SHDN pin and a
software-selectable power-down, and can be pro-
grammed to automatically shut down at the end of a
conversion. Accessing the serial interface automatically
powers up the MAX1248/MAX1249, and the quick
turn-on time allows them to be shut down between all
conversions. This technique can cut supply current to
under 60µA at reduced sampling rates.
The MAX1248/MAX1249 are available in a 16-pin DIP
and a very small QSOP that occupies the same board
area as an 8-pin SO.
For 8-channel versions of these devices, see the
MAX148/MAX149 data sheet.
________________________Applications
Portable Data Logging Data Acquisition
Medical Instruments Battery-Powered Instruments
Pen Digitizers System Supervision
____________________________Features
♦4-Channel Single-Ended or 2-Channel
Differential Inputs
♦Single +2.7V to +5.25V Operation
♦Internal 2.5V Reference (MAX1248)
♦Low Power: 1.2mA (133ksps, +3V supply)
54µA (1ksps, +3V supply)
1µA (power-down mode)
♦SPI/QSPI/MICROWIRE/TMS320-Compatible
4-Wire Serial Interface
♦Software-Configurable Unipolar or Bipolar Inputs
♦16-Pin QSOP Package (same area as 8-pin SO)
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
________________________________________________________________
Maxim Integrated Products
1
19-1072; Rev 2; 5/98
PART†
MAX1248ACPE
MAX1248BCPE
MAX1248ACEE 0°C to +70°C
0°C to +70°C
0°C to +70°C
TEMP. RANGE PIN-PACKAGE
16 Plastic DIP
16 Plastic DIP
16 QSOP
_____________
Ordering Information
Ordering Information continued at end of data sheet.
†
Contact factory for availability of alternate surface-mount
packages.
Pin Configuration appears at end of data sheet.
MAX1248BCEE 0°C to +70°C 16 QSOP
INL
(LSB)
±1/2
±1
±1/2
±1
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corp.
VDD
I/O
SCK (SK)
MOSI (SO)
MISO (SI)
VSS
SHDN
SSTRB
DOUT
DIN
SCLK
CS
COM
AGND
DGND
VDD
CH3
C1
4.7µF
C2
0.01µF
C3
0.1µF
CH0
0V TO
+2.5V
ANALOG
INPUTS
MAX1248 CPU
+3V
VREF
REFADJ
__________Typical Operating Circuit
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800.
For small orders, phone 408-737-7600 ext. 3468.
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS
(VDD = +2.7V to +5.25V; COM = 0V; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX1248—4.7µF capacitor at VREF pin; MAX1249—external reference, VREF = 2.500V applied to VREF pin; TA= TMIN to TMAX,
unless otherwise noted.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to AGND, DGND.............................................. -0.3V to +6V
AGND to DGND.................................................... -0.3V to +0.3V
CH0–CH3, COM to AGND, DGND............ -0.3V to (VDD + 0.3V)
VREF to AGND........................................... -0.3V to (VDD + 0.3V)
Digital Inputs to DGND............................................ -0.3V to +6V
Digital Outputs to DGND........................... -0.3V to (VDD + 0.3V)
Digital Output Sink Current.................................................25mA
Continuous Power Dissipation (TA= +70°C)
Plastic DIP (derate 10.53mW/°C above +70°C) ......... 842mW
QSOP (derate 8.30mW/°C above +70°C)................... 667mW
CERDIP (derate 10.00mW/°C above +70°C).............. 800mW
Operating Temperature Ranges
MAX1248_C_E/MAX1249_C_E.......................... 0°C to +70°C
MAX1248_E_E/MAX1249_E_E........................ -40°C to +85°C
MAX1248_MJE/MAX1249_MJE.................... -55°C to +125°C
Storage Temperature Range............................ -60°C to +150°C
Lead Temperature (soldering, 10sec)............................ +300°C
6µs
35 65
tCONV
Conversion Time (Note 5) 5.5 7.5
MHz1.0Full-Power Bandwidth MHz2.25Small-Signal Bandwidth dB-75Channel-to-Channel Crosstalk dB70SFDRSpurious-Free Dynamic Range dB-70THDTotal Harmonic Distortion dB66SINADSignal-to-Noise + Distortion Ratio
LSB±0.05
Channel-to-Channel Offset
Matching
ppm/°C±0.25Gain Temperature Coefficient
±0.5 Bits10Resolution
±1
Offset Error
LSB
±1.0
INLRelative Accuracy (Note 2)
LSB±1DNL ±1 LSB
±2
UNITSMIN TYP MAXSYMBOLPARAMETER
External clock = 2MHz, 12 clocks/conversion
Internal clock, SHDN = VDD
Internal clock, SHDN = FLOAT
MAX124_A
-3dB rolloff
65kHz, 2.500Vp-p (Note 4)
Up to the 5th harmonic
MAX124_A
MAX124_B
No missing codes over temperature
MAX124_A
MAX124_B
CONDITIONS
Differential Nonlinearity
ns30Aperture Delay
MHz
1.8
SHDN = FLOAT ps<50Aperture Jitter
MHz
0.1 2.0
µs1.5tACQ
Track/Hold Acquisition Time
0.225
Internal Clock Frequency SHDN = VDD
02.0
External Clock Frequency Data transfer only
LSBGain Error (Note 3) ±2MAX124_B
DC ACCURACY (Note 1)
DYNAMIC SPECIFICATIONS (10kHz sine-wave input, 0V to 2.500Vp-p, 133ksps, 2.0MHz external clock, bipolar input mode)
CONVERSION RATE
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
_______________________________________________________________________________________ 3
Multiplexer Leakage Current
pF15CIN
DIN, SCLK, CS Input Capacitance µA±0.01 ±1IIN
DIN, SCLK, CS Input Leakage V0.2VHYST
DIN, SCLK, CS Input Hysteresis V0.8VIL
DIN, SCLK, CS Input Low Voltage
2.0
µA0.01 10Shutdown VREF Input Current kΩ18 25VREF Input Resistance µA100 150VREF Input Current
V
1.0 VDD +
50mV
VREF Input Voltage Range
(Note 9)
pF16Input Capacitance
0 to VREF V
±VREF / 2
Input Voltage Range, Single-
Ended and Differential (Note 6) µA±0.01 ±1
UNITSMIN TYP MAXSYMBOLPARAMETER
(Note 10)
VIN = 0V or VDD
Unipolar, COM = 0V
VDD ≤3.6V
VREF = 2.500V
Bipolar, COM = VREF / 2
On/off leakage current, VCH_ = 0V or VDD
CONDITIONS
µA±4.0IS
SHDN Input Current V0.4VSL
SHDN Input Low Voltage
VVDD - 0.4VSH
SHDN Input High Voltage
SHDN = 0V or VDD
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V; COM = 0V; fSCLK = 2.0MHz; external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX1248—4.7µF capacitor at VREF pin; MAX1249—external reference, VREF = 2.500V applied to VREF pin; TA= TMIN to TMAX,
unless otherwise noted.)
V
3.0
VIH
DIN, SCLK, CS Input High Voltage VDD > 3.6V
V2.470 2.500 2.530VREF Output Voltage TA= +25°C (Note 7) mA30VREF Short-Circuit Current ppm/°C±30VREF Temperature Coefficient MAX1248
µF
0
Capacitive Bypass at VREF Internal compensation mode 4.7External compensation mode
mV0.35Load Regulation (Note 8) 0mA to 0.2mA output load
µF0.01Capacitive Bypass at REFADJ ±1.5REFADJ Adjustment Range %
V
VDD -
0.5
REFADJ Buffer-Disable Threshold
Capacitive Bypass at VREF Internal compensation mode 0 µF
External compensation mode 4.7
Reference-Buffer Gain MAX1248 2.06 V/V
MAX1249 2.00
REFADJ Input Current MAX1248 ±50 µA
MAX1249 ±10
V1.1 VDD - 1.1VSM
SHDN Input Mid Voltage
ANALOG/COM INPUTS
EXTERNAL REFERENCE AT VREF (Buffer disabled)
DIGITAL INPUTS (DIN, SCLK, CS, SHDN)
EXTERNAL REFERENCE AT REFADJ
INTERNAL REFERENCE (MAX1248 only, reference buffer enabled)
VDD = 5.25V
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
4 _______________________________________________________________________________________
1.2 2.0
3.5 15
Operating mode,
full-scale input (Note 11)
30 70Fast power-down (MAX1248)
nA±100
SHDN Maximum Allowed
Leakage, Mid Input
VVDD / 2VFLT
SHDN Voltage, Floating
SHDN = FLOAT
SHDN = FLOAT UNITSMIN TYP MAXSYMBOLPARAMETER
µA
1.2 10
IDD
CONDITIONS
Positive Supply Current
mA
1.6 3.0
µA±0.01 ±10IL
Three-State Leakage Current VVDD - 0.5VOH
Output Voltage High
V
0.8
VOL
Output Voltage Low 0.4
V2.70 5.25VDD
Positive Supply Voltage
pF15COUT
Three-State Output Capacitance
Full power-down
CS = VDD (Note 10)
CS = VDD
ISOURCE = 0.5mA
ISINK = 16mA
ISINK = 5mA
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +2.7V to +5.25V; COM = 0V; fSCLK = 2.0MHz, external clock (50% duty cycle); 15 clocks/conversion cycle (133ksps);
MAX1248—4.7µF capacitor at VREF pin; MAX1249—external reference; VREF = 2.500V applied to VREF pin, TA= TMIN to TMAX,
unless otherwise noted.)
mV±0.3PSRSupply Rejection (Note 12) VDD = 2.7V to 5.25V, full-scale input,
external reference = 2.500V
DIGITAL OUTPUTS (DOUT, SSTRB)
POWER REQUIREMENTS
IDD
VDD = 5.25V
VDD = 3.6V
VDD = 5.25V
VDD = 3.6V
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
_______________________________________________________________________________________
5
TIMING CHARACTERISTICS
(VDD = +2.7V to +5.25V, TA= TMIN to TMAX, unless otherwise noted.)
Note 1: Tested at VDD = 2.7V; COM = 0V; unipolar single-ended input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3: MAX1248—internal reference, offset nulled; MAX1249—external reference (VREF = +2.500V), offset nulled.
Note 4: Ground “on” channel; sine wave applied to all “off” channels.
Note 5: Conversion time defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle.
Note 6: The common-mode range for the analog inputs is from AGND to VDD.
Note 7 Sample tested to 0.1% AQL.
Note 8: External load should not change during conversion for specified accuracy.
Note 9: ADC performance is limited by the converter’s noise floor, typically 300µVp-p.
Note 10 Guaranteed by design. Not subject to production testing.
Note 11: The MAX1249 typically draws 400µA less than the values shown.
Note 12: Measured as |VFS(2.7V) - VFS(5.25V)|.
DIN to SCLK Setup
ns240tSTR
CS Rise to SSTRB Output Disable ns240tSDV
CS Fall to SSTRB Output Enable 240tSSTRB
SCLK Fall to SSTRB ns
200tCL
SCLK Pulse Width Low ns200SCLK Pulse Width High ns0
CS to SCLK Rise Hold ns100tCSS
CS to SCLK Rise Setup ns240tTR
CS Rise to Output Disable ns240tDV
CS Fall to Output Enable
tDO
SCLK Fall to Output Data Valid
ns0tDH
DIN to SCLK Hold
ns
µs1.5tACQ
Acquisition Time
0tSCK
SSTRB Rise to SCLK Rise
ns100tDS
UNITSMIN TYP MAXSYMBOLPARAMETER
Internal clock mode only (Note 10)
External clock mode only, Figure 2
External clock mode only, Figure 1
Figure 1
Figure 2
Figure 1
CONDITIONS
ns
20 240
Figure 1
tCSH
tCH ns
MAX124__C/E
MAX124__M 20 200
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
6 _______________________________________________________________________________________
2.00
0.502.25 2.75
SUPPLY CURRENT
vs. SUPPLY VOLTAGE
1.75
1.25
1.50
1.00
0.75
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (mA)
3.75 5.253.25 4.25 4.75
MAX1248-01
RL = ∞
CODE = 10101010
MAX1249
MAX1248
CLOAD = 20pF
CLOAD = 50pF
CLOAD = 50pF
CLOAD = 20pF
4.0
3.5
02.25 2.75
SHUTDOWN SUPPLY CURRENT
vs. SUPPLY VOLTAGE
3.0
2.5
1.5
2.0
1.0
0.5
VDD (V)
SHUTDOWN SUPPLY CURRENT (µA)
3.75 5.253.25 4.25 4.75
MAX1248/49-02
FULL POWER-DOWN
2.5025
2.49752.25 2.75
INTERNAL REFERENCE VOLTAGE
vs. SUPPLY VOLTAGE
2.5000
SUPPLY VOLTAGE (V)
INTERNAL REFERENCE VOLTAGE (V)
3.75 5.253.25 4.25 4.75
MAX1248-09
0.8
0.9
1.0
1.1
1.2
1.3
-60 -20 20 60 100 140
SUPPLY CURRENT vs. TEMPERATURE
TEMPERATURE (°C)
SUPPLY CURRENT (mA)
MAX1247-04
MAX1249
MAX1248
RLOAD = ∞
CODE = 1010101000
00
0.10
0.05
0.20
0.15
0.25
0.30
2.25 3.25 3.752.75 4.25 4.75 5.25
INTERGRAL NONLINEARITY
vs. SUPPLY VOLTAGE
MAX1248-07
SUPPLY VOLTAGE (V)
INL (LSB)
MAX1248
MAX1249
0
0.4
0.8
1.2
1.6
2.0
-60 -20 20 60 100 140
SHUTDOWN CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
SHUTDOWN CURRENT (µA)
MAX1248-05
2.494
2.495
2.496
2.497
2.498
2.499
2.500
2.501
-60 -20-40 200 6040 100 12080 140
INTERNAL REFERENCE VOLTAGE
vs. TEMPERATURE
TEMPERATURE (°C)
INTERNAL REFERENCE VOLTAGE, VREF
MAX1248-06
VDD = 2.7V
VDD = 3.6V
VDD = 5.25V
0
0.15
0.10
0.05
0.20
0.25
0.30
-60 200-40 -20 40 60 80 100 120 140
INTEGRAL NONLINEARITY
vs. TEMPERATURE
MAX1248-08
TEMPERATURE (°C)
INL (LSB)
VDD = 2.7V
MAX1248
MAX1249
0.100
INTEGRAL NONLINEARITY
vs. CODE
0.050
-0.100
0
-0.025
-0.050
-0.075
0.075
0.025
MAX1248-09
INL (LSB)
CODE
256 512 768 10240
__________________________________________Typical Operating Characteristics
(VDD = 3.0V, VREF = 2.500V, fSCLK = 2.0MHz, CLOAD = 20pF, TA= +25°C, unless otherwise noted.)
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
_______________________________________________________________________________________ 7
NAME FUNCTION
1 VDD Positive Supply Voltage
2–5 CH0–CH3 Sampling Analog Inputs
PIN
6 COM Ground reference for analog inputs. Sets zero-code voltage in single-ended mode. Must be stable to
±0.5LSB.
7SHDN Three-Level Shutdown Input. Pulling SHDN low shuts the MAX1248/MAX1249 down; otherwise, the
devices are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compen-
sation mode. Letting SHDN float puts the reference-buffer amplifier in external compensation mode.
12 DOUT Serial Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
11 DGND Digital Ground
9 REFADJ Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD.
8VREF
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion. In
internal reference mode (MAX1248 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
REFADJ to VDD.
16 SCLK Serial Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed. (Duty cycle must be 40% to 60%.)
15 CS Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT is
high impedance.
14 DIN Serial Data Input. Data is clocked in at SCLK’s rising edge.
13 SSTRB
Serial Strobe Output. In internal clock mode, SSTRB goes low when the MAX1248/MAX1249 begin the
A/D conversion and goes high when the conversion is completed. In external clock mode, SSTRB
pulses high for one clock period before the MSB decision. High impedance when CS is high (external
clock mode).
______________________________________________________________Pin Description
VDD
6k
DGND
DOUT
CLOAD
50pF CLOAD
50pF
DGND
6k
DOUT
a) High-Z to VOH and VOL to VOH b) High-Z to VOL and VOH to VOL
VDD
6k
DGND
DOUT
CLOAD
50pF CLOAD
50pF
DGND
6k
DOUT
a) VOH to High-Z b) VOL to High-Z
Figure 1. Load Circuits for Enable Time Figure 2. Load Circuits for Disable Time
10 AGND Analog Ground
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
8 _______________________________________________________________________________________
_______________Detailed Description
The MAX1248/MAX1249 analog-to-digital converters
(ADCs) use a successive-approximation conversion
technique and input track/hold (T/H) circuitry to convert
an analog signal to a 10-bit digital output. A flexible
serial interface provides easy interface to microproces-
sors (µPs). Figure 3 is a block diagram of the
MAX1248/MAX1249.
Pseudo-Differential Input
The sampling architecture of the ADC’s analog com-
parator is illustrated in the equivalent input circuit
(Figure 4). In single-ended mode, IN+ is internally
switched to CH0–CH3, and IN- is switched to COM. In
differential mode, IN+ and IN- are selected from two
pairs: CH0/CH1 and CH2/CH3. Configure the channels
with Tables 2 and 3. Please note that the codes for
CH0–CH3 in the MAX1248/MAX1249 correspond to
the codes for CH2–CH5 in the eight-channel
(MAX148/MAX149) versions.
In differential mode, IN- and IN+ are internally switched
to either of the analog inputs. This configuration is
pseudo-differential to the effect that only the signal at
IN+ is sampled. The return side (IN-) must remain sta-
ble within ±0.5LSB (±0.1LSB for best results) with
respect to AGND during a conversion. To accomplish
this, connect a 0.1µF capacitor from IN- (the selected
analog input) to AGND.
During the acquisition interval, the channel selected as
the positive input (IN+) charges capacitor CHOLD. The
acquisition interval spans three SCLK cycles and ends
on the falling SCLK edge after the last bit of the input
control word has been entered. At the end of the acqui-
sition interval, the T/H switch opens, retaining charge
on CHOLD as a sample of the signal at IN+.
The conversion interval begins with the input multiplex-
er switching CHOLD from the positive input (IN+) to the
negative input (IN-). In single-ended mode, IN- is sim-
ply COM. This unbalances node ZERO at the compara-
tor’s input. The capacitive DAC adjusts during the
remainder of the conversion cycle to restore node
ZERO to 0V within the limits of 10-bit resolution. This
action is equivalent to transferring a charge of 16pF x
[(VIN+) - (VIN-)] from CHOLD to the binary-weighted
capacitive DAC, which in turn forms a digital represen-
tation of the analog input signal.
Track/Hold
The T/H enters its tracking mode on the falling clock
edge after the fifth bit of the 8-bit control word has been
shifted in. It enters its hold mode on the falling clock
edge after the eighth bit of the control word has been
shifted in. If the converter is set up for single-ended
inputs, IN- is connected to COM, and the converter
samples the “+” input. If the converter is set up for dif-
ferential inputs, IN- connects to the “-” input, and the
difference of |IN+ - IN-|is sampled. At the end of the
conversion, the positive input connects back to IN+,
and CHOLD charges to the input signal.
The time required for the T/H to acquire an input signal
is a function of how quickly its input capacitance is
charged. If the input signal’s source impedance is high,
INPUT
SHIFT
REGISTER CONTROL
LOGIC
INT
CLOCK
OUTPUT
SHIFT
REGISTER
+1.21V
REFERENCE
(MAX1248)
T/H
ANALOG
INPUT
MUX SAR
ADC
IN
DOUT
SSTRB
VDD
DGND
AGND
SCLK
DIN
COM
REFADJ
VREF
OUT
REF
CLOCK
+2.500V
20k A ≈ 2.06*
*A ≈ 2.00 (MAX1249)
7
8
9
6
12
13
14
15
16
CH3 5
CH2 4
CH1 3
CH0 2
MAX1248
MAX1249
CS
SHDN
1
11
10
Figure 3. Block Diagram
CH0
CH1
CH2
CH3
COM
CSWITCH
TRACK
T/H
SWITCH
RIN
9k
CHOLD
HOLD
CAPACITIVE DAC
VREF
ZERO COMPARATOR
–+
16pF
SINGLE-ENDED MODE: IN+ = CHO–CH3, IN- = COM.
DIFFERENTIAL MODE: IN+ AND IN- SELECTED FROM PAIRS OF
CH0/CH1 AND CH2/CH3.
AT THE SAMPLING INSTANT,
THE MUX INPUT SWITCHES
FROM THE SELECTED IN+
CHANNEL TO THE SELECTED
IN- CHANNEL.
INPUT
MUX
Figure 4. Equivalent Input Circuit
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
_______________________________________________________________________________________ 9
the acquisition time lengthens, and more time must be
allowed between conversions. The acquisition time,
tACQ, is the maximum time the device takes to acquire
the signal, and is also the minimum time needed for the
signal to be acquired. It is calculated by:
tACQ = 7.6 x (RS+ RIN) x 16pF
where RIN = 9kΩ, RS= the source impedance of the
input signal, and tACQ is never less than 1.5µs. Note
that source impedances below 3kΩdo not significantly
affect the ADC’s AC performance.
Higher source impedances can be used if a 0.01µF
capacitor is connected to the individual analog inputs.
Note that the input capacitor forms an RC filter with the
input source impedance, limiting the ADC’s signal
bandwidth.
Input Bandwidth
The ADC’s input tracking circuitry has a 2.25MHz
small-signal bandwidth, so it is possible to digitize
high-speed transient events and measure periodic sig-
nals with bandwidths exceeding the ADC’s sampling
rate by using undersampling techniques. To avoid
high-frequency signals being aliased into the frequency
band of interest, anti-alias filtering is recommended.
Analog Input Protection
Internal protection diodes, which clamp the analog input
to VDD and AGND, allow the channel input pins to swing
from AGND - 0.3V to VDD + 0.3V without damage.
However, for accurate conversions near full scale, the
inputs must not exceed VDD by more than 50mV or be
lower than AGND by 50mV.
If the analog input exceeds 50mV beyond the sup-
plies, do not forward bias the protection diodes of off
channels over 4mA.
How to Start a Conversion
A conversion is started by clocking a control byte into
DIN. With CS low, each rising edge on SCLK clocks a bit
from DIN into the MAX1248/MAX1249’s internal shift reg-
ister. After CS falls, the first arriving logic “1” bit defines
the control byte’s MSB. Until this first “start” bit arrives,
any number of logic “0” bits can be clocked into DIN with
no effect. Table 1 shows the control-byte format.
The MAX1248/MAX1249 are compatible with SPI/QSPI
and MICROWIRE devices. For SPI, select the correct
clock polarity and sampling edge in the SPI control reg-
isters: set CPOL = 0 and CPHA = 0. MICROWIRE, SPI,
and QSPI all transmit a byte and receive a byte at the
same time. Using the
Typical Operating Circuit,
the sim-
Table 1. Control-Byte Format
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
(MSB) (LSB)
START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0
BIT NAME DESCRIPTION
7(MSB) START The first logic “1” bit after CS goes low defines the beginning of the control byte.
6 SEL2 These three bits select which of the four channels are used for the conversion (Tables 2 and 3).
5 SEL1
4 SEL0
3 UNI/BIP 1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, an
analog input signal from 0V to VREF can be converted; in bipolar mode, the signal can range
from -VREF / 2 to +VREF / 2.
2 SGL/DIF 1 = single ended, 0 = differential. Selects single-ended or differential conversions. In single-
ended mode, input signal voltages are referred to COM. In differential mode, the voltage
difference between two channels is measured (Tables 2 and 3).
1 PD1 Selects clock and power-down modes.
0(LSB) PD0 PD1 PD0 Mode
0 0 Full power-down
0 1 Fast power-down (MAX1248 only)
1 0 Internal clock mode
1 1 External clock mode
MAX1248/MAX1249
plest software interface requires only three 8-bit transfers
to perform a conversion (one 8-bit transfer to configure
the ADC, and two more 8-bit transfers to clock out the
10-bit conversion result). See Figure 19 for MAX1248/
MAX1249 QSPI connections.
Simple Software Interface
Make sure the CPU’s serial interface runs in master
mode so the CPU generates the serial clock. Choose a
clock frequency from 100kHz to 2MHz.
1) Set up the control byte for external clock mode and
call it TB1. TB1 should be of the format: 1XXXXX11
binary, where the Xs denote the particular channel
and conversion mode selected.
2) Use a general-purpose I/O line on the CPU to pull
CS low.
3) Transmit TB1 and, simultaneously, receive a byte
and call it RB1. Ignore RB1.
4) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB2.
5) Transmit a byte of all zeros ($00 hex) and, simulta-
neously, receive byte RB3.
6) Pull CS high.
Figure 5 shows the timing for this sequence. Bytes RB2
and RB3 contain the result of the conversion padded
with one leading zero, two sub-bits, and three trailing
zeros. The total conversion time is a function of the
serial-clock frequency and the amount of idle time
between 8-bit transfers. To avoid excessive T/H droop,
make sure the total conversion time does not exceed
120µs.
Digital Output
In unipolar input mode, the output is straight binary
(Figure 16). For bipolar inputs, the output is two’s com-
plement (Figure 17). Data is clocked out at the falling
edge of SCLK in MSB-first format.
Clock Modes
The MAX1248/MAX1249 may use either an external
serial clock or the internal clock to perform the succes-
sive-approximation conversion. In both clock modes,
the external clock shifts data in and out of the
MAX1248/MAX1249. The T/H acquires the input signal
as the last three bits of the control byte are clocked into
DIN. Bits PD1 and PD0 of the control byte program the
clock mode. Figures 6–9 show the timing characteristics
common to both modes.
External Clock
In external clock mode, the external clock not only shifts
data in and out, it also drives the analog-to-digital con-
version steps. SSTRB pulses high for one clock period
after the last bit of the control byte. Successive-approxi-
mation bit decisions are made and appear at DOUT on
each of the next 10 SCLK falling edges (Figure 5).
SSTRB and DOUT go into a high-impedance state when
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
10 ______________________________________________________________________________________
SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3 COM
0 0 1 + –
1 0 1 + –
0 1 0 + –
1 1 0 + –
Table 2. Channel Selection in Single-Ended Mode (SGL/DDIIFF= 1)
SEL2 SEL1 SEL0 CH0 CH1 CH2 CH3
0 0 1 + –
0 1 0 + –
1 0 1 – +
1 1 0 – +
Table 3. Channel Selection in Differential Mode (SGL/DDIIFF= 0)
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
______________________________________________________________________________________ 11
CS goes high; after the next CS falling edge, SSTRB will
output a logic low. Figure 7 shows the SSTRB timing in
external clock mode.
The conversion must complete in some minimum time,
or droop on the sample-and-hold capacitors may
degrade conversion results. Use internal clock mode if
the serial-clock frequency is less than 100kHz, or if
serial-clock interruptions could cause the conversion
interval to exceed 120µs.
Figure 6. Detailed Serial-Interface Timing
Figure 5. 24-Clock External Clock Mode Conversion Timing (MICROWIRE and SPI-Compatible, QSPI-Compatible with fSCLK
≤
2MHz)
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
12 ______________________________________________________________________________________
Internal Clock
In internal clock mode, the MAX1248/MAX1249 gener-
ate their own conversion clocks internally. This frees the
µP from the burden of running the SAR conversion clock
and allows the conversion results to be read back at the
processor’s convenience, at any clock rate from 0MHz
to 2MHz. SSTRB goes low at the start of the conversion
and then goes high when the conversion is complete.
SSTRB is low for a maximum of 7.5µs (SHDN = FLOAT),
during which time SCLK should remain low for best
noise performance.
An internal register stores data when the conversion is
in progress. SCLK clocks the data out of this register at
any time after the conversion is complete. After SSTRB
goes high, the next falling clock edge produces the
MSB of the conversion at DOUT, followed by the
remaining bits in MSB-first format (Figure 8). CS does
not need to be held low once a conversion is started.
Pulling CS high prevents data from being clocked into
the MAX1248/MAX1249 and three-states DOUT, but it
does not adversely affect an internal clock mode con-
version already in progress. When internal clock mode
is selected, SSTRB does not go into a high-impedance
state when CS goes high.
Figure 9 shows the SSTRB timing in internal clock
mode. In this mode, data can be shifted in and out of
the MAX1248/MAX1249 at clock rates exceeding
2.0MHz if the minimum acquisition time, tACQ, is kept
above 1.5µs.
SSTRB
CS
SCLK
DIN
DOUT
1 4 8 12 18 20 24
START
SEL2 SEL1 SEL0 UNI/
BIP SGL/
DIF PD1 PD0
B9
MSB B8 B7 B0
LSB S1 S0 FILLED WITH
ZEROS
IDLE
CONVERSION
7.5µs MAX
(SHDN = FLOAT)
2 3 5 6 7 9 10 11 19 21 22 23
tCONV
ACQUISITION
(fSCLK = 2MHz)
IDLE
A/D STATE 1.5µs
Figure 8. Internal Clock Mode Timing
• • •
• • • • • •
• • •
tSDV
tSSTRB
PD0 CLOCKED IN
tSTR
SSTRB
SCLK
CS
tSSTRB
• • • • • • • •
Figure 7. External Clock Mode SSTRB Detailed Timing
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
______________________________________________________________________________________ 13
Data Framing
The falling edge of CS does not start a conversion. The
first logic high clocked into DIN is interpreted as a start
bit and defines the first bit of the control byte. A conver-
sion starts on the falling edge of SCLK, after the eighth
bit of the control byte (the PD0 bit) is clocked into DIN.
The start bit is defined as:
The first high bit clocked into DIN with CS low any
time the converter is idle; e.g., after V DD is applied.
OR
The first high bit clocked into DIN after bit 3 of a con-
version in progress is clocked onto the DOUT pin.
If CS is toggled before the current conversion is com-
plete, the next high bit clocked into DIN is recognized as
a start bit; the current conversion is terminated, and a
new one is started.
The fastest the MAX1248/MAX1249 can run with CS
held low between conversions is 15 clocks per conver-
sion. Figure 10a shows the serial-interface timing nec-
essary to perform a conversion every 15 SCLK cycles
in external clock mode. If CS is tied low and SCLK is
continuous, guarantee a start bit by first clocking in 16
zeros.
Most microcontrollers require that conversions occur in
multiples of 8 SCLK clocks; 16 clocks per conversion is
typically the fastest that a microcontroller can drive the
MAX1248/MAX1249. Figure 10b shows the serial-inter-
face timing necessary to perform a conversion every 16
SCLK cycles in external clock mode.
__________ Applications Information
Power-On Reset
When power is first applied, and if SHDN is not pulled
low, internal power-on reset circuitry activates the
MAX1248/MAX1249 in internal clock mode, ready to
convert with SSTRB = high. After the power supplies
have stabilized, the internal reset time is 10µs, and no
conversions should be performed during this phase.
SSTRB is high on power-up and, if CS is low, the first
logical 1 on DIN is interpreted as a start bit. Until a con-
version takes place, DOUT shifts out zeros (also see
Table 4).
Reference-Buffer Compensation
In addition to its shutdown function, SHDN selects inter-
nal or external compensation. The compensation
affects both power-up time and maximum conversion
speed. The 100kHz minimum clock rate is limited by
droop on the sample-and-hold, and is independent of
the compensation used.
Figure 9. Internal Clock Mode SSTRB Detailed Timing
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
14 ______________________________________________________________________________________
Float SHDN to select external compensation. The
Typical Operating Circuit
uses a 4.7µF capacitor at
VREF. A value of 4.7µF or greater ensures reference-
buffer stability and allows converter operation at the
2MHz full clock speed. External compensation increas-
es power-up time (see
Choosing Power-Down Mode
and Table 4).
Pull SHDN high to select internal compensation.
Internal compensation requires no external capacitor at
VREF and allows for the shortest power-up times. The
maximum clock rate is 2MHz in internal clock mode
and 400kHz in external clock mode.
Choosing Power-Down Mode
You can save power by placing the converter in a low-
current shutdown state between conversions. Select full
power-down or fast power-down mode via bits 1 and 0
of the DIN control byte with SHDN high or floating
(Tables 1 and 5). In both software power-down modes,
the serial interface remains operational, but the ADC
does not convert. Pull SHDN low at any time to shut
down the converter completely. SHDN overrides bits 1
and 0 of the control byte.
Full power-down mode turns off all chip functions that
draw quiescent current, reducing supply current typically
to 2µA. Fast power-down mode turns off all circuitry
except the bandgap reference. With fast power-down
mode, the supply current is 30µA. Power-up time can be
shortened to 5µs in internal compensation mode.
Table 4 shows how the choice of reference-buffer com-
pensation and power-down mode affects both power-up
delay and maximum sample rate. In external compensa-
tion mode, power-up time is 20ms with a 4.7µF compen-
sation capacitor when the capacitor is initially fully
discharged. From fast power-down, start-up time can be
eliminated by using low-leakage capacitors that do not
discharge more than 1/2LSB while shut down. In power-
down, leakage currents at VREF cause droop on the ref-
erence bypass capacitor. Figures 11a and 11b show
the various power-down sequences in both external and
internal clock modes.
SCLK
DIN
DOUT
CS
S CONTROL BYTE 0 CONTROL BYTE 1S
CONVERSION RESULT 0
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONVERSION RESULT 1
SSTRB
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0
CONTROL BYTE 2S
18 1 8 1
CS
SCLK
DIN
DOUT
S CONTROL BYTE 0 CONTROL BYTE 1S
CONVERSION RESULT 0
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 S1 S0 B9 B8 B7 B6
CONVERSION RESULT 1
• • •
• • •
• • •
• • •
Figure 10a. External Clock Mode, 15 Clocks/Conversion Timing
Figure 10b. External Clock Mode, 16 Clocks/Conversion Timing
POWERED UP HARDWARE
POWER-
DOWN POWERED UP
POWERED UP
10+2 DATA BITS 10+2 DATA BITS INVALID
DATA
VALID
DATA
EXTERNAL
EXTERNAL
SXXXXX1 1 S 0 0
X XXXX X X X X X
S 1 1
SOFTWARE
POWER-DOWN
MODE
DOUT
DIN
CLOCK
MODE
SHDN SETS EXTERNAL
CLOCK MODE SETS EXTERNAL
CLOCK MODE
SETS SOFTWARE
POWER-DOWN
POWER-DOWN POWERED UP
POWERED UP
DATA VALID DATA VALID
INTERNAL
SXXXXX1 0 S 0 0
X XXXX S
MODE
DOUT
DIN
CLOCK
MODE SETS INTERNAL
CLOCK MODE SETS
POWER-DOWN
CONVERSION
CONVERSION
SSTRB
Figure 11a. Timing Diagram Power-Down Modes, External Clock
Figure 11b. Timing Diagram Power-Down Modes, Internal Clock
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
______________________________________________________________________________________ 15
REFERENCE
BUFFER
REFERENCE-BUFFER
COMPENSATION
MODE
VREF
CAPACITOR
(µF)
POWER-DOWN
MODE
POWER-UP
DELAY
(µs)
MAXIMUM
SAMPLING RATE
(ksps)
Disabled — — Full 2 133
Enabled Internal — Fast 5 26
Enabled Internal — Full 300 26
Enabled External 4.7 Fast See Figure 13c 133
Enabled External 4.7 Full See Figure 13c 133
Disabled — — Fast 2 133
Table 4. Typical Power-Up Delay Times
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
16 ______________________________________________________________________________________
Software Power-Down
Software power-down is activated using bits PD1 and PD0
of the control byte. As shown in Table 5, PD1 and PD0
also specify the clock mode. When software shutdown is
asserted, the ADC operates in the last specified clock
mode until the conversion is complete. Then the ADC
powers down into a low quiescent-current state. In internal
clock mode, the interface remains active, and conversion
results may be clocked out after the MAX1248/MAX1249
enter a software power-down.
The first logical 1 on DIN is interpreted as a start bit
and powers up the MAX1248/MAX1249. Following the
start bit, the data input word or control byte also deter-
mines clock mode and power-down states. For exam-
ple, if the DIN word contains PD1 = 1, then the chip
remains powered up. If PD0 = PD1 = 0, a power-down
resumes after one conversion.
Hardware Power-Down
Pulling SHDN low places the converter in hardware
power-down (Table 6). Unlike software power-down
mode, the conversion is not completed; it stops coinci-
dentally with SHDN being brought low. SHDN also con-
trols the clock frequency in internal clock mode. Letting
SHDN float sets the internal clock frequency to 1.8MHz.
When returning to normal operation with SHDN floating,
there is a tRC delay of approximately 2MΩx CL, where
CLis the capacitive loading on the SHDN pin. Pulling
SHDN high sets the internal clock frequency to 225kHz.
This feature eases the settling-time requirement for the
reference voltage. With an external reference, the
MAX1248/MAX1249 can be considered fully powered
up within 2µs of actively pulling SHDN high.
Power-Down Sequencing
The MAX1248/MAX1249 auto power-down modes can
save considerable power when operating at less than
maximum sample rates. Figures 12, 13a, and 13b show
the average supply current as a function of the sampling
rate. The following discussion illustrates the various
power-down sequences.
Lowest Power at up to 500
Conversions/Channel/Second
The following examples illustrate two different power-
down sequences. Other combinations of clock rates,
compensation modes, and power-down modes may
give lowest power consumption in other applications.
Figure 13a depicts the MAX1248 power consumption
for one or eight channel conversions, utilizing full
power-down mode and internal-reference compensa-
tion. A 0.01µF bypass capacitor at REFADJ forms an
RC filter with the internal 20kΩreference resistor with a
0.2ms time constant. To achieve full 10-bit accuracy, 8
time constants or 1.6ms are required after power-up.
Waiting 1.6ms in FASTPD mode instead of in full power-
up can reduce the power consumption by a factor of 10
or more. This is achieved by using the sequence shown
in Figure 14.
Table 5. Software Power-Down and
Clock Mode
Table 6. Hardware Power-Down and
Internal Clock Frequency
SSHHDDNN
STATE DEVICE
MODE
REFERENCE-
BUFFER
COMPENSATION
INTERNAL
CLOCK
FREQUENCY
1 Enabled Internal 225kHz
Floating Enabled External 1.8MHz
0Power-
Down N/A N/A
1000
10,000
0.10.1
100
10
1
CONVERSION RATE (Hz)
IDD (µA)
1 10010 1k 10k 1M100k
VREF = VDD = 3.0V
RLOAD = ∞
CODE = 1010101000
1 CHANNEL
4 CHANNELS
Figure 12. Average Supply Current vs. Conversion Rate
with External Reference
PD1 PD0 DEVICE
0 0 Full Power-Down
0 1 Fast Power-Down
1 0 Internal Clock
1 1 External Clock
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
Lowest Power at Higher Throughputs
Figure 13b shows the power consumption with
external-reference compensation in fast power-down,
with one and four channels converted. The external
4.7µF compensation requires a 75µs wait after power-up
with one dummy conversion. This circuit combines fast
multi-channel conversion with lowest power consumption
possible. Full power-down mode may provide increased
power savings in applications where the
MAX1248/MAX1249 are inactive for long periods of time,
but where intermittent bursts of high-speed conversions
are required.
Internal and External References
The MAX1248 can be used with an internal or external
reference voltage, whereas an external reference is
required for the MAX1249. An external reference can
be connected directly at VREF or at the REFADJ pin.
An internal buffer is designed to provide 2.5V at VREF
for both the MAX1248 and the MAX1249. The
MAX1248’s internally trimmed 1.21V reference is
buffered with a gain of 2.06. The MAX1249’s REFADJ
pin is also buffered with a gain of 2.06 to scale an
external 1.25V reference at REFADJ to 2.5V at VREF.
Internal Reference (MAX1248)
The MAX1248’s full-scale range with the internal refer-
ence is 2.5V with unipolar inputs and ±1.25V with bipo-
lar inputs. The internal-reference voltage is adjustable
to ±1.5% with the circuit of Figure 15.
1
10
100
0.01 0.1 1 10 100 1k
CONVERSION RATE (Hz)
AVERAGE SUPPLY CURRENT (µA)
1 CHANNEL
RLOAD = ∞
CODE = 1010101000
4 CHANNELS
Figure 13a. MAX1248 Supply Current vs. Conversion Rate,
FULLPD
1
10
100
10,000
1000
0.1 101 100 1k 10k 100k 1M
CONVERSION RATE (Hz)
AVERAGE SUPPLY CURRENT (µA)
RLOAD = ∞
CODE = 1010101000
4 CHANNELS
1 CHANNEL
3.0
2.5
2.0
1.5
1.0
0.5
00 0.01 0.1 1 10
TIME IN SHUTDOWN (sec)
POWER-UP DELAY (ms)
Figure 13b. MAX1248 Supply Current vs. Conversion Rate,
FASTPD
Figure 13c. Typical Reference-Buffer Power-Up Delay vs. Time
in Shutdown
______________________________________________________________________________________ 17
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
External Reference
With both the MAX1248 and MAX1249, an external ref-
erence can be placed at either the input (REFADJ) or
the output (VREF) of the internal reference-buffer ampli-
fier. The REFADJ input impedance is typically 20kΩfor
the MAX1248 and higher than 100kΩfor the MAX1249,
where the internal reference is omitted. At VREF, the
DC input resistance is a minimum of 18kΩ. During con-
version, an external reference at VREF must deliver
up to 350µA DC load current and have an output
impedance of 10Ωor less. If the reference has higher
output impedance or is noisy, bypass it close to the
VREF pin with a 4.7µF capacitor.
Using the REFADJ input makes buffering the external
reference unnecessary. To use the direct VREF input,
disable the internal buffer by tying REFADJ to VDD. In
power-down, the input bias current to REFADJ can be
as much as 25µA with REFADJ tied to VDD. Pull
REFADJ to AGND to minimize the input bias current in
power-down.
Transfer Function
Table 7 shows the full-scale voltage ranges for unipolar
and bipolar modes.
The external reference must have a temperature coeffi-
cient of 20ppm/°C or less to achieve accuracy to within
1LSB over the commercial temperature range of 0°C to
+70°C.
Figure 16 depicts the nominal, unipolar input/output
(I/O) transfer function, and Figure 17 shows the bipolar
input/output transfer function. Code transitions occur
halfway between successive-integer LSB values.
Output coding is binary, with 1LSB = 2.44mV (2.500V /
1024) for unipolar operation and 1LSB = 2.44mV
[(2.500V / 2 - -2.500V / 2) / 1024] for bipolar operation.
OUTPUT CODE
FULL-SCALE
TRANSITION
11 . . . 111
11 . . . 110
11 . . . 101
00 . . . 011
00 . . . 010
00 . . . 001
00 . . . 000 1 2 3
0
(COM) FS
FS - 3/2LSB
FS = VREF + COM
ZS = COM
INPUT VOLTAGE (LSBs)
1LSB =
VREF
1024
Figure 16. Unipolar Transfer Function, Full Scale (FS) = VREF
+ COM, Zero Scale (ZS) = COM
+3.3V
510k
24k
100k
0.01µF
9REFADJ
MAX1248
Figure 15. MAX1248 Reference-Adjust Circuit
1 0 0
DIN
REFADJ
VREF
1.21V
0V
2.50V
0V
1 0 1 1 11 1 0 0 1 0 1
FULLPD FASTPD NOPD FULLPD FASTPD
1.6ms WAIT
COMPLETE CONVERSION SEQUENCE
tBUFFEN ≈ 75µs
τ = RC = 20kΩ x CREFADJ
(ZEROS) CH1 CH7 (ZEROS)
Figure 14. MAX1248 FULLPD/FASTPD Power-Up Sequence
18 ______________________________________________________________________________________
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
______________________________________________________________________________________ 19
UNIPOLAR MODE BIPOLAR MODE
Full Scale Zero Scale Positive Zero Negative
Full Scale Scale Full Scale
VREF + COM COM VREF / 2 COM -VREF / 2
+ COM + COM
011 . . . 111
011 . . . 110
000 . . . 010
000 . . . 001
000 . . . 000
111 . . . 111
111 . . . 110
111 . . . 101
100 . . . 001
100 . . . 000
- FS COM*
OUTPUT CODE
ZS = COM
+FS - 1LSB
INPUT VOLTAGE (LSB)
+ COM
FS = VREF
2
-FS = + COM
-VREF
2
1LSB = VREF
1024
*COM ≥ VREF / 2
+3V +3V GND
SUPPLIES
DGND+3VDGNDCOM
AGNDVDD
DIGITAL
CIRCUITRY
MAX1248
MAX1249
R* = 10Ω
* OPTIONAL
Figure 17. Bipolar Transfer Function, Zero Scale (ZS) = COM,
Full Scale (FS) = VREF / 2 + COM Figure 18. Power-Supply Grounding Connection
Table 7. Full Scale and Zero Scale
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards.
Wire-wrap boards are not recommended. Board layout
should ensure that digital and analog signal lines are
separated from each other. Do not run analog and digi-
tal (especially clock) lines parallel to one another, or
digital lines underneath the ADC package.
Figure 18 shows the recommended system ground
connections. Establish a single-point analog ground
(star ground point) at AGND, separate from the logic
ground. Connect all other analog grounds and DGND
to the star ground. No other digital system ground
should be connected to this ground. For lowest noise
operation, the ground return to the star ground’s power
supply should be low impedance and as short as pos-
sible.
High-frequency noise in the VDD power supply may
affect the ADC’s high-speed comparator. Bypass the
supply to the star ground with 0.1µF and 1µF capaci-
tors close to pin 1 of the MAX1248/MAX1249. Minimize
capacitor lead lengths for best supply-noise rejection.
If the +3V power supply is very noisy, a 10Ωresistor
can be connected as a lowpass filter (Figure 18).
High-Speed Digital Interfacing with QSPI
The MAX1248/MAX1249 can interface with QSPI using
the circuit in Figure 19 (fSCLK = 2.0MHz, CPOL = 0,
CPHA = 0). This QSPI circuit can be programmed to do a
conversion on each of the four channels. The result is
stored in memory without taxing the CPU, since QSPI
incorporates its own micro-sequencer.
The MAX1248/MAX1249 are QSPI compatible up to their
maximum external clock frequency of 2MHz.
MAX1248/MAX1249
TMS320LC3x Interface
Figure 20 shows an application circuit to interface the
MAX1248/MAX1249 to the TMS320 in external clock
mode. The timing diagram for this interface circuit is
shown in Figure 21.
Use the following steps to initiate a conversion in the
MAX1248/MAX1249 and to read the results:
1) The TMS320 should be configured with CLKX
(transmit clock) as an active-high output clock and
CLKR (TMS320 receive clock) as an active-high
input clock. CLKX and CLKR on the TMS320 are
tied together with the MAX1248/MAX1249’s SCLK
input.
2) The MAX1248/MAX1249’s CS pin is driven low by
the TMS320’s XF_ I/O port, to enable data to be
clocked into the MAX1248/MAX1249’s DIN.
3) An 8-bit word (1XXXXX11) should be written to the
MAX1248/MAX1249 to initiate a conversion and
place the device into external clock mode. Refer to
Table 1 to select the proper XXXXX bit values for
your specific application.
4) The MAX1248/MAX1249’s SSTRB output is moni-
tored via the TMS320’s FSR input. A falling edge on
the SSTRB output indicates that the conversion is in
progress and data is ready to be received from the
MAX1248/MAX1249.
5) The TMS320 reads in one data bit on each of the
next 16 rising edges of SCLK. These data bits rep-
resent the 10 + 2-bit conversion result followed by
four trailing bits, which should be ignored.
6) Pull CS high to disable the MAX1248/MAX1249 until
the next conversion is initiated.
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
20 ______________________________________________________________________________________
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
MAX1248
MAX1249
MC683XX
SCK
PCS0
MOSI
MISO
CLOCK CONNECTIONS NOT SHOWN
1µF
0.1µF
0.1µF
(GND)
ANALOG
INPUTS
+3V
+3V
VDD
CH0
CH1
CH2
CH3
COM
SHDN
VREF
SCLK
CS
DIN
SSTRB
DOUT
DGND
AGND
REFADJ
+2.5V
XF
CLKX
CLKR
DX
DR
FSR
CS
SCLK
DIN
DOUT
SSTRB
TMS320LC3x MAX1249
Figure 20. MAX1248/MAX1249-to-TMS320 Serial Interface
Figure 19. MAX1248/MAX1249 QSPI Connections External Reference
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
______________________________________________________________________________________ 21
___________________________________________Ordering Information (continued)
†
Contact factory for availability of alternate surface-mount packages.
*
Contact factory for availability of CERDIP package, and for processing to MIL-STD-883B.
CS
SCLK
DIN
SSTRB
DOUT
START SEL2 SEL1 SEL0 UNI/BIP SGL/DIF PD1 PD0
MSB B8 B0
LSB S1 S0 HIGH
IMPEDANCE
HIGH
IMPEDANCE
Figure 21. TMS320 Serial-Interface Timing Diagram
±116 Plastic DIP0°C to +70°CMAX1249BCPE ±1/216 Plastic DIP0°C to +70°C
MAX1249ACPE
±116 Plastic DIP-40°C to +85°CMAX1248BEPE
±1
±1/2
16 CERDIP*-55°C to +125°C
±1
16 CERDIP*-55°C to +125°C
±1/2
±1/2
INL
(LSB)
MAX1248BMJE
MAX1248AMJE 16 QSOP
16 QSOP
16 Plastic DIP
PIN-PACKAGETEMP. RANGE
-40°C to +85°C
-40°C to +85°C
-40°C to +85°CMAX1248BEEE
MAX1248AEEE
MAX1248AEPE
PART†INL
(LSB)
PIN-PACKAGETEMP. RANGEPART†
±116 QSOP-40°C to +85°CMAX1249BEEE ±1/216 QSOP-40°C to +85°CMAX1249AEEE ±116 Plastic DIP-40°C to +85°CMAX1249BEPE
±116 CERDIP*-55°C to +125°CMAX1249BMJE ±1/2
±1/2
16 CERDIP*-55°C to +125°C
±1
16 Plastic DIP-40°C to +85°C
±1/2
MAX1249AMJE
MAX1249AEPE 16 QSOP
16 QSOP0°C to +70°C
0°C to +70°CMAX1249BCEE
MAX1249ACEE
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
22 ______________________________________________________________________________________
QSOP.EPS
________________________________________________________Package Information
___________________Chip Information
TRANSISTOR COUNT: 2554
16
15
14
13
12
11
10
9
1
2
3
4
5
6
7
8
SCLK
CS
DIN
SSTRB
DOUT
DGND
AGND
REFADJ
VDD
CH0
CH1
CH2
CH3
COM
SHDN
VREF
TOP VIEW
MAX1248
MAX1249
DIP/QSOP
_________________
Pin Configuration
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
______________________________________________________________________________________ 23
PDIPN.EPS
CDIPS.EPS
___________________________________________Package Information (continued)
MAX1248/MAX1249
+2.7V to +5.25V, Low-Power, 4-Channel,
Serial 10-Bit ADCs in QSOP-16
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
24
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