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EN5322QI 2A PowerSoC
Step-Down DC-DC Switching Converter with Integrated Inductor
DESCRIPTION
The EN5322QI is a high efficiency synchronous buck
converter with integrated inductor, PWM controller,
MOSFETS, and compensation providing the smallest
possible solution size.
The 4 MHz operation allows for the use of tiny MLCC
capacitors. It also enables a very wide control loop
bandwidth providing excellent transient performance
and reduced output impedance. The internal
compensation is designed for unconditional stability
across all operating conditions.
Three VID output voltage select pins provide seven
pre-programmed output voltages along with an
option for external resistor divider. Output voltage
can be programmed on-the-fly to provide fast,
dynamic voltage scaling with smooth transitions
between VID programmed output voltages.
Intel Enpirion Power Solutions significantly help in
system design and productivity by offering greatly
simplified board design, layout and manufacturing
requirements. In addition, a reduction in the number
of components required for the complete power
solution helps to enable an overall system cost
saving.
All Intel Enpirion products are RoHS compliant and
lead-free manufacturing environment compatible.
FEATURES
• Revolutionary Integrated Inductor
• Total Solution Footprint as Small as 50 mm2
• High Efficiency, up to 95 %
• Low Ripple Voltage; 8 mVP-P Typical
• 2% Initial VOUT Accuracy with VID Codes
• 2.4 V to 5.5 V Input Voltage Range
• 2 A Continuous Output Current Capability
• Low Dropout Operation: 100 % Duty Cycle
• Power OK Signal with 5 mA Sink Capability
• Dynamic Voltage Scaling with VID Codes
• 17 µA Typical Shutdown Current
• Under Voltage Lockout, Over Current, Short
Circuit, and Thermal Protection
• RoHS Compliant; MSL 3 260 °C Reflow
APPLICATIONS
• Low Power Processors, Network Processors,
DSPs’ FPGAs and ASICs
• Replacement of LDOs
• Noise Sensitive Applications such as A/V and RF
• Computing, Computer Peripherals, Storage,
Networking, and Instrumentation
• DSL, STB, DVR, DTV, and iPC
EN5322
10 uF 47 uF
VO UTPV IN
AG ND
V
IN VS ENSE
PO K
VS0
VS1
VS2
ENAB LE
AV IN
PG ND
C
IN
C
OUT
1 uF
V
OUT
PG ND
OFF
ON
Figure 1. Typical Application Circuit
Figure 2. Efficincy at VIN =5V
50
55
60
65
70
75
80
85
90
95
00.5 11 .5 2
EFFICIENCY (%)
OUTPUT CURRENT (A)
Efficiency vs. Output Current
VOUT= 2.5V
DataSheeT
– enpirion® power solutions
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Datasheet | Intel® Enpirion® Power Solutions: EN5322QI
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ORDERING INFORMATION
Part Number Package Markings TJ Rating Package Description
EN5322QI EN5322 -40°C to +125°C 24-pin (4mm x 6mm x 1.1mm) QFN
EVB-EN5322QI EVB-EN5322QI QFN Evaluation Board
Packing and Marking Information: https://www.intel.com/support/quality-and-reliability/packing.html
PIN FUNCTIONS
Figure 3. Pin Diagram (Top View)
NOTE A: NC pins are not to be electrically connected to each other or to any external signal, ground, or voltage. However,
they must be soldered to the PCB. Failure to follow this guideline may result in part malfunction or damage.
NOTE B: White ‘dot’ on top left is pin 1 indicator on top of the device package.
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PIN DESCRIPTIONS
PIN NAME TYPE FUNCTION
1, 21-
24 NC(SW) -
No Connect. These pins are internally connected to the common drain
output of the internal MOSFETs. NC(SW) pins are not to be electrically
connected to any external signal, ground, or voltage. However, they must
be soldered to the PCB. Failure to follow this guideline may result in part
malfunction or damage.
2-3, 8-
9 PGND Power
Input/Output Power Ground. Connect these pins to the ground electrode
of the input and output filter capacitors. Refer to Layout Considerations
section for details.
4-7 VOUT Power Voltage and Power Output. Connect these pins to output capacitor(s).
10-12 VS2-VS0 Analog
Output Voltage Select. These pins set one of seven preset output
voltages and the external divider option (refer to Electrical Characteristics
table for more details), and can be directly pulled up to VIN or pulled down
to GND; these pins must not be left floating.
13 VSENSE Analog
Sense Pin for Internally Programmed Output Voltages with VID Codes.
For either VID code or external resistor divider applications, connect this
pin to the last local output filter capacitor for internal compensation.
14 VFB Analog
Feedback Pin for External Voltage Divider Network. Connect a resistor
divider to this pin to set the output voltage. Use 340 kΩ, 1% or better for
the upper resistor.
15 AGND Power Analog Ground for the Controller Circuits.
16 AVIN Power Analog Voltage Input for the Controller Circuits. Connect this pin to the
input power supply. Use a 1 µF bypass capacitor on this pin.
17 POK Analog Power OK with an Open Drain Output. Refer to Power OK section.
18 ENABLE Analog
Input Enable. A logic high signal on this pin enables the output and
initiates a soft start. A logic low signal disables the output and discharges
the output to GND. The ENABLE pin should not be left floating as it could
be in an unknown and random state. It is recommended to enable the
device after both PVIN and AVIN is in regulation. See ENABLE operation
for details.
19-20 PVIN Power Input Power Supply. Connect to input supply. Decouple with input
capacitor(s) to PGND.
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ABSOLUTE MAXIMUM RATINGS
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond the recommended
operating conditions is not implied. Stress beyond the absolute maximum ratings may impair device
life. Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
Absolute Maximum Pin Ratings
PARAMETER SYMBOL MIN MAX UNITS
Voltages on: PVIN, AVIN, VOUT -0.3 6.5 V
Voltages on: VSENSE, VS0, VS1,
VS2, ENABLE, POK -0.3 VIN V
Voltage on: VFB -0.3 2.7 V
Absolute Maximum Thermal Ratings
PARAMETER CONDITION MIN MAX UNITS
Maximum Operating Junction
Temperature +150 °C
Storage Temperature Range -65 +150 °C
Reflow Peak Body Temperature (10 Sec) MSL3 JEDEC J-STD-
020A +260 °C
Absolute Maximum ESD Ratings
PARAMETER CONDITION MIN MAX UNITS
HBM (Human Body Model) ±2000 V
CDM (Charged Device Model) ±500 V
RECOMMENDED OPERATING CONDITIONS
PARAMETER SYMBOL MIN MAX UNITS
Input Voltage Range VIN 2.4 5.5 V
Output Voltage Range VOUT 0.6 VIN – VDR (1) V
Output Current Range IOUT 0 2 A
Operating Ambient Temperature Range TA -40 +85 °C
Operating Junction Temperature TJ -45 +125 °C
(1) VDROPOUT is defined as (ILOAD x Dropout Resistance) including temperature effect.
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THERMAL CHARACTERISTICS
PARAMETER SYMBOL TYPICAL UNITS
Thermal Shutdown TSD 155 °C
Thermal Shutdown Hysteresis TSDHYS 15 °C
Thermal Resistance: Junction to Ambient (0 LFM) (2) θJA 36 °C/W
Thermal Resistance: Junction to Case (0 LFM) θJC 6 °C/W
(2) Based on a 2 oz. copper board and proper thermal design in line with JEDEC EIJ-JESD51 standards
ELECTRICAL CHARACTERISTICS
NOTE: TA = 25°C unless otherwise noted. Typical values are at VIN = 5V.
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Operating Input Voltage VIN 2.4 5.5 V
Under Voltage Lock-out VUVLO VIN going low to high 2.2 V
UVLO Hysteresis 0.15 V
Output Voltage with VID
Codes (3) VOUT TA = 25 °C; VIN = 5V
ILOAD = 100 mA
-2.0 +2.0 %
Feedback Pin Voltage VFB
TA = 25 °C; VIN = 5V
ILOAD = 100 mA, VS0 = VS1 =
VS2 = 1
0.588 0.600 0.612 V
Output Voltage with VID
Codes (3) VOUT
2.4 V ≤ VIN ≤ 5.5 V, ILOAD = 0
~ 2 A, -40°C ≤ TA ≤ +85°C
VOUT> 0.8V
VOUT≤ 0.8V
-3.0
-3.5
+3.0
+3.0
%
Feedback Pin Voltage VFB
2.4V ≤ VIN ≤ 6.6V, ILOAD = 0 -2A,
TA = -40°C to +85°C,
VS0=VS1=VS2=1
0.582 0.600 0.618 V
Dynamic Voltage Slew
Rate Switching between VID
settings 0.975 1.5 2.025 V/ms
Soft Start Slew Rate VID Mode VOUT Programming 0.975 1.5 2.025 V/ms
Soft Start Time VFB Mode VOUT
Programming 0.78 1.2 1.62 ms
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PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
VFB, ENABLE, VS0-VS2
Pin Input Current (4) -40°C ≤ TA ≤ +85°C +/-40 nA
ENABLE, VS0-VS2
Voltage Threshold Logic Low
Logic High
0.0
1.4
0.4
VIN
V
POK Upper Threshold VOUT Rising 111 %
POK Upper Threshold VOUT Falling 102 %
POK Lower Threshold VOUT Rising 92 %
POK Lower Threshold VOUT Falling 90 %
POK Low Voltage ISINK = 5 mA, -40°C ≤ TA ≤
+85°C 0.15 0.4 V
POK Pin VOH Leakage
Current POK High, -40°C ≤ TA ≤ +85°C 500 nA
Shutdown Current ENABLE Low 17 µA
Quiescent Current No Switching 800 µA
Quiescent Current Switching, VOUT = 1.2 V 15 mA
Current Limit Threshold 2.4 V ≤ VIN ≤ 5.5 V,
-40°C ≤ TA ≤ +85°C
2.1 3.0 A
PFET On Resistance 160 mΩ
NFET On Resistance 60 mΩ
Dropout Resistance 200 300 mΩ
Operating Frequency FOSC 4 MHz
Output Ripple Voltage VRIPPLE
COUT = 1 x 47 µF 1206 X5R
MLCC, VOUT = 1.2 V, ILOAD = 2 A 14 mVP-P
COUT = 2 x 22 µF 0805 X5R
MLCC, VOUT = 1.2 V, ILOAD = 2 A 8 mVP-P
(3) The tolerances hold true only if VIN is greater than (VOUT + VDROPOUT).
(4) VFB, ENABLE, VS0-VS2 pin input current specification is guaranteed by design.
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TYPICAL PERFORMANCE CURVES
Top to Bottom: VOUT = 3.3V, 2.5V, 1.8V, 1.5V, 1.2V, 0.8V
Top to Bottom: VOUT = 2.5V, 1.8V, 1.5V, 1.2V, 0.8V
Quiescent Currect (No Switching) vs. Input Voltage
Quiescent Currect (Switching) vs. Input Voltage
Load Regulation (VIN= 5 V, VOUT= 1.2V)
Load Regulation (VIN= 5 V, VOUT= 3.3V)
Efficiency vs. Load Current (Vin = 5.0V)
50
55
60
65
70
75
80
85
90
95
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Load Current (A)
Efficiency (%)
Efficiency vs. Load Current (Vin = 3.3V)
50
55
60
65
70
75
80
85
90
95
0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
Load Current (A)
Efficiency (%)
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TYPICAL PERFORMANCE CHARACTERISTICS
Output Ripple: VIN = 3.3V, VOUT = 1.2V, ILOAD = 2A, COUT =
1 x 47µF
Output Ripple: VIN = 3.3V, VOUT = 1.2V, ILOAD = 2A, COUT =
2 x 22µF
Transient Response: VIN= 5V, VOUT= 1.2V, COUT= 1x47μF,
0-2A Load Step, Slew Rate ≥ 10A/μS
CH1: VOUT, CH4: ILOAD
Transient Response: VIN= 5V, VOUT= 3.3V, COUT= 1x47μF,
0-2A Load Step, Slew Rate ≥ 10A/μS
CH1: VOUT, CH4: ILOAD
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TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
VOUT Scaling with VID Codes at VIN= 5V
(VOUT = 1.2 V – 2.5 V, IOUT = 0 – 2 A)
CH1: VS2, CH2: VOUT, CH3: POK
VOUT Scaling with VID Codes at VIN= 3.3V
(VOUT = 1.2 V – 2.5 V, IOUT = 0 – 2 A)
CH1: VS2, CH2: VOUT, CH3: POK
Power Up/Down at No Load: VIN= 5V, VOUT= 1.2V
CH1: ENABLE, CH2: VOUT, CH3: POK, CH4: IINDUCTOR
Power Up/Down at 0.6Ω: VIN= 5V, VOUT= 1.2V
CH1: ENABLE, CH2: VOUT, CH3: POK, CH4: IINDUCTOR
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TYPICAL PERFORMANCE CHARACTERISTICS (CONTINUED)
Output Over Load at No Load: VIN= 5V, VOUT= 1.2V
CH2: VOUT, CH3: POK, CH4: IINDUCTOR
Output Over Load at 2A Load: VIN= 5V, VOUT= 1.2V
CH2: VOUT, CH3: POK, CH4: IINDUCTOR
Output Over Load at No Load: VIN= 5V, VOUT= 1.2V
CH2: VOUT, CH3: POK, CH4: IINDUCTOR
Output Over Load at 2A Load: VIN= 5V, VOUT= 1.2V
CH2: VOUT, CH3: POK, CH4: IINDUCTOR
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FUNCTIONAL BLOCK DIAGRAM
Voltage
Select
DAC
Switch
VREF
(+)
(-)
Error
Amp
VSENSE
VFB
VOUT
VS0 VS1 VS2
Package Boundary
P-Drive
N-Drive
UVLO
Thermal Limit
Current Limit
Soft Start
Sawtooth
Generator
(+)
(-)
PWM
Comp
PVIN
ENABLE
PGND
Logic
Compensation
Network
NC (SW)
POK
POK
AVIN AGND
BIAS
Figure 4. Functional Block Diagram
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FUNCTIONAL DESCRIPTION
Synchronous DC-DC Step-Down PowerSoC
The EN5322QI leverages advanced CMOS technology to provide high switching frequency, while also
maintaining high efficiency.
Packaged in a 4 mm x 6 mm x 1.1 mm QFN, the EN5322QI provides a high degree of flexibility in circuit design
while maintaining a very small footprint. High switching frequency allows for the use of very small MLCC input
and output filter capacitors.
The converter uses voltage mode control to provide high noise immunity, low output impedance and excellent
load transient response. No external compensation components are needed for most applications.
Output voltage is chosen from one of seven preset values via a three-pin VID voltage select scheme. An
external divider option enables the selection of any output voltage ≥ 0.6 V. The VID pins can be toggled
dynamically to implement glitch-free dynamic voltage scaling between any two VID preset values.
POK monitors the output voltage and signals if it is within ±10% of nominal. Protection features include under
voltage lockout (UVLO), over current protection, short circuit protection, and thermal overload protection.
Stability over Wide Range of Operating Conditions
The EN5322QI utilizes an internal compensation network and is designed to provide stable operation over a
wide range of operating conditions. To improve transient performance or reduce output voltage ripple with
dynamic loads you have the option to add supplementary capacitance to the output. When programming
VOUT using the VID pins, the EN5322QI is stable with up to 60µF of output capacitance without compensation
adjustment. Additional output capacitance above 60µF can be accommodated with compensation adjustment
depending on the application. When programming VOUT with the resistor divider option, the maximum output
capacitance may be limited. Please refer to the section on soft start for more details. The high switching
frequency allows for a wide control loop bandwidth.
Soft Start
The EN5322QI has an internal soft-start circuit that controls the ramp of the output voltage. The control
circuitry limits the VOUT ramp rate to levels that are safe for the Power MOSFETS and the integrated inductor.
The EN5322QI has two soft start operating modes. When VOUT is programmed using a preset voltage in VID
mode, the device has a constant slew rate. When the EN5322QI is configured in external resistor divider mode,
the device has a constant VOUT ramp time. Output voltage slew rate and ramp time is given in the Electrical
Characteristics Table.
Excess bulk capacitance on the output of the device can cause an over-current condition at startup.
When operating in VID mode, the maximum total capacitance on the output, including the output filter
capacitor and bulk and decoupling capacitance, at the load, is given as:
COUT_TOTAL_MAX = COUT_Filter + COUT_BULK = 1000μF
When the EN5322QI output voltage is programmed using and external resistor divider the maximum total
capacitance on the output is given as:
COUT_TOTAL_MAX = 1.867x10-3/VOUT Farads
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The above number and formula assume a no load condition at startup.
Over Current/Short Circuit Protection
When an over current condition occurs, VOUT is pulled low. This condition is maintained for a period of 1.2 ms
and then a normal soft start cycle is initiated. If the over current condition still persists, this cycle will repeat.
Under Voltage Lockout
An under voltage lockout circuit will hold off switching during initial power up until the input voltage reaches
sufficient level to ensure proper operation. If the voltage drops below the UVLO threshold the lockout circuitry
will again disable switching. Hysteresis is included to prevent chattering between UVLO high and low states.
Enable
The ENABLE pin provides means to shut down the converter or initiate normal operation. A logic high will
enable the converter to go through the soft start cycle and regulate the output voltage to the desired value.
A logic low will allow the device to discharge the output and go into shutdown mode for minimal power
consumption. When the output is discharged, an auxiliary NFET turns on and limits the discharge current to
300 mA or below. In shutdown mode, the device typically drains 17µA. The ENABLE pin should not be left
floating as it could be in an unknown and random state. It is recommended to enable the device after both
PVIN and AVIN is in regulation.
At extremely cold conditions below -30°C, the controller may not be properly powered if ENABLE is tied
directly to AVIN during startup. It is recommended to use an external RC circuit to delay the ENABLE voltage
rise so that the internal controller has time to startup into regulation (see circuit below). The RC circuit may be
adjusted so that AVIN and PVIN are above UVLO before ENABLE is high. The startup time will be delayed by
the extra time it takes for the capacitor voltage to reach the ENABLE threshold.
Figure 5. ENABLE Delay Circuit
AVIN
ENABLE
1k
1µF
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Thermal Shutdown
When excessive power is dissipated in the device, its junction temperature rises. Once the junction
temperature exceeds the thermal shutdown temperature 155 °C, the thermal shutdown circuit turns off the
converter, allowing the device to cool. When the junction temperature drops 15 °C, the device will be re-
enabled and go through a normal startup process.
Power OK
The EN5322QI provides an open drain output to indicate if the output voltage stays within 92% to 111% of
the set value. Within this range, the POK output is allowed to be pulled high. Outside this range, POK remains
low. However, during transitions such as power up, power down, and dynamic voltage scaling, the POK output
will not change state until the transition is complete for enhanced noise immunity.
The POK has 5 mA sink capability for events where it needs to feed a digital controller with standard CMOS
inputs. When POK is pulled high, the pin leakage current is as low as 500 nA maximum over temperature. This
allows a large pull up resistor such as 100 kΩ to be used for minimal current consumption in shutdown mode.
The POK output can also be conveniently used as an ENABLE input of the next stage for power sequencing of
multiple converters.
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APPLICATION INFORMATION
Output Voltage Setting
To provide the highest degree of flexibility in choosing output voltage, the EN5322QI uses a 3 pin VID (Voltage
ID) output voltage select arrangement. This allows the designer to choose one of seven preset voltages, or to
use an external voltage divider. Figure 6 shows a typical application circuit with VID codes. Internally, the
output of the VID multiplexer sets the value for the voltage reference DAC, which in turn is connected to the
non-inverting input of the error amplifier. This allows the use of a single feedback divider with constant loop
gain and optimum compensation, independent of the output voltage selected.
EN5322
10 uF 47 uF
VO UTPV IN
AG ND
V
IN
VS ENSE
PO K
VS0
VS1
VS2
ENAB LE
AV IN
PG ND
C
IN
C
OUT
1 uF
V
OUT
PG ND
R
POK
100k
* Leave open if the POK function is not used.
*
R
POK
POK
OFF
ON
Figure 6. Typical Application Circuit with VID Codes
NOTE: Enable can be separated from PVIN if the application requires it
Table 1 shows the various VS0-VS2 pin logic states and the associated output voltage levels. A logic “1”
indicates a connection to VIN or to a “high” logic voltage level. A logic “0” indicates a connection to ground or
to a “low” logic voltage level. These pins can be either hardwired to VIN or GND or alternatively can be driven
by standard logic levels. Logic low is defined as VLOW ≤ 0.4V. Logic high is defined as VHIGH ≥ 1.4V. Any level
between these two values isindeterminate. These pins must not be left floating.
Table 1. VID voltage select settings
VS2 VS1 VS0 VOUT
0 0 0 3.3V
0 0 1 2.5V
0 1 0 1.8V
0 1 1 1.5V
1 0 0 1.25V
1 0 1 1.2V
1 1 0 0.8V
1 1 1 User
Selectable
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External Voltage Divider
As described above, the external voltage divider option is chosen by connecting the VS0, VS1, and VS2 pins
to VIN or logic “high”. The EN5322QI uses a separate feedback pin, VFB, when using the external divider.
VSENSE must be connected to VOUT as indicated in Figure 7.
EN5322
10 uF 47 uF
VO UTPV IN
AG ND
VIN VS ENSE
PO K
VS0
VS1
VS2
ENAB LE
AV IN PG ND
CIN COUT
1 uF
VOUT
PG ND
RPOK 100k
* Leave open if the POK function is not used.
*
RPOK
Ra
340k
Rb
VFB
POK
OFF
ON
Figure 7. Typical Application Circuit with External Resistor Divider.
NOTE: Enable can be separated from PVIN if the application requires it
If the external voltage divider option is chosen, use 340 kΩ, 1% or better for the upper resistor Ra. Then the
value of the bottom resistor Rb in kΩ is given as:
Ω
−
=k
V
Rb
OUT 6.
0
204
Where VOUT is the output voltage. Rb should also be a 1% or better resistor.
Input and Output Capacitor Selection
Low ESR MLC capacitors with X5R or X7R or equivalent dielectric should be used for input and output
capacitors. Y5V or equivalent dielectrics lose too much capacitance with frequency, DC bias, and temperature.
Therefore, they are not suitable for switch-mode DC-DC converter filtering, and must be avoided.
A 10 µF, 10 V, 0805 MLC capacitor is needed on PVIN for all applications. A 1 µF, 10 V, 0402 MLC capacitor on
AVIN is needed for high frequency bypass to ensure clean chip supply for optimal performance.
A 47 µF, 6.3 V, 1206 MLC capacitor is recommended on the output for most applications. The output ripple
can be reduced by approximately 50% by using 2 x 22 µF, 6.3V, 0805 MLC capacitors rather than 1 x 47 µF.
As described in the Soft Start section, there is a limitation on the maximum bulk capacitance that can be placed
on the output of this device. Please refer to that section for more details.
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Table 2. Recommended input and output capacitors
Description MFG P/N
CIN
10µF, 10V, 10%,
X5R, 0805
Murata GRM21BR71A106KE51L
Taiyo Yuden LMK212BJ106KG
Panasonic ECJ-2FB1A106K
COUT
47µF, 6.3V,
20%, X5R, 1206
Taiyo Yuden JMK316BJ476ML
Murata GRM31CR60J476ME19L
Kemet C1206C476M9PACTU
POK Pull Up Resistor Selection
POK can be pulled up through a resistor to any voltage source as high as VIN. The simplest way is to connect
POK to the power input of the converter through a resistor. A 100 kΩ pull up resistor is typically recommended
for most applications for minimal current drain from the voltage source and good noise immunity. POK can
sink up to 5mA.
Power-Up/Down Sequencing
During power-up, ENABLE should not be asserted before PVIN, and PVIN should not be asserted before
AVIN. The PVIN should never be powered when AVIN is off. During power down, the AVIN should not be
powered down before the PVIN. It is recommended to follow the power-up and power-down sequencing to
ensure that the EN5322QI is always sufficiently powered before the device begins operation.
Pre-Bias Start-up
The EN5322QI does not support startup into a pre-biased condition. Be sure the output capacitors are not
charged or the output of the EN5322QI is not pre-biased when the EN5322QI is first enabled.
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LAYOUT RECOMMENDATIONS
Recommendation 1: Input and output filter capacitors should be placed on the same side of the PCB, and as
close to the EN5322QI package as possible. They should be connected to the device with very short and wide
traces. Do not use thermal reliefs or spokes when connecting the capacitor pads to the respective nodes. The
+V and GND traces between the capacitors and the EN5322QI should be as close to each other as possible so
that the gap between the two nodes is minimized, even under the capacitors.
Recommendation 2: The system ground plane should be the first layer immediately below the surface layer.
This ground plane should be continuous and un-interrupted below the converter and the input/output
capacitors.
Figure 8. Optimized Layout Recommendations
Recommendation 3: The thermal pad underneath the component must be connected to the system ground
plane through as many vias as possible. The drill diameter of the vias should be 0.33mm, and the vias must
have at least 1 oz. copper plating on the inside wall, making the finished hole size around 0.20-0.26mm. Do
not use thermal reliefs or spokes to connect the vias to the ground plane. This connection provides the path
for heat dissipation from the converter.
Recommendation 4: Multiple small vias (the same size as the thermal vias discussed in recommendation 3)
should be used to connect ground terminal of the input capacitor and output capacitors to the system ground
plane. It is preferred to put these vias along the edge of the GND copper closest to the +V copper. These vias
connect the input/output filter capacitors to the GND plane, and help reduce parasitic inductances in the input
and output current loops.
Recommendation 5: AVIN is the power supply for the small-signal control circuits. It should be connected to
the input voltage at a quiet point. In Figure 8 this connection is made at the input capacitor. Connect a 1µF
capacitor from the AVIN pin to AGND.
Recommendation 6: The layer 1 metal under the device must not be more than shown in Figure 7. See the
section regarding exposed metal on bottom of package. As with any switch-mode DC-DC converter, try not to
run sensitive signal or control lines underneath the converter package on other layers.
Recommendation 7: The VOUT sense point should be just after the last output filter capacitor. Keep the sense
trace short in order to avoid noise coupling into the node.
Recommendation 8: Keep RA, RB close to the VFB pin (See Figures 8). The VFB pin is a high-impedance,
sensitive node. Keep the trace to this pin as short as possible. Whenever possible, connect RB directly to the
AGND pin instead of going through the GND plane.
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Datasheet | Intel® Enpirion® Power Solutions: EN5322QI
Page 19
DESIGN CONSIDERATIONS FOR LEAD-FRAME BASED MODULES
Exposed Metal on Bottom of Package
QFN lead-frame based package technology utilizes exposed metal pads on the bottom of the package that
provide improved thermal dissipation and low package thermal resistance, smaller package footprint and
thickness, large lead size and pitch, and excellent lead co-planarity. As the EN5322QI package is a fully
integrated module consisting of multiple internal devices, the lead-frame provides circuit interconnection
and mechanical support of these devices resulting in multiple exposed metal pads on the package bottom.
Only the two large thermal pads and the perimeter leads are to be mechanically/electrically connected to the
PCB through a SMT soldering process. All other exposed metal is to remain free of any interconnection to
the PCB. Figure 8 shows the recommended PCB metal layout for the EN5322QI package. A GND pad with a
solder mask "bridge" to separate into two pads and 24 signal pads are to be used to match the metal on the
package. The PCB should be clear of any other metal, including traces, vias, etc., under the package to avoid
electrical shorting.
Figure 9. Recommended Footprint for PCB
03454 March,18, 2019 Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5322QI
Page 20
PACKAGE DIMENSIONS
Figure 10. Package mechanical dimensions.
03454 March,18, 2019 Rev I
Datasheet | Intel® Enpirion® Power Solutions: EN5322QI
WHERE TO GET MORE INFORMATION
For more information about Intel® and Enpirion® PowerSoCs, visit:
www.Intel.com/enpirion
© 2017 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, ARRIA, CYCLONE, ENPIRION, MAX, MEGACORE, NIOS, QUARTUS, and STRATIX words and logos are trademarks of Intel
Corporation or its subsidiaries in the U.S. and/or other countries. Other marks and brands may be claimed as the property of others. Intel reserves the right to make changes to any products and
services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any information, product, or service described herein except as expressly agreed to
in writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services.
* Other marks and brands may be claimed as the property of others.
Page 21
REVISION HISTORY
Rev Date Change(s)
G Feb. 2014
• ENABLE functional description has been rewritten and updated to include
delay circuit.
H Feb. 2014
• Updated Typical Application Circuits to show that ENABLE is best toggled
after PVIN is stable.
• Updated Power Up/Down Sequencing description.
I March. 2019 • Changed datasheet into Intel format.
03454 March,18, 2019 Rev I
