ADE-203-223 (A) (Z) HM5283206 Series 131,072-word x 32-bit x 2-bank Synchronous Graphic RAM Preliminary Rev. 0.1 Nov. 11, 1994 All inputs and outputs signals refers to the rising edge of the clock input. The HM5283206 provides 2 banks to realize better performance. 8 column block write function and write per bit function are provided for graphic applications. Ordering Information Type No. Frequency Package Features HM5283206FP-10 HM5283206FP-12 HM5283206FP-15 100 MHz 83 MHz 66 MHz 100-pin plastic QFP (FP-100) HM5283206TT-10 HM5283206TT-12 HM5283206TT-15 100 MHz 83 MHz 66 MHz 400-mil 80-pin plasticTSOP II (Under study) * 3.3V Power supply * Clock frequency: -- 100 MHz/83 MHz/66 MHz * LVTTL interface * 2 Banks can operates simultaneously and independently * Burst read/write operation and burst read/ single write operation capability * Programmable burst length: -- 1/2/4/8/full page * Programmable burst sequence: -- Sequential/interleave * Full page burst length capability: -- Sequential burst -- Burst stop capability * Programmable CAS latency: -- 1/2/3 * Byte control by DQM * 8 column block write function with column address mask * Write per bit function (old mask) * 2 variations of refresh -- Auto refresh Note: -- Self refresh (1024 refresh cycles: 16 ms) This document contains information on a new product. Specifications and information contained herein are subject to change without notice. HM5283206 Series Pin Arrangement 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQ28 VDDQ DQ27 DQ26 VSSQ DQ25 DQ24 VDDQ DQ15 DQ14 VSSQ DQ13 DQ12 VDDQ VSS VDD DQ11 DQ10 VSSQ DQ9 DQ8 VDDQ NC(Vref) DQM3 DQM1 CLK CKE DSF NC A8 HM5283206FP Series 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 A7 A6 A5 A4 VSS NC NC NC NC NC NC NC NC NC NC VDD A3 A2 A1 A0 DQ3 VDDQ DQ4 DQ5 VSSQ DQ6 DQ7 VDDQ DQ16 DQ17 VSSQ DQ18 DQ19 VDDQ VDD VSS DQ20 DQ21 VSSQ DQ22 DQ23 VDDQ DQM0 DQM2 WE CAS RAS CS A9 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 DQ29 VSSQ DQ30 DQ31 VSS NC NC NC NC NC NC NC NC NC NC VDD DQ0 DQ1 VSSQ DQ2 (Top view) Pin Description Pin name Function Pin name Function A0 - A9 Address input -- Row address A0 - A8 -- Column address A0 - A7 CLK Clock input CKE Clock enable VDD Power for internal circuit (3.3 V) VSS Ground for internal circuit VDDQ Power for DQ pin (3.3 V) VSSQ Ground for DQ pin DSF Special function input flag NC No connection A9 Bank select address BS DQ0 - DQ31 Data-input/output RAS Row address asserted bank enable CS Chip select CAS Column address asserted WE Write enable DQM0 - DQM3 Byte input/output mask 2 HM5283206 Series Pin Functions * CLK (input pin): CLK is the master clock input pin. The other input signals are referred at CLK rising edge. * CS (input pin): When CS is Low, the command input cycle becomes valid. When CS is High, all inputs are ignored. However, internal operations (bank active, burst operations, etc.) are held. * RAS, CAS, and WE (input pins): These pins define operation commands (read, write, etc.) depending on the combination of their voltage levels. For details, refer to the command operation section. * DSF (input pin): DSF is a part of inputs of graphic commands of the HM5283206. If DSF is LOW, the HM5283206 operates as standard synchronous DRAM. * A0 to A8 (input pins): Row address (AX0 to AX8) is determined by A0 to A8 pins at the CLK rising edge when a bank active command is input. Column address (AY0 to AY7) is determined by levels on A0 to A7 pins at the CLK rising edge when a read or write command is input. A8 determins precharge mode. When A8 is low, only the bank selected by A9(BS) is precharged by a precharge command. When A8 is high, both banks are precharged by a precharge command. * CKE (input pin): By referring low level on CKE pin, HM5283206 determines to go into clock suspend modes or power down modes. In self refresh mode, low level on this pin is also referred to turn on refresh process. * DQM0, DQM1, DQM2 and DQM3 (input pins): DQM0 applies to DQ0 to DQ7. DQM1 applies to DQ8 to DQ15. DQM2 applies to DQ16 to DQ23. DQM3 applies to DQ24 to DQ31. In read mode, referring high level on DQM pins, HM5283206 floats related DQ pins. In write mode, referring high level on DQM pins, HM5283206 ignores input data through related DQ pins. * DQ0 to DQ31 (input/output): These are the data line for the HM5283206. * VDD and VDDQ (power supply pins): 3.3 V is applied. (VDD is for the internal circuit and VDDQ is power supply pin for DQ output buffer.) * VSS and VSSQ (power supply pins): Ground is connected. (VSS is for the internal circuit and VSSQ is for DQ output buffer.) * A9 (input pin): A9 is the bank select signal (BS). The memory array of the HM5283206 is divided into the bank 0 and the bank 1, both contain 512 row x 256 column x 32 bits. If A9 is Low, the bank 0 is selected, and if A9 is High, the bank 1 is selected. 3 HM5283206 Series Block Diagram A0 - A9 A0 - A7 Column address counter A0 - A9 Column address buffer Column decoder Memory array Bank 0 Output buffer Memory array Bank 1 512 row X 256 column X 32 bit Control logic & timing generator Mask register 512 row X 256 column X 32 bit Sense amplifier & I/O bus Row decoder Color register Sense amplifier & I/O bus Column decoder Row decoder Input buffer Refresh counter Row address buffer 4 DSF DQM0 DQM1 DQM2 WE DQM3 CAS RAS CS CKE CLK DQ0 - DQ31 HM5283206 Series Simplified State Diagram SELF REFRESH SR ENTRY SR EXIT MRS MODE REGISTER SET REFRESH IDLE *1 AUTO REFRESH CKE SMRS CKE_ ACTIVM IDLE POWER DOWN ACTIV SPECIAL MODE REGISTER SET Active Power Down CKE_ SMRS ROW ACTIVE BST WRITE Write CKE_ WRITE/ BWRITE SUSPEND CKE WRITE/ BWRITE WRITE WITH AP WRITE/ BWRITEA SUSPEND CKE_ BST READ WRITE/ BWRITE WITH AP READ READ WITH AP WRITE/ BWRITE READ WRITE/ WITH AP BWRITE WITH AP Read CKE_ READ CKE POWER ON CKE_ READA CKE READ SUSPEND READ WITH AP PRECHARGE WRITE/ BWRITEA CKE PRECHARGE POWER APPLIED CKE READA SUSPEND PRECHARGE PRECHARGE PRECHARGE Automatic transition after completion of command. Transition resulting from command input. Note: 1. After the auto-refresh operation, precharge operation is performed automatically and enter the IDLE state. 5 HM5283206 Series Commands Operation CLK Commands explanation VIH CKE CS RAS CAS WE Every operations of HM5283206 are executed by input commands. A command is input, at the rising edge of CLK, by setting the levels on CS, RAS, CAS, WE, A8 (auto precharge) and DSF pins, HIGH (VIH) or LOW (VIL). * Precharge command [PRE, PALL]: At the CLK rising edge, by setting CS, RAS, WE, DSF; LOW, CAS; HIGH DSF A8 A9 A0 to A7 High-Z DQ bank can be precharged to idle state. Precharge command A8 = LOW: the bank selected by A9 is precharged. A8 = HIGH: Both banks are precharged. CLK [State transition] power on->Idle Command tCMS Row active->Idle Note: The setup and hold condition should be obeyed when command, address or data is input. t CMH Address t AS t AH Data t DS t DH Set-up and hold condition of command, address and data input 6 HM5283206 Series * Mode register set command [MRS]: CLK If both banks have been precharged or are in idle state, at the CLK rising edge, by setting CS, RAS, CAS, WE, DSF; LOW VIH CKE CS RAS CAS an internal register (the mode register; MRS) are set if both banks are idle state. WE DSF [Data input through A0 to A9] A8, A9 The data through address pins, at the cycle when this command is input, are stored in the mode register. A8, A9 bits determine burst write or single write. A6 to A4 bits determine CAS latency. A3 bit determines burst type, sequential or interleave. A2 to A0 bits determine burst length. A7 bit should be set to low. See table below for details. A6 to A4 A3 A2 to A0 OP CODE CAS Latency Burst type Burst length A7 DQ High-Z Mode register set command [State transition] Idle->Idle Mode register configuration A9 A8 Operation CODE 0 0 Burst Read and Burst Write 0 1 R 1 0 Burst Read and Single Write 1 1 R A6 A5 A4 CAS Latency 0 0 0 R 0 0 1 1 0 1 0 2 0 1 1 3 1 X X R A3 Burst Type 0 Sequencial 1 Interleave 7 HM5283206 Series Mode register configuration (cont) Burst Length A2 A1 A0 BT = 0 BT = 1 0 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 R R 1 0 1 R R 1 1 0 R R 1 1 1 Full page R Note: R: Reserved * Bank and row active command [ACTV, ACTVM]: If a bank has been precharged or is in idle state. At the CLK rising edge, by setting CKE CS, RAS; LOW, RAS CAS, WE: HIGH CAS a row of the bank is activated. The bank is selected by setting the level on A9 pin HIGH (bank 1) or LOW (bank 0) at this timing. A0 to A8 determine the row address. DSF [Option] DSF = LOW; write per bit function disable (ACTV) DSF = HIGH; write per bit function enable (ACTVM) [State transition] Idle->Row active 8 CLK VIH CS WE A9 A0 to A8 DQ High-Z Bank and row active command HM5283206 Series * Column address and read command: CLK For a row of one of two banks activated by ACTV or ACTVM, at the CLK rising edge, by setting CS, CAS, DSF; LOW, RAS, WE; HIGH, data is output through DQ pins. A9 determines the bank address. A0 to A7 determine the column address. CAS latency stored in MRS determines the timing when data are driven. In case, CL (CAS latency) = 1, 1 clock cycle after the command input, data start to be output. CKE VIH CS RAS CAS WE DSF A8 A9 A0 to A7 DQ (out) High-Z Column address and read command CL = 1, BL = 1. In case CL = 2, 2 clock cycle after the command input, data start to be output. In case CL = 3, 3 clock cycle after the command input, data start to be output. Burst Length (BL) stored in MRS determines data length of output . [Option] A8 = HIGH; auto precharge mode or execute precharge automatically after finishing data output. A8 = LOW; Read mode without auto precharge. [State transition] Row active->Row active Row active->Idle (auto precharge) 9 HM5283206 Series * Column address and write command: CLK For a row of one of two banks activated by ACTV or ACTVM, at the CLK rising edge, by setting CS, CAS, DSF, WE; LOW, RAS; HIGH, the data on DQ pins are input. A9 determines the bank address. A0 to A7 determine the column address. For write, data should start to be input at the same cycle of the command input. Burst length stored in MRS determines the expected data length to be input. If the bank, for which command is input, is activated by ACTVM, then I/O bit mask function or write per bit is available. [Option] A8 = HIGH; auto precharge mode or execute precharge automatically after finishing data input. A8 = LOW; write mode without auto precharge. [State transition] Row active->Row active Row active->Idle (auto precharge case) 10 CKE VIH CS RAS CAS WE DSF A8 A9 A0 to A7 DQ (in) High-Z Column address and write command BL = 2. HM5283206 Series * Burst stop command (BST): At the CLK rising edge, by setting CLK CS, WE, DSF: LOW, CKE RAS, CAS; HIGH, VIH CS RAS CAS If BL is set to 1, 2, 4, 8, to try to execute this command is illegal. DSF full page burst (BL = 256) read/write is interupted. WE A0 to A9 [State transition] Burst stop command Row active -> Row active * Auto refresh command (REF): CLK If both banks are in idle state, at the CLK rising edge, by setting CS CS, RAS, CAS, DSF; LOW, RAS WE; HIGH, CAS the HM5283206 starts auto-refresh (CBR type) operation. Refresh address is internaly generated. No precharge commands are required after autorefresh, since precharge is automatically performed for both banks. VIH CKE WE DSF A0 to A9 DQ High-Z Auto refresh command [State transition] Idle -> Idle 11 HM5283206 Series * Self refresh command (REF): CLK If both banks are in idle state, at the CLK rising edge, by setting CKE CS RAS WE; HIGH, CAS CS, RAS, CAS, DSF; LOW, and if CKE's falling edge is detected, the HM5283206 starts self-refresh operation. Selfrefresh operation is kept while CKE is LOW. [State transition] WE DSF A0 to A9 DQ High-Z Self-refresh command Idle -> Self refresh mode * No-operation command (NOP): CLK At the CLK rising edge, by setting CS, WE, DSF; LOW, RAS, CAS; HIGH, full page burst (BL = 256) read/write is interupted. If BL is set to 1, 2, 4, 8, to try to execute this command is illegal. [State transition] No transition VIH CKE CS RAS CAS WE DSF A0 to A9 DQ High-Z No operation command * Ignore command (DESL): At the CLK rising edge, by setting CS; LOW, any command input is ignored. 12 HM5283206 Series Graphic commands CLK * Special mode register set command (SMRS): CKE If both banks are in idle state or activated, at the CLK rising edge, by setting CS, RAS, CAS, WE; LOW, DSF; HIGH, an internal register (the special mode register; SMRS) are set. [Data input through A0 to A9] The data through address pins, at the cycle when this command is input, are stored in the special mode register. A0 to A4: reserved. should be LOW when SMRS is issued. VIH CS RAS CAS WE DSF A0 to A4 A5 Load mask A6 Load color A7 to A9 DQ High-Z Special mode register set command A5: determines whether loading mask data or not when SMRS is issued. A6: determines whether loading color data or not when SMRS is issued. A0 to A4: reserved. should be set LOW when SMRS is issued. 13 HM5283206 Series Special mode register configuration A5 A6 Function 0 X Disable 1 0 Enable X 0 Disable 0 1 Enable 1 1 ILLEGAL Note: Load Mask Load Color X: VIH or VIL Reserved bits A0 A1 A2 A3 A4 A7 A8 A9 0 0 0 0 0 0 0 0 [Data input through DQ pins] In case A5 bit of the mode register = HIGH, the data through DQ pins, at the cycle this command is issued, are stored in the MASK register (32 bits). If write per bit function is available*, and DQi (i = 1,..,31)bit of the MASK register = LOW, DQi data path to memory array is masked. In case A6 bit of the mode register HIGH, the data through DQ pins, at the cycle when this command is issued, are stored in the COLOR register (32 bits). This specific data is written to 8 columns in one clock cycle by block write command. Note: When bank active command is issued and DSF set to LOW, write per bit function is enabled. 14 HM5283206 Series Graphic function block diagram Write per bit and Block write MASK register DQ 0 0 DQ 1 1 DQ 30 30 DQ 31 31 COLOR register 0 1 30 31 Memory Array I1 I2 When block write command is issued, data I1 stored in the COLOR register is loaded O into column block (8 columns) of memory array. For burst and single write, the data I2 from DQ pins are loaded into a single column. I1 I2 O When write per bit function is available, if mask data I1 stored in the MASK register is LOW then the data path from I2 to O is cut. 15 HM5283206 Series * Column address and block write command: CLK For a row of one of two banks activated by ACTV or ACTVM, at the CLK rising edge, by setting CKE VIH CS RAS CS, CAS, WE; LOW, CAS RAS, DSF; HIGH, WE DSF a block write *2 is executed. A8 A9 determines the bank address. A9 A0 to A1 HIGH or LOW (ignored). A0 to A7 A3 to A7 determine the column block address. DQ High-Z [The data through DQ pins] Column address and block write command The data through DQ pins, at the cycle when the block write command input, are referred to stop the color data to be written onto the specific column. (Column mask) [Option] A8 = HIGH; Auto precharge mode or execute precharge automatically after finishing a block write execution. A8 = LOW; Write mode precharge. without [State transition] Row active->Row active Row active->Idle(auto precharge case) 16 auto HM5283206 Series Column block Column location Column block location A0 A1 A2 A3 A4 A5 A6 A7 0 0 0 a3 a4 a5 a6 a7 1 0 0 a3 a4 a5 a6 a7 0 1 0 a3 a4 a5 a6 a7 1 1 0 a3 a4 a5 a6 a7 0 0 1 a3 a4 a5 a6 a7 1 0 1 a3 a4 a5 a6 a7 0 1 1 a3 a4 a5 a6 a7 1 1 1 a3 a4 a5 a6 a7 Notes: 1. a3, a4, a5, a6, a7; VIH or VIL. 2. Block write allows a single 32 bit data, stored in the color register to be written on 8 columns location included in a column block in one write cycle. DQ input at the block write cycle and column mask location DQ pin NO. DQ group*1 Column location A0 A1 A2 Column mask no mask mask DQ0 00 0 0 0 High Low DQ1 00 1 0 0 High Low DQ2 00 0 1 0 High Low DQ3 00 1 1 0 High Low DQ4 00 0 0 1 High Low DQ5 00 1 0 1 High Low DQ6 00 0 1 1 High Low DQ7 00 1 1 1 High Low DQ8 01 0 0 0 High Low DQ9 01 1 0 0 High Low DQ10 01 0 1 0 High Low DQ11 01 1 1 0 High Low DQ12 01 0 0 1 High Low DQ13 01 1 0 1 High Low DQ14 01 0 1 1 High Low DQ15 01 1 1 1 High Low DQ16 10 0 0 0 High Low DQ17 10 1 0 0 High Low DQ18 10 0 1 0 High Low 17 HM5283206 Series DQ input at the block write cycle and column mask location (cont) DQ pin NO. DQ group*1 Column location A0 A1 A2 Column mask no mask mask DQ19 10 1 1 0 High Low DQ20 10 0 0 1 High Low DQ21 10 1 0 1 High Low DQ22 10 0 1 1 High Low DQ23 10 1 1 1 High Low DQ24 11 0 0 0 High Low DQ25 11 1 0 0 High Low DQ26 11 0 1 0 High Low DQ27 11 1 1 0 High Low DQ28 11 0 0 1 High Low DQ29 11 1 0 1 High Low DQ30 11 0 1 1 High Low DQ31 11 1 1 1 High Low Note: 18 DQ Group: 00; DQ0 to DQ7, 01; DQ8 to DQ15, 10; DQ16 to DQ23, 11; DQ24 to DQ31 HM5283206 Series Command Truth Table The HM5283206 recognizes the following commands specified by the CS, RAS, CAS, WE, DSF and address pins. All other combinations than those in the table bellow are illegal. Function Symbol CKE n-1 n CS RAS CAS WE DSF A9 A8 A7 -0 Ignore command DESL*2 H X H X X X X X X X No operation NOP H X L H H H X X X X Burst stop in full page BST*3 H X L H H L L X X X Column address and read command READ H X L H L H L V L V Read with auto precharge READ A H X L H L H L V H V Column address and write command WRIT H X L H L L L V L V Write with auto precharge WRIT A H X L H L L L V H V Row address strobe and bank act. ACTV H X L L H H L V V V Precharge select bank PRE H X L L H L L V L X Precharge all bank PALL H X L L H L L X H X Refresh (auto, self) REF, SELF H X L L L H L X X X Mode register set MRS H X L L L L L L L V Row address strobe and bank act and Masked write enable ACTVM H X L L H H H V V V Column address and block write command BWRIT H X L H L L H V L V Block write with auto precharge BWRITA H X L H L L H V H V Special mode register set SMRS H X L L L L H L L V Notes: 1. H: VIH. L: VIL. X: VIH or VIL. V: Valid address input. 2. When CS is high, the HM5283206 ignores command input. Internal operation is held. 3. Illegal if the burst length is 1, 2, 4 or 8. 19 HM5283206 Series DQM Truth Table Function Symbol CKE n-1 n DQM i Ith byte write enable/output enable ENB i H X L Ith byte write input/output disable MASK i H X H Note: H: VIH. L: VIL. X: VIH or VIL. i = 0, 1, 2, 3. DQM0 for DQ0 to DQ7, DQM1 for DQ8 to DQ15, DQM2 for DQ16 to DQ23, DQM3 for DQ24 to DQ31 CKE Truth Table Current state Function CKE n-1 n CS RAS CAS WE DSF Address Active Clock suspend mode entry H L X X X X X X Any Clock suspend L L X X X X X X Clock suspend Clock suspend mode exit L H X X X X X X Idle Auto-refresh command REF H H L L L H L X Idle Self-refresh entry H L L L L H L X Idle Power down entry H L L H H H L X Self refresh Self refresh exit L H L H H H L X L H H X X X L X L H L H H H L X L H H X X X X X Power down Note: 20 Power down exit H: VIH. L: VIL. X: VIH or VIL. SELF HM5283206 Series Function Truth Table The following tables show how each command works and what command can be executed in the state given. Current state CS RAS CAS WE DSF Address Command Operation Precharge H X X X X X DESL NOP->Idle after tRP L H H H X X NOP NOP->Idle after tRP L H H L L X BST ILLEGAL 2 L H L H L BA, CA, A8 READ/READ A ILLEGAL 2 L H L L L BA, CA, A8 WRIT/WRIT A ILLEGAL 2 L L H H L BA, RA ACTV ILLEGAL 2 L L H L L BA, A8 PRE, PALL NOP 3 L L L X X X L L H H H BA, RA ACTVM ILLEGAL 2 L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL 2 H X X X X X DESL NOP L H H H X X NOP NOP L H H L L X BST NOP L H L H L BA, CA, A8 READ/READ A ILLEGAL 2 L H L L L BA, CA, A8 WRIT/WRIT A ILLEGAL 2 L L H H L BA, RA ACTV Bank and row active L L H L L BA, A8 PRE, PALL NOP 3 L L L H L X REF, SELF Auto or self refresh 4 L L L L L MODE MRS Mode register set 4 L L H H H BA, RA ACTVM Bank and row active and write per bit enable L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL 2 L L L L H Special MODE SMRS 4 Idle Note ILLEGAL Special mode register set 21 HM5283206 Series Function Truth Table (cont) Current state CS RAS CAS WE DSF Address Command Operation Row active H X X X X X DESL NOP L H H H X X NOP NOP L H H L L X BST NOP L H L H L BA, CA, A8 READ/READ A Start read L H L L L BA, CA, A8 WRIT/WRIT A Start write L L H H L BA, RA ACTV ILLEGAL L L H L L BA, A8 PRE, PALL Precharge L L L X L L L H H H BA, RA ACTVM L H L L H BA, CA, A8 BWRIT/BWRIT A Start block write L L L L H Special MODE SMRS Special mode register set H X X X X X DESL NOP-> Burst end -> Row active L H H H X X NOP NOP-> Burst end -> Row active L H H L L X BST Burst stop-> Row active L H L H L BA, CA, A8 READ/READ A Term burst -> Start new read L H L L L BA, CA, A8 WRIT/WRIT A Term burst-> Start write L L H H L BA, RA ACTV ILLEGAL L L H L L BA, A8 PRE, PALL Term burst-> Precharge L L L X X X L L H H H BA, RA ACTVM L H L L H BA, CA, A8 BWRIT/BWRIT A Term burst -> Start block write Read 22 Note 2 ILLEGAL ILLEGAL 2 5 2 ILLEGAL ILLEGAL 2 HM5283206 Series Function Truth Table (cont) Current state CS RAS CAS WE DSF Address Command Operation H X X X X X DESL NOP-> Burst end -> Precharge L H H H X X NOP NOP-> Burst end -> Precharge L H H L L X BST ILLEGAL 2 L H L H L BA, CA, A8 READ/READ A ILLEGAL 2 L H L L L BA, CA, A8 WRIT/WRIT A ILLEGAL 2 L L H H L BA, RA ACTV ILLEGAL 2 L L H L L BA, A8 PRE, PALL ILLEGAL 2 L L L X X X L L H H H BA, RA ACTVM ILLEGAL 2 L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL 2 Write/Bwrite H X X X X X DESL NOP-> Burst end -> Write recovering L H H H X X NOP NOP-> Burst end -> Write recovering L H H L L X BST Burst stop-> Row active L H L H L BA, CA, A8 READ/READ A Term burst-> Start read L H L L L BA, CA, A8 WRIT/WRIT A Term burst -> Start new write L L H H L BA, RA ACTV ILLEGAL L L H L L BA, A8 PRE, PALL Term burst-> Precharge L L L X X X L L H H H BA, RA ACTVM L H L L H BA, CA, A8 BWRIT/BWRIT A Term burst -> Start block write Read with auto precharge Note ILLEGAL 2 ILLEGAL ILLEGAL 2 23 HM5283206 Series Function Truth Table (cont) Current state RAS CAS WE DSF Address Command Operation Write/Bwrite H with auto precharge X X X X X DESL NOP-> Burst end -> Write recovering with precharge L H H H X X NOP NOP-> Burst end -> Write recovering with precharge L H H L L X BST ILLEGAL 2 L H L H L BA, CA, A8 READ/READ A ILLEGAL 2 L H L L L BA, CA, A8 WRIT/WRIT A ILLEGAL 2 L L H H L BA, RA ACTV ILLEGAL 2 L L H L L BA, A8 PRE, PALL ILLEGAL 2 L L L X X X L L H H H BA, RA ACTVM ILLEGAL 2 L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL 2 Write/Bwrite H recovering X X X X X DESL NOP-> Row active after tWR/tBWR L H H H X X NOP NOP-> Row active after tWR/tBWR L H H L L X BST NOP-> Row active after tWR/tBWR L H L H L BA, CA, A8 READ/READ A Start read 2 L H L L L BA, CA, A8 WRIT/WRIT A Start new write 2 L L H L L BA, A8 PRE, PALL ILLEGAL 2 L L H H L BA, RA ACTV ILLEGAL 2 L L L X X X L L H H H BA, RA ACTVM ILLEGAL 2 L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL 2 24 CS Note ILLEGAL ILLEGAL HM5283206 Series Function Truth Table (cont) Current state RAS CAS WE DSF Address Command Operation Write/Bwrite H recovering with L precharge X X X X X DESL NOP-> Precharge after tWR/tBWR H H H X X NOP NOP-> Precharge after tWR/tBWR L H H L L X BST NOP-> Precharge after tWR/tBWR L H L H L BA, CA, A8 READ/READ A ILLEGAL 2 L H L L L BA, CA, A8 WRIT/WRIT A ILLEGAL 2 L L H L L BA, A8 PRE, PALL ILLEGAL 2 L L H H L BA, RA ACTV ILLEGAL 2 L L L X X X L L H H H BA, RA ACTVM ILLEGAL 2 L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL 2 H X X X X X DESL NOP-> Row active after tRCD L H H H X X NOP NOP-> Row active after tRCD L H H L L X BST NOP-> Row active after tRCD L H L H L BA, CA, A8 READ/READ A ILLEGAL 2 L H L L L BA, CA, A8 WRIT WRIT A ILLEGAL 2 L L H H L BA, RA ACTV ILLEGAL 2 L L H L L BA, A8 PRE, PALL ILLEGAL 2 L L L X X X L L H H H BA, RA ACTVM ILLEGAL 2 L H L L H BA, CA, A8 BWRIT/BWRIT A ILLEGAL 2 Row activating CS Note ILLEGAL ILLEGAL 25 HM5283206 Series Function Truth Table (cont) Current state CS RAS CAS WE DSF Address Command Operation H X X X X X DESL NOP-> Idle after tRC L H H H X X NOP NOP-> Idle after tRC L H H L L X BST NOP-> Idle after tRC L H L X X BA, CA, A8 ILLEGAL L L X X X X ILLEGAL H X X X X X DESL NOP-> Idle after tRSC L H H H X X NOP NOP-> Idle after tRSC L H H L L X BST ILLEGAL L H L X X BA, CA, A8 ILLEGAL L L X X X X ILLEGAL Special Mode H register set X X X X X DESL NOP-> Idle after tRSC or row active after tSBW L H H H X X NOP NOP-> Idle after tRSC or row active after tSBW L H H L L X BST ILLEGAL L H L X X BA, CA, A8 ILLEGAL L L X X X X ILLEGAL Refresh (auto precharge) Mode register set Note Notes: 1. H: VIH. L: VIL. X: VIH or VIL. 2. To execute this command for the current bank is illegal. However this command can be executed for another bank depends on the state of another bank. 3. NOP for the current bank or the bank in idle state. Precharge for the bank in other state. 4. Illegal, if both banks are not in idle state. 5. Illegal, if both banks are not in active state. 26 HM5283206 Series Operations of HM5283206 Series 1. * Power on sequence: 2. In order to get rid of data contention of I/O bus when power on, the following power on sequence recommended to be performed before any operation. 3. 4. 5. Apply power and start clock. Keep a NOP condition. Maintain stable power, stable clock, and NOP condition for 200 s. Execute precharge command (PALL: A8 = HIGH). Execute 8 or more auto-refresh commands (REF) t RP after the precharge command as dummy. An interval tRC is necessary between two consecutive auto-refresh commands. Execute a mode register set command (MRS) tRC after the last auto-refresh command input. Power on sequence CLK tRP Command Address NOP PALL REF REF MRS ACTV OP CODE A8='H' t RC t RC t RSA Repeat this auto-refresh cycle 8 times or more 27 HM5283206 Series Read/Write Operations Starting address of a burst data is defined by column address (AY0 to AY7) and bank select address (A9) loaded through A0 to A9 in the cycle when the read command is issued. * Bank active: A read/write operation begins with a bank active command (ACTV or ACTVM). The bank active command determines a bank (A9) and a row address (AX0 to AX8). For the bank and the row, a read/write command can be applied. CAS latency (CL) determines the delay of data output after read command input. When burst length is 1, 2, 4 or 8, DQ buffers automatically become High-Z at the next cycle after completion of burst read. An interval not less than tRCD, after an ACTV/ ACTVM command to a read/write command, is required. When burst length is full-page (256), data are repeatedly output until a burst stop command, a read/write command or a precharge command is input. * Read operation: Burst length (BL), CAS latency (CL) and burst type (BT) of the mode register are referred when read command is executed. Burst length (BL) determines the length of a sequential data by a single read command, which can be set to 1, 2, 4, 8 or 256 (full-page). Burst Length CLK t RCD Command ACT read Address row column BL=1 BL=2 DQout BL=4 BL=8 BL=Full page 0 0 1 0 1 2 3 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 256 0 1 BL: Burst Length CAS Latency = 2 BT: sequential 28 HM5283206 Series Read/Write Operations (cont) CAS Latency CLK t RCD Command Address DQ out ACT read row column 0 CL= 1 CL= 2 1 2 3 0 1 2 3 0 1 2 CL= 3 3 Burst Length = 4 CL = CAS Latency BT: sequential * Burst operation (on read or write): One burst data output/input by one read/write command are included in a column block determined by A1 to A7 in case BL (Burst Length) = 2, by A2 to A7 in case BL = 4 and by A3 to A7 in case BL = 8. Burst type (BT) determines the order how data of the column block are output/input. There are two burst types, sequential (wrap around) or interleave. The order of the burst data depends also on the start cloumn location of the burst data. See tables below for details. Column block BL = 2 Column location Column block location A0 A1 A2 A3 A4 A5 A6 A7 0 a1 a2 a3 a4 a5 a6 a7 1 a1 a2 a3 a4 a5 a6 a7 Note: a1, a2, a3, a4, a5, a6, a7; VIH or VIL. BL = 4 Column location Column block location A0 A1 A2 A3 A4 A5 A6 A7 0 0 a2 a3 a4 a5 a6 a7 1 0 a2 a3 a4 a5 a6 a7 0 1 a2 a3 a4 a5 a6 a7 1 1 a2 a3 a4 a5 a6 a7 Note: a2, a3, a4, a5, a6, a7; VIH or VIL. 29 HM5283206 Series Read/Write Operations (cont) Column block (cont) BL = 8 Column location Column block location A0 A1 A2 A3 A4 A5 A6 A7 0 0 0 a3 a4 a5 a6 a7 1 0 0 a3 a4 a5 a6 a7 0 1 0 a3 a4 a5 a6 a7 1 1 0 a3 a4 a5 a6 a7 0 0 1 a3 a4 a5 a6 a7 1 0 1 a3 a4 a5 a6 a7 0 1 1 a3 a4 a5 a6 a7 1 1 1 a3 a4 a5 a6 a7 Note: 30 a3, a4, a5, a6, a7; VIH or VIL. HM5283206 Series Read/Write Operations (cont) The Order of burst operation BL = 2 Start column location Order in decimal BL = 2 A0 Sequential 0 0 1 0 1 1 1 0 1 0 Interleave BL = 4 Start column location Order in decimal BL = 4 A0 A1 Sequential 0 0 0 1 2 3 0 1 2 3 1 0 1 2 3 0 1 0 3 2 0 1 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 Interleave BL = 8 Start column location Order in decimal BL = 8 A0 A1 A2 Sequential 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 1 0 0 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 1 1 0 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 0 0 1 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 0 1 1 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 Interleave 31 HM5283206 Series Read/Write Operations (cont) Starting address of a burst data is defined by column address (AY0 to AY7) and bank select address (A9) loaded through A0 to A9 in the cycle when the burst write command is issued. * Write operation: OPCODE (A9, A8) of the mode register is referred when a write command is executed as well as BL (Burst Length) and BT (Burst Type). CL (CAS Latency) is ignored and CL is fixed to 0 for write operation, that is, write data input starts on the same cycle when the write command is issued. 1. 2. Burst write: Before executing a burst write operation, OPCODE (A9, A8) should be set to (0, 0). Single write: Before executing a single write operation, OPCODE (A9, A8) should be set to (1, 0). In the single write operation, data are only written to the single column defined by the column address and the bank select address loaded at the write command set cycle regardless of the defined burst length. (The latency of data input is 0). Burst length (BL) determines the length of a sequential data by the burst write command, which can be set to 1, 2, 4, 8 or 256 (fullpage). Burst write CLK t RCD Command ACT write Address row column 0 BL=1 BL=2 DQ in BL=4 BL=8 BL=Full page 0 1 0 1 2 3 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 256 0 1 BL:Burst Length CAS Latency = 1, 2, 3 Single write CLK t RCD Command ACT write Address row column DQ in 0 BL: Burst Length = 1, 2, 4, 8, full page 32 HM5283206 Series Read/Write Operation (cont) 2. Use ACTVM command to activate the bank for which write per bit operation is performed. An interval not less than t RCD , after an ACTVM command to a write or a block write command, is necessary. 3. Execute a write or a block write command. In this write operation, DQ paths defined by mask register are masked to preserve the previous data. (See the example below) * Write per bit: To use write per bit function, 1. Set mask data in advance, which define DQ paths to be masked, to the MASK register by SMRS command. An interval not less than tRSC after a SMRS command to an ACTVM command is necessary. Special mode register set (load mask) in idle state and write per bit CLK t RCD SMRS ACTM write Address A5=1 A6=0 row column DQ in mask data Command 0 1 BL: Burst Length = 2 tRSC Special mode register set (load mask) in active state and write per bit CLK Command SMRS write Address A5=1 A6=0 col DQ in mask data 0 tRSC 1 BL: Burst Length = 2 33 HM5283206 Series Read/Write Operation (cont) Write per bit example MASK data stored in the MASK register DQ input data Data to be written DQ 0 A 0 DQ 1 B 1 B DQ 2 C 1 C DQ 3 D 0 DQ 28 E 1 DQ 29 DQ 30 DQ 31 F G H 0 1 0 * Block write: Before executing a block write command, a color data (32 bit) should be set in advance, which is allowed to be written in 8 columns at one write cycle, to the color register by SMRS command. E data through this bit will not be written. G If a block write command is applied to the bank which is activated by ACTVM command, write per bit function is also available. DQ inputs at the cycle, when a block write command is executed, are reffered to mask the specific columns. See the example below. An interval not less than tRSC after a SMRS command to an ACTVM command is necessary. If a SMRS command is executed in active state to set the color register, an interval not less than tSBW is required before executing a block write command after the SMRS command. Special mode register set (load mask) in idle state and block write CLK t RCD Command SMRS ACTM Bwrite Address A5=0 A6=1 row column DQ in Color data Column MASK t RSC 34 BL: Burst Length = 2 HM5283206 Series Read/Write Operation (cont) Block write example with write per bit Data to be written (Column block) Color data MASK data 0 1 A B 0 1 A B A B A B 7 D 0 D D D 24 E 1 E E E 30 G 1 G G G 31 H 0 H H H 0 1 7 k as lu DQ input DQ 0 1 DQ 1 0 DQ 7 1 DQ 24 1 DQ 25 1 DQ 31 0 m mn Co Column location data through this bit will not be written. k as m mn lu Co * Read with auto precharge: In this operation, since precharge is automatically performed after completing a read operation, so no precharge commands are necessary after each read operation. The command next to this command must be a bank active (ACTV, ACTVM) command. In addition, an interval defined by lAPR is required prior to the next command. CAS latency Precharge start cycle 3 2 cycle before the last data out 2 1 cycle before the last data out 1 0 cycle before the last data out 35 HM5283206 Series Read/Write Operations (cont) CLK t RCD Command CL=1 ACT read ACT IAPR DQ out Command CL=2 0 ACT 1 ACT IAPR 0 ACT 3 read DQ out Command CL=3 2 1 2 3 read ACT IAPR 0 DQ out 1 2 3 Internal precharge starts here * Write with auto-precharge: The command next to this command must be a bank active command (ACTV, ACTVM). In addition, an interval of l APBW is required between the last valid data and the following command. In this operation, since precharge is automatically performed after completion of a burst write or a single write operation, so no precharge commands are necessary after the write operation. Burst write (Burst Length = 4) CLK Command ACT write ACT Address row column row DQ in 0 1 2 3 IAPW 36 HM5283206 Series Read/Write Operations (cont) Single write CLK Command ACT write ACT Address row column row DQ in 0 I APW * Block write with auto-precharge: In this operation, since precharge is automatically performed after completion of a block write operation, so no need to execute precharge command. The following command must be a bank active command (ACTV, ACTVM). In addition, an interval of lAPBW is required between the last valid data input and the following command. CLK Command ACT Bwrite ACT Address row column row IAPBW 37 HM5283206 Series Full page burst stop * Burst stop command during burst read: Burst stop command is used to stop data output during a full-page burst read. This command sets the output buffer to High-Z and stops the full-page burst read. The timing, from command input to the last data, depends on CAS latency. BST command is legitimate only in case full page burst mode, and is illegal in case burst length 1, 2, 4 or 8. CAS latency BST to valid data BST to high Impedance 1 0 1 2 1 2 3 2 3 CAS Latency = 1, Burst Length = full page CLK Command BST DQ out IBSH = 1 IBSR = 0 CAS Latency = 2, Burst Length = full page CLK Command BST DQ out IBSH = 2 IBSR = 1 38 HM5283206 Series Full-page Burst Stop (cont) CAS Latency = 3, Burst Length = full page CLK BST Command DQ out IBSH = 3 IBSR = 2 * Burst stop command at burst write: For full page burst write cycle, when a burst stop command is issued, the write data at that cycle and the following write data input are ignored. The BST command is legitimate only in case full page burst mode, and is illegal for burst length 1, 2, 4 or 8. Burst length = full page CLK Command DQ input Burst stop Precharge in in t WR 39 HM5283206 Series DQM control * Writing: The DQM i (i=0, 1, 2, 3) controls the ith byte of DQ data. DQM control operation for read and for write are different in terms of latency. Input data can be controlled by DQMi. While DQMi is LOW, data is driven into the HM5283206. By setting DQMi to LOW, corresponding ith byte of DQ input data are kept from being written to the HM5283206 and the previous data are protected. The latency of DQM control operation is 0. * Reading: When data are read, output buffer can be controlled by DQMi. By setting DQMi to LOW, the corresponding DQ output buffers become active. By setting DQMi to HIGH, the corresponding DQ output buffers are made floated so that the ith byte of data are not driven out. The latency of DQM operation for read operation is 2. Reading CLK DQM DQout 0 1 3 IDOD= 2 Latency Writing CLK DQM DQin 0 1 3 I DID = 0 Latency 40 HM5283206 Series Refresh Others * Auto-refresh: * Power down mode: All the banks must be precharged before executing an auto-refresh command. Auto refresh command increments the internal counter every time when it is executed. This command also determines the row to be refreshed. Therefore external address specification is not necessary. Refresh cycle is 1024 cycles/16ms. (1024 cycles are required to refresh all the row addresses.) All output buffers become High-Z after auto-refresh start. No prechrage commands are necessary after this operation. * Self-refresh: When issuing a self refresh command, by changing the level on CKE pin from HIGH to LOW simultaneously, a self refresh operation starts and is kept while CKE is LOW. During the self-refresh operation, all data schedule to be refreshed internally. This operation managed by an internal refresh timer. After exiting from the self refresh, since the last row refreshed cannot be determined, auto-refresh commands should immediately be performed for all addresses. Change the level on the CKE pin from LOW to HIGH to exit from Self refresh mode. Power down mode is a state in which all input buffers except the CKE input buffer are made inactive and clock signal is masked to cut power dissipation. To enter into power down mode, CKE should be set to low. Power down mode is kept as long as CKE is low. Change the level on the CKE pin from LOW to HIGH to exit from Self refresh mode. Note that during a burst read or a burst write, only clock signal is masked. To exit from power down or clock mask state, CKE should be set to high. * Clock suspend: The HM5283206 enters into clock suspend mode from active mode by setting CKE to low. There are several types of clock suspend mode depends on the state when CKE level is changed from HIGH to LOW. -- ACTIVE clock suspend: If CKE-transition (1 to 0) happens during a bank active state, the bank active status is kept. Any input signals are ignored during this mode. -- READ and READ A suspend: If CKE transition (1 to 0) happens during a read operation, the read operation is kept or DQ output data is driven out until completion. Any input signals are ignored during this mode. -- WRITE (BLOCK WRITE) and WRITE A (BLOCK WRITE A) suspend: If CKEtransition (1 to 0) happens during a write operation, though any input signals include DQ input data ignored, the write operation is kept until completion. Any input signals are ignored during this mode. Change the level on the CKE pin from LOW to HIGH to exit from Clock suspend mode. 41 HM5283206 Series Command intervals Note that the latest read command has the priority to the preceding read command, that is, any read command can interrupt the preceding burst read operation to get valid data aimed by this interruption. * Read command to read command interval: 1. Operation for a column in the same row: Read command can be issued every cycle. CLK tRCD Command ACT Address row read read A B A9(BS) A0 DQ out Bank 0 Active 2. 42 B0 B1 Column A Column B Column A Column B read read Dout Operation for a column in other row of the same bank: It is necessary to execute a precharge command and a bank-active command before executing the new read command. Dout 3. B2 B3 CAS Latency = 3 Burst Length = 4 Bank 0 Operation for another bank: For another bank in active state, the new read command can be executed in the next cycle after the preceding read command is issued. If another bank is in idle state, a bank active command should be executed before executing the new read command. HM5283206 Series Command intervals (cont) CLK tRRD Command Address ACT 0 ACT read read 1 A B A9(BS) A0 DQ out B0 B1 B2 B3 CAS Latency = 3 Burst Length = 4 Bank 0 Bank1 Column A Column B Bank0 Bank1 Active Active read read Dout Dout * Write command to write command interval: 1. Operation for a column in the same row : Write command can be issued every cycle. Note that the latest write command has the priority to the preceding write command, that is, any write command can interrupt the preceding burst write operation to get valid data CLK tRCD Command ACT Address row write write A B A0 B0 A9(BS) DQ in Bank 0 Active B1 Column A Column B write B2 B3 Burst Write Mode Burst Length = 4 Bank 0 write 43 HM5283206 Series Command intervals (cont) 2. 3. Operation for a column in other row of the same bank: It is necessary to execute a precharge command and a bank active command before executing the following write command. Operation for another bank: For another bank in active state, the following burst write command can be executed in the next cycle after the preceding write command is issued. If another bank is in the idle state, bank active command should be executed. CLK tRRD Command Address ACT 0 ACT write write 1 A B A0 B0 A9(BS) DQ in B1 B2 B3 Burst Write Mode Burst Length = 4 Bank 0 Bank1 Bank Bank 1 Active Active 0write write * Block Write command to write or block write command interval: 1. Operation for a column in the same row: It is necessary to take no less than tBWC internal between a block write and another block write or the following write. If tCK is less than tBWC, NOP command should be issued for the cycle between a block write command and the following write or another block write command. CLK t BWC t RCD Command ACT Bwrite Address row A Bank 0 Active 44 Bwrite /Write B Column A Column B Block write Block write /Write HM5283206 Series Command intervals (cont) 2. 3. Operation for a column in other row of the same bank: It is necessary to execute a precharge command and a bank active command before the following write or another block write operation. Operation for another bank: To execute the following write command or another block write command for another bank in active state, tBWC interval to the next command is necessary. If another bank is in the idle state, bank active command should be executed. If tCK is less than tBWC, NOP command should be issued for the cycle between block write command and the following write or another block write command. CLK t RRD Command Address t BWC ACT ACT Bwrite 0 1 A Bwrite /Write B A9(BS) Bank 0 Active Bank1 Column A Column B Active Block write Block write /Write * Read command to write or block write command interval: driven in, DQM must be used depending on CAS latency as the timing shown below. 1. Note that the latest write or block write command has the priority to the preceding read command, that is, any write or block write command can interrupt the preceding burst read operation to get valid data. Operation for a column in the same row: The write or the block write command following the preceding read command can be performed after an interval of no less than 1 cycle. To set DQ output High-Z when data are CLK Command read write CL= 1 DQM CL= 2 CL= 3 DQ in DQ out 0 1 2 3 High-Z 45 HM5283206 Series Command intervals (cont) * Write command to read command interval: 2. Operation for a column in other row of the same bank: It is necessary to execute a precharge command and a bank active command before executing the next write or another block write command. 1. 3. Operation for another bank: For another bank in active state, the following write or block write command can be executed from the next cycle after the preceding write command is issued. If another bank is in idle state, bank active command should be executed, prior to execute the following write or block write command. Operation for a column in the same row: The read command following the preceding write command can be performed after an interval of no less than 1cycle. Note that the latest read command has the priority to the preceding writing command, that is, any read command can interrupt the preceding write operation to get valid data. WRITE to READ Command Interval (1) CLK Command write read DQM DQ in A0 DQ out B0 Column A write B1 CAS Latency Column B Column B read 46 B2 Dout B3 Burst Write Mode CAS Latency = 1 Burst Length = 4 Bank 0 HM5283206 Series Command intervals (cont) WRITE to READ Command Interval (2) CLK Command write read DQM DQ in A0 A0 DQ out B0 Column A B1 B2 B3 Burst Write Mode CAS Latency = 1 Burst Length = 4 Bank 0 CAS Latency write Column B Column B read 2. 3. Dout Operation for a column in other row of the same bank: To execute the following read command, it is necessary to execute a precharge command and a bank active command. * Block Write command to read command interval: 1. Operation for another bank: For another bank in active state, the following read command can be executed from the next cycle after the preceding write command is issued. If another bank is in idle state, a bank active command should be executed prior to execute the following read command. Operation for a column in the same row : Within the same row, it is necessary to take no less than tBWC between a block write and the following read command. If tCK is less than tBWC, NOP command should be issued for the cycle between a block write command and the following read command. CLK Command DQM read Bwrite t BWC DQ out B0 Column A Block write B1 B2 CAS Latency B3 CAS Latency = 1 Burst Length = 4 Column B Column B read Dout 47 HM5283206 Series Command intervals (cont) * Read command to precharge command: 2. Operation for a column in other row of the same bank: It is necessary to execute a precharge command and a bank active command before the following write or another block write operation. 3. Operation for another bank: To execute a read command for another bank in active state, t BWC interval to the next command is necessary. If another bank is in idle state, bank active command should be executed. If tCK is less than tBWC, NOP command should be issued for the cycle between a block write command and the following read command. The minimum interval between read command and precharge command is one cycle. However, since the output buffer then becomes High-Z after the cycles defined by l HZP , there is a possibility that burst read data output will be interrupted, if the precharge command is input during burst read. To read all data by burst read, the cycles defined by lEP must be assured as an interval from the final data output to precharge command execution. READ to PRECHARGE Command Interval (same bank): Output all data. CAS Latency = 1, Burst Length = 4 CLK Command Pre. read DQout 0 1 2 CL = 1 3 I EP = 0 cycle CAS Latency = 2, Burst Length = 4 CLK Command read 0 DQout CL = 2 48 Pre. 1 2 3 I EP = -1cycle HM5283206 Series Command intervals (cont) CAS Latency = 3, Burst Length = 4 CLK Command read Pre. DQout 0 1 2 3 I EP = -2cycle CL = 3 READ to PRECHARGE Command Interval (same bank): Stop output data. CAS Latency = 1, Burst Length = 4 CLK Command read Pre. High-Z DQout 0 I@@ HZP = 1 CAS Latency = 2, Burst Length = 4 CLK Command read Pre. High-Z DQout 0 I@@ HZP = 2 CAS Latency = 3, Burst Length = 4 CLK Command read Pre. High-Z DQout 0 IHZP = 3 49 HM5283206 Series Command intervals (cont) * Write command to precharge command: The minimum interval between a write command and the following precharge command is 1 cycle. However, if the burst write operation is not finished, input must be masked by means of DQM for the cycle defined by t WR , for assurance. WRITE to Precharge Command Interval (same bank) Burst Length = 4 (To stop write operation) CLK Command write Pre. DQM DQin A0 A1 t WR Burst Length = 4 (To write all data) CLK Command write Pre. DQM DQin A0 A1 A2 A3 tWR 50 HM5283206 Series Command intervals (cont) * Block write command to precharge command interval: The minimum interval between block write command and the following precharge command is tBWR. Block write to precharge command Interval (same bank) CLK Command Pre. Bwrite t BWR * Register set to register set interval: The minimum interval between two successive register set commands (mode/special mode) is lRR. Mode register set to spacial mode register interval CLK Command MRS SMRS Address A0-A9 A5,A6 color /mask DQ in IRR 51 HM5283206 Series Command intervals (cont) * Special mode register set to block write/write interval: The minimum interval between a special mode register set and a block write/write is tSBW. Special mode register set to burst write interval CLK Command SMRS write Address A5,A6 column DQ in color /mask 0 1 tSBW burst length = 2 * Bank active command interval: 1. Operation for the same bank: The interval between two bank-active commands must be no less than tRC. 2. Operation for another bank: The interval between two bank-active commands must be no less than tRRD. Bank active to bank active for the same bank CLK Command ACT Address row ACT Pre row A9(BS) t RP t RAS t RC 52 HM5283206 Series Command intervals (cont) Bank active to bank active for another bank CLK Command ACT ACT Address row row A9(BS) t RRD 53 HM5283206 Series Absolute Maximum Ratings Parameter Symbol Value Unit Note Voltage on any pin relative to VSS VT -1.0 to +5.5 V 2 Supply voltage relative to VSS VDD -1.0 to +4.6 V Short circuit output current Iout 50 mA Power dissipation PT 1.0 W Operating temperature Topr 0 to +70 C Storage temperature Tstg -55 to +125 C Note: 1. VIH (max) = 5.75 V for pulse width 5 ns Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Symbol Min Max Unit Note Supply voltage VDD, VDDQ 3.0 3.6 V 1 VSS, VSSQ 0 0 V Input high voltage VIH 2.0 4.6 V 1, 2 Input low voltage VIL -0.3 0.8 V 1, 3 Notes: 1. All voltage referred to VSS 2. VIH (max) = 5.5 V for pulse width 5 ns 3. VIL (min) = -1.0 V for pulse width 5 ns 54 HM5283206 Series DC Characteristics (Ta = 0 to 70C, VDD, VDDQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V) HM5283206 -10 -12 -15 Parameter Symbol Min Max Min Max Min Max Unit Test conditions Notes Operating current ICC1 -- TBD -- TBD -- TBD mA Burst length=1 tRC = min 1 Standby current (Bank Disable) ICC2 -- TBD -- TBD -- TBD mA CKE=VIL, tCK = min -- TBD -- TBD -- TBD mA CKE=VIL CLK=VIL or VIH Fixed -- TBD -- TBD -- TBD mA CKE=VIH, NOP command tCK = min -- TBD -- TBD -- TBD mA CKE=VIL, tCK = min, DQ = High-Z -- TBD -- TBD -- TBD mA CKE=VIH, NOP command tCK = min, DQ = High-Z ICC4 -- -- -- TBD -- TBD -- TBD -- TBD -- TBD -- TBD -- TBD mA TBD mA TBD mA tCK = min Refresh current ICC5 -- TBD -- TBD -- TBD mA tRC = min Self refresh current ICC6 -- 2 2 2 mA VIH VDD - 0.2 VIL 0.2 V Input leakage current ILI -10 10 -10 10 -10 10 A 0 Vin VDD Output leakage current ILO -10 10 -10 10 -10 10 A 0 Vout VDD DQ = disable Output high voltage VOH 2.4 -- 2.4 -- 2.4 -- V IOH = -2 mA Output low voltage VOL -- 0.4 -- 0.4 -- 0.4 V IOL = 2 mA Active standby current (Bank active) Burst operating current Note: (CL = 1) (CL = 2) (CL = 3) ICC3 -- -- 1 1 1. ICC depends on output load condition when the device is selected. ICC (max) is specified on condition that all output pins are floated. Capacitance (Ta = 25C, VDD, VDDQ = 3.3 V 0.3 V) Parameter Symbol Typ Max Unit Notes Input capacitance (Address) CI1 -- 5 pF 1 Input capacitance (Signals) CI2 -- 5 pF 1 Output capacitance (DQ) CO -- 7 pF 1, 2 Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. DQM = VIH to disable Dout. 55 HM5283206 Series AC Characteristics (Ta = 0 to 70C, VDD, VDDQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V) HM5283206 -10 -12 -15 Parameter Symbol Min Max Min Max Min Max Unit Notes System clock cycle time (CL = 3) (CL = 2) (CL = 1) tCK 10 15 30 -- -- -- 12 18 36 -- -- -- 15 22.5 45 -- -- -- ns ns ns 1 CLK high pulse width tCH 3 -- 4 -- 5 -- ns 1 CLK low pulse width tCL 3 -- 4 -- 5 -- ns 1 tAC -- -- -- 8 13 28 -- -- -- 10 15 32 -- -- -- 12 17 36 ns ns ns 1, 2 1, 2 1, 2 Access time from CAS tCAC -- 28 -- 32 -- 36 ns Data-out hold time tOH 3 -- 3 -- 3 -- ns 1, 2 CLK to Data-out low impedance tLZ 0 -- 0 -- 0 -- ns 1, 2 CLK to Data-out high impedance tHZ 2 2 7 13 2 2 9 15 2 2 11 17 ns ns 1, 3 Access time from CLK (CL = 3) (CL = 2) (CL = 1) (CL = 2, 3) (CL = 1) Data-in setup time tDS 3 -- 3 -- 3 -- ns 1 Data in hold time tDH 1 -- 1 -- 1 -- ns 1 Address setup time tAS 3 -- 3 -- 3 -- ns 1 Address hold time tAH 1 -- 1 -- 1 -- ns 1 CKE setup time tCKS 3 -- 3 -- 3 -- ns 1 CKE hold time tCKH 1 -- 1 -- 1 -- ns 1 Command (CS, RAS, CAS, WE, DQM, DSF) setup time tCMS 3 -- 3 -- 3 -- ns 1 Command (CS, RAS, CAS, WE, DQM) hold time tCMH 1 -- 1 -- 1 -- ns 1 Ref/Active to Ref/Active command period tRC 90 -- 108 -- 135 -- ns 1 Active to Precharge command period tRAS 60 10000 72 10000 90 10000 ns 1 Active command to column command tRCD 30 -- 36 -- 45 -- ns 1 Precharge to active command period tRP 30 -- 36 -- 45 -- ns 1 The last data-in to Precharge lead time tWR 20 -- (1CLK + 10) 15 -- 15 -- 24 -- (1CLK + 12) 18 -- 18 -- 30 -- ns (1CLK + 15) 21 -- ns 21 -- ns 1 tBWR 30 -- (1CLK + 20) 30 -- 30 -- 36 -- (1CLK + 24) 34 -- 34 -- 45 -- ns (1CLK + 30) 42 -- ns 42 -- ns 1 (CL = 3) (CL = 2) (CL = 1) Block write to Precharge lead time (CL = 3) (CL = 2) (CL = 1) 56 HM5283206 Series AC Characteristics (Ta = 0 to 70C, VDD, VDDQ = 3.3 V 0.3 V, VSS, VSSQ = 0 V) (cont) HM5283206 -10 -12 -15 Parameter Symbol Min Max Min Max Min Max Unit Notes Active (a) to Active (b) command period tRRD 20 -- 24 -- 30 -- ns 1 Register set to active command tRSC 20 -- 24 -- 30 -- ns 1 Block write cycle time tBWC 20 -- 24 -- 30 -- ns 1 Special mode register set to write/Bwrite command tSBW 20 -- 24 -- 30 -- ns 1 Transition time (rise to fall) tT 1 5 1 5 1 5 ns Refresh period tREF -- 16 -- 16 -- 16 ms Notes: 1. AC measurement assumes tT = 1 ns. Reference level for timing of input signals is 1.4 V. Test load (A) is used with CL = 30 pF in general except fpr the measurement of access time (note2) and tHZ (note3). 2. Access time is measured at 1.4 V. Test load (B) is used with current source. 3. tHZ (max) defines the time at which the outputs achieves 200 mV. Test load (A) is used with CL = 5 pF and with current source. 4. If tT is longer than 1 ns, input timing referred level should be VIH (min)/VIL (max) and 1 ns should be subtraced parameter. LVTTL interface and Test circuit 2.8 V 80% input 20% V SS t T tT LVTTL interface +1.4 V I/O 500 50 +1.4 V CL Test Load (A) 30 pF Test Load (B) 57 HM5283206 Series Relationship Between Frequency and Minimum Latency HM5283206 Parameter CL tCK (ns) -10 -12 -15 Symbol 3 10 2 15 1 30 3 12 2 18 1 36 3 2 1 15.0 22.5 45 Last data in to active command (Auto precharge, same bank) lAPW 5 3 2 5 3 2 5 3 2 Block write to active command (Auto precharge, same bank) lAPBW 6 4 2 6 4 2 6 4 2 Precharge command to high impedance lHZP 3 2 1 3 2 1 3 2 1 Last data out to active command lAPR 1 1 1 1 1 1 1 1 1 Last data out to precharge lEP -2 -1 0 -2 -1 0 -2 -1 0 Column command to column command lCCD 1 1 1 1 1 1 1 1 1 Write command to data in latency lWCD 0 0 0 0 0 0 0 0 0 DQM to data in lDID 0 0 0 0 0 0 0 0 0 DQM to data out lDOD 2 2 2 2 2 2 2 2 2 CKE to CLK disable lCLE 1 1 1 1 1 1 1 1 1 Burst stop to output valid data hold lBSR 2 1 0 2 1 0 2 1 0 Burst stop to output high impedance lBSH 3 2 1 3 2 1 3 2 1 Burst stop to write data ignore lBSW 0 0 0 0 0 0 0 0 0 MRS to data in latency lMSD 0 0 0 0 0 0 0 0 0 SMRS to data in latency lSSD 0 0 0 0 0 0 0 0 0 Register set to register set lRR 2 2 1 2 2 1 2 2 1 58 Notes HM5283206 Series Timing Waveforms Read Cycle tCK t CH t CL CLK t RC VIH CKE t CMS t CMH t t RAS t RCD t CMS t CMH RP t CMS t CMH t CMS t CMH CS t CMS t CMH t CMS t CMH t CMS t CMH t CMS t t CMS t CMH t CMS t CMH RAS t CMS t CMH t CMS t CMH CAS t CMS t CMH t CMS t CMH t AS t AH t AS t AH t AS t AH t AS t AH t AS t AH t CMS t CMH t CMS t CMH WE t AS t AH A9 t AS t AH t AS t AH A8 t AS t AH t AS t AH t AS t AH Address t CMS t CMH DQM DQ(input) tCAC DQ(output) t AC t AC t AC t AC Bank 0 Active Bank 0 Read t LZ t OH t OH t OH Bank 0 Precharge t HZ Burst length = 4 Bank0 Access 59 HM5283206 Series Write Cycle t CK t CH tCL CLK t RC VIH CKE t RAS t RCD t CMS t CMH t RP t CMS t CMH t CMS t CMH t CMS t CMH t CMS t CMH t CMS t CMH t CMS t CMH t CMS t CMH CS t CMS t CMH t CMS t CMH RAS t CMS t CMH t CMS t CMH CAS t CMS t CMH t CMS t CMH t CMS t CMH t AS t AH t AS t AH t AS t AH t AS t AH t CMS t CMH WE t AS t AH t AS t AH A9 t AS t AH t AS t AH A8 t AS t AH t AS t AH t AS t AH Address t CMS t CMH DQM t DS t DH tDS t DH t DS t DH t DS t DH DQ(input) t WR DQ(output) Bank 0 Active 60 Bank 0 Write Bank 0 Precharge Burst length = 4 Bank 0 Access HM5283206 Series Mode Register Set Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK VIH CKE CS RAS CAS WE A9(BS) Address code valid C: b' C: b R: b DQM DQ(output) b+3 b b' b'+1 b'+2 b'+3 High-Z DQ(input) t RSC t RP Precharge If needed Mode register Set t RCD Output mask Bank 1 Active Bank 1 Read tRCD = 3 CAS latency = 3 Burst length = 4 Read Cycle/Write Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE VIH Read cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 CS RAS CAS WE A9(BS) Address DQM DQ (output) DQ (input) CKE R:a C:a R:b C:b a C:b' a+1 a+2 a+3 b C:b" b+1 b+2 b+3 b' b'+1 b" b"+1 b"+2 b"+3 High-Z Bank 0 Active Bank 0 Read Bank 1 Active Bank 1 Bank 0 Read Precharge Bank 1 Read Bank 1 Read Bank 1 Precharge Write cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = 4 VIH CS RAS CAS WE A9(BS) Address DQM R:a C:a R:b C:b C:b' C:b" High-Z DQ (output) DQ (input) a Bank 0 Active Bank 0 Write a+1 a+2 a+3 Bank 1 Active b Bank 1 Write b+1 b+2 b+3 b' Bank 0 Precharge Bank 1 Write b'+1 b" Bank 1 Write b"+1 b"+2 b"+3 Bank 1 Precharge 61 HM5283206 Series Read/Single Write Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE VIH CS RAS CAS WE A9(BS) R:a Address C:a R:b DQM DQ (input) DQ (output) a a Bank 0 Active CKE C:a' C:a Bank 0 Read Bank 1 Active C:a R:b a+1 a+2 a+3 a Bank 0 Bank 0 Write Read a+1 a+2 a+3 Bank 0 Precharge Bank 1 Precharge VIH CS RAS CAS WE A9(BS) Address DQM R:a DQ (input) DQ (output) a Bank 0 Active Bank 0 Read Bank 1 Active a+1 C:a C:b C:c a b c a+3 Bank 0 Write Bank 0 Bank 0 Write Write Bank 0 Precharge Read/Single write RAS-CAS delay = 3 CAS Latency = 3 Burst length = 4 62 HM5283206 Series Read/Burst Write Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE CS RAS CAS WE A9(BS) R:a Address DQM DQ (input) DQ (output) CKE C:a R:b C:a' a a Bank 0 Active Bank 0 Read Bank 1 Active C:a R:b a+1 a+2 a+3 a+1 a+2 a+3 Clock suspend Bank 0 Write Bank 0 Precharge Bank 1 Precharge VIH CS RAS CAS WE A9(BS) Address DQM R:a DQ (input) DQ (output) C:a a a Bank 0 Active Bank 0 Read Bank 1 Active a+1 a+1 a+2 a+3 a+3 Bank 0 Write Bank 0 Precharge Read/Single write RAS-CAS delay = 3 CAS Latency = 3 Burst length = 4 63 HM5283206 Series Full Page Read/Write Cycle 0 1 2 3 4 5 6 7 8 9 260 261 262 263 264 265 266 267 268 269 CLK CKE Read cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = full page VIH CS RAS CAS WE A9(BS) Address DQM DQ (output) DQ (input) CKE R:a C:a R:b a a+1 a+2 a+3 a-2 a-1 a a+1 a+2 a+3 a+4 a+5 High-Z Bank 0 Active Bank 0 Read Bank 1 Active Burst stop Bank 1 Precharge VIH Write cycle RAS-CAS delay = 3 CAS latency = 3 Burst length = full page CS RAS CAS WE A9(BS) Address DQM R:a R:b High-Z DQ (output) DQ (input) a Bank 0 Active 64 C:a Bank 0 Write a+1 a+2 Bank 1 Active a+3 a+4 a+5 a+6 a+1 a+2 a+3 a+4 a+5 Burst stop Bank 1 Precharge HM5283206 Series Auto Refresh Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a a+1 CLK CKE VIH CS RAS CAS WE A9(BS) Address R:a A8=1 C:a DQM DQ(input) High-Z DQ(output) t RC t RP Auto Refresh Precharge If needed tRC Active Bank 0 Auto Refresh Read Bank 0 Refresh cycle and Read cycle RAS-CAS delay=2 CAS latency=2 Burst length=4 Auto refresh Self refresh cycle RAS-CAS delay=3 CAS latency=3 Burst length=4 Self Refresh Cycle CLK CKE Low CKE CS RAS CAS WE A9(BS) Address A8=1 DQM DQ(input) High-Z DQ(output) tRP Precharge command If needed tRC Self refresh entry command Self refresh exit ignore command or No operation 65 HM5283206 Series Clock Suspend Mode t CKS 0 1 2 3 4 5 t CKS t CKH 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CLK CKE CS Read cycle RAS-CAS delay = 2 CAS latency = 2 Burst length = 4 RAS CAS WE A9(BS) Address R:a C:a R:b DQM DQ (output) DQ (input) a C:b a+1 a+2 a+3 b b+1 b+2 b+3 High-Z Bank0 Active clock Active suspend start Active clock Bank0 suspend end Read Bank1 Active Read suspend start Read suspend end Bank1 Read Bank0 Precharge Earliest Bank1 Precharge CKE CS RAS CAS WE A9(BS) Address DQM C:a R:b R:a High-Z DQ (output) DQ (input) a Bank0 Active 66 C:b Active clock suspend start a+1 a+2 Active clock Bank0 Bank1 supend end Write Active Write suspend start a+3 b Write suspend end b+1 b+2 b+3 Bank1 Bank0 Write Precharge Earliest Bank1 Precharge Write cycle RAS-CAS delay = 2 CAS latency = 2 Burst length = 4 HM5283206 Series Power Down Mode t CKS CLK CKE Low CKE CS RAS CAS WE A9(BS) Address R: a A8=1 DQM DQ(input) High-Z DQ(output) tRP Precharge command If needed Power down entry Power down mode exit Active Bank 0 Power down cycle RAS-CAS delay=3 CAS latency=3 Burst length=4 67 HM5283206 Series Mask Register Set Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLK CKE VIH CS RAS CAS WE DSF Mask No Mask A9 A8 A0 to A7 A5 = 1 Ra Rb Ra Rb Cb Ca DQM Mask Data DQ in a+2 a+3 b b+1 t RSC t RP Precharge If needed a Bank 0 ACTVM Mask register Set Bank 1 Bank 0 ACTV Write per bit Bank 1 Write Color Register Set Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 CLK CKE VIH CS RAS CAS WE DSF Mask No Mask A9 A8 A0 to A7 A6 = 1 Ra Rb Ra Rb Ca Cb Cc Column MASK Column MASK Column MASK DQM Color Data DQ in t RP Precharge If needed 68 t RSC Color register Set Bank 0 ACTVM Bank 1 ACTV Bank 0 Mask Block Write Bank 1 Block Write 14 HM5283206 Series Write Cycle (with I/O Mask) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLK CKE VIH CS RAS CAS WE DSF A9 A8 Ra Rb A0 to A7 Ra Rb Cb Ca DQM a DQ in Bank 0 ACTVM Bank 1 ACTV a+2 a+3 Bank 0 Write per bit b b+1 b+3 Bank 1 Write Bank 0 Precharge Block Write Cycle 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CLK CKE VIH CS RAS CAS WE DSF A9 A8 Ra Rb A0 to A7 Ra Rb Cc Cd Ca Cb Column MASK Column MASK Column MASK Column MASK Bank 0 Mask Block Write Bank 1 Block Write Bank 1 Block Write DQM DQ in tBWC Bank 0 ACTVM Bank 1 Bank 0 ACTV Mask Block Write Bank 0 Precharge 69