| Honeywell Aerospace Electronics 256K x 1 STATIC RAMSOI FEATURES RADIATION Fabricated with RICMOS IV Silicon on Insulator (SOl) 0.75 um Process (L,, = 0.6 um) Total Dose Hardness through 1x10 rad(SiO,) Neutron Hardness through 1x10" cm? Dynamic and Static Transient Upset Hardness through 1x10 rad(Si)/s Dose Rate Survivability through 1x10" rad(Si)/s Soft Error Rate of <1x10"' upsets/bit-day in Geosynchronous Orbit Advance Information HX6156 OTHER * Fast Read/Write Cycle Times < 15 ns (Typical) <= 25 ns (-55 to 125C) * Asynchronous Operation * CMOS or TTL Compatible I/O * Single 5 V + 10% Power Supply * Packaging Options 24-Lead Flat Pack (0.540 in. x 0.600 in.) 28-LeadFlat Pack (0.500 in. x 0.720 in.) GENERAL DESCRIPTION The 256K x 1 Radiation Hardened Static RAM is a high performance 262,144 word x 1-bit static random access memory with industry-standard functionality. Itis fabricated with Honeywell's radiation hardened technology, and is designed for use in systems operating in radiation environ- ments. The RAM operates over the full military temperature range and requires only a single 5 V + 10% power supply. The RAM is available with either TTL or CMOS compatible /O. Power consumption is typically less than 15 mW/MHz in operation, and less than 5 mW when de-selected. The RAM read operation is fully asynchronous, with an associ- ated typical access time of 15 ns at 5 V. Honeyweils enhanced SOI RICMOS I{V (Radiation In- sensitive CMOS) technology is radiation hardened through the use of advanced and proprietary design, layout, and process hardening techniques. The RICMOS" IV process is a 5-volt, SIMOX CMOS technology with a 150 A gate oxide and a minimum drawn feature size of 0.75 um (0.6 um effective gate lengthL,,). Additional features include tungsten via plugs, Honeywells proprietary SHARP pla- narization process, and a lightly doped drain (LDD) struc- ture for improved short channel reliability. A 7 transistor (7T) memory cell is used for superior single event upset hardening, while three layer metal power bussing and the law collection volume SIMOX substrate provide improved dose rate hardening. Solid State Electronics Center * 12001 State Highway 55, Plymouth, MN 55441 (800) 323-8295 http:/Avww.ssec.honeywell.comHX6156 FUNCTIONAL DIAGRAM Decoder . Memory Array A:0-2, 5, 13-17 IN, Row . 262,144 x 1 Ur CE* > NCS r NWE Column Decoder Data Input/Output MM we QO WE *CS*CE NOE* Co eC es 1 = enabled A \ _NWE*CS*CE*0E Sianal ' } (0 = high Z) Signal All controls must be enabled for a signal to pass. (#: number of buffers, default = 1) A:3-4, 6-12 yyy SIGNAL DEFINITIONS A: 0-17 NCS NWE NOE* CE* D Q Address input pins which select a particular bit within the memory array. Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS forces the SRAM to a precharge condition, holds the data output driver in a high impedance state and disaales all input buffers except CE. If this signal is not used it must be connected to VSS. Negative write enable, when at a low level activates a write operation and holds the data output driver in a high impedance state. When at a high level NWE allows normal read operation. Negative output enable, when at a high level holds the data output driver in a high impedance state. Wheri ai a low level, the data output driver state is defined by NCS, NWE and CE. /f this signal is not used it must be connected to VSS. Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a precharge condition, holds the data output driver in a high impedance state and disables all the input buffers except the NCS input buffer. ff this signal is not used it must be connected to VDD. Data input pin during a write operation. Remains in the high impedance state during a read operation. Data output pin during a read operation. Remains in the high impedance state during a write operation. TRUTH TABLE NCS CE* NWE NOE* MODE D Q H L Read x Data Out Notes: Write Dataln | High Z X: VIEVIH or VIL XX XX Deselected XX High Z XX: VSSsVIsVDD <x fo [Om |e - x joy - x< . . NOE=H: High Z output state maintained XX XX Disabled XX High Z for NCS=X, CE=X. NWE=X Available in 28-pin package only.HX6156 RADIATION CHARACTERISTICS Total lonizing Radiation Dose The SRAM will meet all stated functional and electrical specifications over the entire operating temperature range after the specified total ionizing radiation dose. All electrical and timing performance parameters will remain within specifications after rebound at VDD = 5.5 V and T =125C extrapolated to ten years of operation. Total dose hardness is assured by wafer level testing of process monitor transis- tors and RAM product using 10 keV X-ray and Co60 radiation sources. Transistor gate threshoid shift correla- tions have been made between 10 keV X-rays applied ata dose rate of 1x10 rad(SiO,)/min at T = 25C and gamma rays (Cobalt 60 source) to ensure that wafer level X-ray testing is consistent with standard military radiation test environments. Transient Pulse tonizing Radiation The SRAM is capable of writing, reading, and retaining stored data during and after exposure to a transient ionizing radiation pulse up to the transient dose rate upset specification, when applied under recommended operat- ing conditions. To ensure validity of all specified performance param- eters before, during, and after radiation (timing degrada- tion during transient pulse radiation is <10%), it is sug- gested that stiffening capacitance be placed on or near the package VDD and VSS, with a maximum inductance between the package (chip) and stiffening capacitance of 0.7 nH per part. If there are no operate-through or valid stored data requirements, typical circuit board mounted de-coupling capacitors are recommended. RADIATION HARDNESS RATINGS (1) The SRAM will meet any functional or electrical specifica- tion after exposure to a radiation pulse up to the transient dose rate survivability specification, when applied under recommended operating conditions. Note that the current conducted during the pulse by the RAM inputs, outputs, and power supply may significantly exceed the normal operating levels. The application design must acccmmo- date these effects. Neutron Radiation The SRAM will meet any functional or timing specification after exposure to the specified neutron fluence under recommended operating or storage conditions. This as- sumes an equivalent neutron energy of 1 MeV. Soft Error Rate The SRAM has an extremely low Soft Error Rate (SER) as specified in the table below. This hardness level is defined by the Adams 90% worst case cosmic ray environment. The low SER is achieved by the use of a unique 7-transistor memory cell and the oxide isolation of the SOI substrate. Latchup The SRAM will not latch up due to any of the above radiation exposure conditions when applied under recom- mended operating conditions. Fabrication with the SIMOX substrate material provides oxide isolation between acja- cent PMOS and NMOS transistors and eliminates any potential SCR latchup structures. Sufficient transistcr body tie connections to the p- and n-channel substrates are made to ensure no source/drain snapback occurs. Parameter Limits (2) Units Test Conditions Total Dose 21x10 rad(SiO,) Ta=25C Transient Dose Rate Upset 21x10 rad(Si)/s Pulse width <1 us Transient Dose Rate Survivability 21x10" rad(Si)/s VODee OV, Tenney Soft Error Rate (SER) <1x10" upsets/bit-day worst case envronment Neutron Fluence >1x10" N/cm? eee algat energy. (1) Device will not latch up due to any of the specified radiation exposure conditions. (2) Operating conditions (unless otherwise specified): VDD=4.5 V to 5.5 V, TA=-55C to 125C.HX6156 ABSOLUTE MAXIMUM RATINGS (1) Rating Symbol Parameter Min Max Units VDD Positive Supply Voltage (2) -0.5 6.5 Vv VPIN Voltage on Any Pin (2) -0.5 VDD+0.5 V TSTORE Storage Temperature (Zero Bias) -65 150 C TSOLDER Soldering Temperature Time 27095 Ces PD Total Package Power Dissipation (3) 2.5 Ww IOUT DC or Average Output Current 25 mA VPROT ESD Input Protection Voltage (4) 2000 Vv 24 FP 2 @UJC Thermal Resistance (Jct-to-Case) CWW 28 FP 2 TJ Junction Temperature 175 C (1) Stresses in excess of those listed above may result in permanent damage. These are stress ratings only, and operation at these levels is not implied. Frequent or extended exposure to absolute maximum conditions may affect device reliability. (2) Voltage referenced to VSS. (3) RAM power dissipation (IDDSB + IDDOP) plus RAM output driver power dissipation due to external loading must not exceed this specification. (4) Class 2 electrostatic discharge (ESD) input protection. Tested per MIL-STD-883, Method 3015 by DESC certified lab. RECOMMENDED OPERATING CONDITIONS Description Symbol Parameter Min Typ Max Units VDD Supply Voltage (referenced to VSS) 4.5 5.0 5.5 Vv TA Ambient Temperature -55 25 125 C VPIN Voltage on Any Pin (referenced to VSS) -0.3 VDD+0.3 Vv CAPACITANCE (1) Typical Worst Case ; _ Symbol Parameter (1) Min | Max Units Test Conditions Cl Input Capacitance 5 7 pF VI=VDD or VSS, f=1 MHz CO Output Capacitance 7 9 pF | VIO=VDD or VSS, f=1 MHz (1) This parameter is tested during initial design characterization only. DATA RETENTION CHARACTERISTICS 5 Typical Worst Case (2) ; 7 ymbol Parameter (4) Min | Max Units Test Conditions VDR Data Retention Voltage 2.5 Vv | NESBPR ss IDR Data Retention Current 500 | wA | Vicvbnorvse. (1) Typical operating conditions: TA= 25C, pre-radiation. (2) Worst case operating conditions: TA= -55C to +125C, post total dose at 25C.mo HX6156 DC ELECTRICAL CHARACTERISTICS ical Worst Case (2 Symbol Parameter Typical - (2) Units Test Conditions (1) Min | Max iDDSB1 | Static Supply Current 1.5 mA WiLeVSS. SOMHz IDDSBMF | Standby Supply Current - Deselected 1.5 | mA NGSSMBD, 1O=0, IDDOPW | Dynamic Supply Current, Selected (Write) 4.0 mA NOSevievas (yO IDDOPR | Dynamic Supply Current, Selected (Read) 4.0 mA NOSVILVSSIS I Input Leakage Current 5 +5 WA |VSSs<VisVDD 1OZ Output Leakage Current -10 | +10 | pA Oumutchgh VIL Low-Level Input Voltage CMOS 1.7 0.3xVo0} V March Pattern TTL 0.8 Vv VDD = 4.5V VIH High-Level Input Voltage CMOS | 3.2 | 0.7xVpbo Vv March Pattern TTL 2.2 Vv VDD = 5.5V VOL Low-Level Output Voltage 0.3 0.4 | V [vod = 4.5v, lol = 5 nee 0.005 0.05 V VDD = 4.5V, IOL = 200 LA VOH High-Level Output Voltage 4.3 4.2 V_ [VDD = 4.5V, IOH = -5 mA 4.5 | Vop-0.05 Vv VDD = 4.5V, IOH = -200 pA (1) Typical operating conditions: VDD= 5.0 V,TA=25C, pre-radiation. (2) Worst case operating conditions: VDD=4.5 V to 5.5 V, TA=-55C to +125C, post total dose at 25C. (3) All inputs switching. DC average current. 2.9V 2490 DUT output Cy 250 pF* Vref1 ok > Vref2 f Valid high output Valid low output sb *C, = 5 pF for TWLQZ, TSHQZ, TELQZ, and TGHQZ Tester Equivalent Load CircuitHX6156 READ CYCLE AC TIMING CHARACTERISTICS (1) Worst Case (3) Symbol Parameter Typical -55 to 125C Units (2) Min Max TAVAVR | Address Read Cycle Time 25 ngs TAVQV | Address Access Time 25 ns TAXQX_ | Address Change to OQuiput Invalid Time 3 ns TSLQV Chip Select Access Time 25 ns TSLQX Chip Select Output Enable Time 5 nsi TSHQZ_ | Chip Select Output Disable Time 10 ns: TEHQV_ | Chip Enable Access Time (4) 25 ns TEHQX | Chip Enable Output Enable Time (4) 5 ns. TELQZ Chip Enable Output Disable Time (4) 10 ng TGLQV | Output Enable Access Time 9 ng TGLQX | Output Enable Output Enable Time 0 ng TGHQZ j Output Enable Output Disable Time 9 ns (1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V, input and output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading C, >50 pF, or equivalent capacitive output loading C,=5 pF for TSHQZ, TELQZ TGHQZ. For C_ >50 pF, derate access times by 0.02 ns/pF (typical). (2) (4) Typical operating conditions: VDD=5.0 V, TA=25C, pre-radiation. Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 125C, post total dose at 25C. Chip Enable (CE) pin only available with 28-lead FP. _ TAVAVR _ ADDRESS Xk - Tavav __ TAXQX __Tstoev Tox _._TsHaz_ DATA OUT _ ae DATA VALID ae ___TEHOX CHV | __TELQZ_ | * | CE TGLax i \ Terex AMA i. Totav wa 1GHOZ SSRN (IE (NWE = high) *Only available in 28-lead package.HX6156 WRITE CYCLE AC TIMING CHARACTERISTICS (1) Worst Case (3) Symbol Parameter Typical (2) Units Min Max TAVAVW | Write Cycle Time (4) 25 ns TWLWH Write Enable Write Pulse Width 20 ns TSLWH Chip Select to End of Write Time 20 ns TDVWH Data Valid to End of Write Time 15 ns TAVWH Address Valid to End of Write Time 20 ns TWHDX Data Hold Time after End of Write Time 0 ns TAVWL Address Valid Setup to Start of Write Time 0 ns TWHAX Address Valid Hold after End of Write Time 0 ns TWLOQZ Write Enable to Output Disable Time 0 9 ns TWHQX Write Disable to Output Enable Time 5 ns TWHWL Write Disabie to Write Enable Pulse Width(5) 5 ns TEHWH Chip Enable to End of Write Time (6) 20 ns (1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fail times <1 ns/V, input and output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output Joading >50 pF, or equivalent capacitive load of 5 pF for TWLQZ. Typical operating conditions: VDD=5.0 V, TA=25C, pre-radiation. TAVAV = TWLWH + TWHWL Guaranteed but not tested. Chip Enable (CE) pin only available with 28-lead FP. SGEGH Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 125C, post total dose at 25C. TAVAVW ADDRESS X _ TAVWH TWHAX __| _Tawt | _ TWHWL _ TWLWH _ NWE / \ / <___ Two? TwHax DATA OUT HIGH IMPEDANCE _ TovwH TwHox DATA IN X DATA VALID Y ___ TSLWH _ TEHWH *Only available in 28-lead package.HX6156 DYNAMIC ELECTRICAL CHARACTERISTICS Read Cycie The RAM is asynchronous in operation, allowing the read cycle to be controlled by address, chip select (NCS), or chip enable (CE) (refer to Read Cycle timing diagram). To perform a valid read operation, both chip select and output enable (NOE) must be low and chip enable and write enable (NWE) must be high. The output driver can be controlled independently by the NOE signal. Consecutive read cycles can be executed with NCS held continuously low, and with CE held continuously high, and toggling the addresses. For an address activated read cycle, NCS must be valid prior to, coincident with or within (TAVQV minus TSLQV) time following edge transition(s). CE must be valid a minimum of (TEHQV minimums TAVQV) time prior to the activating address edge transitions(s). Any amount of toggling or skew between address edge transitions is permissible; however, data outputs will become valid TAVQV time following the latest occurring address edge transition. The minimum ad- dress activated read cycie time is TAVAV. When the RAM is operated at the minimum address activated read cycle time, the data output will remain valid on the RAM I/O until TAXQX time following the next sequential address transition. To conirol a read cycle with NCS, all addresses must be valid at least (TAVQV minus TSLQV) time prior to the enabling NCS edge transition. CE must be valid aminimum of (TEHQV minus TSLQV) time prior to the enabling NCS edge transition. Address or CE edge transitions can occur later than the specified setup times to NCS, however, the valid data access time will be delayed. Any address edge transition, which occurs during the time when NCS is low, will initiate a new read access, and the data output will not become valid until TAVQV time following the address edge transition. The data output will enter a high impedance state TSHQZ time following a disabling NCS edge transi- tion. To control a read cycle with CE, all addresses and NCS must be valid prior to or coincident with the enabling CE edge transition. Address or NCS edge transitions can occur later than the specified setup times to CE; however, the valid data access time will be delayed. Any address edge transition which occurs during the time when CE is high will initiate a new read access, and data output will not become valid until TAVQV time following the address edge transition. The data output will enter a high impedance state TELQZ time following a disabling CE edge transition. Write Cycle The write operation is synchronous with respect to the address bits, and control is governed by write enable (NWE), chip select (NCS), or chip enable (CE) edge transitions (refer to Write Cycle timing diagrams). To per- form a write operation, both NWE and NCS must be tow, and CE must be high. The ouput driver can be conitrelled independently by the output enable (NOE) signal. Con- secutive write cycles can be performed with NWE or NCS held continuously low, or CE held continuously high. At least one of the control signals must transition to the opposite state between consecutive write operations. To write data into the RAM, NWE and NCS mustbe held low and CE must be held high for at least TWLWH/TSLSH/ TEHEL time. Any amount of edge skew between the signals can be tolerated, and any one of the control signals can initiate or terminate the write operation. For consecu- tive write operations, write pulses must be separated by the minimum specified TWHWL/TSHSL/TELEH time. Address inputs must be valid at least TAVWL/TAVSL/TAVEH time before the enabling NWE/NCS/CE edge transition, and must remain valid during the entire write time. A valid data overlap of write pulse width time of TDVWH/TDVSH/TDVEL, and an address valid to end of write time of TAVWH/ TAVSH/TAVEL also must be provided for during the write operation. Hold times for address inputs and data input with respect to the disabling NWE/NCS/CE edge transition must be a minimum of TWHAX/TSHAX/TELAX time and TWHDX/TSHDX/TELDX time, respectively. The minimum write cycle time is TAVAV.HX6156 TESTER AC TIMING CHARACTERISTICS High Z = 2.9V TTL /O Configuration CMOS I/O Configuration VDD-0.5 V Input Levels* O8V Output N. Sense Deer ree a High 2 Levels . 34V---f7% High Z 24V% High Z = 2.9V * Input rise and fail times <1 ns/V QUALITY AND RADIATION HARDNESS ASSURANCE Honeyweil maintains a high level of product integrity through process control, utilizing statistical process control, acom- plete Total Quality Assurance System, a computer data base process performance tracking system, and a radia- tion-hardness assurance strategy. The radiation hardness assurance strategy starts with a technology that is resistant to the effects of radiation. Radiation hardness is assured on every wafer by irradiating test structures as well as SRAM product, and then monitor- ing key parameters which are sensitive to ionizing radiation. Conventional MIL-STD-883 TM 5005 Group E testing, which includes total dose exposure with Cobalt 60, may also be performed as required. This Total Quality approach ensures our customers of a reliable product by engineering in reliability, starting with process development and con- tinuing through product qualification and screening. SCREENING LEVELS Honeywell offers several Jevels of device screening to meet your system needs. Engineering Devices are available with limited performance and screening for breadboarding and/or evaluation testing. Hi-Rel Level B and S devices undergo additional screening per the requirements of MIL- STD-883. As a QML supplier, Honeywell also offers QML Class Q and V devices per MIL-PRF-38535 and are avail- able per the applicable Standard Microcircuit Drawing (SMD). QML devices offer ease of procurement by eliminating the need to create detailed specifications and offer benefits of improved quality and cost savings through standardization. RELIABILITY Honeywell understands the stringent reliability require- ments for space and defense systems and has exiensive experience in reliability testing on programs of this nature. This experience is derived from comprehensive testing of VLSI processes. Reliability attributes of the RICMOS process were characterized by testing specially designed irradiated and non-irradiated test structures from which specific failure mechanisms were evaluated. These specific mechanisms included, but were not limited to, hot carriers, electromigration and time dependent dielectric breakdown. This data was then used to make changes to the design models and process to ensure more reliable products. In addition, the reliability of the RICMOS process and product in a military environment was monitored by testing irradiated and non-irradiated circuits in accelerated dy- namic life test conditions. Packages are qualified for prod- uct use after undergoing Groups B & D testing as outlined in MIL-STD-883, TM 5005, Class S. The productis cualified by following a screening and testing flow to meet the customer's requirements. Quatity conformance testing is performed as an option on all production lots to ensure the ongoing reliability of the product.HX6156 PACKAGING The 256K x 1 SRAM is offered in a custom 24-lead and 28- lead flat pack. These packages are constructed of multi- layerceramic (Al,O,) and contain internal power and ground planes. All NC pins must be connected to either VDD, VSS or an active driver to prevent charge buildup in the radiation environment. Optional capacitors can be mounted to the package by the user to maximize supply noise decoupling and increase board packing density. The capacitors attach electrically to the internal package power and ground planes. This design minimizes resistance and inductance of the bond wire and package, both of which are critical in a transient radiation environment. 24-LEAD FP PINOUT AO 1 VDD At 2 Ai7 A2 3 A16 A3 4 A15 A4 5 A14 AS 6 256K x 1 A13 A6 7 Ai2 A7 a lop Att Ag View A10 Q AQ NWE D vss NCS 28-LEAD FP PINOUT AO _; VDD Al > A17 A2 5 A16 A3 mmm A15 a5 aa: Aig 6 256K x 1 oo 8 AG mmm, FOP A12 A7 View Att A8 At0 Q AQ NWE D vss NCS DYNAMIC BURN-IN DIAGRAM VDD 1 24 F9 oCR}-Y AO vop 22] F8 0a} At A172. x} 0 F18 22 F7 oLA}-4 A2 A16|-s-}0 F10 Feopap{| as | StS oF 1 F5 LE} A4 co A14 Eo F 12 oLE | AS A13 12-3} 0 F13 a oLE | AS TT A128 a F14 oa} A7 att Lo F15 Fe 9 =< 16 Figotr 7] As = wT S$} 0 F168 VDD/2 oCa_-Y| @ ASE oF 17 VW FO oa}] NWE DL+ 0 Ft 12) vss NCS| 2-7-0 F18 vss[ VDD = 5.6V, R<10KQ, VIH = VDD, VIL = VSS Ambient Temperature > 125C, FO > 100 KHz Sq Wave Frequency of F1 = F0/2, F2 = F0/4, F3 = FO0/8, etc. STATIC BURN-IN DIAGRAM VDD VDD | AO vpp [24 At AI7/23_-e4 A2 s A16 22 A} 21 a =z A15 ELE | oc A14|2 wr} AS O A139 a4 A6 7 A128 pa A7 e Ali? |A8 o A10 LS 74 Q Q ASLS pa NWE DL a4 vss NCS/3_ 77 _ VDD = 5.5V, R < 10 KQ Ambient Temperature > 125CHX6156 24-LEAD FLAT PACK Optional capacitors Lid Marking in cutout" - + E ~ ok ces sue y A i yb a (width) & g 2 Wo Ee a 2 = - Y Y a _ 6 4 (pitch (pi ly L > < L > Kovar Ceramic A Lid [4] Body Cc Lead Q G , . (Alloy 42) A | 0.150 + 0.015 , b | 0.015 + 0.002 C | 0.003 to 0.006 D 0.600 + 0.007 e 0.050 + 0.005 [1] E 0.540 + 0.007 E2 0.450 + 0.007 3 0.030 min F 0.550 + 0.005 [2] yo CE { f [ [ VDD vss N<xS<MOrO VDD All dimensions in inches 0.050 + 0.005 0.376 min [3] 0.026 to 0.045 0.025 + 0.010 0.300 ref 0.050 ref 0.030 ref 0.100 ref 0.080 ref 1] Tolerances are non-accumulative 2] Where lead is brazed to package 3] Parts delivered with leads unformed 4] Lid is connected to VSS 28-LEAD FLAT PACK + b (width) Capacitor Pads os All dimensions in inches Kovar Lid [4] Body Lead (Alloy 42) [3] A a C A b Cc D e E E2 Ceramic E3 F G L Q $s U Ww X 0.050 ref 0.075 ref Y | 0.010 ref 0,105 + 0.015 0.017 + 0.002 0.003 to 0.006 0.720 + 0.008 0,050 + 0.005 [1] [1] BSC Basic lead spacing between centers [2] Where lead is brazed to package [3] Parts delivered with leads unformed [4] Lid connected to VSS 11HX6156 ORDERING INFORMATION (1) H xX 6156 N S H Cc | | | PART NUMBER SCREEN LEVEL INPUT V=QML Class V BUFFER TYPE Q=QML Class Q C=CMOS Level PROCESS S=Class $ T=TTL Level X=SOl B=Class B E=Engr Device (2) SOURCE PACKAGE DESIGNATION TOTAL DOSE H=HONEYWELL L=24-Lead FP HARDNESS N=28-Lead FP F=3x10 rad(SiO,) K=Known Good Die G=5x10 rad(SiO,) - = Bare Die (No Package) H=1x10 rad(SiO,) (1) Orders may be faxed to 612-954-2051. Please contact our Customer Logistics Department at 612-954-2888 for further information. (2) Engineering Device description: Parameters are tested from -55 to 125C, 24 hr burn-in, no radiation guaranteed. Contact Factory with other needs. To learn more about Honeywell Solid State Electronics Center, visit our web site at http://www.ssec.honeywell.com Honeywell reserves the right to make changes to any products or technology herein to improve reliability, function or design. Honeywell does not assume any liability arising out of the application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others. Honeywell Helping You Control Your World 900197 Rev. A 6-97