DS07-13745-1E
FUJITSU SEMICONDUCTOR
DATA SHEET
Copyright©2007 FUJITSU LIMITED All rights reserved
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Be sure to refer to the “Check Sheet” for the latest cautions on development.
16-bit Microcontroller
CMOS
F2MC-16LX MB90925 Series
MB90F927/F927S/V925-101/V925-102
■DESCRIPTION
MB90925 series is a 16-bit general-purpose high-capacity microcontroller designed for vehicle meter control
applications etc.
The instruction set retains the same AT architecture as F2MC-8L and F2MC-16L series, with further refinements
including high-level language instructions, expanded addressing mode, enhanced signed multiplication and
division computation and bit processing.
In addition, a 32-bit accumulator is built in to enable long word processing.
Note : F2MC is the abbreviation of FUJITSU Flexible Microcontroller.
■FEATURES
•Clock
Built-in PLL clock frequency multiplication circuit.
Selection of machine clocks (PLL clocks) is allowed among frequency division by 2 on oscillation clock and
multiplication of 1 to 4 times of oscillation clock(for 4 MHz oscillation clock, 4 MHz to 16 MHz).
Operation by sub clock(up to 50 kHz : 100 kHz oscillation clock divided by 2).
(Continued)
MB90925 Series
2
• 16-bit input capture (4 channels)
Detects rising, falling, or both edges.
16-bit capture register × 4
Pin input edge detection latches the 16-bit free-run timer counter value, and generates an interrupt request.
• 16-bit reload timer (2 channels)
16-bit reload timer operation (select toggle output or one-shot output)
Event count function selection provided
• Real Time watch timer (main clock)
Operates directly from oscillator clock.
Interrupt can be generated by second/minute/hour/date counter overflow.
• 16-bit PPG (3 channels)
Output pins (3 channels) , external trigger input pin (1 channel)
Output clock frequencies : fCP, fCP/22, fCP/24, fCP/26
• Delay interrupt
Generates interrupt for task switching.
Interrupts to CPU can be generated/deleted by software setting.
• External interrupts (8 channels)
8-channel independent operation
Interrupt source setting available : “L” to “H” edge/ “H” to “L” edge/ “L” level/ “H” level.
• A/D converter
10-bit or 8-bit resolution × 8 channels (input multiplexed)
Conversion time : 2.6µs (at fCP = 16 MHz)
External trigger startup available (P50/INT0/ADTG)
Internal timer startup available (16-bit reload timer 1)
• UART(LIN/SCI) (2 channels)
Equipped with full duplex double buffer
Clock-asynchronous or clock-synchronous serial transfer is available
• SIO (1 channel)
Clock synchronized data transmission.
LSB-first or MSB-first data transfer selection is available.
• CAN interface
Conforms to CAN specifications version 2.0 Part A and B.
Automatic resend in case of error.
Automatic transfer in response to remote frame.
16 prioritized message buffers for data and ID
Multiple message support
Receiving filter has flexible configuration : Full bit compare/full bit mask/two partial bit masks
Supports up to 1 Mbps
CAN WAKEUP function (connects RX internally to INT0)
• LCD controller/driver (32 segment x 4 common)
Segment driver and command driver with direct LCD panel (display) drive capability
• Low voltage/Program looping detect reset
Automatic reset when low voltage is detected
Program looping detection function
(Continued)
MB90925 Series
3
(Continued)
• Stepping motor controller (4 channels)
High current output for each channel × 4
Synchronized 8/10-bit PWM for each channel × 2
• Sound generator
8-bit PWM signal mixed with tone frequency from 8-bit reload counter.
PWM frequencies : 62.5 kHz, 31.2 kHz, 15.6 kHz, 7.8 kHz (at fCP = 16 MHz)
Tone frequencies : 1/2 PWM frequency, divided by (reload frequency +1)
• Input/output ports
General-purpose input/output port (CMOS output)
- 70 ports (dual clock system)
- 72 ports (single clock system)
• Input level select function for port
Automotive/CMOS-Schmitt (initial level is Automotive in single chip mode)
• Flash memory security function
Protect the content of Flash memory (Flash memory product only)
MB90925 Series
4
■PRODUCT LINEUP
MB90F927 MB90F927S MB90V925-101 MB90V925-102
Type Flash memory product Evaluation product
CPU F2MC-16LX CPU
System clock PLL clock multiplier circuit ( × 1, × 2, × 3, × 4, 1/2 when PLL stopped)
Minimum instruction execution time 62.5 ns (with 4 MHz oscillation clock × 4)
Sub clock pin
(X0A, X1A) Yes No Yes
ROM Flash memory 64 Kbytes External
RAM 4 Kbytes 13.5 Kbytes
I/O port 70 ports 72 ports 70 ports
SIO 1 channel
LCD segment 32
UART UART(LIN/SCI) 2 channels
CAN interface 1 channel
16-bit input capture 4 channels
16-bit reload timer 2 channels
16-bit free-run timer 1 channel
Real time watch timer 1 channel
16-bit PPG 3 channels
External interrupt 8 channels
8/10-bit A/D converter 8 channels
LVD/CPU loop reset Yes No
Stepping motor controller 4 channels
Sound generator 1 channel
Flash memory security Yes No
Operation voltage 3.7 V to 5.5 V 4.5 V to 5.5 V
Packages QFP-100, LQFP-100 PGA-299
Part number
Parameter
MB90925 Series
5
■PIN ASSIGNMENTS
(TOP VIEW)
(FPT-100P-M06)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
COM2
COM3
P22/SEG0
P23/SEG1
P24/SEG2
P25/SEG3
P26/SEG4
P27/SEG5
P30/SEG6
P31/SEG7
VSS
P32/SEG8
P33/SEG9
P34/SEG10
P35/SEG11
P36/SEG12
P37/SEG13
P40/SEG14
P41/SEG15
P42/SEG16
P43/SEG17
P44/SEG18
VCC
P45/SEG19
P46/SEG20
P47/SEG21
C
P90/SEG22
P91/SEG23
V0
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P92/X0A
P93/X1A
P57/SGA
RST
P56/SGO/FRCK
P55/RX0
P54/TX0
DVSS
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
DVCC
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DVSS
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
DVCC
P73/PWM2M0
P72/PWM2P0
P71/PWM1M0
P70/PWM1P0
DVSS
P53/INT3/SCK
MD2
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
COM1
COM0
P15/IN0
P14/IN1
P13/IN2
P12/TIN0/IN3
P11/TOT0
P10/PPG2
P07/PPG1/TIN1/SEG31
P06/PPG0/TOT1/SEG30
P05/SCK1/TRG/SEG29
P04/SOT1/SEG28
P03/SIN1/INT7/SEG27
P02/SCK0/INT6/SEG26
P01/SOT0/INT5/SEG25
P00/SIN0/INT4/SEG24
VCC
X1
X0
VSS
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
V1
V2
V3
AVCC
AVRH
P50/INT0/ADTG
AVSS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
VSS
P64/AN4
P65/AN5
P66/AN6
P67/AN7
P51/INT1/SI
P52/INT2/SO
MD0
MD1
MB90925 Series
6
(TOP VIEW)
(FPT-100P-M05)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P22/SEG0
P23/SEG1
P24/SEG2
P25/SEG3
P26/SEG4
P27/SEG5
P30/SEG6
P31/SEG7
V
SS
P32/SEG8
P33/SEG9
P34/SEG10
P35/SEG11
P36/SEG12
P37/SEG13
P40/SEG14
P41/SEG15
P42/SEG16
P43/SEG17
P44/SEG18
V
CC
P45/SEG19
P46/SEG20
P47/SEG21
C
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RST
P56/SGO/FRCK
P55/RX0
P54/TX0
DV
SS
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
DV
CC
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
DV
SS
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
DV
CC
P73/PWM2M0
P72/PWM2P0
P71/PWM1M0
P70/PWM1P0
DV
SS
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
P90/SEG22
P91/SEG23
V0
V1
V2
V3
AV
CC
AVRH
P50/INT0/ADTG
AV
SS
P60/AN0
P61/AN1
P62/AN2
P63/AN3
V
SS
P64/AN4
P65/AN5
P66/AN6
P67/AN7
P51/INT1/SI
P52/INT2/SO
MD0
MD1
MD2
P53/INT3/SCK
COM3
COM2
COM1
COM0
P15/IN0
P14/IN1
P13/IN2
P12/TIN0/IN3
P11/TOT0
P10/PPG2
P07/PPG1/TIN1/SEG31
P06/PPG0/TOT1/SEG30
P05/SCK1/TRG/SEG29
P04/SOT1/SEG28
P03/SIN1/INT7/SEG27
P02/SCK0/INT6/SEG26
P01/SOT0/INT5/SEG25
P00/SIN0/INT4/SEG24
V
CC
X1
X0
V
SS
P92/X0A
P93/X1A
P57/SGA
MB90925 Series
7
■PIN DESCRIPTIONS
(Continued)
Pin no.
Pin name
I/O
circuit
type*3
Function
LQFP*1QFP*2
80 82 X0 AHigh speed oscillator input pin
81 83 X1 High speed oscillator output pin
78 80
P92 G General-purpose I/O port
X0A A Low speed oscillator input pin. If no oscillator is connected,
apply pull-down processing.
77 79
P93 G General-purpose I/O port
X1A A Low speed oscillator output pin. If no oscillator is connected,
leave open.
75 77 RST B Reset input pin
83 85
P00
J
General-purpose input/output port
SIN0 UART ch.0 serial data input pin
INT4 INT4 external interrupt input pin
SEG24 LCD controller/driver segment output
84 86
P01
E
General-purpose input/output port
SOT0 UART ch.0 serial data output pin
INT5 INT5 external interrupt input pin
SEG25 LCD controller/driver segment output
85 87
P02
E
General-purpose input/output port
SCK0 UART ch.0 serial clock input/output pin
INT6 INT6 external interrupt input pin
SEG26 LCD controller/driver segment output
86 88
P03
J
General-purpose input/output port
SIN1 UART ch.1 serial data input pin
INT7 INT7 external interrupt input pin
SEG27 LCD controller/driver segment output
87 89
P04
E
General-purpose input/output port
SOT1 UART ch.1 serial data output pin
SEG28 LCD controller/driver segment output
88 90
P05
E
General-purpose input/output port
SCK1 UART ch.1 serial clock input/output pin
TRG 16-bit PPG ch.0 to ch.2 external trigger input pin
SEG29 LCD controller/driver segment output
MB90925 Series
8
(Continued)
Pin no.
Pin name
I/O
circuit
type*3
Function
LQFP*1QFP*2
89 91
P06
E
General-purpose input/output port
PPG0 16-bit PPG ch.0 output pin
TOT1 16-bit reload timer ch.1 TOT output pin
SEG30 LCD controller/driver segment output
90 92
P07
E
General-purpose input/output port
PPG1 16-bit PPG ch.1 output pin
TIN1 16-bit reload timer ch.1 TIN output pin
SEG31 LCD controller/driver segment output
91 93 P10 GGeneral-purpose input/output port
PPG2 16-bit PPG ch.2 output pin
92 94 P11 GGeneral-purpose input/output port
TOT0 16-bit reload timer ch.0 TOT output pin
93 95
P12
G
General-purpose input/output port
TIN0 16-bit reload timer ch.0 TIN output pin
IN3 Input capture ch.3 trigger input pin
94 to 96 96 to 98 P13 to P15 GGeneral-purpose input/output port
IN2 to IN0 Input capture ch.2 to ch.0 trigger input pins
97 to 100 99, 100,
1, 2
COM0 to
COM3 I LCD controller/driver common output pins
1 to 6 3 to 8
P22 to P27
E
General-purpose input/output ports
SEG0 to
SEG5 LCD controller/driver segment output pins
7, 8,
10 to 15
9, 10,
12 to 17
P30 to P37
E
General-purpose input/output port
SEG6 to
SEG13 LCD controller/driver segment output pins
16 to 20,
22 to 24
18 to 22,
24 to 26
P40 to P47
E
General-purpose input/output port
SEG14 to
SEG21 LCD controller/driver segment output pins
26, 27 28, 29
P90, P91
E
General-purpose input/output port
SEG22,
SEG23 LCD controller/driver segment output pins
34 36
P50
G
General-purpose input/output port
INT0 INT0 external interrupt input pin
ADTG A/D converter external trigger input pin
MB90925 Series
9
(Continued)
Pin no.
Pin name
I/O
circuit
type*3
Function
LQFP*1QFP*2
36 to 39,
41 to 44
38 to 41,
43 to 46
P60 to P67
F
General-purpose input/output port
AN0 to
AN7 A/D converter input pins
45 47
P51
K
General-purpose input/output port
INT1 INT1 external interrupt input pin
SI SIO data input pin
46 48
P52
G
General-purpose input/output port
INT2 INT2 external interrupt input pin
SO SIO data output pin
50 52
P53
G
General-purpose input/output port
INT3 INT3 external interrupt input pin
SCK SIO clock input/output pin
52 to 55 54 to 57
P70 to P73
H
General-purpose input/output port
PWM1P0,
PWM1M0,
PWM2P0,
PWM2M0
Stepping motor controller ch.0 output pins
57 to 60 59 to 62
P74 to P77
H
General-purpose input/output port
PWM1P1,
PWM1M1,
PWM2P1,
PWM2M1
Stepping motor controller ch.1 output pins
62 to 65 64 to 67
P80 to P83
H
General-purpose input/output port
PWM1P2,
PWM1M2,
PWM2P2,
PWM2M2
Stepping motor controller ch.2 output pins
67 to 70 69 to 72
P84 to P87
H
General-purpose input/output port
PWM1P3,
PWM1M3,
PWM2P3,
PWM2M3
Stepping motor controller ch.3 output pins
72 74 P54 GGeneral-purpose input/output port
TX0 CAN interface 0 TX output pin
73 75 P55 GGeneral-purpose output port
RX0 CAN interface 0 RX input pin
MB90925 Series
10
(Continued)
*1: FPT-100P-M05
*2: FPT-100P-M06
*3: For the I/O circuit type, refer to “■ I/O CIRCUIT TYPE”
*4: Type C in MB90F927 and MB90F927S, type D in MB90V925-101 and MB90V925-102.
Pin no.
Pin name
I/O
circuit
type*3
Function
LQFP*1QFP*2
74 76
P56
G
General-purpose input/output port
SGO Sound generator SGO output pin
FRCK Free-run timer clock input pin
76 78 P57 GGeneral-purpose input/output port
SGA Sound generator SGA output pin
28 to 31 30 to 33 V0 to V3 ⎯LCD controller /driver reference power supply pins
56, 66 58, 68 DVCC ⎯Power supply input pins dedicated for high current output buffer
(pin numbers 54 to 57, 59 to 62, 64 to 67, 69 to 72) .
51, 61, 71 53, 63, 73 DVSS ⎯Power supply GND pins dedicated for high current output buffer (pin
numbers 54 to 57, 59 to 62, 64 to 67, 69 to 72) .
32 34 AVCC ⎯A/D converter dedicated power supply input pin
35 37 AVSS ⎯A/D converter dedicated power supply GND pin
33 35 AVRH ⎯A/D converter Vref + input pin
47,
48
49,
50
MD0,
MD1 C Test mode input pins. Connect to VCC.
49 51 MD2 C/D*4 Test mode input pin. Connect to VSS.
25 27 C ⎯External capacitor pin. Connect an 0.1 µF capacitor between this
pin and VSS.
21, 82 23, 84 VCC ⎯Power supply input pins
9, 40, 79 11, 42, 81 VSS ⎯Power supply GND pins
MB90925 Series
11
■I/O CIRCUIT TYPE
(Continued)
Type Circuit Remarks
A
• High-speed oscillation pin
Oscillation feedback resistance :
approx. 1 MΩ (X0, X1 : MAIN)
• Low-speed oscillation pin
Oscillation feedback resistance :
approx. 10 MΩ (X0A, X1A : SUB)
B
Input dedicated pin (with pull-up resis-
tance)
• Pull-up resistance attached :
approx. 50 kΩ
• Hysteresis input
(VIH/VIL = 0.8VCC/0.2VCC)
C
Input dedicated pin
Hysteresis input
(VIH/VIL = 0.8VCC/0.2VCC)
D
Input dedicated pin (with pull-down re-
sistance)
• Pull-down resistance attached :
approx. 50 kΩ
• Hysteresis input
(VIH/VIL = 0.8VCC/0.2VCC)
E
LCDC output common general-
purpose port
• CMOS output
(IOH/IOL = ± 4 mA)
• Hysteresis input
(VIH/VIL = 0.8VCC/0.2VCC)
• Automotive input
(VIH/VIL = 0.8VCC/0.5VCC)
X1
X0
Xout
Standby control signal
Hysteresis input
Hysteresis input
Hysteresis input
P-ch
N-ch
Standby control signal or
LCDC output switching signal
LCDC output
Hysteresis input
Standby control signal or
LCDC output switching signal
Automotive input
Pout
Nout
MB90925 Series
12
(Continued)
Type Circuit Remarks
F
A/D converter input common general-
purpose port
• CMOS output
(IOH/IOL = ± 4 mA)
• Hysteresis input
(VIH/VIL = 0.8VCC/0.2VCC)
• Automotive input
(VIH/VIL = 0.8VCC/0.5VCC)
G
General-purpose port
• CMOS output
(IOH/IOL = ± 4 mA)
• Hysteresis input
(VIH/VIL = 0.8VCC/0.2VCC)
• Automotive input
(VIH/VIL = 0.8VCC/0.5VCC)
H
High current output common general-
purpose port
• CMOS output
(IOH/IOL = ± 30 mA)
• Hysteresis input
(VIH/VIL = 0.8VCC/0.2VCC)
• Automotive input
(VIH/VIL = 0.8VCC/0.5VCC)
P-ch
N-ch
Standby control signal or
Analog input enable signal
Analog input
Hysteresis input
Standby control signal or
Analog input enable signal
Automotive input
Pout
Nout
P-ch
N-ch
Standby control signal
Hysteresis input
Standby control signal
Automotive input
Pout
Nout
P-ch
N-ch
Standby control signal
Hysteresis input
Standby control signal
Automotive input
Pout high current output
Nout high current output
MB90925 Series
13
(Continued)
Type Circuit Remarks
I
LCDC output pin (COM pin)
J
LCDC output common general-
purpose port (serial input)
• CMOS output
(IOH/IOL = ± 4 mA)
• Hysteresis input
(VIH/VIL = 0.8VCC/0.2VCC)
• CMOS input (SIN)
(VIH/VIL = 0.7VCC/0.3VCC)
• Automotive input
(VIH/VIL = 0.8VCC/0.5VCC)
K
General-purpose port (serial input)
• CMOS output
(IOH/IOL = ± 4 mA)
• Hysteresis input
(VIH/VIL = 0.8VCC/0.2VCC)
• CMOS input (SIN)
(VIH/VIL = 0.7VCC/0.3VCC)
• Automotive input
(VIH/VIL = 0.8VCC/0.5VCC)
N-ch
P-ch
LCDC output
P-ch
N-ch
Standby control signal or
LCDC output enable signal
LCDC output
Hysteresis input
Standby control signal or
LCDC output enable signal
Automotive input
Standby control signal or
LCDC output enable signal
CMOS input (SIN)
Pout
Nout
P-ch
N-ch
Standby control signal
Hysteresis input
Standby control signal
Automotive input
Standby control signal
CMOS input (SIN)
Pout
Nout
MB90925 Series
14
■HANDLING DEVICES
• Strictly observe maximum rated voltages (preventing latch-up)
In CMOS IC devices, a condition known as latch-up may occur if voltages higher than VCC or lower than VSS are
applied to input or output pins other than medium-or high-voltage pins, or if the voltage applied between VCC and
VSS exceeds the rated voltage level. In a latch-up condition, the power supply current can increase dramatically
and may destroy semiconductor elements. In using semiconductor devices, always take sufficient care to avoid
exceeding maximum ratings.
Also care must be taken when the analog system power supply is switched on or off to ensure that the analog
power supply (AVCC, AVRH) , the analog input voltages and the power supply voltage for the high current output
buffer pins (DVCC) do not exceed the digital power supply voltage (VCC) .
Once the digital power supply voltage (VCC) has been disconnected, the analog power supply (AVCC, AVRH) and
the power supply voltage for the high current output buffer pins (DVCC) may be turned on in any sequence.
• Stable supply voltage
Even within the warranted operating range of VCC power supply voltage, rapid fluctuations in the power supply
voltage can cause malfunctions. The recommended stability for ripple fluctuations (P-P value) at commercial
frequencies (50 Hz/60 Hz) should be within 10% of the standard VCC value, and voltage fluctuations that occur
during switching of power supplies etc. should be limited to transient fluctuation rates of 0.1 V/ms or less.
• Notes on energization Power-on procedures
In order to prevent the built-in step-down circuits from malfunctioning, the voltage rising time (0.2 V to 2.7 V)
during power-on should be attained within 50 µs.
• Treatment of unused pins
If unused input pins are left open, they may cause malfunctions or latch-up which may lead to permanent damage
to the semiconductor. Unused input pins should therefore be pulled up or pulled down through a resistor of at
least 2 kΩ.
Any unused input/output pins should be left open in output status, or if found set to input status, they should be
treated in the same way as input pins.
• Treatment of A/D converter power supply pins
Even if the A/D converter is not used, pins should be connected so that AVCC = VCC, and AVSS = AVRH = VSS.
• Notes on Using an external clock
Even when an external clock is used, an oscillation stabilization wait time is required following power-on reset
or release from sub clock mode or stop mode. Also, when an external clock is used, it should drive only the X0
pin and the X1 pin should be left open, as shown below.
X0
X1
OPEN
MB90925 Series
Sample external clock connection
MB90925 Series
15
• Power supply pins
Devices are designed to prevent problems such as latch-up when multiple VCC and VSS pins are used, by providing
internal connections between pins having the same potential. However, in order to reduce unwanted radiation,
to prevent abnormal operation of strobe signals due to rise in ground level, and to maintain total output current
ratings, all VCC and VSS pins should always be connected externally to power supplies and ground respectively.
As shown in the figure below, all VCC pins must have the same potential and all VSS pins must be at the same
potential. If there are multiple VCC or VSS systems, the device will not operate properly even within the warranted
operating range.
In addition, care must be given to connecting the VCC and VSS pins of this device to the current supply source
with as low impedance as possible. It is recommended that a 1.0 µF bypass capacitor be connected between
the VCC and VSS pins as close to the pins as possible.
• Turning-on sequence of power supply to A/D converter and analog inputs
The A/D converter power supply (AVCC, AVRH) and analog inputs (AN0 to AN7) must be applied after the digital
power supply (VCC) is switched on. When power is shut off, the A/D converter power supply and analog inputs
must be cut off before the digital power supply is switched off (VCC) . In both power-on and power-off, care should
be taken that AVRH does not exceed AVCC. Even when pins which double as analog input pins are used as input
ports, be sure that the input voltage does not exceed AVCC.
• Handling the power supply for high-current output buffer pins (DVCC, DVSS)
Always apply power supply to high-current output buffer pins (DVCC, DVSS) after the digital power supply (VCC) is
turned on. Also when switching the power off, always shut off the power supply to the high-current output buffer
pins (DVCC, DVSS) before switching off the digital power supply (VCC) . There is no problem if the high-current
output buffer pins and digital power supplies are turned off and on at the same time.
Even when the high-current output buffer pins are used as general-purpose ports, the power supply for high
current output buffer pins (DVCC, DVSS) should be applied to these pins.
• Pull-up/pull-down resistor
MB90925 series does not support internal pull-up/pull-down resistor. If necessary, use external components.
VCC
VCC
VCC
VCC
VCC
VSS
VSS
VSS
VSS
VSS
Power supply input pins (VCC/VSS)
MB90925 Series
16
• Precautions for when not using a sub clock signal
If the X0A and X1A pins are not connected to an oscillator, apply pull-down treatment to the X0A pin and leave
the X1A pin open.
• Notes on operation when external clock is stopped
When there is no external oscillator or external clock input is stopped, performance of the operation by MB90925
series the internal oscillation circuit cannot be guaranteed.
MB90925 Series
17
■BLOCK DIAGRAM
X0, X1
P92/X0A
P93/X1A
RST
P57/SGA
P56/SGO/FRCK
P55/RX0
P54/TX0
P53/INT3/SCK
P52/INT2/SO
P51/INT1/SI
P50/INT0/ADTG
P87/PWM2M3
P86/PWM2P3
P85/PWM1M3
P84/PWM1P3
P83/PWM2M2
P82/PWM2P2
P81/PWM1M2
P80/PWM1P2
P77/PWM2M1
P76/PWM2P1
P75/PWM1M1
P74/PWM1P1
P73/PWM2M0
P72/PWM2P0
P71/PWM1M0
P70/PWM1P0
P67 to P60/
AN7 to AN0
AVCC/AVSS
AVRH
P91, P90/
SEG23, SEG22
P47 to P40/
SEG21 to SEG14
P37 to P30/
SEG13 to SEG6
COM3 to COM0
V3 to V0
P00/SIN0/INT4/SEG24
P01/SOT0/INT5/SEG25
P02/SCK0/INT6/SEG26
P03/SIN1/INT7/SEG27
P04/SOT1/SEG28
P05/SCK1/TRG/SEG29
P06/PPG0/TOT1/SEG30
P07/PPG1/TIN1/SEG31
P10/PPG2
P11/TOT0
P12/TIN0/IN3
P13/IN2
P14/IN1
P15/IN0
RAM 4 Kbytes*
ROM 64 Kbytes*
UART0/1
ICU0/1/2/3
PPG0/1/2
F2MC-16LX BUS
Clock control
circuit
CPU
F2MC-16LX core
Interrupt
controller
Sound generator
CAN controller
Prescaler
0/1
Reload timer
0/1
Real-time
watch timer
Free-run timer
External interrupt
(8 channels)
Port 8
Port 7
Port 6
Port 9
Port 4
Port 3
Port 5
Port 0
Port F
Stepping
motor
controller
0/1/2/3
A/D converter
(8 channels)
LCD controller/
driver
* : Evaluation device (MB90V925-101/102)
No built-in ROM
Built-in RAM is 6 Kbytes.
Port 2
P27 to P22/
SEG5 to SEG0
Prescaler (SIO)
SIO
Low voltage/
CPU operation
detection reset
MB90925 Series
18
■ MEMORY MAP
Note : To select models without the ROM mirror function, refer to the “ROM Mirror Function Selection Module” in
Hardware Manual. The image of the ROM data in the FF bank appears at the top of the 00 bank, in order
to enable efficient use of small C compiler models. The lower 16-bit address for the FF bank will be assigned
to the same address, so that tables in ROM can be referenced without declaring a “far” indication with the
pointer. For example when accessing the address 00C000H, the actual access is to address FFC000H in
ROM. Here the FF bank ROM area exceeds 48 Kbytes, so that it is not possible to see the entire area in the
00 bank image. Therefore because the ROM data from FF4000H to FFFFFFH will appear in the image from
004000H to 00FFFFH, it is recommended that the ROM data table be stored in the area from FF4000H to
FFFFFFH.
000000H
0000D0H
000100H
Address #2
Address #1
003900H
004000H
010000H
FFFFFFH
Single chip mode
(with ROM mirror function)
Peripheral area
ROM area
(FF bank image)
Register
ROM area
RAM area
Peripheral area
: Internal access memor
y
: Access prohibited
Part number Address #1 Address #2
MB90F927/MB90F927S FF0000H001100H
MB90V925-101/MB90V925-102 F80000H003700H
MB90925 Series
19
■I/O MAP
• Other than CAN Interface
(Continued)
Address Register name Symbol Read/write Resource name Initial value
000000HPort 0 data register PDR0 R/W Port 0 X X X X X X X XB
000001HPort 1 data register PDR1 R/W Port 1 - - XXX X XXB
000002HPort 2 data register PDR2 R/W Port 2 X X X X X X - -B
000003HPort 3 data register PDR3 R/W Port 3 X X X X X X X X B
000004HPort 4 data register PDR4 R/W Port 4 X X X X X X X X B
000005HPort 5 data register PDR5 R/W Port 5 X X X X X X X X B
000006HPort 6 data register PDR6 R/W Port 6 X X X X X X X X B
000007HPort 7 data register PDR7 R/W Port 7 X X X X X X X X B
000008HPort 8 data register PDR8 R/W Port 8 X X X X X X X X B
000009HPort 9 data register PDR9 R/W Port 9 - - - - X X X X B
00000AH
to
00000FH
(Disabled)
000010HPort 0 direction register DDR0 R/W Port 0 0 0 0 0 0 0 0 0B
000011HPort 1 direction register DDR1 R/W Port 1 - - 0 0 0 0 0 0B
000012HPort 2 direction register DDR2 R/W Port 2 0 0 0 0 0 0 - -B*
000013HPort 3 direction register DDR3 R/W Port 3 0 0 0 0 0 0 0 0B*
000014HPort 4 direction register DDR4 R/W Port 4 0 0 0 0 0 0 0 0B
000015HPort 5 direction register DDR5 R/W Port 5 0 0 0 0 0 0 0 0B
000016HPort 6 direction register DDR6 R/W Port 6 0 0 0 0 0 0 0 0B
000017HPort 7 direction register DDR7 R/W Port 7 0 0 0 0 0 0 0 0B
000018HPort 8 direction register DDR8 R/W Port 8 0 0 0 0 0 0 0 0B
000019HPort 9 direction register DDR9 R/W Port 9 - - - - 0 0 0 0B
00001AHAnalog input enable ADER R/W Port 6, A/D 1 1 1 1 1 1 1 1B
00001BH
to
00001FH
(Disabled)
000020HA/D control status register lower ADCS0 R/W
8/10-bit
A/D converter
0 0 0 - - - - 0B
000021HA/D control status register higher ADCS1 R/W 0 0 0 0 0 0 0 -B
000022HA/D data register lower ADCR0 R 0 0 0 0 0 0 0 0B
000023HA/D data register higher ADCR1 R - - - - - - 0 0B
000024HCompare clear register CPCLR R/W
16-bit free-run timer
XXXXXXXXB
000025HR/W XXXXXXXXB
000026HTimer data register TCDT R/W 0 0 0 0 0 0 0 0B
000027HR/W 0 0 0 0 0 0 0 0B
000028HTimer control status register lower TCCSL R/W 0 0 0 0 0 0 0 0B
000029HTimer control status register higher TCCSH R/W 0 1 - 0 0 0 0 0B
MB90925 Series
20
(Continued)
Address Register name Symbol Read/write Resource name Initial value
00002AHPPG0 control status register lower PCNTL0 R/W 16-bit PPG0 0 0 0 0 0 0 0 0B
00002BHPPG0 control status register higher PCNTH0 R/W 0 0 0 0 0 0 0 1B
00002CHPPG1 control status register lower PCNTL1 R/W 16-bit PPG1 0 0 0 0 0 0 0 0B
00002DHPPG1 control status register higher PCNTH1 R/W 0 0 0 0 0 0 0 1B
00002EHPPG2 control status register lower PCNTL2 R/W 16-bit PPG2 0 0 0 0 0 0 0 0B
00002FHPPG2 control status register higher PCNTH2 R/W 0 0 0 0 0 0 0 1B
000030HExternal interrupt enable ENIR R/W
External interrupt
0 0 0 0 0 0 0 0B
000031HExternal interrupt request EIRR R/W 0 0 0 0 0 0 0 0B
000032HExternal interrupt level lower ELVRL R/W 0 0 0 0 0 0 0 0B
000033HExternal interrupt level higher ELVRH R/W 0 0 0 0 0 0 0 0B
000034HSerial mode register 0 SMR0 R/W
UART(LIN/SCI) 0
0 0 0 0 0 0 0 0B
000035HSerial control register 0 SCR0 R/W 0 0 0 0 0 0 0 0B
000036HReception/transmission data
register 0
RDR0/
TDR0 R/W 0 0 0 0 0 0 0 0B
000037HSerial status register 0 SSR0 R/W 0 0 0 0 1 0 0 0B
000038HExtended communication control
register 0 ECCR0 R/W 0 0 0 0 0 0 X X B
000039HExtended status control register ESCR0 R/W 0 0 0 0 0 1 0 0B
00003AHBaud rate generator register 00 BGR00 R/W 0 0 0 0 0 0 0 0B
00003BHBaud rate generator register 01 BGR01 R/W 0 0 0 0 0 0 0 0B
00003CH,
00003DH (Disabled)
00003EHCAN wake-up control register CWUCR R/W CAN - - - - - - - 0B
00003FH (Disabled)
000040H
to
00004FH
Area reserved for CAN interface 0
000050HTimer control status register 0
lower TMCSR0L R/W
16-bit reload timer 0
0 0 0 0 0 0 0 0B
000051HTimer control status register 0
higher TMCSR0H R/W - - 1 0 0 0 0 0B
000052HTimer register 0/reload register 0 TMR0/
TMRLR0 R/W XXXXXXXXB
000053HXXXXXXXXB
000054HTimer control status register 1
lower TMCSR1L R/W
16-bit reload timer 1
0 0 0 0 0 0 0 0B
000055HTimer control status register 1
higher TMCSR1H R/W - - 1 0 0 0 0 0B
000056HTimer register 1/reload register 1 TMR1/
TMRLR1 R/W XXXXXXXXB
000057HXXXXXXXXB
MB90925 Series
21
(Continued)
Address Register name Symbol Read/write Resource name Initial value
000058HLCD output control register 1 LOCR1 R/W LCD 1 1 1 1 1 1 1 1B
000059HLCD output control register 2 LOCR2 R/W 0 0 0 0 0 0 0 0B
00005AHSound control register lower SGCRL R/W
Sound generator
0 0 0 0 0 0 0 0B
00005BHSound control register higher SGCRH R/W 0 - - - - 1 0 0B
00005CHFrequency data register SGFR R/W X X X X X X X X B
00005DHAmplitude data register SGAR R/W 0 0 0 0 0 0 0 0B
00005EHDecrement grade register SGDR R/W XX X X X X X X B
00005FHTone count register SGTR R/W X X X X X X X X B
000060HInput capture register 0 IPCP0 R
Input capture 0/1
XXXXXXXXB
000061HXXXXXXXXB
000062HInput capture register 1 IPCP1 R XXXXXXXXB
000063HXXXXXXXXB
000064HInput capture register 2 IPCP2 R
Input capture 2/3
XXXXXXXXB
000065HXXXXXXXXB
000066HInput capture register 3 IPCP3 R XXXXXXXXB
000067HXXXXXXXXB
000068HInput capture control status 0/1 ICS01 R/W Input capture 0/1 0 0 0 0 0 0 0 0B
000069HInput capture edge register 0/1 ICE01 R/W Input capture 0/1 X X X 0 X 0 X X B
00006AHInput capture control status 2/3 ICS23 R/W Input capture 2/3 0 0 0 0 0 0 0 0B
00006BHInput capture edge register 2/3 ICE23 R/W Input capture 2/3 X X X X X X X X B
00006CHLCD control register lower LCRL R/W LCD controller/
driver
0 0 0 1 0 0 0 0B
00006DHLCD control register higher LCRH R/W 0 0 0 0 0 0 0 0B
00006EHLow voltage/CPU operation
detection reset control register LVRC R/W Low voltage/CPU opera-
tion detection reset 0 0 1 1 1 0 0 0B
00006FHROM mirror ROMM W ROM mirror XXXXXXX1B
000070H
to
00007FH
(Disabled)
000080HPWM control register 0 PWC0 R/W Stepping motor
controller 0 0 0 0 0 0 - - 0B
000081H (Disabled)
000082HPWM control register 1 PWC1 R/W Stepping motor
controller 1 0 0 0 0 0 - - 0B
000083H (Disabled)
000084HPWM control register 2 PWC2 R/W Stepping motor
controller 2 0 0 0 0 0 - - 0B
000085H (Disabled)
000086HPWM control register 3 PWC3 R/W Stepping motor
controller 3 0 0 0 0 0 - - 0B
MB90925 Series
22
(Continued)
Address Register name Symbol Read/write Resource name Initial value
000087H
to
000089H
(Disabled)
00008AHA/D setting register 0 ADSR0 R/W A/D 0 0 0 0 0 0 0 0B
00008BHA/D setting register 1 ADSR1 R/W 0 0 0 0 0 0 0 0B
00008CHPort input level select 0 PIL0 R/W Port Input Level Select 0 0 0 0 0 0 0 0B
00008DHPort input level select 1 PIL1 R/W - - - 0 0 0 0 0B
00008EH
to
00009DH
(Disabled)
00009EHROM correction control register PACSR R/W Address match
detection function - - - - - 0 - 0B
00009FHDelay interrupt/release DIRR R/W Delay interrupt - - - - - - - 0B
0000A0HPower saving mode LPMCR R/W Power saving
control circuit
0 0 0 1 1 0 0 0B
0000A1HClock select CKSCR R/W 1 1 1 1 1 1 0 0B
0000A2H
to
0000A7H
(Disabled)
0000A8HWatchdog control WDTC R/W Watchdog timer X X X X X 1 1 1B
0000A9HTime-base timer control regis-
ter TBTC R/W Time-base timer 1 - - 0 0 1 0 0B
0000AAHWatch timer control register WTC R/W Watch timer
(sub clock) 1 X 0 0 0 0 0 0B
0000ABH
to
0000ADH
(Disabled)
0000AEHFlash control register FMCS R/W Flash memory interface 0 0 0 X 0 XX 0B
0000AFH (Disabled)
0000B0HInterrupt control register 00 ICR00 R/W
Interrupt controller
0 0 0 0 0 1 1 1B
0000B1HInterrupt control register 01 ICR01 R/W 0 0 0 0 0 1 1 1B
0000B2HInterrupt control register 02 ICR02 R/W 0 0 0 0 0 1 1 1B
0000B3HInterrupt control register 03 ICR03 R/W 0 0 0 0 0 1 1 1B
0000B4HInterrupt control register 04 ICR04 R/W 0 0 0 0 0 1 1 1B
0000B5HInterrupt control register 05 ICR05 R/W
Interrupt controller
0 0 0 0 0 1 1 1B
0000B6HInterrupt control register 06 ICR06 R/W 0 0 0 0 0 1 1 1B
0000B7HInterrupt control register 07 ICR07 R/W 0 0 0 0 0 1 1 1B
0000B8HInterrupt control register 08 ICR08 R/W 0 0 0 0 0 1 1 1B
0000B9HInterrupt control register 09 ICR09 R/W 0 0 0 0 0 1 1 1B
0000BAHInterrupt control register 10 ICR10 R/W 0 0 0 0 0 1 1 1B
0000BBHInterrupt control register 11 ICR11 R/W 0 0 0 0 0 1 1 1B
0000BCHInterrupt control register 12 ICR12 R/W 0 0 0 0 0 1 1 1B
MB90925 Series
23
(Continued)
Address Register name Symbol Read/write Resource name Initial value
0000BDHInterrupt control register 13 ICR13 R/W
Interrupt controller
0 0 0 0 0 1 1 1B
0000BEHInterrupt control register 14 ICR14 R/W 0 0 0 0 0 1 1 1B
0000BFHInterrupt control register 15 ICR15 R/W 0 0 0 0 0 1 1 1B
0000C0HSerial mode control register (lower) SMCSL R/W
SIO
- - - - 0 0 0 0B
0000C1HSerial mode control register (higher) SMCSH R/W 0 0 0 0 0 0 1 0B
0000C2HSerial data register SDR R/W X X X X X X X X B
0000C3HCommunication prescaler
control register SDCR R/W Communication
prescaler (SIO) 0 - - - 0 0 0 0B
0000C4HSerial mode register 1 SMR1 R/W
UART(LIN/SCI) 1
0 0 0 0 0 0 0 0B
0000C5HSerial control register 1 SCR1 R/W 0 0 0 0 0 0 0 0B
0000C6HReception/transmission
data register 1
RDR1/
TDR1 R/W 0 0 0 0 0 0 0 0B
0000C7HSerial status register 1 SSR1 R/W 0 0 0 0 1 0 0 0B
0000C8HExtended communication
control register 1 ECCR1 R/W 0 0 0 0 0 0 X X B
0000C9HExtended status control register 1 ESCR1 R/W 0 0 0 0 0 1 0 0B
0000CAHBaud rate generator register 10 BGR10 R/W 0 0 0 0 0 0 0 0B
0000CBHBaud rate generator register 11 BGR11 R/W 0 0 0 0 0 0 0 0B
0000CCHWatch timer control register lower WTCRL R/W
Real-time
watch timer
0 0 0 - - 0 0 0B
0000CDHWatch timer control register middle WTCRM R/W 0 0 0 0 0 0 0 0B
0000CEHWatch timer control register higher WTCRH R/W - - - - 0 0 0 0B
0000CFHSub clock control register SCCR W Sub clock - - - - 0 0 0 0B
0000D0H
to
0000FFH
(Disabled)
001FF0HROM correction address 0 PADR0 R/W
Address match
detection function
XXXXXXXXB
001FF1HROM correction address 1 PADR0 R/W X X X X X X X X B
001FF2HROM correction address 2 PADR0 R/W X X X X X X X X B
001FF3HROM correction address 3 PADR1 R/W
Address match
detection function
XXXXXXXXB
001FF4HROM correction address 4 PADR1 R/W X X X X X X X X B
001FF5HROM correction address 5 PADR1 R/W X X X X X X X X B
003900H
to
00391FH
(Disabled)
003920HPPG0 down counter register PDCR0 R
16-bit PPG 0
1 1 1 1 1 1 1 1B
003921H1 1 1 1 1 1 1 1B
003922HPPG0 cycle setting register PCSR0 W XXXXXXXXB
003923HXXXXXXXXB
003924HPPG0 duty setting register PDUT0 W XXXXXXXXB
003925HXXXXXXXXB
MB90925 Series
24
(Continued)
Address Register name Symbol Read/write Resource name Initial value
003926H,
003927H (Disabled)
003928HPPG1 down counter register PDCR1 R
16-bit PPG 1
1 1 1 1 1 1 1 1B
003929H1 1 1 1 1 1 1 1B
00392AHPPG1 cycle setting register PCSR1 W XXXXXXXXB
00392BHXXXXXXXXB
00392CHPPG1 duty setting register PDUT1 W XXXXXXXXB
00392DHXXXXXXXXB
00392EH,
00392FH (Disabled)
003930HPPG2 down counter register PDCR2 R
16-bit PPG 2
1 1 1 1 1 1 1 1B
003931H1 1 1 1 1 1 1 1B
003932HPPG2 cycle setting register PCSR2 W XXXXXXXXB
003933HXXXXXXXXB
003934HPPG2 duty setting register PDUT2 W XXXXXXXXB
003935HXXXXXXXXB
003936H
to
003957H
(Disabled)
003958H
Sub second data register WTBR R/W
Real time
watch timer
XXXXXXXXB
003959HXXXXXXXXB
00395AH- - - XXXXXB
00395BHSecond data register WTSR R/W - - 0 0 0 0 0 0B
00395CHMinute data register WTMR R/W - - 0 0 0 0 0 0B
00395DHHour data register WTHR R/W - - - 0 0 0 0 0B
00395EHDay data register WTDR R/W 0 0 - 0 0 0 0 1B
00395FH(Disabled)
003960H
to
00396FH
LCD display RAM VRAM R/W LCD controller/
driver XXXXXXXXB
003970H
to
00397FH
(Disabled)
003980HPWM1 compare register 0 PWC10 R/W
Stepping motor
controller 0
XXXXXXXXB
003981H- - - - - - XXB
003982HPWM2 compare register 0 PWC20 R/W XXXXXXXXB
003983H- - - - - - XXB
003984HPWM1 select register 0 PWS10 R/W - - 0 0 0 0 0 0B
003985HPWM2 select register 0 PWS20 R/W - 0 0 0 0 0 0 0B
MB90925 Series
25
(Continued)
Address Register name Symbol Read/write Resource name Initial value
003986H,
003987H (Disabled)
003988HPWM1 compare register 1 PWC11 R/W
Stepping motor
controller 1
XXXXXXXXB
003989H- - - - - - XXB
00398AHPWM2 compare register 1 PWC21 R/W XXXXXXXXB
00398BH- - - - - - XXB
00398CHPWM1 select register 1 PWS11 R/W - - 0 0 0 0 0 0B
00398DHPWM2 select register 1 PWS21 R/W - 0 0 0 0 0 0 0B
00398EH,
00398FH (Disabled)
003990HPWM1 compare register 2 PWC12 R/W
Stepping motor
controller 2
XXXXXXXXB
003991H- - - - - - XXB
003992HPWM2 compare register 2 PWC22 R/W XXXXXXXXB
003993H- - - - - - XXB
003994HPWM1 select register 2 PWS12 R/W - - 0 0 0 0 0 0B
003995HPWM2 select register 2 PWS22 R/W - 0 0 0 0 0 0 0B
003996H,
003997H (Disabled)
003998HPWM1 compare register 3 PWC13 R/W
Stepping motor
controller 3
XXXXXXXXB
003999H- - - - - - XXB
00399AHPWM2 compare register 3 PWC23 R/W XXXXXXXXB
00399BH- - - - - - XXB
00399CHPWM1 select register 3 PWS13 R/W - - 0 0 0 0 0 0B
00399DHPWM2 select register 3 PWS23 R/W - 0 0 0 0 0 0 0B
00399EH
to
0039FFH
(Disabled)
003A00H
to
003AFFH
Area reserved for CAN interface 0
003B00H
to
003BFFH
(Disabled)
003C00H
to
003CFFH
Area reserved for CAN interface 0
003D00H
to
003EFFH
(Disabled)
MB90925 Series
26
(Continued)
• Initial value symbols :
“0” : initial value 0
“1” : initial value 1
“X” : initial value undetermined
“-” : initial value undetermined (none)
• Write/read symbols :
“R/W” : read/write enabled
“R” : read only
“W” : write only
• Addresses in the area 0000H to 00FFH are reserved for the principal functions of the MCU. Read access
attempts to reserved areas will result in an “X” value. Also, write access to reserved areas is prohibited.
* : P22/SEG0 to P27/SEG5 and P30/SEG6 to P35/SEG11 initially will be LCD segment output as LCD output
control register LOCR1 (58H) is “11111111B” initially. To use port 2 and port 3 as the general-purpose input/
output ports, set LOCR1 to “00000000B” to disable the LCD segment output first.
MB90925 Series
27
• CAN Interface
(Continued)
Address Register name Symbol Read/
write Initial value
000040HMessage buffer valid area BVALR R/W 0 0 0 0 0 0 0 0B
000041H0 0 0 0 0 0 0 0B
000042HTransmission request register TREQR R/W 0 0 0 0 0 0 0 0B
000043H0 0 0 0 0 0 0 0B
000044HTransmission cancel register TCANR W 0 0 0 0 0 0 0 0B
000045H0 0 0 0 0 0 0 0B
000046HTransmission completed register TCR R/W 0 0 0 0 0 0 0 0B
000047H0 0 0 0 0 0 0 0B
000048HReceiving completed register RCR R/W 0 0 0 0 0 0 0 0B
000049H0 0 0 0 0 0 0 0B
00004AHRemote request receiving register RRTRR R/W 0 0 0 0 0 0 0 0B
00004BH0 0 0 0 0 0 0 0B
00004CHReceiving overrun register ROVRR R/W 0 0 0 0 0 0 0 0B
00004DH0 0 0 0 0 0 0 0B
00004EHReceiving interrupt enable register RIER R/W 0 0 0 0 0 0 0 0B
00004FH0 0 0 0 0 0 0 0B
003C00HControl status register CSR R/W, R 0 0 - - - 0 0 0B
003C01H0 - - - - 0 - 1B
003C02HLast event indicator register LEIR R/W - - - - - - - -B
003C03H0 0 0 - 0 0 0 0B
003C04HRX/TX error counter RTEC R 0 0 0 0 0 0 0 0B
003C05H0 0 0 0 0 0 0 0B
003C06HBit timing register BTR R/W - 1 1 1 1 1 1 1B
003C07H1 1 1 1 1 1 1 1B
003C08HIDE register IDER R/W XXXXXXXXB
003C09HXXXXXXXXB
003C0AHTransmission RTR register TRTRR R/W 0 0 0 0 0 0 0 0B
003C0BH0 0 0 0 0 0 0 0B
003C0CHRemote frame receiving wait register RFWTR R/W XXXXXXXXB
003C0DHXXXXXXXXB
003C0EHTransmission interrupt enable register TIER R/W 0 0 0 0 0 0 0 0B
003C0FH0 0 0 0 0 0 0 0B
MB90925 Series
28
(Continued)
Address Register name Symbol Read/
write Initial value
003C10H
Acceptance mask select register AMSR R/W
XXXXXXXXB
003C11HXXXXXXXXB
003C12HXXXXXXXXB
003C13HXXXXXXXXB
003C14H
Acceptance mask register 0 AMR0 R/W
XXXXXXXXB
003C15HXXXXXXXXB
003C16HXXXXX- - -B
003C17HXXXXXXXXB
003C18H
Acceptance mask register 1 AMR1 R/W
XXXXXXXXB
003C19HXXXXXXXXB
003C1AHXXXXX- - -B
003C1BHXXXXXXXXB
003A00H
to
003A1FH
General-purpose RAM ⎯R/W
XXXXXXXXB
to
XXXXXXXXB
003A20H
ID register 0 IDR0 R/W
XXXXXXXXB
003A21HXXXXXXXXB
003A22HXXXXX- - -B
003A23HXXXXXXXXB
003A24H
ID register 1 IDR1 R/W
XXXXXXXXB
003A25HXXXXXXXXB
003A26HXXXXX- - -B
003A27HXXXXXXXXB
003A28H
ID register 2 IDR2 R/W
XXXXXXXXB
003A29HXXXXXXXXB
003A2AHXXXXX- - -B
003A2BHXXXXXXXXB
003A2CH
ID register 3 IDR3 R/W
XXXXXXXXB
003A2DHXXXXXXXXB
003A2EHXXXXX- - -B
003A2FHXXXXXXXXB
003A30H
ID register 4 IDR4 R/W
XXXXXXXXB
003A31HXXXXXXXXB
003A32HXXXXX- - -B
003A33HXXXXXXXXB
MB90925 Series
29
(Continued)
Address Register name Symbol Read/
write Initial value
003A34H
ID register 5 IDR5 R/W
XXXXXXXXB
003A35HXXXXXXXXB
003A36HXXXXX- - -B
003A37HXXXXXXXXB
003A38H
ID register 6 IDR6 R/W
XXXXXXXXB
003A39HXXXXXXXXB
003A3AHXXXXX- - -B
003A3BHXXXXXXXXB
003A3CH
ID register 7 IDR7 R/W
XXXXXXXXB
003A3DHXXXXXXXXB
003A3EHXXXXX- - -B
003A3FHXXXXXXXXB
003A40H
ID register 8 IDR8 R/W
XXXXXXXXB
003A41HXXXXXXXXB
003A42HXXXXX- - -B
003A43HXXXXXXXXB
003A44H
ID register 9 IDR9 R/W
XXXXXXXXB
003A45HXXXXXXXXB
003A46HXXXXX- - -B
003A47HXXXXXXXXB
003A48H
ID register 10 IDR10 R/W
XXXXXXXXB
003A49HXXXXXXXXB
003A4AHXXXXX- - -B
003A4BHXXXXXXXXB
003A4CH
ID register 11 IDR11 R/W
XXXXXXXXB
003A4DHXXXXXXXXB
003A4EHXXXXX- - -B
003A4FHXXXXXXXXB
003A50H
ID register 12 IDR12 R/W
XXXXXXXXB
003A51HXXXXXXXXB
003A52HXXXXX- - -B
003A53HXXXXXXXXB
MB90925 Series
30
(Continued)
Address Register name Symbol Read/
write Initial value
003A54H
ID register 13 IDR13 R/W
XXXXXXXXB
003A55HXXXXXXXXB
003A56HXXXXX- - -B
003A57HXXXXXXXXB
003A58H
ID register 14 IDR14 R/W
XXXXXXXXB
003A59HXXXXXXXXB
003A5AHXXXXX- - -B
003A5BHXXXXXXXXB
003A5CH
ID register 15 IDR15 R/W
XXXXXXXXB
003A5DHXXXXXXXXB
003A5EHXXXXX- - -B
003A5FHXXXXXXXXB
003A60HDLC register 0 DLCR0 R/W - - - -XXXXB
003A61H- - - -XXXXB
003A62HDLC register 1 DLCR1 R/W - - - -XXXXB
003A63H- - - -XXXXB
003A64HDLC register 2 DLCR2 R/W - - - -XXXXB
003A65H- - - -XXXXB
003A66HDLC register 3 DLCR3 R/W - - - -XXXXB
003A67H- - - -XXXXB
003A68HDLC register 4 DLCR4 R/W - - - -XXXXB
003A69H- - - -XXXXB
003A6AHDLC register 5 DLCR5 R/W - - - -XXXXB
003A6BH- - - -XXXXB
003A6CHDLC register 6 DLCR6 R/W - - - -XXXXB
003A6DH- - - -XXXXB
003A6EHDLC register 7 DLCR7 R/W - - - -XXXXB
003A6FH- - - -XXXXB
003A70HDLC register 8 DLCR8 R/W - - - -XXXXB
003A71H- - - -XXXXB
003A72HDLC register 9 DLCR9 R/W - - - -XXXXB
003A73H- - - -XXXXB
003A74HDLC register 10 DLCR10 R/W - - - -XXXXB
003A75H- - - -XXXXB
MB90925 Series
31
(Continued)
Address Register name Symbol Read/
write Initial value
003A76HDLC register 11 DLCR11 R/W - - - -XXXXB
003A77H- - - -XXXXB
003A78HDLC register 12 DLCR12 R/W - - - -XXXXB
003A79H- - - -XXXXB
003A7AHDLC register 13 DLCR13 R/W - - - -XXXXB
003A7BH- - - -XXXXB
003A7CHDLC register 14 DLCR14 R/W - - - -XXXXB
003A7DH- - - -XXXXB
003A7EHDLC register 15 DLCR15 R/W - - - -XXXXB
003A7FH- - - -XXXXB
003A80H
to
003A87H
Data register 0 (8 bytes) DTR0 R/W
XXXXXXXXB
to
XXXXXXXXB
003A88H
to
003A8FH
Data register 1 (8 bytes) DTR1 R/W
XXXXXXXXB
to
XXXXXXXXB
003A90H
to
003A97H
Data register 2 (8 bytes) DTR2 R/W
XXXXXXXXB
to
XXXXXXXXB
003A98H
to
003A9FH
Data register 3 (8 bytes) DTR3 R/W
XXXXXXXXB
to
XXXXXXXXB
003AA0H
to
003AA7H
Data register 4 (8 bytes) DTR4 R/W
XXXXXXXXB
to
XXXXXXXXB
003AA8H
to
003AAFH
Data register 5 (8 bytes) DTR5 R/W
XXXXXXXXB
to
XXXXXXXXB
003AB0H
to
003AB7H
Data register 6 (8 bytes) DTR6 R/W
XXXXXXXXB
to
XXXXXXXXB
003AB8H
to
003ABFH
Data register 7 (8 bytes) DTR7 R/W
XXXXXXXXB
to
XXXXXXXXB
003AC0H
to
003AC7H
Data register 8 (8 bytes) DTR8 R/W
XXXXXXXXB
to
XXXXXXXXB
003AC8H
to
003ACFH
Data register 9 (8 bytes) DTR9 R/W
XXXXXXXXB
to
XXXXXXXXB
MB90925 Series
32
(Continued)
Address Register name Symbol Read/
write Initial value
003AD0H
to
003AD7H
Data register 10 (8 bytes) DTR10 R/W
XXXXXXXXB
to
XXXXXXXXB
003AD8H
to
003ADFH
Data register 11 (8 bytes) DTR11 R/W
XXXXXXXXB
to
XXXXXXXXB
003AE0H
to
003AE7H
Data register 12 (8 bytes) DTR12 R/W
XXXXXXXXB
to
XXXXXXXXB
003AE8H
to
003AEFH
Data register 13 (8 bytes) DTR13 R/W
XXXXXXXXB
to
XXXXXXXXB
003AF0H
to
003AF7H
Data register 14 (8 bytes) DTR14 R/W
XXXXXXXXB
to
XXXXXXXXB
003AF8H
to
003AFFH
Data register 15 (8 bytes) DTR15 R/W
XXXXXXXXB
to
XXXXXXXXB
MB90925 Series
33
■INTERRUPT SOURCES, INTERRUPT VECTORS, AND INTERRUPT CONTROL REGISTERS
(Continued)
Interrupt source
EI2OS
corre-
sponding
Interrupt vector Interrupt control register Priority
*2
Number Address ICR Address
Reset × #08 08HFFFFDCH⎯⎯High
INT9 instruction × #09 09HFFFFD8H⎯⎯
Exception processing × #10 0AHFFFFD4H⎯⎯
CAN0 RX × #11 0BHFFFFD0HICR00 0000B0H *1
CAN0 TX/NS × #12 0CHFFFFCCH
( Reserved) *3 × #13 0DHFFFFC8HICR01 0000B1H *1
SIO *3 #14 0EHFFFFC4H
Input capture 0 #15 0FHFFFFC0HICR02 0000B2H *1
DTP/external interrupt - ch.0 detected #16 10HFFFFBCH
Reload timer 0 #17 11HFFFFB8HICR03 0000B3H *1
DTP/external interrupt - ch.1 detected #18 12HFFFFB4H
Input capture 1 #19 13HFFFFB0HICR04 0000B4H *1
DTP/external interrupt - ch.2 detected #20 14HFFFFACH
Input capture 2 #21 15HFFFFA8HICR05 0000B5H *1
DTP/external interrupt - ch.3 detected #22 16HFFFFA4H
Input capture 3 #23 17HFFFFA0H
ICR06 0000B6H *1
DTP/external interrupt - ch.4/ch.5
detected #24 18HFFFF9CH
PPG timer 0 #25 19HFFFF98H
ICR07 0000B7H *1
DTP/external interrupt - ch.6/ch.7
detected #26 1AHFFFF94H
PPG timer 1 #27 1BHFFFF90HICR08 0000B8H *1
Reload timer 1 #28 1CHFFFF8CH
PPG timer 2 #29 1DHFFFF88HICR09 0000B9H *1
Real time watch timer × #30 1EHFFFF84H
Free-run timer overflow × #31 1FHFFFF80HICR10 0000BAH *1
A/D converter conversion end #32 20HFFFF7CH
Free-run timer clear × #33 21HFFFF78HICR11 0000BBH *1
Sound generator × #34 22HFFFF74H
Time-base timer × #35 23HFFFF70HICR12 0000BCH *1
Watchdog (sub clock) × #36 24HFFFF6CH
UART 1 RX #37 25HFFFF68HICR13 0000BDH *1
UART 1 TX #38 26HFFFF64H
UART 0 RX #39 27HFFFF60HICR14 0000BEH *1
UART 0 TX #40 28HFFFF5CH
Flash memory status × #41 29HFFFF58HICR15 0000BFH *1
Delay interrupt generator module × #42 2AHFFFF54HLow
MB90925 Series
34
(Continued)
: Usable, with EI2OS stop function
: Usable
: Usable when interrupt sources sharing ICR are not in use
× : Unusable
*1 : • Peripheral functions sharing the ICR register have the same interrupt level.
• If peripheral functions sharing the ICR register are using expanded intelligent I/O services, one or the other
cannot be used.
• When peripheral functions are sharing the ICR register and one specifies expanded intelligent I/O services,
the interrupt from the other function cannot be used.
*2 : Priority applies when interrupts of the same level are generated.
*3 : SIO and CAN1 TX/NX will share IRQ3 in evaluation chip (MB90V925-101/102) .
MB90925 Series
35
■ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
*1 : The parameter is based on VSS = AVSS = DVSS = 0.0 V.
*2 : AVCC, AVRH and DVCC shall never exceed VCC.
Also, AVRH shall never exceed AVCC.
*3 : The maximum current to/from and input are limited by some means with external components, the ICLAMP rating
supersedes the VI rating.
*4 : Maximum output current is defined as the peak value of the current of any one of the corresponding pins.
*5 : Average output current is defined as the value of the average current flowing over 100 ms at any one of the
corresponding pins. The “average value” can be calculated from the formula of “operating current” times
“operating factor”.
(Continued)
Parameter Symbol Rating Unit Remarks
Min Max
Power supply voltage*1
VCC VSS − 0.3 VSS + 6.0 V
AVCC VSS − 0.3 VSS + 6.0 V AVCC = VCC*2
AVRH VSS − 0.3 VSS + 6.0 V AVCC ≥ AVRH*2
DVCC VSS − 0.3 VSS + 6.0 V DVCC = VCC*2
Input voltage*1VIVSS − 0.3 VCC + 0.3 V *3
Output voltage*1VOVSS − 0.3 VCC + 0.3 V
Maximum clamp current ICLAMP − 400 + 400 µA*7
Total maximum clamp current Σ| ICLAMP |⎯4mA*7
“L” level maximum
output current*4
IOL1 ⎯15 mA Other than P70 to P77 and P80 to P87
IOL2 ⎯40 mA P70 to 77 and P80 to87
“L” level average output
current*5
IOLAV1 ⎯4 mA Other than P70 to P77 and P80 to P87
IOLAV2 ⎯30 mA P70 to 77 and P80 to 87
“L” level maximum
total output current
ΣIOL1 ⎯100 mA Other than P70 to P77 and P80 to P87
ΣIOL2 ⎯330 mA P70 to 77 and P80 to 87
“L” level average total
output current
ΣIOLAV1 ⎯50 mA Other than P70 to P77 and P80 to P87
ΣIOLAV2 ⎯250 mA P70 to 77 and P80 to 87
“H” level maximum
output current
IOH1*4⎯−15 mA Other than P70 to P77 and P80 to P87
IOH2*4⎯−40 mA P70 to 77 and P80 to 87
“H” level average
output current
IOHAV1*5⎯−4 mA Other than P70 to P77 and P80 to P87
IOHAV2*5⎯−30 mA P70 to 77 and P80 to 87
“H” level maximum
total output current
ΣIOH1 ⎯−100 mA Other than P70 to P77 and P80 to P87
ΣIOH2 ⎯−330 mA P70 to 77 and P80 to 87
“H” level average total
output current
ΣIOHAV1*6⎯−50 mA Other than P70 to P77 and P80 to P87
ΣIOHAV2*6⎯−250 mA P70 to 77 and P80 to 87
Power consumption PD⎯500 mW
Operating temperature TA−40 +105 °C
Storage temperature TSTG −55 +150 °C
MB90925 Series
36
(Continued)
*6 : Average total output current is defined as the value of the average current flowing over 100 ms at all of the
corresponding pins. The “average value” can be calculated from the formula of “operating current” times
“ operating factor”.
*7 : • Applicable to pins : P10 to P15, P50 to P57, P70 to P77, P80 to P87
• Use within recommended operating conditions.
• Use at DC voltage (current) .
• The +B signal should always be applied with a limiting resistance placed between the +B signal and the
microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied, the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that when the microcontroller drive current is low, such as in the power saving modes, the +B input
potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect
other devices.
• Note that if a +B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power
supply is provided from the pins, so that incomplete operation may result.
• Note that if the +B input is applied during power-on, the power supply is provided from the pins and the
resulting power supply voltage may not be sufficient to operate the power-on reset.
• Care must be taken not to leave the +B input pin open.
• Note that analog system input/output pins (LCD drive pins, comparator input pins, etc.) cannot accept +B
signal input.
• Sample recommended circuits :
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
P-ch
N-ch
VCC
R
+B input (0 V to 16 V)
Limiting
resistance
Protective diode
• Input/Output equivalent circuits
MB90925 Series
37
2. Recommended Operating Conditions
(VSS = DVSS = AVSS = 0.0 V)
* : For smoothing capacitor Cs connections, refer to the illustration below.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
Parameter Symbol Value Unit Remarks
Min Max
Power supply
voltage
VCC
AVCC
DVCC
3.7 5.5 V
(MB90F927/MB90F927S)
Low voltage detection reset starts to work when power
supply voltage is 4.0 V ± 0.3 V.
4.3 5.5 V Holding stop operation status
(MB90F927/MB90F927S)
Smoothing
capacitor* CS0.1 1.0 µF
Use a ceramic capacitor or other capacitor of equivalent
frequency characteristics. A bypass capacitor on the VCC pin
should have a capacitance greater than Cs.
Operating
temperature TA − 40 + 105 °C
C
CSVSS DVSS AVSS
• C pin connection diagram
MB90925 Series
38
3. DC Characteristics
(VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
(Continued)
Parameter Symbol Pin
name Conditions Value Unit Remarks
Min Typ Max
“H” level
input voltage
VIHA ⎯⎯0.8 VCC ⎯VCC + 0.3 V
Pin inputs if
Automotive input
levels are selected*1
VIHS2 ⎯⎯0.8 VCC ⎯VCC + 0.3 V
Pin inputs if CMOS
hysteresis input
levels are selected*1
(0.8Vcc/0.2Vcc
CMOS hysteresis is
selected for P00,
P03 and P51)
VIHS1 ⎯⎯0.7 VCC ⎯VCC + 0.3 V
Pin inputs if 0.7Vcc/
0.3Vcc CMOS hys-
teresis input levels is
selected for P00,
P03 and P51.
VIHR ⎯⎯0.8 VCC ⎯VCC + 0.3 VRST input pin
(CMOS hysteresis)
VIHM ⎯ ⎯VCC − 0.3 ⎯VCC + 0.3 V MD pin*2
“L” level
input voltage
VILA ⎯⎯VSS − 0.3 ⎯0.5 VCC V
Pin inputs if
Automotive input
levels are selected*1
VILS2 ⎯⎯VSS − 0.3 ⎯0.2 VCC V
Pin inputs if CMOS
hysteresis input
levels are selected*1
(0.8Vcc/0.2Vcc
CMOS hysteresis is
selected for P00,
P03 and P51)
VILS1 ⎯⎯VSS − 0.3 ⎯0.3 VCC V
Pin inputs if 0.7Vcc/
0.3Vcc CMOS hys-
teresis input levels is
selected for P00,
P03 and P51.
VILR ⎯⎯VSS − 0.3 ⎯0.2 VCC VRST input pin
(CMOS hysteresis)
VILM ⎯⎯VSS − 0.3 ⎯VSS + 0.3 V MD pin*2
MB90925 Series
39
(VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
(Continued)
Parameter Symbol Pin name Conditions Value Unit Remarks
Min Typ Max
Power supply
current*3
ICC
VCC
Operating frequency
FCP = 16 MHz,
normal operation
⎯35 45 mA
Operating frequency
FCP = 16 MHz,
writing Flash memory
⎯50 60 mA
Flash
memory
product
Operating frequency
FCP = 16 MHz,
erasing Flash memory
⎯50 60 mA
ICCS
Operating frequency
FCP = 16 MHz,
sleep mode
⎯12 20 mA
ICTS
Operating frequency
FCP = 2 MHz,
time-base timer mode
⎯0.4 1.0 mA
ICTSPLL
Operating frequency
FCP = 16 MHz,
PLL timer mode,
External frequency = 4MHz
⎯47mA
ICCL
Operating frequency
FCP = 8 kHz, TA = + 25 °C,
sub clock operation
⎯90 200 µA
ICCLS
Operating frequency
FCP = 8 kHz, TA = + 25 °C,
sub sleep operation ⎯60 150 µA
ICCT
Operating frequency
FCP = 8 kHz, TA = + 25 °C,
watch mode
⎯60 130 µA
ICCH TA = + 25 °C,
stop mode ⎯50 130 µA
Input leakage
current IIL All input pins VCC = DVCC = AVCC = 5.5 V
VSS < VI < VCC −5⎯+5µA
Input
capacitance 1 CIN1
Other than
VCC, VSS,
DVCC, DVSS,
AVCC, AVSS, C,
P70 to P77,
P80 to P87
⎯⎯515pF
MB90925 Series
40
(Continued)
(VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
*1 : All input pins except X0, X0A, MD0, MD1, and MD2.
*2 : MD0, MD1, and MD2 pins.
*3 : Power supply current values assume external clock feed from the X1 pin and X1A pin. Users must be aware
that power supply current levels differ depending on whether an external clock or oscillator is used.
*4 : Defined as maximum variation in VOH2/VOL2 with all ch.0 PWM1P0/PWM1M0/PWM2P0/PWM2M0 simultaneously
ON. Similarly for other channels.
Parameter Symbol Pin name Conditions Value Unit Remarks
Min Typ Max
Input capacitance 2 CIN2 P70 to P77,
P80 to P87 ⎯⎯15 45 pF
Pull-up resistance RUP RST ⎯25 50 100 kΩ
Pull-down resistance RDOWN MD2 ⎯25 50 100 kΩExcept Flash
memory product
Output “H”
voltage 1 VOH1
Other than
P70 to P77,
P80 to P87
VCC = 4.5 V
IOH = −4.0 mA
VCC −
0.5 ⎯⎯V
Output “H”
voltage 2 VOH2 P70 to P77,
P80 to P87
VCC = 4.5 V
IOH = −30.0 mA
VCC −
0.5 ⎯⎯V
Output “L”
voltage 1 VOL1
Other than
P70 to P77,
P80 to P87
VCC = 4.5 V
IOL = 4.0 mA ⎯⎯0.4 V
Output “L”
voltage 2 VOL2 P70 to P77,
P80 to P87
VCC = 4.5 V
IOL = 30.0 mA ⎯⎯0.55 V
Large current
output drive
capacity variation 1
∆VOH2
PWM1Pn,
PWM1Mn,
PWM2Pn,
PWM2Mn,
(n = 0 to 3)
VCC = 4.5 V
IOH = 30.0 mA
VOH2 maximum
variation
0⎯90 mV *4
Large current
output drive
capacity variation 2
∆VOL2
PWM1Pn,
PWM1Mn,
PWM2Pn,
PWM2Mn,
(n = 0 to 3)
VCC = 4.5 V
IOH = 30.0 mA
VOL2 maximum
variation
0⎯90 mV *4
LCD internal divider
resistance RLCD V0 to V3 ⎯50 100 200 kΩ
COM0 to COM3
output impedance RVCOM COMn
(n = 0 to 3) ⎯⎯⎯2.5 kΩ
SEG0 to SEG31
output impedance RVSEG SEGn
(n = 0 to 31) ⎯⎯⎯15 kΩ
LCD leakage
current ILCDC
V0 to V3
COMm
(m = 0 to 3)
SEGn
(n = 0 to 31)
⎯−5.0 ⎯+5.0 µA
MB90925 Series
41
4. AC Characteristics
(1) Clock timing
(VCC = 5.0 V±10%, VSS = DVSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin name Condi-
tions
Value Unit Remarks
Min Typ Max
Base oscillation
clock frequency
FCX0, X1
⎯
4⎯12 MHz 1/2 (when PLL stops)
4⎯12 MHz PLL x 1
4⎯8 MHz PLL x 2
4⎯5.33 MHz PLL x 3
4⎯4 MHz PLL x 4
FLC X0A, X1A ⎯32.768 ⎯kHz
Base oscillation
clock cycle time
tCYL X0, X1 ⎯250 ⎯ns
tLCYL X0A, X1A ⎯30.5 ⎯µs
Input clock pulse
width
PWH, PWL X0 10 ⎯⎯ns Use duty ratio of
40 to 60% as a guideline
PWLH, PWLL X0A ⎯15.2 ⎯µs
Input clock
rise and fall time tcr, tcf X0, X0A ⎯⎯ 5ns
external
clock signal
Internal operating
clock frequency
FCP ⎯2⎯16 MHz Using main clock
(PLL clock)
FLCP ⎯⎯8.192 ⎯kHz Using sub clock
Internal operating
clock cycle time
tCP ⎯62.5 — 500 ns Using main clock
(PLL clock)
tLCP ⎯⎯122.1 ⎯µs Using sub clock
X0
tcf tcr
0.8 VCC
0.2 VCC
PWL
tCYL
PWH
X0A
tLCYL
tcf tcr
0.8 VCC
0.2 VCC
PWLH PWLL
• X0 clock timing
• X0A clock timing
MB90925 Series
42
• Range of guaranteed operation
Note : The MB90F927/ MB90F927S enters reset mode at power supply voltage below 4 V ± 0.3 V.
164
2
5.5
3.7
Relation between internal operating clock frequency and power supply voltage
guaranteed operation range
Power supply voltage V
CC
(V)
Guaranteed PLL
operation range
Internal operating clock frequency F
CP
(MHz)
4.0
Guaranteed A/D converter
operation range
16
8
16
8
Guaranteed oscillation
frequency range
Internal clock
fcp (MHz)
External clock Fc (MHz)
12
2
4
412
x 1/2
(PLL off)
x 1
x 2
x 4 x3
MB90925 Series
43
(2) Reset input
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
*: Oscillator’s oscillation time is the time that the amplitude reaches 90%. The oscillation time of a crystal oscillator
is between several ms and tens of ms. The oscillation time of a ceramic oscillator is between hundreds of µs
and several ms. The oscillation time of an external clock is 0 ms.
Parameter Symbol Pin name Value Unit Remarks
Min Max
Reset input time tRSTL RST
500 ⎯ns At normal operation
Oscillator oscillation
time* + 100 µs⎯ms
At stop mode,
sub clock mode,
sub sleep mode, and watch mode
100 ⎯µs At time-base timer mode
RST
X0
100 µs
t
RSTL
0.2 Vcc 0.2 Vcc
Internal
operation
clock
Internal
reset
90 % of
amplitude
Oscillator
oscillation time
Oscillation stabilization wait time
Execution of the instruction
• At stop mode, sub clock mode, sub sleep mode, watch mode, and power-on
RST
0.2 VCC
tRSTL
0.2 VCC
• At normal operation
MB90925 Series
44
(3) Power-on reset
(VSS = 0.0 V, TA = −40 °C to +105 °C)
Note : Extreme variations in power supply voltage may activate a power-on reset. As the illustration below shows,
when varying power supply voltage during operation, the use of a smooth voltage rise with suppressed
fluctuation is recommended. Also in this situation, the PLL clock on the device should not be used, however
it is permissible to use the PLL clock during a voltage drop of 1V/s or less.
Parameter Symbol Pin
name Conditions Value Unit Remarks
Min Max
Power supply rise time tR
VCC ⎯
0.05 30 ms
Power supply start voltage VOFF ⎯0.2 V
Power supply attained voltage VON 2.7 ⎯V
Power supply cutoff time tOFF 50 ⎯ms Waiting time until
power-on
VCC
tR
tOFF
2.7 V
0.2 V 0.2 V0.2 V
0 V
VCC
VSS
5.0 V
3.0 V
RAM data hold
A rise slope of 50 mV/ms or
less is recommended
MB90925 Series
45
(4) SIO timing
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Notes : • AC ratings are for CLK synchronous mode.
• CL is load capacitance connected to pin during testing.
• tCP is internal operating clock cycle time. Refer to “ (1) Clock timing”.
Parameter Symbol Pin name Conditions Value Unit
Min Max
Serial clock cycle time tSCYC SCK
Internal shift clock mode
output pin CL = 80 pF +
1TTL
8 tCP ⎯ns
SCK ↓ → SO delay time tSLOV SCK, SO −80 + 80 ns
Valid SI → SCK ↑tIVSH SCK, SI 100 ⎯ns
SCK ↑ → valid SI hold time tSHIX 60 ⎯ns
Serial clock “H” pulse width tSHSL SCK
External shift clock mode
output pin CL = 80 pF +
1TTL
4 tCP ⎯ns
Serial clock “L” pulse width tSLSH 4 tCP ⎯ns
SCK ↓ → SO delay time tSLOV SCK, SO ⎯150 ns
Valid SI → SCK ↑tIVSH SCK, SI 60 ⎯ns
SCK ↑ → valid SI hold time tSHIX 60 ⎯ns
• Internal shift clock mode
• External shift clock mode
SCK
SO
SI
tSCYC
tSLOV
tIVSH tSHIX
0.8 V 0.8 V
2.4 V
2.4 V
0.8 V
0.8 VCC
0.5 VCC
0.8 VCC
0.5 VCC
SCK
SO
SI
tSLSH tSHSL
tSLOV
tIVSH tSHIX
0.5 VCC 0.5 VCC
0.8 VCC 0.8 VCC
2.4 V
0.8 V
0.8 VCC
0.5 VCC
0.8 VCC
0.5 VCC
MB90925 Series
46
(5) UART0/1 (LIN/SCI)
• Bit setting: ESCR0/1:SCES=0, ECCR0/1:SCDE=0
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Notes : • AC characteristic in CLK synchronized mode.
• CL is load capacity value of pins when testing.
• tCP is internal operating clock cycle time (machine clock). Refer to “ (1) Clock timing”.
Parameter Symbol Pin name Conditions Value Unit
Min Max
Serial clock cycle time tSCYC SCK0, SCK1
Internal shift clock
mode output pins are
CL = 80 pF + 1TTL
5 tCP ⎯ns
SCK ↓ → SOT delay time tSLOVI SCK0, SCK1,
SOT0, SOT1 − 50 + 50 ns
Valid SIN → SCK ↑tIVSHI SCK0, SCK1,
SIN0, SIN1
tCP + 80 ⎯ns
SCK ↑ → valid SIN hold time tSHIXI 0⎯ns
Serial clock “L” pulse width tSLSH SCK0, SCK1
External shift clock
mode output pins are
CL = 80 pF + 1TTL
tCP + 10 ⎯ns
Serial clock “H” pulse width tSHSL 3 tCP − tR⎯ns
SCK ↓ → SOT delay time tSLOVE SCK0, SCK1,
SOT0, SOT1 ⎯2 tCP + 60 ns
Valid SIN → SCK ↑tIVSHE SCK0, SCK1,
SIN0, SIN1
30 ⎯ns
SCK ↑ → valid SIN hold time tSHIXE tCP + 30 ⎯ns
SCK fall time tFSCK0, SCK1 ⎯10 ns
SCK rise time tR⎯10 ns
MB90925 Series
47
• Internal shift clock mode
• External shift clock mode
SCK
SOT
SIN
tSLSHtSHSL
tSLOVE
t
IVSHE
tSHIXE
VIL VIL
VIH VIH
2.4 V
0.8 V
VIH
VIL
VIH
VIL
tFtR
VIH
SCK
SOT
SIN
tSLSHtSHSL
tSLOVE
t
IVSHE
tSHIXE
VIL VIL
VIH VIH
2.4 V
0.8 V
VIH
VIL
VIH
VIL
tFtR
VIH
MB90925 Series
48
• Bit setting: ESCR0/1:SCES=1, ECCR0/1:SCDE=0
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin name Conditions Value Unit
Min Max
Serial clock cycle time tSCYC SCK0, SCK1
Internal shift clock
mode output pins are
CL = 80 pF + 1TTL
5 tCP ⎯ns
SCK ↑ → SOT delay time tSLOVI SCK0, SCK1,
SOT0, SOT1 − 50 + 50 ns
Valid SIN → SCK ↓tIVSHI SCK0, SCK1,
SIN0, SIN1
tCP + 80 ⎯ns
SCK ↓ → valid SIN hold time tSHIXI 0⎯ns
Serial clock “H” pulse width tSHSL SCK0, SCK1
External shift clock
mode output pins are
CL = 80 pF + 1TTL
3 tCP − tR⎯ns
Serial clock “L” pulse width tSLSH tCP + 10 ⎯ns
SCK ↑ → SOT delay time tSLOVE SCK0, SCK1,
SOT0, SOT1 ⎯2 tCP + 60 ns
Valid SIN → SCK ↓tIVSHE SCK0, SCK1,
SIN0, SIN1
30 ⎯ns
SCK ↓ → valid SIN hold time tSHIX tCP + 30 ⎯ns
SCK fall time tFSCK0, SCK1 ⎯10 ns
SCK rise time tR⎯10 ns
MB90925 Series
49
• Internal shift clock mode
• External shift clock mode
SCK
SOT
SIN
tSCYC
tSHOVI
tIVSLI tSLIXI
2.4 V 2.4 V
0.8 V
2.4 V
0.8 V
VIH
VIL
VIH
VIL
SCK
SOT
SIN
tSHSLtSLSH
tSHOVE
tIVSLE tSLIXE
VIH
VIL
VIH
VIL
2.4 V
0.8 V
VIH
VIL
VIH
VIL
tRtF
VIL
MB90925 Series
50
• Bit setting: ESCR0/1:SCES=0, ECCR0/1:SCDE=1
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Notes : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing”rating for tCP.
Parameter Symbol Pin name Conditions Value Unit
Min Max
Serial clock cycle time tSCYC SCK0, SCK1
Internal clock operation
output pins are
CL = 80 pF + 1TTL
5 tCP ⎯ns
SCK ↑ → SOT delay time tSHOVI SCK0, SCK1,
SOT0, SOT1 − 50 + 50 ns
Valid SIN → SCK ↓tIVSLI SCK0, SCK1,
SIN0, SIN1
tCP + 80 ⎯ns
SCK ↓ → valid SIN hold time tSLIXI 0⎯ns
SOT → SCK ↓ delay time tSOVLI SCK0, SCK1,
SOT0, SOT1 3 tCP − 70 ⎯ns
SCK
SOT
SIN
tSHOVI
tSCYC
tSOVLI
tIVSLI tSLIXI
0.8 V
2.4 V
0.8 V
2.4 V
0.8 V
VIH
VIL
VIH
VIL
2.4 V
0.8 V
MB90925 Series
51
• Bit setting: ESCR0/1:SCES=1, ECCR0/1:SCDE=1
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Notes : tCP is the machine clock cycle time (Unit : ns) . Refer to “ (1) Clock timing”rating for tCP.
Parameter Symbol Pin name Conditions Value Unit
Min Max
Serial clock cycle time tSCYC SCK0, SCK1
Internal clock operation
output pins are
CL = 80 pF + 1TTL
5 tCP ⎯ns
SCK ↓ → SOT delay time tSLOVI SCK0, SCK1,
SOT0, SOT1 − 50 + 50 ns
Valid SIN → SCK ↑tIVSHI SCK0, SCK1,
SIN0, SIN1
tCP + 80 ⎯ns
SCK ↑ → valid SIN hold time tSHIXI 0⎯ns
SOT → SCK ↑ delay time tSOVHI SCK0, SCK1,
SOT0, SOT1 3 tCP − 70 ⎯ns
SCK
SOT
SIN
tSLOVI
tSCYC
tSOVHI
tIVSHI tSHIXI
0.8 V
2.4 V 2.4 V
2.4 V
0.8 V
VIH
VIL
VIH
VIL
2.4 V
0.8 V
MB90925 Series
52
(6) Timer input timing
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Note : tCP is internal operating clock cycle time. Refer to “ (1) Clock timing”.
Parameter Symbol Pin name Conditions Value Unit
Min Max
Input pulse width tTIWH
tTIWL
TIN0, TIN1,
IN0 to IN3 ⎯4 tCP ⎯ns
TIN0 , TIN1
IN0 to IN3
VIH VIH
VIL VIL
tTIWH tTIWL
• Timer input timing
MB90925 Series
53
(7) Trigger input timing
(VCC = 5.0 V±10%, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Note : tCP is internal operating clock cycle time (machine clock) . Refer to “ (1) Clock timing”.
Parameter Symbol Pin name Conditions Value Unit
Min Max
Input pulse width tTRGH,
tTRGL
INT0 to INT7 ⎯200 ⎯ns
ADTG ⎯tCP + 200 ⎯ns
INT0 to INT7
VIH VIH
VIL VIL
tTRGH tTRGL
• Trigger input timing
MB90925 Series
54
(8) Low voltage detection
(VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
Parameter Symbol Pin name Conditions Value Unit Remarks
Min Typ Max
Detection voltage VDL VCC ⎯3.7 4.0 4.3 V During voltage
drop
Hysteresis width VHYS VCC ⎯0.1 ⎯⎯VDuring voltage
rise
Power supply voltage
fluctuation ratio dV/dt VCC ⎯−0.1 ⎯+0.02 V/µs
Detection delay time td⎯⎯⎯⎯35 µs
VHYS
dV
dt
Vni
td
VCC
td
Internal reset
MB90925 Series
55
5. A/D Converter
(1) Electrical Characteristics
(VCC = AVCC = 5.0 V±10%, 3.0V ≤ AVRH-AVss, VSS = AVSS = 0.0 V, TA = −40 °C to +105 °C)
* : Defined as supply current (when VCC = AVCC = AVRH = 5.0 V) with A/D converter not operating, and CPU in
stop mode.
Parameter Symbol Pin name Value Unit Remarks
Min Typ Max
Resolution ⎯⎯ ⎯⎯10 bit
Total error ⎯⎯ ⎯⎯±3.0 LSB
Non-linear error ⎯⎯ ⎯⎯±2.5 LSB
Differential linear error ⎯⎯ ⎯⎯±1.9 LSB
Zero transition voltage VOT AN0 to AN7 AVSS −
1.5 LSB
AVSS +
0.5 LSB
AVSS +
2.5 LSB V1 LSB =
(AVRH − AVSS) /
1024
Full scale transition
voltage VFST AN0 to AN7 AVRH −
3.5 LSB
AVRH −
1.5 LSB
AVRH +
0.5 LSB V
Sampling time tSMP ⎯1.4 ⎯16500 µs4.5 V ≤ AVcc ≤ 5.5 V
2.0 4.0 V ≤ AVcc ≤ 4.5 V
Compare time tCMP ⎯0.5 ⎯ ⎯µs4.5 V ≤ AVcc ≤ 5.5 V
1.2 4.0 V ≤ AVcc ≤ 4.5 V
Analog port
input current IAIN AN0 to AN7 − 0.3 ⎯+0.3 µA
Analog input voltage VAIN AN0 to AN7 AVss ⎯AVRH V
Reference voltage AVRH AVRH AVss+2.7 ⎯AVCC V
Power supply current IAAVCC
⎯3.5 7.5 mA
IAH ⎯⎯ 5µA*
Reference voltage
supply current
IRAVRH ⎯600 900 µAVAVRH = 5.0 V
IRH AVRH ⎯⎯ 5µA*
Inter-channel variation — AN0 to AN7 ⎯⎯ 4LSB
MB90925 Series
56
• Notes of the external impedance of the analog input and its sampling time
A/D converter with sample and hold circuit. If the external impedance is too high to keep sufficient sampling
time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting
A/D conversion precision. Therefore, to satisfy the A/D conversion precision standard, consider the relationship
between the external impedance and minimum sampling time and either adjust the register value and operating
frequency or decrease the external impedance so that the sampling time is longer than the minimum value. Also,
if the sampling time cannot be sufficient, connect a capacitor of about 0.1 µF to the analog input pin.
R
Comparator
C
Analog input
• Analog input equivalent circuit
During sampling : ON
Note : The values are reference values.
MB90F927/MB90F927S
R C
4.5 V ≤ AVcc ≤ 5.5 V : 2.0 kΩ (Max) 16.0 pF (Max)
4.0 V ≤ AVcc ≤ 4.5 V : 8.2 kΩ (Max) 16.0 pF (Max)
MB90V925-101/102
4.5 V ≤ AVcc ≤ 5.5 V : 2.0 kΩ (Max) 14.4 pF (Max)
4.0 V ≤ AVcc ≤ 4.5 V : 8.2 kΩ (Max) 14.4 pF (Max)
MB90925 Series
57
•About errors
As |AVRH - AVSS| becomes smaller, values of relative errors grow larger.
100
90
80
70
60
50
40
30
20
10
0
0 5 10 15 20 25 3035
MB90F927/F927S
MB90V925-101/102 20
18
16
14
12
10
8
6
4
2
0
0123456 87
MB90F927/F927S
MB90V925-101/102
(External impedance = 0 kΩ to 100 kΩ)
External impedance [kΩ]
Minimum sampling time [µs]
(External impedance = 0 kΩ to 20 kΩ)
External impedance [kΩ]
Minimum sampling time [µs]
• The relationship between the external impedance and minimum sampling time
20
18
16
14
12
10
8
6
4
2
0
0123456 87
MB90F927/F927S
MB90V925-101/102
(External impedance = 0 kΩ to 20 kΩ)
External impedance [kΩ]
Minimum sampling time [µs]
100
90
80
70
60
50
40
30
20
10
0
0 5 10 15 20 25 3035
MB90F927/F927S
MB90V925-101/102
(External impedance = 0 kΩ to 100 kΩ)
External impedance [kΩ]
Minimum sampling time [µs]
• At 4.5 V ≤ AVcc ≤ 5.5 V
• At 4.0 V ≤ AVcc ≤ 4.5 V
MB90925 Series
58
(2) Definition of terms
Resolution : Analog changes that are identifiable with the A/D converter.
Non-Linear error : The deviation of the straight line connecting the zero transition point
(“00 0000 0000” ↔ “00 0000 0001”) with the full-scale transition point
(“11 1111 1110” ↔ “11 1111 1111”) from actual conversion characteristics.
Differential linear error : The deviation of input voltage needed to change the output code by 1 LSB from the
ideal value.
Total error : The total error is defined as a difference between the actual value and the theoretical value,
which includes zero-transition error/full-scale transition error and linear error.
(Continued)
Total error
Actual conversion
value
Analog input
Total error for digital output N = VNT − {1 LSB × (N − 1) + 0.5 LSB}
1 LSB [LSB]
1 LSB(Ideal) = AVRH − AVSS
1024 [V]
VOT (Ideal) = AVss + 0.5 LSB [V]
VFST (Ideal) = AVRH − 1.5 LSB [V]
VNT : Voltage at a transition of digital output from (N - 1)H to NH
Actual conversion
value
Ideal
characteristics
(Measured value)
Digital output
AVSS AVRH
3FFH
3FEH
3FDH
004H
003H
002H
001H
1.5 LSB
VNT
{1 LSB x (N - 1) + 0.5 LSB}
0.5 LSB
N : A/D converter digital output value
MB90925 Series
59
(Continued)
6. Flash Memory Program/Erase Characteristics
* : This value comes from the technology qualification. (using Arrhenius equation to translate high temperature
measurements into normalized value at + 85 °C)
Parameter Conditions Value Unit Remarks
Min Typ Max
Chip erase time TA = + 25 °C
VCC = 5.0 V
⎯115s
Excludes pre-programming before
erase
Byte (8-bit width)
programming time ⎯32 3600 µs Excludes system-level overhead
Erase/program cycle ⎯10000 ⎯⎯cycle
Flash memory data
retention time
Average
TA = + 85 °C20 ⎯⎯year *
Non-Linear error
Digital output
Differential linear error
(Measured
value)
(Measured value)
Non-Linear error of
digital output N
VNT − {1 LSB × (N − 1) + VOT}
1 LSB [LSB]
=
Differential linear error
of digital output N
V (N + 1) T − VNT
1 LSB − 1 [LSB]
=
VFST − VOT
1022 [V]
1 LSB =
N : A/D converter digital output value
VOT : Voltage at transition of digital output from “000H” to “001H”
VFST : Voltage at transition of digital output from “3FEH” to “3FFH”
Actual conversion
value
Actual conversion
value
Ideal
characteristics
Digital output
Analog input Analog input
Actual conversion
value
{1 LSB x (N -1)
+ VOT}
Actual conversion
value
Ideal
characteristics
(Measured value)
AVss AVRH
3FFH
3FEH
3FDH
004H
003H
002H
001H
VNT
VOT (Measured value)
VFST
(Measured
value)
AVss AVRH
N + 1H
NH
N - 1H
N - 2H
V(N + 1)T
VNT
MB90925 Series
60
■ORDERING INFORMATION
Part number Package Remarks
MB90F927PF-GE1
MB90F927SPF-GE1
100-pin plastic QFP
(FPT-100P-M06)
MB90F927PFV-GE1
MB90F927SPFV-GE1
100-pin plastic LQFP
(FPT-100P-M05)
MB90V925-101
MB90V925-102
299-pin ceramic PGA
(PGA-299C-A01) For evaluation
MB90925 Series
61
■PACKAGE DIMENSIONS
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
(Continued)
100-pin plastic QFP Lead pitch 0.65 mm
Package width ×
package length 14.00 × 20.00 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
3.35 mm MAX
Code
(Reference) P-QFP100-14×20-0.65
100-pin plastic QFP
(FPT-100P-M06)
(
FPT-100P-M06
)
C
2002 FUJITSU LIMITED F100008S-c-5-5
130
31
50
5180
81
100
20.00±0.20(.787±.008)
23.90±0.40(.941±.016)
14.00±0.20
(.551±.008)
17.90±0.40
(.705±.016)
INDEX
0.65(.026) 0.32±0.05
(.013±.002) M
0.13(.005)
"A"
0.17±0.06
(.007±.002)
0.10(.004)
Details of "A" part
(.035±.006)
0.88±0.15
(.031±.008)
0.80±0.20
0.25(.010)
3.00 +0.35
–0.20
+.014
–.008
.118
(Mounting height)
0.25±0.20
(.010±.008)
(Stand off)
0~8˚
*
*
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
MB90925 Series
62
(Continued)
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
100-pin plastic LQFP Lead pitch 0.50 mm
Package width ×
package length 14.0 × 14.0 mm
Lead shape Gullwing
Sealing method Plastic mold
Mounting height
1.70 mm MAX
Weight 0.65g
Code
(Reference) P-LFQFP100-14×14-0.50
100-pin plastic LQFP
(FPT-100P-M05)
(FPT-100P-M05)
C
2003 FUJITSU LIMITED F100007S-c-4-6
14.00±0.10(.551±.004)SQ
16.00±0.20(.630±.008)SQ
125
26
51
76 50
75
100
0.50(.020) 0.20±0.05
(.008±.002) M
0.08(.003)0.145±0.055
(.0057±.0022)
0.08(.003)
"A"
INDEX .059 –.004
+.008
–0.10
+0.20
1.50
(Mounting height)
0˚~8˚
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.25(.010)
0.10±0.10
(.004±.004)
Details of "A" part
(Stand off)
*
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
Note 1) * : These dimensions do not include resin protrusion.
Note 2) Pins width and pins thickness include plating thickness.
Note 3) Pins width do not include tie bar cutting remainder.
MB90925 Series
F0705
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
All Rights Reserved.
The contents of this document are subject to change without notice.
Customers are advised to consult with FUJITSU sales
representatives before ordering.
The information, such as descriptions of function and application
circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
Fujitsu semiconductor device; Fujitsu does not warrant proper
operation of the device with respect to use based on such
information. When you develop equipment incorporating the
device based on such information, you must assume any
responsibility arising out of such use of the information. Fujitsu
assumes no liability for any damages whatsoever arising out of
the use of the information.
Any information in this document, including descriptions of
function and schematic diagrams, shall not be construed as license
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party or does Fujitsu warrant non-infringement of any third-party’s
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Fujitsu assumes no liability for any infringement of the intellectual
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from the use of information contained herein.
The products described in this document are designed, developed
and manufactured as contemplated for general use, including
without limitation, ordinary industrial use, general office use,
personal use, and household use, but are not designed, developed
and manufactured as contemplated (1) for use accompanying fatal
risks or dangers that, unless extremely high safety is secured, could
have a serious effect to the public, and could lead directly to death,
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reaction control in nuclear facility, aircraft flight control, air traffic
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Please note that Fujitsu will not be liable against you and/or any
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Any semiconductor devices have an inherent chance of failure. You
must protect against injury, damage or loss from such failures by
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over-current levels and other abnormal operating conditions.
If any products described in this document represent goods or
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