HDV26 ADP II SRAM o 3.3 Volt x16 Asynchronous Dual-Port Static RAM Memory Configuration Device 16K x 16 HDV26 Key Features: * * * * * * * * * * Industry leading Dual-Port Static RAM Low power operation Simultaneous memory access through two ports LVTTL compatible; 3.3V power supply Easily expands bus width to 32 bits or more using the MASTER/SLAVE select function Supports Semaphore, Busy Logic, and on-chip port arbitration logic Available package: 84-pin Plastic Lead Chip Carrier (PLCC) (0C to 70C) Commercial operating temperature available for access time of 15ns and above (-40C to 85C) Industrial operating temperature available for access time of 25ns Pin-to-pin compatible with conventional dual-port devices including IDT (70V26) Product Description: HBA's Asynchronous Dual-Port (ADP) II Static RAM offers industry leading 0.25um process technology and 16K x 16 memory configuration. The device supports two memory ports with independent control, address, and I/O pins that enable simultaneous, asynchronous access to any location in memory. System designers have full flexibility of implementing deeper and wider memory using the depth and width expansion features. The HDV26 is a stand alone 16K x 16 Asynchronous Dual-Port SRAM. For applications using buses of 32 bits or wider, the MASTER/SLAVE configuration can provide bus width expansion without additional discrete logic. Dual-chip depth expansion can easily be done without external logic as well. These devices have low power consumption, hence minimizing system power requirements. They are ideal for applications such as data communication, telecommunication, multiprocessing, test equipment, network switching, etc. 3HD163A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. PRELIMINARY Page 1 of 17 HDV26 ADP II SRAM Block Diagram of Dual Port StaticRAM 16K x 16 R/ W L R/ W R UB L UB R LB R CE R OE R LB L CE L OE L I/O 8 -1 5 L I/O Co n t ro l I/O 8 -1 5 R I/O Co n t ro l I/O 0 -7 L I/O 0 -7 R (1 ,2 ) (1 ,2 ) BUSY L BUSYR A 13 L Address Deco der A0 L CEL SEM NOTES: 1. 2. L ___________ SRAM Address Deco der Arbit rat io n Sem ap h o re Lo gic CE R M/S A 1 3R A 0R SEM R ___________ Master: BUSY is output; Slave: BUSY is input. ___________ BUSY outputs are non-tri-stated push-pull. Figure 1. Device Architecture 3HD163A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. PRELIMINARY Page 2 of 17 HDV26 84 83 82 UBL LBL A13L 1 SEML CEL 2 81 80 79 A9L 3 A10L 4 A11L 5 A12L 6 R/WL 7 I/O1L I/O0L 8 I/O3L I/O2L GND 9 VCC 10 OEL 11 I/O4L Index I/O5L I/O7L I/O6L ADP II SRAM 78 77 76 75 I/O8L 12 74 A8L I/O9L 13 73 A7L I/O10L I/O11L 14 72 15 71 A6L A5L I/O12L 16 70 A4L I/O13L GND 17 69 18 68 A3L A2L I/O14L 19 67 A1L I/O15L 20 66 A0L VCC GND 21 65 64 BUSYL GND I/O0R 23 63 M/S I/O1R I/O2R 24 62 25 61 BUSYR A0R PLCC-84 (Drw No: J-03A; Order Code: J) Top View 22 32 54 A6R A7R 35 36 37 38 39 40 I/O15R 34 I/O9R I/O10R 33 41 42 43 44 45 46 47 48 49 50 51 52 53 A8R I/O7R I/O8R A9R A5R 55 A10R 56 31 A11R 30 A12R I/O6R LBR A13R A3R A4R UBR 57 CER 58 29 GND SEMR 28 OER I/O4R I/O5R R/WR A2R I/O14R GND A1R 59 I/O13R 60 27 I/O12R 26 I/O11R VCC I/O3R Figure 2. Device Pin-Out 3HD163A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. PRELIMINARY Page 3 of 17 HDV26 ADP II SRAM Left Port Right Port _____ Name _____ Symbol Rating Com & Ind Unit VTERM Terminal Voltage with respect to GND -0.5 to + 4.6 V TBIAS Temperature Under Bias -55 to +125 C C CEL CER Chip Enable R/WL R/WR Read / Write Enable OEL OER Output Enable A0L-13L A0R-13R Address I/O15L - 0L I/O15R - 0R Data Inputs / Outputs TSTG Storage Temperature -65 to +150 SEML SEMR Semaphore Enable 50 UB R Upper Byte Select IOUT DC Output Current UB L LBR Lower Byte Select ____ ____ _____ _____ ________ ________ ______ ______ _____ _____ LBL NOTES: Master or Slave Select Absolute Max Ratings are for reference only. Permanent damage to the device may occur if extended period of operation is outside this range. Standard operation should fall within the Recommended Operating Conditions. Vcc Power Table 2. Absolute Maximum Ratings GND Ground __________ BUSYL mA __________ ___ BUSYR M/ S Busy Flag Table 1. Pin Descriptions Symbol Parameter Commercial Temperature Industrial Temperature Min. Typ. Max. Min. Typ. Max. 3.0 3.3 3.6 3.0 3.3 3.6 V 0 0 0 0 0 0 V Unit Recommended Operating Conditions VCC Supply Voltage Com'l/Ind'l GND Supply Voltage VIH VIL TA Input High Voltage Com'l/Ind'l 2.0 - - 2.0 - - V Input Low Voltage Com'l/Ind'l - - 0.8 - - 0.8 V Operating Temperature 0 - 70 -40 - 85 Input Leakage Current (any input) - - 5 - - 5 A Output Leakage Current - - 5 - - 5 A Output Logic "1" Voltage, IOH=-4mA 2.4 - - 2.4 - - V Output Logic "0" Voltage, IOL = 4mA - - 0.4 - - 0.4 V C DC Electrical Characteristics ILI(1) ILO VOH VOL Capacitance at 1.0MHz Ambient Temperature (25C) Symbol Parameter (2) Input Capacitance CIN (2) Output Capacitance COUT Conditions(3) VIN= 3dV VOUT= 3dV Max. 9 10 Unit pF pF NOTES: 1. At Vcc < 2.0V, input leakage is undefined. 2. This parameter is determined by device characterization but is not production tested. 3. 3dV represents the interpolated capacitance when input and output signals switch from 0V to 3V or from 3V to 0V. 3HD163A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. PRELIMINARY Page 4 of 17 HDV26 ADP II SRAM Power Consumption Symbol ICC ISB1 Parameter Dynamic Operating Current (Both Ports Active) Standby Current (Both Ports - TTL Level Inputs) ISB2 Standby Current (One Port - TTL Level Inputs) ISB3 Full Standby Current (Both Ports - All CMOS Level Inputs) ISB4 Standby Current (One Port - All CMOS Level Inputs) Conditions _____ Outputs CE = VIL,________ Disabled, SEM = VIH, f=fMAX (1) _____ HDV26L15 HDV26L25 HDV26L35 Typ. Max. Typ. Max. Typ. Max. C 120 180 100 140 90 120 I - - 125 185 - - C 12 24 12 24 10 24 I - - 30 50 - - C 75 110 50 85 45 75 I - - 75 105 - - C 0.2 3.0 0.2 3.0 0.2 3.0 Unit mA _____ CE L = CE R = VIH, ________ ________ SEMR = SEML = VIH, f=fMAX (1) _____ Temp mA _____ CEA = VIL and CEB = VIH Active Port Outputs (1) MAX Disabled, f=f _____ Both Ports CEL and _____ CER > Vcc - 0.2V, VIN > Vcc - 0.2V or V IN < 0.2V, f = 0 (2), ________ ________ SEMR = SEML > Vcc - 0.2V _____ _____ CEA < 0.2V and CEB ________ - 0.2V, SEMR > Vcc ________ = SEML > Vcc - 0.2V, Active Port Outputs Disabled, f=fMAX (1) mA mA I - - 0.2 3.0 - - C 80 100 60 80 55 74 mA I - - 70 90 - - NOTES: 1. At f = fMAX, address and I/O's are cycling at the maximum frequency read cycle of 1/tRC, and using "AC Test Conditions" of input levels of GND to 3V. 2. f = 0: no control and address bits change. 3HD163A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. PRELIMINARY Page 5 of 17 HDV26 ADP II SRAM Commercial & Industrial HDV26-15 Symbol Parameter HDV26-25 HDV26-35 Min. Max. Min. Max. Min. Max. Unit 15 - 25 - 35 - ns - 15 - 25 - 35 ns - 15 - 25 - 35 ns - 15 - 25 - 35 ns - 10 - 15 - 20 ns Read Cycle tRC Read Cycle Time tAA Address Access Time tACE tABE Chip Enable Access Time (3) Byte Enable Access Time (3) (3) tAOE Output Enable Access Time tOH Output Hold from Address Change 3 - 3 - 3 - ns tLZ Output Low-Z Time (1,2) 3 - 3 - 3 - ns tHZ (1,2) - 10 - 15 - 20 ns 0 - 0 - 0 - ns - 15 - 25 - 35 ns 10 - 15 - 15 - ns - 25 - 35 - 45 ns Output High-Z Time tPU Chip Enable to Power Up Time (1,2) (1,2) tPD Chip Disable to Power Down Time tSOP Semaphore Flag Update Pulse tSAA Semaphore Address Access Time (3) Write Cycle tWC Write Cycle Time 15 - 25 - 35 - ns tEW Chip Enable to End-of-Write (3) 12 - 20 - 25 - ns tAW Address Valid to End-of-Write 12 - 20 - 25 - ns 0 - 0 - 0 - ns (3) tAS Address Set-up Time tWP Write Pulse Width 12 - 20 - 25 - ns tWR Write Recovery Time 0 - 0 - 0 - ns tDW Data Valid to End-of-Write 10 - 15 - 20 - ns - 10 - 15 - 20 ns 0 - 0 - 0 - ns - 10 - 15 - 20 ns tHZ Output High-Z Time tDH Data Hold Time (1,2) (4) (1,2) tWZ Write Enable to Output in High-Z tOW Output Active from End-of-Write (1,2,4) 0 - 0 - 0 - ns tSWRD ________ SEM Flag Write to Read Time 5 - 5 - 5 - ns tSPS SEM Flag Contention Window ________ 5 - 5 - 5 - ns NOTES: 1. 2. 3. 4. Test conditions defined in Figs. 3 & 4 are used. This parameter is guaranteed, but not tested. ______ __________ ______ __________ To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL. The specification for tDH must be met by the device supplying write data to the RAM under all operating conditions. Although tDH and tOW values will vary over voltage and temperature, the actual tDH will always be smaller than the actual tOW. Table 3. AC Electrical Characteristics 3HD163A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. PRELIMINARY Page 6 of 17 HDV26 ADP II SRAM Commercial & Industrial HDV26-15 Symbol Parameter ___________ HDV26-25 HDV26-35 Min Max. Min. Max. Min. Max. Unit - 15 - 25 - 35 ns - 15 - 25 - 35 ns - 15 - 25 - 35 ns ___ BUSY Timing (M/S = VIH) __________ tBAA BUSY Access Time form Address Match tBDA BUSY Disable Time from Address Not Matched tBAC BUSY Access Time from Chip Enable Low tBDC BUSY Access Time from Chip Enable High - 15 - 25 - 35 ns tAPS Arbitration Priority Set-up Time (2) 5 - 5 - 5 - ns tBDD __________ BUSY Disable to Valid Data (3) - 30 - 35 - 40 ns tWH Write Hold after BUSY (5) 15 - 20 - 25 - ns 0 - 0 - 0 - ns 20 - 25 - 25 - ns - 55 - 65 - 85 ns - 40 - 60 - 80 ns __________ __________ __________ __________ ___________ ___ BUSY Timing (M/S = VIL) tWB tWH __________ BUSY Input to Write (4) __________ Write Hold after BUSY (5) Port-to-Port Delay Timing tWDD tDDD Write Pulse to Data Delay (1) Write Data Valid to Read Data Delay (1) NOTES: 1. 2. 3. 4. 5. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and BUSY". To ensure that the earlier of the two ports wins. tBDD is a calculated parameter and is the greater of 0, tWDD - tWP (actual) or tDDD - tDW (actual). To ensure that the write cycle is inhibited on port "B" during contention with port "A". To ensure that a write cycle is completed on port "B" after contention on port "A". Table 3. AC Electrical Characteristics (Continued) 3HD163A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. PRELIMINARY Page 7 of 17 HDV26 ADP II SRAM 3.3V Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V Output Load Refer to Figs. 3 & 4 3.3V 590 D.U.T. BUSY 590 D.U.T. 30pF 435 5pF* 435 Figure 4. Output Test Load for tLZ, tHZ, tWZ, tOW *Includes jig and scope capacitances. Figure 3. AC Output Load NOTES: 1. Include jig and scope capacitances Table 4. AC Test Condition Inputs(1) ______ ____ ______ OE X Outputs ______ UB X _____ LB X _________ SEM H I/O8-15 I/O0-7 High-Z High-Z Mode CE H R/W X X X X H H H High-Z High-Z Both Bytes Deselected L L X L H H Data In High-Z Write to Upper Byte Only L L X H L H High-Z Data In Write to Lower Byte Only L L X L L H Data In Data In Write to Both Bytes Deselected: Power-Down L H L L H H Data Out High-Z Read Upper Byte Only L H L H L H High-Z Data Out Read Lower Byte Only L H L L L H Data Out Data Out Read Both Bytes X X H X X X High-Z High-Z Outputs Disabled NOTES: 1. A0L-13L A0R-13R. Table 5. Truth Table - Non-Contention Read/Write Control Inputs(1) ______ ____ CE H R/W H X H H X ______ Outputs ______ _____ _________ Mode SEM L I/O8-15 I/O0-7 Data Out Data Out Read Data in Semaphore Flag H L Data Out Data Out Read Data in Semaphore Flag X X L Data In Data In Write I/O0 into Semaphore Flag H H L Data In Data In Write I/O0 into Semaphore Flag X L X L - - Not Allowed X X L L - - Not Allowed OE L UB X LB X L H X X L X L X NOTES: 1. There are 8 semaphore flags written to I/O0 and read from all I/Os (I/00-15). These 8 semaphore flags are addressed A0-2. Table 6. Truth Table - Semaphore Read/Write Control 3HD163A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. PRELIMINARY Page 8 of 17 HDV26 ADP II SRAM Inputs ______ ______ CE L X Outputs A13-0 L, R __________ (1) BUSY L H __________ BUSY R(1) H Function CE R X No Match H X Match X H Match H H Normal L L Match (2) (2) Write Inhibit(3) NOTES: 1. 2. 3. H __________ H Normal Normal __________ __________ When part is configured as master, BUSYL and BUSYR are both outputs. When configured as slave, both are inputs and internally inhibits writes. BUSY outputs are push-pull, not open drain. If inputs to opposite port were stable prior to address and enable inputs of this port, then "L." If inputs to the opposite port became stable after the address the enable __________ __________ __________ __________ inputs of port, then "H." If tAPS is not met, then either BUSYL or BUSYR = LOW. BUSYL and BUSYR cannot be LOW simultaneously __________ Writes to one port are internally ignored when its BUSY outputs are LOW regardless of actual logic level on the pin. __________ Table 7. Truth Table - Address BUSY Arbitration Functions Left D0-15 Right D0-15 Status No Action 1 1 Semaphore free Left port writes "0" to semaphore 0 1 Left port has semaphore token Right port writes "0" to semaphore 0 1 No change. Right port has no write access to semaphore Left port writes "1" to semaphore 1 0 Right port obtains semaphore token Left port writes "0" to semaphore 1 0 No change. Left port has no write access to semaphore Right port writes "1" to semaphore 0 1 Left port obtains semaphore token Left port writes "1" to semaphore 1 1 Semaphore free Right port writes "0" to semaphore 1 0 Right port has semaphore token Right port writes "1" to semaphore 1 1 Semaphore free Left port writes "0" to semaphore 0 1 Left port has semaphore token Left port writes "1" to semaphore 1 1 Semaphore free NOTES: 1. Table shows sequence of events for one of the eight semaphores. 2. There are eight semaphore flags (A0-2) written via I/O0 and read from I/O0-15. _____ ________ 3. CE = VIH, SEM = VIL to access semaphores. 4. Refer to Table 6. Table 8. Truth Table - Semaphore Procurement Sequence Example 3HD163A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. PRELIMINARY Page 9 of 17 HDV26 ADP II SRAM Timing Diagrams tRC ADDR t AA t ACE (4) CE t AOE(4) OE t ABE(4) UB, LB R/W t OH t LZ (1) Data Out Valid Data(4) t HZ (2) BUSYOut t BDD (3,4) NOTES: ______ ______ ______ ______ 1. tLZ timing is based on which signal is asserted last, C E______ ,OE______ , UB______ or L B______ . 2. tHZ timing is based on which signal is de-asserted first, C E ,OE , UB or L B . _________ 3. tBDD is needed only where the opposite port is completing a write operation to the same address. BUSY has no effect on valid output data. 4. Valid data starts from the last of tAOE, tACE, tAA or tBDD. Diagram 1. Read Cycles 3HD163A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. PRELIMINARY Page 10 of 17 HDV26 ADP II SRAM tWC ADDR tHZ (7) OE tAW CE, SEM UB, LB tAS (6) tWR (3) tWP (2) R/W tWZ Data Out tOW (4) (4) tDH tDW Data In ____ Diagram 2. Write Cycle No. 1, R/W Controlled Timing tWC ADDR tAW CE, SEM tAS(6) tWR(3) tEW(2) UB, LB R/W tDW Data In _____ Diagram 3. Write Cycle No. 2, CE Controlled Timing NOTES: ____ ______ 1. R/W or C E must be ______ HIGH during all ____ address transitions. 2. A write occurs when C E = VIL and R/W = ____ VIL for memory write cycle. ______ 3. tWR timing is from the earlier of C E or R/W going HIGH to the end of write cycle. 4. The ______ I/O pins are in the output state and input signals must not be applied during DATA out period. ____ 5. For C E =VIL transition simultaneously with or after the R/W = VIL transition, the outputs remain in the high-impedance state. ______ ____ 6. tAS timing is based on latter of C E or R/W . 7. tHZ transition is measured 0mV from steady state with the Output Test Load. _____ ____ 8. For OE =VIL during R/W write cycle, the write pulse width is the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data to be placed on the bus for the required _____ ____ tDW. If OE = VIH during an R/W controlled writing cycle, the write pulse is specified as tWP. 3HD163A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. PRELIMINARY Page 11 of 17 HDV26 ADP II SRAM t SAA A0-A2 Valid Address t AW Valid Address t WR SEM t OH t ACE t EW t SOP t DW Data In Valid I/O0 t AS t WP Data Out Valid (2) t DH R/W t SWRD t AOE OE Write Cycle NOTES: _____ ______ Read Cycle ______ 1. CE = VIH or UB and L B = VIH for the duration of the above timing (both write and read cycle). 2. "DATA OUT VALID" represents all I/O's (I/O0-15) equal to the semaphore value Diagram 4. Semaphore Read after Write Timing, Either Side A 0 A -A 2 A S ID E A M a tc h R /W A SEM A tSP S A 0 B -A 2 B S ID E B M a tc h R /W B SEM B NOTES: _____ _____ 1. DOR = DOL = VIL, CEL = CER =VIH. 2. Timing for both ports is the same. Port B is________ opposite of port A. ____ ____ ________ 3. This parameter is measured from R/W A or SEMA =VIH to R/W B or SEMB= VIH. 4. The semaphore will be sent to either side if tSPS is not met. It cannot be guaranteed which side receives semaphore. Diagram 5. Semaphore Write Contention 3HD163A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. PRELIMINARY Page 12 of 17 HDV26 ADP II SRAM tWC AD D R A M atch tWP R /W A t DW t DH D ata In A Valid t A P S( 1 ) M atch AD D R B t BAA t BDA BUSY B t BD D tW DD Valid D ata OutB t DDD (3 ) NOTES: ___ 1. _____ tAPS is_____ ignored for SLAVE part (M/S = VIL) 2. CE L =CER = VIH. _____ 3. OE = VIL for the reading port. ___________ ___ 4. For SLAVE mode (M/S = VIL), BUSY is an input. 5. Timing for both ports is the same. Port B is opposite of port A. ___________ __ Diagram 6. Write with Port-to-Port Read and BUSY (M/S = VIH) tWP R/WA t W B (3 ) t W H (1) BUSYB R/WB NOTES: ___________ (2) ___________ 1. ___________ SLAVE (BUSY input) and MASTER (BUSY output) must meet tWH. ____ ___________ 2. BUSY is sent to port B blocking R/W B till BUSYB=VIH. 3. tWB is for SLAVE mode. ___________ __ Diagram 7. Write with BUSY (M/S = VIL) 3HD163A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. PRELIMINARY Page 13 of 17 HDV26 ADP II SRAM AD D R A and AD D R B Addre sse s M atch CE A tAPS CE B t BAC t BDC BUSYB NOTES: ___________ 1. If tAPS is not satisfied, the BUSY signal will be asserted randomly on one side or the other. ___________ _____ __ Diagram 8. BUSY Arbitration Controlled by CE Timing (M/S = VIH) Addre sse s N ADDR A t AP S ( 1 ) ADDR B M atching Addre sse s N t BAA t BDA BUSY B NOTES: ___________ 1. If tAPS is not satisfied, the BUSY signal will be asserted randomly on one side or the other. ___________ __ Diagram 9. BUSY Arbitration Controlled by Address Match Timing (M/S = VIH) 3HD163A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. PRELIMINARY Page 14 of 17 HDV26 ADP II SRAM Functional Description HDV26 supports two memory ports with independent control, address, and I/O pins that enable simultaneous, asynchronous access to any location in memory. Busy Logic When both ports attempt to access the same memory location at the same time, data corruption can potentially occur. In ___ the single-device or MASTER configuration (i.e. when the M/ S pin is tied HIGH), the on-chip Busy Logic arbitrates simultaneous accesses to the same memory location, and __________ determines the "winner" between the two ports. If Busy Logic considers the right port lost in the arbitration, then the right port BUSY pin is set active (LOW) to signal the system that this memory location is "busy" being accessed by the other__________ port. Furthermore, the Busy Logic prevents the right port from writing to the same memory location for as long as the right port BUSY signal stays active (LOW). Once the left port finishes access to this memory __________ location, the dual-port SRAM signals the system by setting the right port BUSY pin back to inactive (HIGH), so that the system can resume its normal access from the right port. Note that only the write operation from the losing port is inhibited; the read operation is nondestructive and can thus continue regardless of the arbitration result. __________ The BUSY pins are output pins in the single-device or MASTER mode, but become input pins instead when the device ___ is configured in SLAVE mode (this is accomplished by tying M/ S pin LOW). In SLAVE mode the on-chip arbitration logic is __________ disabled, and the device relies on the input B __________ U S Y signals for the results of arbitration when simultaneous access to the same memory__________ location occurs. Specifically, when a BUSY pin is set to HIGH, normal operation can be performed from this port, but when a BUSY pin is set to LOW, write operations will be inhibited from this port. If width expansion with multiple HBA HDV26 devices is used, it is recommended that only one of them be configured in MASTER mode, and the rest of them in __________ __________ SLAVE mode. The BUSY (output) signal from the master device should be connected to the respective BUSY (input) pins of the slave devices. This means that only one device (the master) is performing the Busy Logic arbitration, and all the other devices (the slaves) will follow this arbitration accordingly. This can prevent the conflicts caused by the potential inconsistent arbitration results from different dual-port SRAM devices. Note that if the user does not wish the write operation to be inhibited by the Busy __________ Logic, the user can disable this feature by configuring the device in SLAVE mode and tying the BUSY input pins to HIGH. The Busy arbitration logic is triggered whenever the two ports simultaneously attempt to access the same memory location, where____ data accesses are determined by the timings and values of the Address and Chip Enable signals only, not by the value of the R/ W signal. This means that both read and write operations can trigger the Busy Logic, even though only the write operation is inhibited from the losing port. Note that in a master/slave configuration, an additional timing constraint concerning ____ the R/ W signal needs to be met in order to prevent data corruption in the slave device: the write operation in the slave device __________ __________ cannot start before the BUSY signal - which originates from the output BUSY pin - is received by the slave device to ensure ____ write inhibition. In other words, the R/ W signal needs to stay high from the__________ time the Busy Logic on the master device is triggered (through the changing of the Address and Chip Enable signals) till the BUSY signal is received by the slave device. Semaphores A semaphore can be considered as a special one-bit dual-port memory cell that can be "owned" by (or granted to) only one port at any given time. Typically a semaphore is used as an arbiter for the exclusive ownership (or access privilege) of any shared resource in a system. A semaphore ownership can be requested by writing a zero "0" to the semaphore; a semaphore ownership can be relinquished by writing a one "1" to the semaphore; and a semaphore ownership can be tested by reading from the semaphore - a readout of zero "0" means that the semaphore is owned by this port, while a readout of one "1" means that either the semaphore is owned by the other port, or there is no owner at all. A token-passing system can be used to conceptualize the semaphore mechanism: requesting for the semaphore ownership is equivalent to requesting for the token, and relinquishing the semaphore ownership is equivalent to releasing the token. HBA HDV26 device provides eight addressable semaphores in addition to the regular 64Kx16 dual-port memory space. A typical sequence of accessing a semaphore is as follows: first a port attempts to request for the token by writing a zero "0" to the semaphore. The result of the request is then tested by reading from the semaphore: if the readout is zero "0", then the token request has succeeded; but if the readout is one "1", then the token request has failed. The requester should then try to repeatedly read from the semaphore until the readout becomes zero "0", upon which time the requester becomes the new possessor of the token, and can be granted exclusive access privilege to the shared resource the semaphore represents. In the case when both ports request for the token at the same time, the semaphore logic ensures that only one port is granted the token. In other words, at most one of the two semaphore readout ports can assume the value of zero "0". When the token is not owned by 3HD163A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. PRELIMINARY Page 15 of 17 HDV26 ADP II SRAM any port, the semaphore will appear to contain the value one "1" to both ports. Note that a failed token request becomes an outstanding token request, and will remain valid until either the other port releases the token (which means the requester now becomes the new possessor of the token), or when the outstanding request is withdrawn by writing a one "1" to the semaphore before the other port releases the token. ________ Semaphore accesses are distinguished from the regular memory access through the use of the semaphore select (SEM) ________ signal: SEM should remain HIGH when the regular dual-port memory is being accessed, but should be tied LOW when _____ ____ semaphores are being accessed. Other control signals such as C E , and R/ W behave identically in both cases. Address pins A0 to A2 are used to address the eight semaphore flags (the values of the other address pins are irrelevant to semaphores). Only data pin D0 is used when writing to a semaphore. However, when reading from a semaphore, the one-bit semaphore value will be duplicated on all data pins (D0-D15). Note that the semaphore logic is not automatically initialized during power up. The system has to handle the initialization of the semaphores during power up by writing ones from both sides to all semaphores to ensure their availabilities for future use. As discussed previously, semaphores are typically used to resolve contentions of shared resources in a system. These shared resources can be a common data bus, a bi-directional shared buffer, or even a segment of the dual-port SRAM on an HBA HDV26 device. Before any component in the system attempts to gain exclusive access to a shared resource, the semaphore can be used to ensure that no resource contention or data corruption will occur. One advantage in using hardware-supported semaphores is performance improvement by eliminating the processor wait states. HBA HDV26 semaphores also provide system designers with higher flexibility because the resource sharing can be managed much more easily. With proper system software support, semaphores can even replace the Busy arbitration logic in certain cases, albeit with a coarser data granularity. 3HD163A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. PRELIMINARY Page 16 of 17 HDV26 ADP II SRAM Order Information: HBA Device Family Device Type Power Speed (ns)* Package** Temperature Range XX HD XXX V26 (16K x 16) X Low XX 15 XX J X Blank - Commercial (0C to 70C) 25 I - Industrial (-40 to 85C) 35 *Speed - Slower speeds available upon request. **Package - 84 pin Plastic Lead Chip Carrier (PLCC) Temperature - Industrial only offered in 25ns Example: HDV26L15J (16K x 16, 15ns, Commercial temp) USA 2107 North First Street, Suite 415 San Jose, CA 95131, USA Tel: 408.453.8885 Fax: 408.453.8886 www.hba.com Taiwan No. 81, Suite 8F-9, Shui-Lee Rd. Hsinchu, Taiwan, R.O.C. Tel: 886.3.516.9118 Fax: 886.3.516.9181 www.hba.com 3HD163A (c) 2003 High Bandwidth Access, Inc. All rights reserved. Product specifications subject to change without notice. Europe CDE Technology B.V. Nijverheidslaan 28 1382 L J Weesp, The Netherlands Tel: 31.294.280.914 Fax: 31.294.280.919 www.hba.com PRELIMINARY Page 17 of 17