AD7703CNZ - Analog Devices

REV. E

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AD7703

MOS

20-Bit A/D Converter

FEATURES

Monolithic 16-Bit ADC

0.0015% Linearity Error

On-Chip Self-Calibration Circuitry

Programmable Low-Pass Filter

0.1 Hz to 10 Hz Corner Frequency

0 V to +2.5 V or ⴞ2.5 V Analog Input Range

4 kSPS Output Data Rate

Flexible Serial Interface

Ultralow Power

APPLICATIONS

Industrial Process Control

Weigh Scales

Portable Instrumentation

Remote Data Acquisition

FUNCTIONAL BLOCK DIAGRAM

4 17

519

DGND

SC1 SC2

7 6

AGND

REF

CALIBRATION

SRAM

CALIBRATION

MICROCONTROLLER CAL

BP/UP

SLEEP

CLOCK

GENERATOR

SDATA

SCLK

2 18

CLKIN CLKOUT MODE CS DRDY

AD7703

ANALOG

MODULATOR

6-POLE GAUSSIAN

LOW-PASS

DIGITAL FILTER

20-BIT CHARGE BALANCE A/D

CONVERTER

3 161

SERIAL INTERFACE

LOGIC

GENERAL DESCRIPTION

The AD7703 is a 20-bit ADC that uses a S-D conversion tech-

nique. The analog input is continuously sampled by an analog

modulator whose mean output duty cycle is proportional to the

input signal. The modulator output is processed by an on-chip

digital filter with a six-pole Gaussian response, which updates the

output data register with 16-bit binary words at word rates up to

4kHz. The sampling rate, filter corner frequency, and output

word rate are set by a master clock input that may be supplied

externally, or by a crystal controlled on-chip clock oscillator.

The inherent linearity of the ADC is excellent and endpoint accu-

racy is ensured by self-calibration of zero and full scale, which

may be initiated at any time. The self-calibration scheme can

also be extended to null system offset and gain errors in the input

channel.

The output data is accessed through a flexible serial port, which

has an asynchronous mode compatible with UARTs and two

synchronous modes suitable for interfacing to shift registers or

the serial ports of industry-standard microcontrollers.

CMOS construction ensures low power dissipation, and a power-

down mode reduces the idle power consumption to only 10 µW.

PRODUCT HIGHLIGHTS

1. The AD7703 offers 20-bit resolution coupled with outstanding

0.0003% accuracy.

2. No missing codes ensures true, usable, 20-bit dynamic range,

removing the need for programmable gain and level-setting

circuitry.

3. The effects of temperature drift are eliminated by on-chip

self-calibration, which removes zero and gain error. External

circuits can also be included in the calibration loop to remove

system offsets and gain errors.

4. Flexible synchronous/asynchronous interface allows the

AD7703 to interface directly to the serial ports of industry-

standard microcontrollers and DSP processors.

5. Low operating power consumption and an ultralow power

standby mode make the AD7703 ideal for loop-powered

remote sensing applications, or battery-powered portable

instruments.

REV. E–2–

AD7703–SPECIFICATIONS

Parameter A/S Version

B Version

C Version

Unit Test Conditions/Comments

STATIC PERFORMANCE

Resolution 20 20 20 Bits

Integral Nonlinearity, T

MIN

to T

MAX

±0.0015 ±0.0007 ±0.0003 % FSR typ

25°C±0.003 ±0.0015 ±0.0008 % FSR max

MIN

to T

MAX

±0.003 ±0.0015 ±0.0012 % FSR max

Differential Nonlinearity, T

MIN

to T

MAX

±0.5 ±0.5 ±0.5 LSB typ Guaranteed No Missing Codes

Positive Full-Scale Error

±4 ±4 ±4 LSB typ

±16 ±16 ±16 LSB max

Full-Scale Drift

±19/±37 ±19 ±19 LSB typ

Unipolar Offset Error

±4 ±4 ±4 LSB typ

±16 ±16 ±16 LSB max

Unipolar Offset Drift

±26 ±26 ±26 LSB typ Temp Range: 0°C to +70°C

±67 +48/–400 ±67 ±67 LSB typ Specified Temp Range

Bipolar Zero Error

±4 ±4 ±4 LSB typ

±16 ±16 ±16 LSB max

Bipolar Zero Drift

±13 ±13 ±13 LSB typ Temp Range: 0°C to +70°C

±34 +24/–200 ±34 ±34 LSB typ Specified Temp Range

Bipolar Negative Full-Scale Errors

±8 ±8 ±8 LSB typ

±32 ±32 ±32 LSB max

Bipolar Negative Full-Scale Drift

±10/±20 ±10 ±10 LSB typ

Noise (Referred to Output) 1.6 1.6 1.6 LSB rms typ

DYNAMIC PERFORMANCE

Sampling Frequency, f

CLKIN

/256 f

CLKIN

/256 f

CLKIN

/256 Hz

Output Update Rate, f

OUT

CLKIN

/1024 f

CLKIN

/1024 f

CLKIN

/1024 Hz

Filter Corner Frequency, f

–3 dB

CLKIN

/409,600 f

CLKIN

/409,600 f

CLKIN

/409,600 Hz

Settling Time to ±0.0007% FS 507904/f

CLKIN

507904/f

CLKIN

507904/f

CLKIN

sec For Full-Scale Input Step

SYSTEM CALIBRATION

Positive Full-Scale Calibration Range V

REF

+ 0.1 V

REF

+ 0.1 V

REF

+ 0.1 V max System calibration applies to

Positive Full-Scale Overrange V

REF

+ 0.1 V

REF

+ 0.1 V

REF

+ 0.1 V max unipolar and bipolar ranges.

Negative Full-Scale Overrange –(V

REF

+ 0.1) –(V

REF

+ 0.1) –(V

REF

+ 0.1) V max After calibration, if A

> V

REF

Maximum Offset Calibration Ranges

5, 6

the device will output all 1s.

Unipolar Input Range –(V

REF

+ 0.1) –(V

REF

+ 0.1) –(V

REF

+ 0.1) V max If A

< 0 (unipolar) or –V

REF

Bipolar Input Range –0.4 V

REF

to +0.4 V

REF

–0.4 V

REF

to +0.4 V

REF

–0.4 V

REF

to +0.4 V

REF

V max (bipolar), the device will

Input Span

0.8 V

REF

0.8 V

REF

0.8 V

REF

V min output all 0s.

2 V

REF

+ 0.2 2 V

REF

+ 0.2 2 V

REF

+ 0.2 V max

ANALOG INPUT

Unipolar Input Range 0 to 2.5 0 to 2.5 0 to 2.5 V

Bipolar Input Range ±2.5 ±2.5 ±2.5 V

Input Capacitance 20 20 20 pF typ

Input Bias Current

111nA typ

LOGIC INPUTS

All Inputs Except CLKIN

INL

, Input Low Voltage 0.8 0.8 0.8 V max

INH

, Input High Voltage 2.0 2.0 2.0 V min

CLKIN

INL

, Input Low Voltage 0.8 0.8 0.8 V max

INH

, Input High Voltage 3.5 3.5 3.5 V min

, Input Current 10 10 10 µA max

LOGIC OUTPUTS

, Output Low Voltage 0.4 0.4 0.4 V max I

SINK

= 1.6 mA

, Output High Voltage DV

– 1DV

– 1V min I

SOURCE

= 100 µA

Floating State Leakage Current ±10 ±10 ±10 µA max

Floating State Output Capacitance 999pF typ

POWER REQUIREMENTS

Power Supply Voltages

Analog Positive Supply (AV

)4.5/5.5 4.5/5.5 4.5/5.5 V min/V max For Specified Performance

Digital Positive Supply (DV

)4.5/AV

4.5/AV

V min/V max

Analog Negative Supply (AV

)–4.5/–5.5 –4.5/–5.5 –4.5/–5.5 V min/V max

Digital Negative Supply (DV

)–4.5/–5.5 –4.5/–5.5 –4.5/–5.5 V min/V max

Calibration Memory Retention

Power Supply Voltage 2.0 2.0 2.0 V min

(TA = 25ⴗC; AVDD = DVDD = +5 V; AVSS = DVSS = –5 V; VREF = +2.5 V; fCLKIN = 4.096 MHz;

BP/UP = +5 V; MODE = +5 V; AIN Source Resistance = 1 k⍀1 with 1 nF to AGND at AIN; unless otherwise noted.)

REV. E

AD7703

–3–

Parameter A/S Version

B Version

C Version

Unit Test Conditions/Comments

POWER REQUIREMENTS

DC Power Supply Currents

Analog Positive Supply (AI

)2.7 2.7 2.7 mA max Typically 2 mA

Digital Positive Supply (DI

)2 22mA max Typically 1 mA

Analog Negative Supply (AI

)2.7 2.7 2.7 mA max Typically 2 mA

Digital Negative Supply (DI

)0.1 0.1 0.1 mA max Typically 0.03 mA

Power Supply Rejection

Positive Supplies 70 70 70 dB typ

Negative Supplies 75 75 75 dB typ

Power Dissipation

Normal Operation 37 37 37 mW max SLEEP = Logic 1,

Typically 25 mW

Standby Operations

SLEEP = Logic 0,

A, B, C 20 20 20 µW max Typically 10 µW

S404040µW max

NOTES

The A

pin presents a very high impedance dynamic load that varies with clock frequency. A ceramic 1 nF capacitor from the A

pin to AGND is necessary.

Source resistance should be 750  or less.

Temperature ranges are as follows: A, B, C Versions: –40°C to +85°C; S Version: –55°C to +125°C.

Applies after calibration at the temperature of interest. Full-scale error applies for both unipolar and bipolar input ranges.

Total drift over the specified temperature range after calibration at power-up at 25°C. This is guaranteed by design and/or characterization. Recalibration at any

temperature will remove these errors.

In Unipolar mode, the offset can have a negative value (–V

REF

) such that the Unipolar mode can mimic Bipolar mode operation.

The specifications for input overrange and for input span apply additional constraints on the offset calibration range.

For Unipolar mode, input span is the difference between full scale and zero scale. For Bipolar mode, input span is the difference between positive and negative full-scale

points. When using less than the maximum input span, the span range may be placed anywhere within the range of ±(V

REF

+ 0.1).

All digital outputs unloaded. All digital inputs at 5 V CMOS levels.

Applies in 0.1 Hz to 10 Hz bandwidth. PSRR at 60 Hz will exceed 120 dB due to the digital filter.

CLKIN is stopped. All digital inputs are grounded.

Specifications subject to change without notice.

ABSOLUTE MAXIMUM RATINGS

= 25°C, unless otherwise noted.)

to AGND . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

to AV

. . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V

to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V

to AGND . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –6 V

AGND to DGND . . . . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V

Digital Input Voltage to DGND . . . . –0.3 V to DV

+ 0.3 V

Analog Input Voltage to AGND . . . AV

– 0.3 V to AV

+ 0.3 V

Input Current to Any Pin Except Supplies

. . . . . . . . ±10 mA

Operating Temperature Range

Industrial (A, B, C Versions) . . . . . . . . . . . –40°C to +85°C

Extended (S Version) . . . . . . . . . . . . . . . . –55°C to +125°C

Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C

Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . . . 300°C

Power Dissipation (DIP Package) to 75°C . . . . . . . . . 450 mW

Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . 10 mW/°C

Power Dissipation (SOIC Package) to 75°C . . . . . . . 250 mW

Derates above 75°C by . . . . . . . . . . . . . . . . . . . . . . 15 mW/°C

NOTES

Stresses above those listed under Absolute Maximum Ratings may cause

permanent damage to the device. This is a stress rating only; functional operation

of the device at these or any other conditions above those listed in the

operational sections of this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may affect device reliability.

Transient currents of up to 100 mA will not cause SCR latch-up.

ORDERING GUIDE

Linearity

Temperature Error Package

Model Range (% FSR) Options*

AD7703AN –40°C to +85°C0.003 N-20

AD7703BN –40°C to +85°C0.0015 N-20

AD7703CN –40°C to +85°C0.0012 N-20

AD7703AR –40°C to +85°C0.003 R-20

AD7703BR –40°C to +85°C0.0015 R-20

AD7703CR –40°C to +85°C0.0012 R-20

AD7703AQ –40°C to +85°C0.003 Q-20

AD7703BQ –40°C to +85°C0.0015 Q-20

AD7703CQ –40°C to +85°C0.0012 Q-20

AD7703SQ –55°C to +125°C0.003 Q-20

*N = Plastic DIP; R = SOIC; Q = CERDIP.

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily

accumulate on the human body and test equipment and can discharge without detection. Although the

AD7703 features proprietary ESD protection circuitry, permanent damage may occur on devices

subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended

to avoid performance degradation or loss of functionality.

REV. E–4–

AD7703

Limit at T

MIN

, T

MAX

Limit at T

MIN

, T

MAX

Parameter (A, B Versions) (S, T Versions) Unit Conditions/Comments

CLKIN3, 4

200 200 kHz min Master Clock Frequency: Internal Gate Oscillator

55MHz max Typically 4.096 MHz

200 200 kHz min Master Clock Frequency: Externally Supplied

55MHz max

50 50 ns max Digital Output Rise Time. Typically 20 ns.

50 50 ns max Digital Output Fall Time. Typically 20 ns.

00ns min SC1, SC2 to CAL High Setup Time

50 50 ns min SC1, SC2 Hold Time after CAL Goes High

1000 1000 ns min SLEEP High to CLKIN High Setup Time

SSC MODE

3/f

CLKIN

3/f

CLKIN

ns max Data Access Time (CS Low to Data Valid)

100 100 ns max SCLK Falling Edge to Data Valid Delay (25 ns typ)

250 250 ns min MSB Data Setup Time. Typically 380 ns.

300 300 ns max SCLK High Pulsewidth. Typically 240 ns.

790 790 ns max SCLK Low Pulsewidth. Typically 730 ns.

l/f

CLKIN

+ 200 l/f

CLKIN

+ 200 ns max SCLK Rising Edge to Hi-Z Delay (l/f

CLKIN

+ 100 ns typ)

108, 9

4/f

CLKIN

+ 200 4/f

CLKIN

+ 200 ns max CS High to Hi-Z Delay

SEC MODE

SCLK

55MHz max Serial Clock Input Frequency

35 35 ns min SCLK Input High Pulsewidth

160 160 ns min SCLK Low Pulsewidth

137, 10

160 160 ns max Data Access Time (CS Low to Data Valid). Typically 80 ns.

1411

150 150 ns max SCLK Falling Edge to Data Valid Delay. Typically 75 ns.

158

250 250 ns max CS High to Hi-Z Delay

168

200 200 ns max SCLK Falling Edge to Hi-Z Delay. Typically 100 ns.

NOTES

Sample tested at 25°C to ensure compliance. All input signals are specified with t

= t

= 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

See Figures 1 to 6.

CLKIN duty cycle range is 20% to 80%. CLKIN must be supplied whenever the AD7703 is not in SLEEP mode. If no clock is present in this case, the device

can draw higher current than specified and possibly become uncalibrated.

The AD7703 is production tested with f

CLKIN

at 4.096 MHz. It is guaranteed by characterization to operate at 200 kHz.

Specified using 10% and 90% points on waveform of interest.

In order to synchronize several AD7703s together using the SLEEP pin, this specification must be met.

and t

are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.

, t

, and t

are derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number

is then extrapolated back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the Timing Characteristics is

the true bus relinquish time of the part and as such is independent of external bus loading capacitance.

If CS is returned high before all 20 bits are output, the SDATA and SCLK outputs will complete the current data bit and then go to high impedance.

If CS is activated asynchronously to DRDY, CS will not be recognized if it occurs when DRDY is high for four clock cycles. The propagation delay time may be

as great as four CLKIN cycles plus 160 ns. To guarantee proper clocking of SDATA when using asynchronous CS, the SCLK input should not be taken high

sooner than four CLKIN cycles plus 160 ns after CS goes low.

SDATA is clocked out on the falling edge of the SCLK input.

Specifications subject to change without notice.

TIMING CHARACTERISTICS

1, 2

(AVDD = DVDD = +5 V ⴞ 10%; AVSS = DVSS = –5 V ⴞ 10%; AGND = DGND = O V;

fCLKIN = 4.096 MHz; Input Levels: Logic O = O V, Logic 1 = DVDD; unless otherwise noted.)

100pF

OUTPUT

IOH

200␮A

2.1V

1.6mA

Figure 1. Load Circuit for Access Time

and Bus Relinquish Time

CAL

SC1, SC2 SC1, SC2 VALID

Figure 2. Calibration Control Timing

CLKIN

SLEEP

Figure 3. Sleep Mode Timing

REV. E

AD7703

–5–

DATA

VA L I D

t15

HI-Z

SDATA

Figure 5b. SEC Mode Data Hold Time

HI-Z

DB19 DB18 DB1 DB0

HI-Z

SCLK

SDATA

CLKIN

HI-Z

Figure 6. SSC Mode Timing Diagram

DEFINITION OF TERMS

Linearity Error

This is the maximum deviation of any code from a straight line

passing through the endpoints of the transfer function. The

endpoints of the transfer function are zero-scale (not to be

confused with bipolar zero), a point 0.5 LSB below the first code

transition (000 . . . 000 to 000 . . . 001) and full-scale, a point

1.5 LSB above the last code transition (111 . . . 110 to 111 . . .

111). The error is expressed as a percentage of full scale.

Differential Linearity Error

This is the difference between any code’s actual width and the

ideal (1 LSB) width. Differential linearity error is expressed in

LSB. A differential linearity specification of ±1 LSB or less

guarantees monotonicity.

Positive Full-Scale Error

Positive full-scale error is the deviation of the last code transition

(111 . . . 110 to 111 . . . 111) from the ideal (V

REF

±3/2 LSB).

It applies to both positive and negative analog input ranges and

is expressed in microvolts.

Unipolar Offset Error

Unipolar offset error is the deviation of the first code transition

from the ideal (AGND + 0.5 LSB) when operating in the

Unipolar mode.

Bipolar Zero Error

This is the deviation of the midscale transition (0111 . . . 111 to

1000 . . . 000) from the ideal (AGND – 0.5 LSB) when operating

in the Bipolar mode. It is expressed in microvolts.

Bipolar Negative Full-Scale Error

This is the deviation of the first code transition from the ideal

(–V

REF

+ 0.5 LSB) when operating in the Bipolar mode.

Positive Full-Scale Overrange

Positive full-scale overrange is the amount of overhead available

to handle input voltages greater than +V

REF

(for example, noise

peaks or excess voltages due to system gain errors in system

calibration routines) without introducing errors due to overloading

the analog modulator or overflowing the digital filter.

Negative Full-Scale Overrange

This is the amount of overhead available to handle voltages below

–V

REF

without overloading the analog modulator or overflowing

the digital filter. Note that the analog input will accept negative

voltage peaks even in the Unipolar mode.

Offset Calibration Range

In the system calibration modes (SC2 low), the AD7703 calibrates

its offset with respect to the A

pin. The offset calibration range

specification defines the range of voltages, expressed as a

percentage of V

REF

, that the AD7703 can accept and still accurately

calibrate offset.

Full-Scale Calibration Range

This is the range of voltages that the AD7703 can accept in the

system calibration mode and still correctly calibrate full scale.

Input Span

In system calibration schemes, two voltages applied in sequence

to the AD7703’s analog input define the analog input range. The

input span specification defines the minimum and maximum

input voltages from zero to full scale that the AD7703 can accept

and still accurately calibrate gain. The input span is expressed

as a percentage of V

REF.

DATA

VA L I D

HI-Z

SDATA

Figure 4. SSC Mode Data Hold Time

HI-Z

DB18 DB1 DB0

HI-Z

SDATA

DRDY

t12

t11

t13 t14

SCLK

t16

DB19

Figure 5a. SEC Mode Timing Diagram

REV. E–6–

AD7703

PIN CONFIGURATION

DIP, CERDIP, SOIC

MODE

SC1

DGND

CLKOUT

CLKIN

AGND

DVSS

AVSS

AIN

VREF

SDATA

SCLK

SC2

CAL

AVDD

DVDD

DRDY

BP/UP

SLEEP

TOP VIEW

(Not to Scale)

AD7703

Table I. Bit Weight Table (2.5 V Reference Voltage)

Unipolar Mode Bipolar Mode

ppm ppm

␮VLSB % FS FS LSB % FS FS

0.596 0.25 0.0000238 0.24 0.13 0.0000119 0.12

1.192 0.5 0.0000477 0.48 0.26 0.0000238 0.24

2.384 1.00 0.0000954 0.95 0.5 0.0000477 0.48

4.768 2.00 0.0001907 1.91 1.00 0.0000954 0.95

9.537 4.00 0.0003814 3.81 2.00 0.0001907 1.91

PIN FUNCTION DESCRIPTIONS

Pin No. Mnemonic Description

1MODE Selects the Serial Interface Mode. If MODE is tied to DGND, the Synchronous External Clocking (SEC)

mode is selected. SCLK is configured as an input, and the output appears without formatting, the MSB

coming first. If MODE is tied to +5 V, the AD7703 operates in the Synchronous Self-Clocking (SSC) mode.

SCLK is configured as an output, with a clock frequency for f

CLKIN

/4 and 25% duty cycle.

2CLKOUT Clock Output to Generate an Internal Master Clock by Connecting a Crystal between CLKOUT and CLKIN.

If an external clock is used, CLKOUT is not connected.

3CLKIN Clock Input for External Clock.

4, 17 SC1, SC2 System Calibration Pins. The state of these pins, when CAL is taken high, determines the type of calibration

performed.

5DGND Digital Ground. Ground reference for all digital signals.

6DV

Digital Negative Supply, –5 V Nominal.

7AV

Analog Negative Supply, –5 V Nominal.

8AGND Analog Ground. Ground reference for all analog signals.

Analog Input.

10 V

REF

Voltage Reference Input, 2.5 V Nominal. This determines the value of positive full scale in the Unipolar

mode and the value of both positive and negative full scale in the Bipolar mode.

11 SLEEP Sleep Mode Pin. When this pin is taken low, the AD7703 goes into a low power mode with typically 10 µW

power consumption.

12 BP/UP Bipolar/Unipolar Mode Pin. When this pin is low, the AD7703 is configured for a unipolar input range going

from AGND to V

REF

. When Pin 12 is high, the AD7703 is configured for a bipolar input range, ±V

REF

13 CAL Calibration Mode Pin. When CAL is taken high for more than four cycles, the AD7703 is reset and performs

a calibration cycle when CAL is brought low again. The CAL pin can also be used as a strobe to synchronize

the operation of several AD7703s.

14 AV

Analog Positive Supply, 5 V Nominal.

15 DV

Digital Positive Supply, 5 V Nominal.

16 CS Chip Select Input. When CS is brought low, the AD7703 will begin to transmit serial data in a format determined

by the state of the MODE pin.

18 DRDY Data Ready Output. DRDY is low when valid data is available in the output register. It goes high after trans-

mission of a word is completed. It also goes high for four clock cycles when a new data-word is being loaded

into the output register, to indicate that valid data is not available, irrespective of whether data transmission

is complete or not.

19 SCLK Serial Clock Input/Output. The SCLK pin is configured as an input or output, dependent on the type of

serial data transmission that has been selected by the MODE pin. When configured as an output in the

Synchronous Self-Clocking mode, it has a frequency of f

CLKIN

/4 and a duty cycle of 25%.

20 SDATA Serial Data Output. The AD7703’s output data is available at this pin as a 20-bit serial word.

REV. E

AD7703

–7–

GENERAL DESCRIPTION

The AD7703 is a 20-bit A/D converter with on-chip digital

filtering, intended for the measurement of wide dynamic range,

low frequency signals such as those representing chemical,

physical, or biological processes. It contains a charge-balancing

(⌺-⌬) ADC, calibration microcontroller with on-chip static

RAM, clock oscillator, and serial communications port.

The analog input signal to the AD7703 is continuously sampled

at a rate determined by the frequency of the master clock, CLKIN.

A charge-balancing A/D converter (⌺-⌬ modulator) converts

the sampled signal into a digital pulse train whose duty cycle

contains the digital information. A six-pole Gaussian digital

low-pass filter processes the output of the ⌺-⌬ modulator and

updates the 20-bit output register at a 4 kHz rate. The output

data can be read from the serial port randomly or periodically at

any rate up to 4 kHz.

AD7703

MODE

SDATA

SC1

DGND

CLKOUT

CLKIN

AGND

SCLK

SC2

CAL

BP/UP

SLEEP

RANGE

SELECT

CALIBRATE

ANALOG

INPUT

ANALOG

GROUND

–5V

ANALOG

SUPPLY

0.1␮F

+5V

ANALOG

SUPPLY

2.5V

0.1␮F

DRDY

0.1␮F

10␮F

REF

VOLTAG E

REFERENCE

10␮F

DATA READY

READ

(TRANSMIT)

SERIAL CLOCK

SERIAL DATA

Figure 7. Typical System Connection Diagram

The AD7703 can perform self-calibration using the on-chip

calibration microcontroller and SRAM to store calibration

parameters. A calibration cycle may be initiated at any time

using the CAL control input.

Other system components may also be included in the calibra-

tion loop to remove offset and gain errors in the input channel.

For battery operation, the AD7703 also offers a standby mode

that reduces idle power consumption to typically 10 µW.

THEORY OF OPERATION

The general block diagram of a ⌺-⌬ ADC is shown in Figure 8.

It contains the following elements:

1. A sample-hold amplifier

2. A differential amplifier or subtracter

3. An analog low-pass filter

4. A 1-bit A/D converter (comparator)

5. A 1-bit DAC

6. A digital low-pass filter

ANALOG

LOW-PASS

FILTER

COMPARATOR

DIGITAL DATA

S/H AMP

DAC

DIGITAL

FILTER

Figure 8. General

⌺

⌬

ADC

In operation, the analog signal sample is fed to the subtracter,

along with the output of the 1-bit DAC. The filtered difference

signal is fed to the comparator, whose output samples the differ-

ence signal at a frequency many times that of the analog signal

sampling frequency (oversampling).

Oversampling is fundamental to the operation of ⌺-⌬ ADCs.

Using the quantization noise formula for an ADC

SNR = (6.02 ¥ number of bits + 1.76) dB

a 1-bit ADC or comparator yields an SNR of 7.78 dB.

The AD7703 samples the input signal at 16 kHz, which spreads

the quantization noise from 0 kHz to 8 kHz. Since the specified

analog input bandwidth of the AD7703 is only 0 Hz to 10 Hz, the

noise energy in this bandwidth would be only 1/800 of the total

quantization noise, even if the noise energy were spread evenly

throughout the spectrum. It is reduced still further by analog

filtering in the modulator loop, which shapes the quantization

noise spectrum to move most of the noise energy to frequencies

above 10 Hz. The SNR performance in the 0 Hz to 10 Hz range

is conditioned to the 20-bit level in this fashion.

The output of the comparator provides the digital input for the

1-bit DAC, so the system functions as a negative feedback loop

that minimizes the difference signal. The digital data that repre-

sents the analog input voltage is in the duty cycle of the pulse train

appearing at the output of the comparator. It can be retrieved as

a parallel binary data-word using a digital filter.

⌺-⌬ ADCs are generally described by the order of the analog

low-pass filter. A simple example of a first-order, ⌺-⌬ ADC is

shown in Figure 8. This contains only a first-order, low-pass

filter or integrator. It also illustrates the derivation of the alter-

native name for these devices: charge-balancing ADCs.

The AD7703 uses a second-order, ⌺-⌬ modulator and a sophis-

ticated digital filter that provides a rolling average of the sampled

output. After power-up or if there is a step change in the input

voltage, there is a settling time that must elapse before valid

data is obtained.

REV. E–8–

AD7703

DIGITAL FILTERING

The AD7703’s digital filter behaves like an analog filter, with a

few minor differences.

First, since digital filtering occurs after the analog-to-digital

conversion, it can remove noise injected during the conversion

process. Analog filtering cannot do this.

On the other hand, analog filtering can remove noise superim-

posed on the analog signal before it reaches the ADC. Digital

filtering cannot do this and noise peaks riding on signals near

full scale have the potential to saturate the analog modulator and

digital filter, even though the average value of the signal is within

limits. To alleviate this problem, the AD7703 has overrange

headroom built into the ⌺-⌬ modulator and digital filter that

allows overrange excursions of 100 mV. If noise signals are larger

than this, consideration should be given to analog input filtering,

or to reducing the gain in the input channel so that a full-scale

input (2.5 V) gives only a half-scale input to the AD7703 (1.25 V).

This will provide an overrange capability greater than 100% at

the expense of reducing the dynamic range by one bit (50%).

FILTER CHARACTERISTICS

The cutoff frequency of the digital filter is f

CLK

/409600. At the

maximum clock frequency of 4.096 MHz, the cutoff frequency

of the filter is 10 Hz and the data update rate is 4 kHz.

Figure 9 shows the filter frequency response. This is a six-pole

Gaussian response that provides 55 dB of 60 Hz rejection for a

10 Hz cutoff frequency. If the clock frequency is halved to give a

5 Hz cutoff, 60 Hz rejection is better than 90 dB.

110 100

FREQUENCY – Hz

–20

–40

–60

–80

–100

–120

–140

–160

GAIN – dB

CLK = 1MHz

CLK = 2MHz

CLK = 4MHz

Figure 9. Frequency Response of AD7703 Filter

Since the AD7703 contains this low-pass filtering, there is a

settling time associated with step function inputs, and data will

be invalid after a step change until the settling time has elapsed.

The AD7703 is, therefore, unsuitable for high speed multiplex-

ing, where channels are switched and converted sequentially at

high rates, as switching between channels can cause a step change

in the input. However, slow multiplexing of the AD7703 is

possible, provided that the settling time is allowed to elapse

before data for the new channel is accessed.

The output settling of the AD7703 in response to a step input

change is shown in Figure 10. The Gaussian response has fast

settling with no overshoot, and the worst-case settling time to

±0.0007% is 125 ms with a 4.096 MHz master clock frequency.

PERCENT OF FINAL VALUE

100

04080120 160

TIME – ms

Figure 10. AD7703 Step Response

USING THE AD7703

SYSTEM DESIGN CONSIDERATIONS

The AD7703 operates differently from successive approximation

ADCs or integrating ADCs. Since it samples the signal continu-

ously, like a tracking ADC, there is no need for a start convert

command. The 20-bit output register is updated at a 4 kHz rate,

and the output can be read at any time, either synchronously or

asynchronously.

CLOCKING

The AD7703 requires a master clock input, which may be an exter-

nal TTL/CMOS compatible clock signal applied to the CLKIN

pin (CLKOUT not used). Alternatively, a crystal of the correct

frequency can be connected between CLKIN and CLKOUT,

when the clock circuit will function as a crystal controlled oscillator.

Figure 11 shows a simple model of the on-chip gate oscillator

and Table II gives some typical capacitor values to be used with

various resonators.

AD7703

C2*

C1*

5M⍀

10pF

gm = 1500␮MHO

*SEE TABLE II

Figure 11. On-Chip Gate Oscillator

REV. E

AD7703

–9–

Table II. Resonator Loading Capacitors

Resonators C1 (pF) C2 (pF)

Ceramic

200 kHz 330 470

455 kHz 100 100

1.0 MHz 50 50

2.0 MHz 20 20

Crystal

2.000 MHz 30 30

3.579 MHz 20 20

4.096 MHz None None

The input sampling frequency, output data rate, filter character-

istics, and calibration time are all directly related to the master

clock frequency, f

CLKIN

, by the ratios given in the Specification

table under Dynamic Performance. Therefore, the first step in

system design with the AD7703 is to select a master clock fre-

quency suitable for the bandwidth and output data rate required

by the application.

ANALOG INPUT RANGES

The AD7703 performs conversion relative to an externally

supplied reference voltage that allows easy interfacing to ratio-

metric systems. In addition, either unipolar or bipolar input

voltage ranges may be selected using the BP/UP input. With

BP/UP tied low, the input range is unipolar and the span is

REF

to V

AGND

), where V

AGND

is the voltage at the device AGND

pin. With BP/UP tied high, the input range is bipolar and the

span is 2V

REF

. In the Bipolar mode, both positive and negative

full scale are directly determined by V

REF

. This offers superior

tracking of positive and negative full scale and better midscale

(bipolar zero) stability than bipolar schemes that simply scale

and offset the input range.

The digital output coding for the unipolar range is unipolar binary;

for the bipolar range it is offset binary. Bit weights for the Unipolar

and Bipolar modes are shown in Table I.

ACCURACY

S-D ADCs, like VFCs and other integrating ADCs, do not

contain any source of nonmonotonicity and inherently offer

no-missing-codes performance.

The AD7703 achieves excellent linearity by the use of high

quality, on-chip silicon dioxide capacitors, which have a very

low capacitance/voltage coefficient. The device also achieves low

input drift through the use of chopper-stabilized techniques in

its input stage. To ensure excellent performance over time and

temperature, the AD7703 uses digital calibration techniques

that minimize offset and gain error to typically ±4 LSB.

AUTOCALIBRATION

The AD7703 offers both self-calibration and system-calibration

facilities. For calibration to occur, the on-chip microcontroller

must record the modulator output for two different input condi-

tions. These are the zero-scale and full-scale points. In Unipolar

self-calibration mode, the zero-scale point is V

AGND

and the

full-scale point is V

REF

. With these readings, the microcontroller

can calculate the gain slope for the input to output transfer

function of the converter. In Unipolar mode, the slope factor is

determined by dividing the span between zero and full scale by

. In Bipolar mode, it is determined by dividing the span by

since the inputs applied represent only half the total codes.

In both Unipolar and Bipolar modes, the slope factor is saved

and used to calculate the binary output code when an analog

input is applied to the device. Table IV gives the output code

size after calibration.

System calibration allows the AD7703 to compensate for system

gain and offset errors. A typical circuit where this might be used

is shown in Figure 12.

System calibration performs the same slope factor calculations

as self-calibration but uses voltage values presented by the system

to the A

pin for the zero- and full-scale points. There are two

system calibration modes.

The first mode offers system level calibration for system offset

and system gain. This is a two step operation. The zero-scale

point must be presented to the converter first. It must be applied

to the converter before the calibration step is initiated and remain

stable until the step is complete. The DRDY output from the

device will signal when the step is complete by going low. After

the zero-scale point is calibrated, the full-scale point is applied

and the second calibration step is initiated. Again, the voltage

must remain stable throughout the calibration step.

The two step calibration mode offers another feature. After the

sequence has been completed, additional offset calibrations can be

performed by themselves to adjust the zero reference point to a

new system zero reference value. This second system calibration

mode uses an input voltage for the zero-scale calibration point

but uses the V

REF

value for the full-scale point.

SYSTEM

REF HI

SYSTEM

REF LO

ANALOG

MUX

A0 A1

SIGNAL

CONDITIONING

AD7703

SCLK

SDATA

CAL

SC1

SC2

MICRO-

COMPUTER

Figure 12. Typical Connections for System Calibration

REV. E–10–

AD7703

Initiating Calibration

Table III illustrates the calibration modes available in the AD7703.

Not shown in the table is the function of the BP/UP pin, which

determines whether the converter has been calibrated to mea-

sure bipolar or unipolar signals. A calibration step is initiated by

bringing the CAL pin high for at least four CLKIN cycles and

then bringing it low again. The states of SC1 and SC2 along

with the BP/UP pin will determine the type of calibration to be

performed. All three signals should be stable before the CAL

pin is taken positive. The SC1 and SC2 inputs are latched when

CAL goes high. The BP/UP input is not latched and, therefore,

must remain in a fixed state throughout the calibration and

measurement cycles. Any time the state of the BP/UP is changed,

a new calibration cycle must be performed to enable the AD7703

to function properly in the new mode.

When a calibration step is initiated, the DRDY signal will go high

and remain high until the step is finished. Table III shows the

number of clock cycles each calibration requires. Once a calibra-

tion step is initiated, it must finish before a new calibration step

can be executed. In the two step system calibration mode, the

offset calibration step must be initiated before initiating the gain

calibration step.

When self-calibration is completed, DRDY falls and the output

port is updated with a data-word that represents the analog input

signal. When a system calibration step is completed, DRDY will

fall and the output port will be updated with the appropriate data

value (all 0s for the zero-scale point and all 1s for the full-scale

point). In the system calibration mode, the digital filter must

settle before the output code will represent the value of the

analog input signal. Tables IV and V indicate the output code

size and output coding of the AD7703 in its various modes. In

these tables, S

OFF

is the measured system offset in volts and

GAIN

is the measured system gain at the full-scale point in volts.

Span and Offset Limits

Whenever a system calibration mode is used, there are limits

on the amount of offset and span that can be accommodated.

The range of input span in both the Unipolar and Bipolar

modes has a minimum value of 0.8 V

REF

and a maximum

value of 2(V

REF

+ 0.1 V).

The amount of offset that can be accommodated depends on

whether the Unipolar or Bipolar mode is being used. In Unipolar

mode, the system calibration modes can handle a maximum

offset of 0.2 V

REF

and a minimum offset of –(V

REF

+ 0.1 V).

Therefore the AD7703 in the Unipolar mode can be calibrated

to mimic bipolar operation.

Table III. Calibration Truth Table*

Calibration Zero-Scale Full-Scale Calibration

CAL SC1 SC2 Type Calibration Calibration Sequence Time

00 Self-Calibration V

AGND

REF

One Step 3,145,655 Clock Cycles

11 System Offset A

First Step 1,052,599 Clock Cycles

01 System Gain A

Second Step 1,068,813 Clock Cycles

10 System Offset A

REF

One Step 2,117,389 Clock Cycles

*DRDY remains high throughout the calibration sequence. In the Self-Calibration mode, DRDY falls once the AD7703 has settled to the analog input. In all other

modes, DRDY falls as the device begins to settle.

Table IV. Output Code Size After Calibration

1 LSB

Calibration Mode Zero Scale Gain Factor Unipolar Bipolar

Self-Calibration V

AGND

REF

(VREF –VAGND )

1048576

2(VREF –VAGND )

1048576

System Calibration S

OFF

GAIN

–S

OFF

)

1048576

2(SGAIN –SOFF )

1048576

REV. E

AD7703

–11–

Table V. Output Coding

nput Voltage, Unipolar Mode

nput Voltage, Bipolar Mode

System Calibration Self-Calibration Output Codes Self-Calibration System Calibration

>(S

GAIN

–1.5 LSB) >(V

REF

– 1.5 LSB) FFFFF >(V

REF

–1.5 LSB) >(S

GAIN

– 1.5 LSB)

GAIN

– 1.5 LSB V

REF

– 1.5 LSB

FFFFF

FFFFE

REF

– 1.5 LSB S

GAIN

– 1.5 LSB

GAIN

– S

OFF

)/2 – 0.5 LSB (V

REF

– V

AGND

)/2 – 0.5 LSB

80000

7FFFF

AGND

– 0.5 LSB S

OFF

– 0.5 LSB

OFF

+ 0.5 LSB V

AGND

+ 0.5 LSB

00001

00000

–V

REF

+ 0.5 LSB –S

GAIN

+ 2 S

OFF

+ 0.5 LSB

<(S

OFF

+ 0.5 LSB) <(V

AGND

+ 0.5 LSB) 00000 <(–V

REF

+ 0.5 LSB) <(–S

GAIN

+2 S

OFF

+ 0.5 LSB)

In the Bipolar mode, the system offset calibration range is

restricted to ±0.4 V

REF

. It should be noted that the span restric-

tions limit the amount of offset that can be calibrated. The span

range of the converter in Bipolar mode is equidistant around the

voltage used for the zero-scale point. When the zero-scale point

is calibrated, it must not cause either of the two endpoints of the

bipolar transfer function to exceed the positive or the negative

input overrange points (+V

REF

+ 0.1) V or (–V

REF

+ 0.1) V. If

the span range is set to a minimum (0.8 V

REF

), the offset voltage

can move +0.4 V

REF

without causing the endpoints of the trans-

fer function to exceed the overrange points. Alternatively, if the

span range is set to 2V

REF

, the input offset cannot move more

than +0.1 V or –0.1 V before an endpoint of the transfer func-

tion exceeds the input overrange limit.

POWER-UP AND CALIBRATION

A calibration cycle must be carried out after power-up to initial-

ize the device to a consistent starting condition and correct

calibration. The CAL pin must be held high for at least four

clock cycles, after which calibration is initiated on the falling

edge of CAL and takes a maximum of 3,145,655 clock cycles

(approximately 768 ms with a 4.096 MHz clock). See Table III.

The type of calibration cycle initiated by CAL is determined by

the SC1 and SC2 inputs, in accordance with Table III.

Drift Considerations

The AD7703 uses chopper stabilization techniques to minimize

input offset drift. Charge injection in the analog switches and

leakage currents at the sampling node are the primary sources of

offset voltage drift in the converter. Figure 13 indicates the typical

offset due to temperature changes after calibration at 25°C. Drift

is relatively flat up to 75°C. Above this temperature, leakage

current becomes the main source of offset drift. Since leakage

current doubles approximately every 10°C, the offset drifts

accordingly. The value of the voltage on the sample capacitor is

updated at a rate determined by the master clock; therefore, the

amount of offset drift that occurs will be proportional to the

elapsed time between samples. Thus, to minimize offset drift at

higher temperatures, higher CLKIN rates are recommended.

Gain drift within the converter depends mainly upon the tem-

perature tracking of the internal capacitors. It is not affected by

leakage currents so it is significantly less than offset drift. The

typical gain drift of the AD7703 is less than 40 LSB over the

specified temperature range.

Measurement errors due to offset drift or gain drift can be

eliminated at any time by recalibrating the converter. Using the

system calibration mode can also minimize offset and gain errors

in the signal conditioning circuitry. Integral and differential

linearity are not significantly affected by temperature changes.

BIPOLAR OFFSET – LSBs

160

–80

–160

–240

–320

–55 5 25 105 125

TEMPERATURE – ⴗC

–35 –15 45 65 85

CLKIN = 4.096MHz

Figure 13. Typical Bipolar Offset vs. Temperature

after Calibration at 25°C

REV. E–12–

AD7703

INPUT SIGNAL CONDITIONING

Reference voltages from 1 V to 3 V may be used with the AD7703,

with little degradation in performance. Input ranges that cannot

be accommodated by this range of reference voltages may be

achieved by input signal conditioning. This may take the form of

gain to accommodate a smaller signal range, or passive attenua-

tion to reduce a larger input voltage range.

Source Resistance

If passive attenuators are used in front of the AD7703, care must

be taken to ensure that the source impedance is sufficiently low.

The dc input resistance for the AD7703 is over 1 GW. In paral-

lel with this, there is a small dynamic load that varies with the

clock frequency (see Figure 14).

AIN

R2 CEXT

AGND

AD7703

V OS 100mV

VIN

1G⍀

CIN

10pF

Figure 14. Equivalent Input Circuit and Input Attenuator

Each time the analog input is sampled, a 10 pF capacitor draws a

charge packet of maximum 1 pC (10 pF ¥ 100 mV) from the

analog source with a frequency f

CLKIN

/256. For a 4.096 MHz

CLKIN, this yields an average current draw of 16 nA. After

each sample, the AD7703 allows 62 clock periods for the input

voltage to settle. The equation that defines settling time is

VO=VIN [1 –e–t/RC ]

where V

, is the final settled value, V

, is the value of the input

signal, R is the value of the input source resistance, and C is the

10 pF sample capacitor. The value of t is equal to 62/f

CLKIN

The following equation can be developed, which gives the maxi-

mum allowable source resistance, R

S(MAX)

, for an error of V

RfpFmVV

SMAX

CLKIN E

()

()( /)

=¥¥

10 100ln

Provided the source resistance is less than this value, the analog

input will settle within the desired error band in the requisite 62

clock periods. Insufficient settling leads to offset errors. These

can be calibrated in system calibration schemes.

If a limit of 600 nV (0.25 LSB at 20 bits) is set for the maximum

offset voltage, then the maximum allowable source resistance is

125 kW from the above equation, assuming that there is no

external stray capacitance.

An RC filter may be added in front of the AD7703 to reduce

high frequency noise. With an external capacitor added from

to AGND, the following equation will specify the maximum

allowable source resistance:

fCC

mV C

S MAX

CLKIN IN EXT

IN EXT

()

() ()

¥+ ¥

¥+

100

The practical limit to the maximum value of source resistance is

thermal (Johnson) noise. A practical resistor may be modeled as

an ideal (noiseless) resistor in series with a noise voltage source

or in parallel with a noise current source:

V kTRf Volts

n=4

ikTf R Amperes

n=4/

where k is Boltzmann’s constant (1.38 ¥ 10

–23

J/K), and T is

temperature in degrees Kelvin (°C + 273).

Active signal conditioning circuits such as op amps generally do

not suffer from problems of high source impedance. Their open-

loop output resistance is normally only tens of ohms and, in any

case, most modern general-purpose op amps have sufficiently fast

closed-loop settling time for this not to be a problem. Offset volt-

age in op amps can be eliminated in a system calibration routine.

Antialias Considerations

The digital filter of the AD7703 does not provide any rejection

at integer multiples of the sampling frequency (nf

CLKIN

/256,

where n = 1, 2, 3 . . . ).

With a 4.096 MHz master clock, there are narrow (±10 Hz)

bands at 16 kHz, 32 kHz, 48 kHz, and so on, where noise passes

unattenuated to the output.

However, due to the AD7703’s high oversampling ratio of 800

(16 kHz to 20 Hz), these bands occupy only a small fraction of

the spectrum, and most broadband noise is filtered.

The reduction in broadband noise is given by

ee ff e

out in C S in

==20035/.

where e

and e

out

are rms noise terms referred to the input, f

the filter –3 dB corner frequency (f

CLKIN

/409600), and f

is the

sampling frequency (f

CLKIN

/256).

Since the ratio of f

to f

CLKIN

is fixed, the digital filter reduces

broadband white noise by 96.5% independent of the master

clock frequency.

REV. E

AD7703

–13–

VOLTAGE REFERENCE CONNECTIONS

The voltage applied to the V

REF

pin defines the analog input

range. The specified reference voltage is 2.5 V, but the AD7703

will operate with reference voltages from 1 V to 3 V with little

degradation in performance.

The reference input presents exactly the same dynamic load as

the analog input, but in the case of the reference input, source

resistance and long settling time introduce gain errors rather

than offset errors. Fortunately, most precision references have

sufficiently low output impedance and wide enough bandwidth

to settle to the required accuracy within 62 clock cycles.

The digital filter of the AD7703 removes noise from the reference

input, just as it does with noise at the analog input, and the same

limitations apply regarding lack of noise rejection at integer

multiples of the sampling frequency. Note that the reference

should be chosen to minimize noise below 10 Hz. The AD7703

typically exhibits 1.6 LSB rms noise in its measurements. This

specification assumes a clean reference. Many monolithic band gap

references are available, which can supply the 2.5 V needed for

the AD7703. However, some of these are not specified for noise,

especially in the 0.1 Hz to 10 Hz bandwidth. If the reference noise

in this bandwidth is excessive, it can degrade the performance of

the AD7703. Recommended references are the AD580 and the

LT1019. Both of these 2.5 V references typically have less than

10 µV p-p noise in the 0.1 Hz to 10 Hz band.

POWER SUPPLIES AND GROUNDING

AGND is the ground reference voltage for the AD7703, and is

completely independent of DGND. Any noise riding on the AGND

input with respect to the system analog ground will cause con-

version errors. AGND should, therefore, be used as the system

ground and also as the ground for the analog input and the

reference voltage.

The analog and digital power supplies to the AD7703 are inde-

pendent and separately pinned out to minimize coupling between

analog and digital sections of the device. The digital filter will

provide rejection of broadband noise on the power supplies,

except at integer multiples of the sampling frequency. There-

fore, the two analog supplies should be individually decoupled

to AGND using 100 nF ceramic capacitors to provide power

supply noise rejection at these frequencies. The two digital

supplies should similarly be decoupled to DGND.

The positive digital supply (DV

) must never exceed the positive

analog supply (AV

) by more than 0.3 V. Power supply sequenc-

ing is, therefore, important. If separate analog and digital supplies

are used, care must be taken to ensure that the analog supply is

powered up first.

It is also important that power is applied to the AD7703 before

signals at V

REF

, A

, or the logic input pins in order to avoid

any possibility of latch-up. If separate supplies are used for

the AD7703 and the system digital circuitry, the AD7703 should

be powered up first.

A typical scheme for powering the AD7703 from a single set of

±5 V rails is shown in Figure 7. In this circuit, AV

and DV

are brought along separate tracks from the same 5 V supply.

Thus, there is no possibility of the digital supply coming up

before the analog supply.

SLEEP MODE

The low power standby mode is initiated by taking the SLEEP

input low, which shuts down all analog and digital circuits and

reduces power consumption to 10 µW. When coming out of

SLEEP mode, it is sometimes possible (when using a crystal to

generate CLKIN, for example) to lose the calibration coeffi-

cients. Therefore, it is advisable as a safeguard to always do a

calibration cycle after coming out of SLEEP mode.

DIGITAL INTERFACE

The AD7703’s serial communications port allows easy inter-

facing to industry-standard microprocessors. Two different

modes of operation are available, optimized for different types

of interface.

REV. E–14–

AD7703

Synchronous Self-Clocking Mode (SSC)

The SSC mode (MODE pin high) allows easy interfacing to

serial-parallel conversion circuits in systems with parallel data

communication. This mode allows interfacing to 74XX299

Universal Shift registers without any additional decoding. The

SSC mode can also be used with microprocessors such as the

68HC11 and 68HC05, which allow an external device to clock

their serial port.

Figure 15 shows the timing diagram for the SSC mode. Data is

clocked out by an internally generated serial clock. The AD7703

divides each sampling interval into 16 distinct periods. Eight

periods of 64 clock pulses are for analog settling and eight peri-

ods of 64 clock pulses are for digital computation. The status of

CS is polled at the beginning of each digital computation period. If

it is low at any of these times, then SCLK will become active

and the data-word currently in the output register will be trans-

mitted, MSB first. After the LSB has been transmitted, DRDY

will go high until the new data-word becomes available. If CS,

having been brought low, is taken high again at any time during

data transmission, SDATA and SCLK will go three-state after

the current bit finishes. If CS is subsequently brought low,

transmission will resume with the next bit during the subse-

quent digital computation period. If transmission has not been

initiated and completed by the time the next data-word is avail-

able, DRDY will go high for four clock cycles then low again as

the new word is loaded into the output register.

A more detailed diagram of the data transmission in the SSC

mode is shown in Figure 16. Data bits change on the falling

edge of SCLK and are valid on the rising edge of SCLK.

ANALOG TIME 0 DIGITAL TIME 7

SCLK (O)

SDATA (O) HI-Z

HI-Z

MSB

DRDY (O)

DIGITAL TIME 0

CS POLLED

CS (I)

INTERNAL

STATUS

72 CLKIN CYCLES

64 CLKIN

CYCLES

64 CLKIN

CYCLES

1024 CLKIN CYCLES

LSB

Figure 15. Timing Diagram for SSC Transmission Mode

CLKIN (I)

DRDY (O)

SDATA (O) DB19 (MSB) DB18 DB2 DB1 DB0 (LSB)

HI-Z

SCLK (O) HI-Z

HI-Z

CS (I)

CLKIN

CYCLES

DB17

Figure 16. SSC Mode Showing Data Timing Relative to SCLK

REV. E

AD7703

–15–

Synchronous External Clock Mode (SEC)

The SEC mode (MODE pin grounded) is designed for direct

interface to the synchronous serial ports of industry-standard

microprocessors such as the 68HC11 and 68HC05. The SEC

mode also allows customized interfaces, using I/O port pins, to

microprocessors that do not have a direct fit with the AD7703’s

other mode.

As shown in Figure 17, a falling edge on CS enables the serial

data output with the MSB initially valid. Subsequent data bits

change on the falling edge of an externally supplied SCLK. After

the LSB has been transmitted, DRDY and SDATA go three-state.

If CS is low and the AD7703 is still transmitting data when a

new data-word becomes available, the old data-word continues

to be transmitted and the new data is lost.

If CS is taken high at any time during data transmission, SDATA

will go three-state immediately. If CS returns low, the AD7703

will continue transmission with the same data bit. If transmis-

sion has not been initiated and completed by the time the next

data-word becomes available, and if CS is high, DRDY returns

high for four clock cycles, then falls as the new word is loaded

into the output register.

DIGITAL NOISE AND OUTPUT LOADING

As mentioned earlier, the AD7703 divides its internal timing

into two distinct phases, analog sampling and settling and digi-

tal computation. In the SSC mode, data is transmitted only

during the digital computation periods, to minimize the effects

of digital noise on analog performance. In the SEC mode, data

transmission is externally controlled, so this automatic safeguard

does not exist. To compensate, synchronize the AD7703 to the

digital system clock via CLKIN when used in the SEC mode.

Whatever mode of operation is used, resistive and capacitive

loads on digital outputs should be minimized in order to reduce

crosstalk between analog and digital portions of the circuit. For

this reason, connection to low power CMOS logic such as one

of the 4000 series or 74C families is recommended.

DRDY (O)

SDATA (O) DB19 (MSB) DB18 DB2 DB1 DB0 (LSB)

HI-Z

SCLK (O)

HI-Z

CS (I)

DB17

Figure 17. Timing Diagram for SEC Mode

REV. E

C01165–0–4/03(E)

–16–

AD7703

OUTLINE DIMENSIONS

Revision History

Location Page

4/03—Data Sheet changed from REV. D to REV. E.

Updated format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal

Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

20-Lead Plastic Dual In-Line Package [PDIP]

(N-20)

Dimensions shown in inches and (millimeters)

110

0.985 (25.02)

0.965 (24.51)

0.945 (24.00) 0.295 (7.49)

0.285 (7.24)

0.275 (6.99)

0.150 (3.81)

0.135 (3.43)

0.120 (3.05)

0.015 (0.38)

0.010 (0.25)

0.008 (0.20)

0.325 (8.26)

0.310 (7.87)

0.300 (7.62)

SEATING

PLANE

0.015 (0.38) MIN

0.180 (4.57)

MAX

0.022 (0.56)

0.018 (0.46)

0.014 (0.36)

0.150 (3.81)

0.130 (3.30)

0.110 (2.79) 0.100

(2.54)

BSC

0.060 (1.52)

0.050 (1.27)

0.045 (1.14)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MO-095-AE

20-Lead Ceramic Dual In-Line Package [CERDIP]

(Q-20)

Dimensions shown in inches and (millimeters)

110

0.310 (7.87)

0.220 (5.59)

PIN 1

0.005

(0.13)

MIN

0.098 (2.49)

MAX

0.320 (8.13)

0.290 (7.37)

0.015 (0.38)

0.008 (0.20)

SEATING

PLANE

0.200 (5.08)

MAX 1.060 (26.92) MAX

0.150 (3.81)

MIN

0.200 (5.08)

0.125 (3.18)

0.023 (0.58)

0.014 (0.36)

0.100

(2.54)

BSC

0.070 (1.78)

0.030 (0.76)

0.060 (1.52)

0.015 (0.38)

CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETERS DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

20-Lead Standard Small Outline Package [SOIC]

Wide Body

(R-20)

Dimensions shown in millimeters and (inches)

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR

REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN

COMPLIANT TO JEDEC STANDARDS MS-013AC

0.75 (0.0295)

0.25 (0.0098)

20 11

0.32 (0.0126)

0.23 (0.0091)

8ⴗ

0ⴗ

ⴛ 45ⴗ

1.27 (0.0500)

0.40 (0.0157)

SEATING

PLANE

0.30 (0.0118)

0.10 (0.0039)

0.51 (0.0201)

0.33 (0.0130)

2.65 (0.1043)

2.35 (0.0925)

1.27

(0.0500)

BSC

10.65 (0.4193)

10.00 (0.3937)

7.60 (0.2992)

7.40 (0.2913)

13.00 (0.5118)

12.60 (0.4961)

COPLANARITY

0.10