M1A3PE3000-1FG896I - Actel Corporation

February 2009 I

ProASIC3E Flash Family FPGAs

with Optional Soft ARM® Support

Features and Benefits

High Capacity

• 600 k to 3 Million System Gates

• 108 to 504 kbits of True Dual-Port SRAM

• Up to 620 User I/Os

Reprogrammable Flash Technology

• 130-nm, 7-Layer Metal (6 Copper), Flash-Based CMOS Process

• Live at Power-Up (LAPU) Level 0 Support

• Single-Chip Solution

• Retains Programmed Design when Powered Off

On-Chip User Nonvolatile Memory

• 1 kbit of FlashROM with Synchronous Interfacing

High Performance

• 350 MHz System Performance

• 3.3 V, 66 MHz 64-Bit PCI

In-System Programming (ISP) and Security

• Secure ISP Using On-Chip 128-Bit Advanced Encryption

Standard (AES) Decryption via JTAG (IEEE 1532–compliant)

•FlashLock

® to Secure FPGA Contents

Low Power

• Core Voltage for Low Power

• Support for 1.5-V-Only Systems

• Low-Impedance Flash Switches

High-Performance Routing Hierarchy

• Segmented, Hierarchical Routing and Clock Structure

• Ultra-Fast Local and Long-Line Network

• Enhanced High-Speed, Very-Long-Line Network

• High-Performance, Low-Skew Global Network

• Architecture Supports Ultra-High Utilization

Pro (Professional) I/O

• 700 Mbps DDR, LVDS-Capable I/Os

• 1.5 V, 1.8 V, 2.5 V, and 3.3 V Mixed-Voltage Operation

• Bank-Selectable I/O Voltages—up to 8 Banks per Chip

• Single-Ended I/O Standards: LVTTL, LVCMOS 3.3 V /

2.5 V / 1.8 V / 1.5 V, 3.3 V PCI / 3.3 V PCI-X, and LVCMOS

2.5 V / 5.0 V Input

• Differential I/O Standards: LVPECL, LVDS, B-LVDS, and

M-LVDS

• Voltage-Referenced I/O Standards: GTL+ 2.5 V / 3.3 V, GTL

2.5 V / 3.3 V, HSTL Class I and II, SSTL2 Class I and II, SSTL3

Class I and II

• I/O Registers on Input, Output, and Enable Paths

• Hot-Swappable and Cold Sparing I/Os

• Programmable Output Slew Rate and Drive Strength

• Programmable Input Delay

• Schmitt Trigger Option on Single-Ended Inputs

• Weak Pull-Up/-Down

• IEEE 1149.1 (JTAG) Boundary Scan Test

• Pin-Compatible Packages across the ProASIC®3E Family

Clock Conditioning Circuit (CCC) and PLL

• Six CCC Blocks, Each with an Integrated PLL

• Configurable Phase-Shift, Multiply/Divide, Delay

Capabilities and External Feedback

• Wide Input Frequency Range (1.5 MHz to 200 MHz)

SRAMs and FIFOs

• Variable-Aspect-Ratio 4,608-Bit RAM Blocks (×1, ×2, ×4, ×9,

and ×18 organizations available)

• True Dual-Port SRAM (except ×18)

• 24 SRAM and FIFO Configurations with Synchronous

Operation up to 350 MHz

ARM Processor Support in ProASIC3E FPGAs

• M1 ProASIC3E Devices—Cortex-M1 Soft Processor Available

with or without Debug

Table 1-1 • ProASIC3E Product Family

ProASIC3E Devices A3PE600 A3PE1500 A3PE3000

Cortex-M1 Devices 1M1A3PE1500 M1A3PE3000

System Gates 600 k 1.5 M 3 M

VersaTiles (D-flip-flops) 13,824 38,400 75,264

RAM kbits (1,024 bits) 108 270 504

4,608-Bit Blocks 24 60 112

FlashROM Bits 1 k 1 k 1 k

Secure (AES) ISP Yes Yes Yes

CCCs with Integrated PLLs266 6

VersaNet Globals318 18 18

I/O Banks 88 8

Maximum User I/Os 270 444 620

Package Pins

PQFP

FBGA

PQ208

FG256, FG484

PQ208

FG484, FG676

PQ208

FG324, FG484, FG896

Notes:

1. Refer to the Cortex-M1 product brief for more information.

2. The PQ208 package has six CCCs and two PLLs.

3. Six chip (main) and three quadrant global networks are available.

4. For devices supporting lower densities, refer to the ProASIC3 Flash Family FPGAs handbook.

v1.1

II v1.1

I/Os Per Package1

ProASIC3E Devices A3PE600 A3PE1500 3A3PE3000 3

Cortex-M1 Devices 2M1A3PE1500 M1A3PE3000

Package

I/O Types

Single-Ended I/O1

Differential I/O Pairs

Single-Ended I/O1

Differential I/O Pairs

Single-Ended I/O1

Differential I/O Pairs

PQ208 147 65 147 65 147 65

FG256 16579––––

FG324 – – – – 221 110

FG484 270 135 280 139 341 168

FG676 – – 444 222 – –

FG896 – – – – 620 310

Notes:

1. When considering migrating your design to a lower- or higher-density device, refer to the ProASIC3E Flash Family FPGAs

handbook to ensure compliance with design and board migration requirements.

2. Each used differential I/O pair reduces the number of single-ended I/Os available by two.

3. For A3PE1500 and A3PE3000 devices, the usage of certain I/O standards is limited as follows:

– SSTL3(I) and (II): up to 40 I/Os per north or south bank

– LVPECL / GTL+ 3.3 V / GTL 3.3 V: up to 48 I/Os per north or south bank

– SSTL2(I) and (II) / GTL+ 2.5 V/ GTL 2.5 V: up to 72 I/Os per north or south bank

4. FG256 and FG484 are footprint-compatible packages.

5. When using voltage-referenced I/O standards, one I/O pin should be assigned as a voltage-referenced pin (VREF) per

minibank (group of I/Os).

6. "G" indicates RoHS-compliant packages. Refer to the "ProASIC3E Ordering Information" on page III for the location of

the "G" in the part number.

Table 1-2 • ProASIC3E FPGAs Package Sizes Dimensions

Package PQ208 FG256 FG324 FG484 FG676 FG896

Length × Width

(mm\mm)

28 × 28 17 × 17 19 × 19 23 × 23 27 × 27 31 × 31

Nominal Area

(mm2)

784 289 361 529 729 961

Pitch (mm) 0.5 1.0 1.0 1.0 1.0 1.0

Height (mm) 3.40 1.60 1.63 2.23 2.23 2.23

ProASIC3E Flash Family FPGAs

v1.1 III

ProASIC3E Ordering Information

*The DC and switching characteristics for the –F speed grade targets are based only on simulation. The characteristics provided

for the –F speed grade are subject to change after establishing FPGA specifications. Some restrictions might be added and will

be reflected in future revisions of this document. The –F speed grade is only supported in the commercial temperature range.

A3PE3000 FG

Part Number

Speed Grade

Blank = Standard

1 = 15% Faster than Standard

2 = 25% Faster than Standard

F = 20% Slower than Standard*

Package Type

PQ =Plastic Quad Flat Pack (0.5 mm pitch)

FG =Fine Pitch Ball Grid Array (1.0 mm pitch)

896 I

Package Lead Count

Application (Temperature Range)

Blank = Commercial (0°C to +70°C Ambient Temperature)

I = Industrial (–40°C to +85°C Ambient Temperature)

PP = Pre-Production

ES = Engineering Sample (Room Temperature Only)

600,000 System Gates

A3PE600 =

1,500,000 System Gates

A3PE1500 =

3,000,000 System Gates

A3PE3000 =

1,500,000 System Gates

M1A3PE1500 =

3,000,000 System Gates

M1A3PE3000 =

Lead-Free Packaging

Blank = Standard Packaging

G = RoHS-Compliant (Green) Packaging

ProASIC3E Devices

ProASIC3E Devices with Cortex-M1

IV v1.1

Temperature Grade Offerings

Speed Grade and Temperature Grade Matrix

References made to ProASIC3E devices also apply to ARM-enabled ProASIC3E devices. The ARM-enabled part numbers start

with M1 (Cortex-M1).

Contact your local Actel representative for device availability:

http://www.actel.com/contact/default.aspx.

Package A3PE600 A3PE1500 A3PE3000

Cortex-M1 Devices M1A3PE1500 M1A3PE3000

PQ208 C, I C, I C, I

FG256 C, I – –

FG324 – – C, I

FG484 C, I C, I C, I

FG676 – C, I –

FG896 – – C, I

Note: C = Commercial temperature range: 0°C to 70°C ambient temperature

I = Industrial temperature range: –40°C to 85°C ambient temperature

Temperature Grade –F 1Std. –1 –2

C2✓✓✓✓

I3–✓✓✓

Notes:

1. The DC and switching characteristics for the –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA specifications. Some

restrictions might be added and will be reflected in future revisions of this document. The –F speed grade is only

supported in the commercial temperature range.

2. C = Commercial temperature range: 0°C to 70°C ambient temperature

3. I = Industrial temperature range: –40°C to 85°C ambient temperature

v1.1 1-1

1 – ProASIC3E Device Family Overview

General Description

ProASIC3E, the third-generation family of Actel flash FPGAs, offers performance, density, and

features beyond those of the ProASICPLUS® family. Nonvolatile flash technology gives ProASIC3E

devices the advantage of being a secure, low-power, single-chip solution that is live at power-up

(LAPU). ProASIC3E is reprogrammable and offers time-to-market benefits at an ASIC-level unit cost.

These features enable designers to create high-density systems using existing ASIC or FPGA design

flows and tools.

ProASIC3E devices offer 1 kbit of on-chip, programmable, nonvolatile FlashROM storage as well as

clock conditioning circuitry based on six integrated phase-locked loops (PLLs). ProASIC3E devices

have up to three million system gates, supported with up to 504 kbits of true dual-port SRAM and

up to 620 user I/Os.

Several ProASIC3E devices support the Cortex-M1 soft IP cores, and the ARM-Enabled devices have

Actel ordering numbers that begin with M1A3PE.

Flash Advantages

Reduced Cost of Ownership

Advantages to the designer extend beyond low unit cost, performance, and ease of use. Unlike

SRAM-based FPGAs, flash-based ProASIC3E devices allow all functionality to be live at power-up; no

external boot PROM is required. On-board security mechanisms prevent access to all the

programming information and enable secure remote updates of the FPGA logic. Designers can

perform secure remote in-system reprogramming to support future design iterations and field

upgrades with confidence that valuable intellectual property (IP) cannot be compromised or

copied. Secure ISP can be performed using the industry-standard AES algorithm. The ProASIC3E

family device architecture mitigates the need for ASIC migration at higher user volumes. This

makes the ProASIC3E family a cost-effective ASIC replacement solution, especially for applications

in the consumer, networking/ communications, computing, and avionics markets.

Security

The nonvolatile, flash-based ProASIC3E devices do not require a boot PROM, so there is no

vulnerable external bitstream that can be easily copied. ProASIC3E devices incorporate FlashLock,

which provides a unique combination of reprogrammability and design security without external

overhead, advantages that only an FPGA with nonvolatile flash programming can offer.

ProASIC3E devices utilize a 128-bit flash-based lock and a separate AES key to secure programmed

intellectual property and configuration data. In addition, all FlashROM data in ProASIC3E devices

can be encrypted prior to loading, using the industry-leading AES-128 (FIPS192) bit block cipher

encryption standard. The AES standard was adopted by the National Institute of Standards and

Technology (NIST) in 2000 and replaces the 1977 DES standard. ProASIC3E devices have a built-in

AES decryption engine and a flash-based AES key that make them the most comprehensive

programmable logic device security solution available today. ProASIC3E devices with AES-based

security allow for secure, remote field updates over public networks such as the Internet, and

ensure that valuable IP remains out of the hands of system overbuilders, system cloners, and IP

thieves. The contents of a programmed ProASIC3E device cannot be read back, although secure

design verification is possible.

Security, built into the FPGA fabric, is an inherent component of the ProASIC3E family. The flash

cells are located beneath seven metal layers, and many device design and layout techniques have

been used to make invasive attacks extremely difficult. The ProASIC3E family, with FlashLock and

AES security, is unique in being highly resistant to both invasive and noninvasive attacks. Your

ProASIC3E Device Family Overview

1-2 v1.1

valuable IP is protected and secure, making remote ISP possible. A ProASIC3E device provides the

most impenetrable security for programmable logic designs.

Single Chip

Flash-based FPGAs store their configuration information in on-chip flash cells. Once programmed,

the configuration data is an inherent part of the FPGA structure, and no external configuration

data needs to be loaded at system power-up (unlike SRAM-based FPGAs). Therefore, flash-based

ProASIC3E FPGAs do not require system configuration components such as EEPROMs or

microcontrollers to load device configuration data. This reduces bill-of-materials costs and PCB

area, and increases security and system reliability.

Live at Power-Up

The Actel flash-based ProASIC3E devices support Level 0 of the LAPU classification standard. This

feature helps in system component initialization, execution of critical tasks before the processor

wakes up, setup and configuration of memory blocks, clock generation, and bus activity

management. The LAPU feature of flash-based ProASIC3E devices greatly simplifies total system

design and reduces total system cost, often eliminating the need for CPLDs and clock generation

PLLs that are used for these purposes in a system. In addition, glitches and brownouts in system

power will not corrupt the ProASIC3E device's flash configuration, and unlike SRAM-based FPGAs,

the device will not have to be reloaded when system power is restored. This enables the reduction

or complete removal of the configuration PROM, expensive voltage monitor, brownout detection,

and clock generator devices from the PCB design. Flash-based ProASIC3E devices simplify total

system design and reduce cost and design risk while increasing system reliability and improving

system initialization time.

Firm Errors

Firm errors occur most commonly when high-energy neutrons, generated in the upper atmosphere,

strike a configuration cell of an SRAM FPGA. The energy of the collision can change the state of the

configuration cell and thus change the logic, routing, or I/O behavior in an unpredictable way.

These errors are impossible to prevent in SRAM FPGAs. The consequence of this type of error can be

a complete system failure. Firm errors do not exist in the configuration memory of ProASIC3E flash-

based FPGAs. Once it is programmed, the flash cell configuration element of ProASIC3E FPGAs

cannot be altered by high-energy neutrons and is therefore immune to them. Recoverable (or soft)

errors occur in the user data SRAM of all FPGA devices. These can easily be mitigated by using error

detection and correction (EDAC) circuitry built into the FPGA fabric.

Low Power

Flash-based ProASIC3E devices exhibit power characteristics similar to an ASIC, making them an

ideal choice for power-sensitive applications. ProASIC3E devices have only a very limited power-on

current surge and no high-current transition period, both of which occur on many FPGAs.

ProASIC3E devices also have low dynamic power consumption to further maximize power savings.

Advanced Flash Technology

The ProASIC3E family offers many benefits, including nonvolatility and reprogrammability through

an advanced flash-based, 130-nm LVCMOS process with seven layers of metal. Standard CMOS

design techniques are used to implement logic and control functions. The combination of fine

granularity, enhanced flexible routing resources, and abundant flash switches allows for very high

logic utilization without compromising device routability or performance. Logic functions within

the device are interconnected through a four-level routing hierarchy.

ProASIC3E Flash Family FPGAs

v1.1 1-3

Advanced Architecture

The proprietary ProASIC3E architecture provides granularity comparable to standard-cell ASICs. The

ProASIC3E device consists of five distinct and programmable architectural features (Figure 1-1 on

page 3):

• FPGA VersaTiles

• Dedicated FlashROM

• Dedicated SRAM/FIFO memory

• Extensive CCCs and PLLs

• Pro I/O structure

The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input

logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate

flash switch interconnections. The versatility of the ProASIC3E core tile as either a three-input

lookup table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the

FPGA fabric. The VersaTile capability is unique to the Actel ProASIC family of third-generation

architecture Flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy.

Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable

interconnect programming. Maximum core utilization is possible for virtually any design.

In addition, extensive on-chip programming circuitry allows for rapid, single-voltage (3.3 V)

programming of ProASIC3E devices via an IEEE 1532 JTAG interface.

Figure 1-1 • ProASIC3E Device Architecture Overview

4,608-Bit Dual-Port SRAM

or FIFO Block

VersaTile

RAM Block

CCC

Pro I/Os

ISP AES Decryption User Nonvolatile

FlashROM Charge Pumps

4,608-Bit Dual-Port SRAM

or FIFO Block

RAM Block

ProASIC3E Device Family Overview

1-4 v1.1

VersaTiles

The ProASIC3E core consists of VersaTiles, which have been enhanced beyond the ProASICPLUS®

core tiles. The ProASIC3E VersaTile supports the following:

• All 3-input logic functions—LUT-3 equivalent

• Latch with clear or set

• D-flip-flop with clear or set

• Enable D-flip-flop with clear or set

Refer to Figure 1-2 for VersaTile configurations.

User Nonvolatile FlashROM

Actel ProASIC3E devices have 1 kbit of on-chip, user-accessible, nonvolatile FlashROM. The

FlashROM can be used in diverse system applications:

• Internet protocol addressing (wireless or fixed)

• System calibration settings

• Device serialization and/or inventory control

• Subscription-based business models (for example, set-top boxes)

• Secure key storage for secure communications algorithms

• Asset management/tracking

• Date stamping

• Version management

The FlashROM is written using the standard ProASIC3E IEEE 1532 JTAG programming interface. The

core can be individually programmed (erased and written), and on-chip AES decryption can be used

selectively to securely load data over public networks, as in security keys stored in the FlashROM for

a user design.

The FlashROM can be programmed via the JTAG programming interface, and its contents can be

read back either through the JTAG programming interface or via direct FPGA core addressing. Note

that the FlashROM can only be programmed from the JTAG interface and cannot be programmed

from the internal logic array.

The FlashROM is programmed as 8 banks of 128 bits; however, reading is performed on a byte-by-

byte basis using a synchronous interface. A 7-bit address from the FPGA core defines which of the 8

banks and which of the 16 bytes within that bank are being read. The three most significant bits

(MSBs) of the FlashROM address determine the bank, and the four least significant bits (LSBs) of

the FlashROM address define the byte.

The Actel ProASIC3E development software solutions, Libero® Integrated Design Environment (IDE)

and Designer, have extensive support for the FlashROM. One such feature is auto-generation of

sequential programming files for applications requiring a unique serial number in each part.

Another feature allows the inclusion of static data for system version control. Data for the

FlashROM can be generated quickly and easily using Actel Libero IDE and Designer software tools.

Comprehensive programming file support is also included to allow for easy programming of large

numbers of parts with differing FlashROM contents.

Figure 1-2 • VersaTile Configurations

LUT-3

Data Y

CLK

Enable

CLR

D-FF

Data Y

CLK

CLR

D-FF

LUT-3 Equivalent D-Flip-Flop with Clear or Set Enable D-Flip-Flop with Clear or Set

ProASIC3E Flash Family FPGAs

v1.1 1-5

SRAM and FIFO

ProASIC3E devices have embedded SRAM blocks along their north and south sides. Each variable-

aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9,

1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be

configured with different bit widths on each port. For example, data can be sent through a 4-bit

port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device

JTAG port (ROM emulation mode) using the UJTAG macro.

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the

SRAM block to be configured as a synchronous FIFO without using additional core VersaTiles. The

FIFO width and depth are programmable. The FIFO also features programmable Almost Empty

(AEMPTY) and Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The

embedded FIFO control unit contains the counters necessary for generation of the read and write

address pointers. The embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

ProASIC3E devices provide designers with very flexible clock conditioning capabilities. Each

member of the ProASIC3E family contains six CCCs, each with an integrated PLL.

The six CCC blocks are located at the four corners and the centers of the east and west sides.

To maximize user I/Os, only the center east and west PLLs are available in devices using the PQ208

package. However, all six CCC blocks are still usable; the four corner CCCs allow simple clock delay

operations as well as clock spine access.

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs

located near the CCC that have dedicated connections to the CCC block.

The CCC block has these key features:

• Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz

• Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz

• Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns

• 2 programmable delay types for clock skew minimization

• Clock frequency synthesis

Additional CCC specifications:

• Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output

divider configuration.

• Output duty cycle = 50% ± 1.5% or better

• Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single

global network used

• Maximum acquisition time = 300 µs

• Low power consumption of 5 mW

• Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns

• Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz /

fOUT_CCC)

Global Clocking

ProASIC3E devices have extensive support for multiple clocking domains. In addition to the CCC

and PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three

quadrant global networks. The VersaNets can be driven by the CCC or directly accessed from the

core via multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for

rapid distribution of high fanout nets.

ProASIC3E Device Family Overview

1-6 v1.1

Pro I/Os with Advanced I/O Standards

The ProASIC3E family of FPGAs features a flexible I/O structure, supporting a range of voltages

(1.5 V, 1.8 V, 2.5 V, and 3.3 V). ProASIC3E FPGAs support 19 different I/O standards, including single-

ended, differential, and voltage-referenced. The I/Os are organized into banks, with eight banks

per device (two per side). The configuration of these banks determines the I/O standards

supported. Each I/O bank is subdivided into VREF minibanks, which are used by voltage-referenced

I/Os. VREF minibanks contain 8 to 18 I/Os. All the I/Os in a given minibank share a common VREF line.

Therefore, if any I/O in a given VREF minibank is configured as a VREF pin, the remaining I/Os in that

minibank will be able to use that reference voltage.

Each I/O module contains several input, output, and enable registers. These registers allow the

implementation of the following:

• Single-Data-Rate applications (e.g., PCI 66 MHz, bidirectional SSTL 2 and 3, Class I and II)

• Double-Data-Rate applications (e.g., DDR LVDS, B-LVDS, and M-LVDS I/Os for point-to-point

communications, and DDR 200 MHz SRAM using bidirectional HSTL Class II)

ProASIC3E banks support M-LVDS with 20 multi-drop points.

Part Number and Revision Date

Part Number 51700098-001-2

Revised February 2009

List of Changes

The following table lists critical changes that were made in the current version of the document.

Previous Version Changes in Current Version (v1.1) Page

v1.0

(March 2008)

Table 1-2 · ProASIC3E FPGAs Package Sizes Dimensions is new. II

51700098-001-1 This document was divided into two sections and given a version number,

starting at v1.0. The first section of the document includes features, benefits,

ordering information, and temperature and speed grade offerings. The second

section is a device family overview.

N/A

51700098-001-0

(January 2008)

The FG324 package was added to the "ProASIC3E Product Family" table, the

"I/Os Per Package1" table, and the "Temperature Grade Offerings" table for

A3PE3000.

I, II, IV

v2.1

(July 2007)

This document was previously in datasheet v2.1. As a result of moving to the

handbook format, Actel has restarted the version numbers. The new version

number is 51700098-001-0.

N/A

v2.0

(April 2007)

CoreMP7 information was removed from the "Features and Benefits" section. i

The M1 device part numbers have been updated in Table 4 • ProASIC3E

Product Family, "Packaging Tables", "Temperature Grade Offerings", "Speed

Grade and Temperature Grade Matrix", and "Speed Grade and Temperature

Grade Matrix".

ii, iii,

iv, iv

The words "ambient temperature" were added to the temperature range in

the "Temperature Grade Offerings", "Speed Grade and Temperature Grade

Matrix", and "Speed Grade and Temperature Grade Matrix" sections.

iii, iv, iv

The "Clock Conditioning Circuit (CCC) and PLL" section was updated. i

ProASIC3E Flash Family FPGAs

v1.1 1-7

Advance v0.6

(January 2007)

In the "Temperature Grade Offerings" section, Ambient was deleted. iii

Ambient was deleted from "Temperature Grade Offerings". iii

Ambient was deleted from the "Speed Grade and Temperature Grade Matrix". iv

Advance v0.5

(April 2006)

In the "Packaging Tables" table, the number of I/Os for the A3PE1500 was

changed for the FG484 and FG676 packages.

Advance v0.4

(October 2005)

B-LVDS and M-LDVS are new I/O standards added to the datasheet. N/A

The term flow-through was changed to pass-through. N/A

Advance v0.2 The "Packaging Tables" table was updated. ii

Previous Version Changes in Current Version (v1.1) Page

ProASIC3E Device Family Overview

1-8 v1.1

Datasheet Categories

Categories

In order to provide the latest information to designers, some datasheets are published before data

has been fully characterized. Datasheets are designated as "Product Brief," "Advance,"

"Preliminary," and "Production." The definitions of these categories are as follows:

Product Brief

The product brief is a summarized version of a datasheet (advance or production) and contains

general product information. This document gives an overview of specific device and family

information.

Advance

This version contains initial estimated information based on simulation, other products, devices, or

speed grades. This information can be used as estimates, but not for production. This label only

applies to the DC and Switching Characteristics chapter of the datasheet and will only be used

when the data has not been fully characterized.

Preliminary

The datasheet contains information based on simulation and/or initial characterization. The

information is believed to be correct, but changes are possible.

Unmarked (production)

This version contains information that is considered to be final.

Export Administration Regulations (EAR)

The products described in this document are subject to the Export Administration Regulations

(EAR). They could require an approved export license prior to export from the United States. An

export includes release of product or disclosure of technology to a foreign national inside or

outside the United States.

Actel Safety Critical, Life Support, and High-Reliability

Applications Policy

The Actel products described in this advance status document may not have completed Actel’s

qualification process. Actel may amend or enhance products during the product introduction and

qualification process, resulting in changes in device functionality or performance. It is the

responsibility of each customer to ensure the fitness of any Actel product (but especially a new

product) for a particular purpose, including appropriateness for safety-critical, life-support, and

other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability

exclusions relating to life-support applications. A reliability report covering all of Actel’s products is

available on the Actel website at http://www.actel.com/documents/ORT_Report.pdf. Actel also

offers a variety of enhanced qualification and lot acceptance screening procedures. Contact your

local Actel sales office for additional reliability information.

v1.2 2-1

2 – ProASIC3E DC and Switching Characteristics

General Specifications

DC and switching characteristics for –F speed grade targets are based only on simulation.

The characteristics provided for the –F speed grade are subject to change after establishing FPGA

specifications. Some restrictions might be added and will be reflected in future revisions of this

document. The –F speed grade is only supported in the commercial temperature range.

Operating Conditions

Stresses beyond those listed in Table 2-1 may cause permanent damage to the device.

Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Absolute Maximum Ratings are stress ratings only; functional operation of the device at these or

any other conditions beyond those listed under the Recommended Operating Conditions specified

in Table 2-2 on page 2-2 is not implied.

Table 2-1 • Absolute Maximum Ratings

Symbol Parameter Limits Units

VCC DC core supply voltage –0.3 to 1.65 V

VJTAG JTAG DC voltage –0.3 to 3.75 V

VPUMP Programming voltage –0.3 to 3.75 V

VCCPLL Analog power supply (PLL) –0.3 to 1.65 V

VCCI DC I/O output buffer supply voltage –0.3 to 3.75 V

VMV DC I/O input buffer supply voltage –0.3 to 3.75 V

VI I/O input voltage –0.3 V to 3.6 V (when I/O hot insertion mode is enabled)

–0.3 V to (VCCI + 1 V) or 3.6 V, whichever voltage is lower

(when I/O hot-insertion mode is disabled)

TSTG 2Storage temperature –65 to +150 °C

TJ2Junction temperature +125 °C

Notes:

1. The device should be operated within the limits specified by the datasheet. During transitions, the input

signal may undershoot or overshoot according to the limits shown in Table 2-3 on page 2-2.

2. For flash programming and retention maximum limits, refer to Table 2-3 on page 2-2, and for

recommended operating limits, refer to Table 2-2 on page 2-2.

ProASIC3E DC and Switching Characteristics

2-2 v1.2

Table 2-2 • Recommended Operating Conditions 1

Symbol Parameter Commercial Industrial Units

TAAmbient temperature 0 to +70 4,6 –40 to +85 5,6 °C

VCC 1.5 V DC core supply voltage 1.425 to 1.575 1.425 to 1.575 V

VJTAG JTAG DC voltage 1.4 to 3.6 1.4 to 3.6 V

VPUMP Programming voltage Programming Mode 3.15 to 3.45 3.15 to 3.45 V

Operation30 to 3.6 0 to 3.6 V

VCCPLL Analog power supply (PLL) 1.4 to 1.6 1.4 to 1.6 V

VCCI and VMV 21.5 V DC supply voltage 1.425 to 1.575 1.425 to 1.575 V

1.8 V DC supply voltage 1.7 to 1.9 1.7 to 1.9 V

2.5 V DC supply voltage 2.3 to 2.7 2.3 to 2.7 V

3.3 V DC supply voltage 3.0 to 3.6 3.0 to 3.6 V

LVDS/B-LVDS/M-LVDS differential I/O 2.375 to 2.625 2.375 to 2.625 V

LVPECL differential I/O 3.0 to 3.6 3.0 to 3.6 V

Notes:

1. All parameters representing voltages are measured with respect to GND unless otherwise specified.

2. The ranges given here are for power supplies only. The recommended input voltage ranges specific to each

I/O standard are given in Table 2-13 on page 2-16. VMV and VCCI should be at the same voltage within a

given I/O bank.

3. VPUMP can be left floating during normal operation (not programming mode).

4. Maximum TJ = 85 °C.

5. Maximum TJ = 100 °C.

6. To ensure targeted reliability standards are met across ambient and junction operating temperatures, Actel

recommends that the user follow best design practices using Actel’s timing and power simulation tools.

Table 2-3 • Flash Programming Limits – Retention, Storage and Operating Temperature 1

Product Grade

Programming

Cycles

Program Retention

(biased/unbiased)

Maximum Storage

Temperature TSTG (°C) 2

Maximum Operating Junction

Temperature TJ (°C) 2

Commercial 500 20 years 110 100

Industrial 500 20 years 110 100

Notes:

1. This is a stress rating only; functional operation at any condition other than those indicated is not implied.

2. These limits apply for program/data retention only. Refer to Table 2-1 on page 2-1 and Table 2-2 for device

operating conditions and absolute limits.

ProASIC3E DC and Switching Characteristics

v1.2 2-3

I/O Power-Up and Supply Voltage Thresholds for Power-On Reset

(Commercial and Industrial)

Sophisticated power-up management circuitry is designed into every ProASIC®3E device. These

circuits ensure easy transition from the powered-off state to the powered-up state of the device.

The many different supplies can power up in any sequence with minimized current spikes or surges.

In addition, the I/O will be in a known state through the power-up sequence. The basic principle is

shown in Figure 2-1 on page 2-4.

There are five regions to consider during power-up.

ProASIC3E I/Os are activated only if ALL of the following three conditions are met:

1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4).

2. VCCI > VCC – 0.75 V (typical)

3. Chip is in the operating mode.

VCCI Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.2 V

Ramping down: 0.5 V < trip_point_down < 1.1 V

VCC Trip Point:

Ramping up: 0.6 V < trip_point_up < 1.1 V

Ramping down: 0.5 V < trip_point_down < 1 V

VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This

specifically built-in hysteresis prevents undesirable power-up oscillations and current surges. Note

the following:

• During programming, I/Os become tristated and weakly pulled up to VCCI.

• JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O

behavior.

Table 2-4 • Overshoot and Undershoot Limits 1

VCCI and VMV

Average VCCI–GND Overshoot or

Undershoot Duration

as a Percentage of Clock Cycle2Maximum Overshoot/

Undershoot2

2.7 V or less 10% 1.4 V

5% 1.49 V

3 V 10% 1.1 V

5% 1.19 V

3.3 V 10% 0.79 V

5% 0.88 V

3.6 V 10% 0.45 V

5% 0.54 V

Notes:

1. Based on reliability requirements at 85°C.

2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two

cycles, the maximum overshoot/undershoot has to be reduced by 0.15 V.

3. The device meets overshoot/undershoot specification requirements for PCI inputs with VCCI 3.45 V at 85°C

maximum, whereas the average toggling of inputs at one-sixth of PCI frequency is considered.

ProASIC3E DC and Switching Characteristics

2-4 v1.2

PLL Behavior at Brownout Condition

Actel recommends using monotonic power supplies or voltage regulators to ensure proper

power-up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLXL exceed

brownout activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1

on page 2-4 for more details).

When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ±

0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the

Power-Up/-Down Behavior of Low-Power Flash Devices chapter of the handbook for information

on clock and lock recovery.

Internal Power-Up Activation Sequence

1. Core

2. Input buffers

3. Output buffers, after 200 ns delay from input buffer activation

Figure 2-1 • I/O State as a Function of VCCI and VCC Voltage Levels

Region 1: I/O buffers are OFF

Region 2: I/O buffers are ON.

I/Os are functional (except differential inputs)

but slower because VCCI/VCC are below

specification. For the same reason, input

buffers do not meet VIH/VIL levels, and

output buffers do not meet VOH/VOL levels.

Min VCCI datasheet specification

voltage at a selected I/O

standard; i.e., 1.425 V or 1.7 V

or 2.3 V or 3.0 V

VCC

VCC = 1.425 V

Region 1: I/O Buffers are OFF

Activation trip point:

Va = 0.85 V ± 0.25 V

Deactivation trip point:

Vd = 0.75 V ± 0.25 V

Activation trip point:

Va = 0.9 V ± 0.3 V

Deactivation trip point:

Vd = 0.8 V ± 0.3 V

VCC = 1.575 V

Region 5: I/O buffers are ON

and power supplies are within

specification.

I/Os meet the entire datasheet

and timer specifications for

speed, VIH/VIL , VOH/VOL , etc.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential

but slower because VCCI is

below specification. For the

same reason, input buffers do not

meet VIH/VIL levels, and output

buffers do not meet VOH/VOL levels.

Region 4: I/O

buffers are ON.

I/Os are functional

(except differential inputs)

where VT can be from 0.58 V to 0.9 V (typically 0.75 V)

VCCI

Region 3: I/O buffers are ON.

I/Os are functional; I/O DC

specifications are met,

but I/Os are slower because

the VCC is below specification.

VCC = VCCI + VT

ProASIC3E DC and Switching Characteristics

v1.2 2-5

Thermal Characteristics

Introduction

The temperature variable in Actel Designer software refers to the junction temperature, not the

ambient temperature. This is an important distinction because dynamic and static power

consumption cause the chip junction to be higher than the ambient temperature.

EQ 2-1 can be used to calculate junction temperature.

TJ = Junction Temperature = ΔT + TA

EQ 2-1

where:

TA = Ambient Temperature

ΔT = Temperature gradient between junction (silicon) and ambient ΔT = θja * P

θja = Junction-to-ambient of the package. θja numbers are located in Table 2-5.

P = Power dissipation

Package Thermal Characteristics

The device junction-to-case thermal resistivity is θjc and the junction-to-ambient air thermal

resistivity is θja. The thermal characteristics for θja are shown for two air flow rates. The absolute

maximum junction temperature is 110°C. EQ 2-2 shows a sample calculation of the absolute

maximum power dissipation allowed for an 896-pin FBGA package at commercial temperature and

in still air.

EQ 2-2

Temperature and Voltage Derating Factors

Maximum Power Allowed Max. junction temp. (°C) Max. ambient temp. (°C)–

θja(°C/W)

--------------------------------------------------------------------------------------------------------------------------------------- 110°C70°C–

13.6°C/W

------------------------------------ 5 . 8 8 W===

Table 2-5 • Package Thermal Resistivities

Package Type Pin Count θjc

θja

UnitsStill Air 200 ft./min. 500 ft./min.

Plastic Quad Flat Package (PQFP) 208 8.0 26.1 22.5 20.8 C/W

Plastic Quad Flat Package (PQFP) with

embedded heat spreader

208 3.8 16.2 13.3 11.9 C/W

Fine Pitch Ball Grid Array (FBGA) 256 3.8 26.9 22.8 21.5 C/W

484 3.2 20.5 17.0 15.9 C/W

676 3.2 16.4 13.0 12.0 C/W

896 2.4 13.6 10.4 9.4 C/W

Table 2-6 • Temperature and Voltage Derating Factors for Timing Delays

(normalized to TJ= 70°C, VCC =1.425V)

Array Voltage

VCC (V)

Junction Temperature (°C)

–40°C 0°C 25°C 70°C 85°C 100°C

1.4250.870.920.951.001.021.05

1.5000.830.880.900.950.971.00

1.5750.800.850.870.920.940.96

ProASIC3E DC and Switching Characteristics

2-6 v1.2

Calculating Power Dissipation

Quiescent Supply Current

Power per I/O Pin

Table 2-7 • Quiescent Supply Current Characteristics

A3PE600 A3PE1500 A3PE3000

Typical (25°C) 5 mA 12 mA 25 mA

Maximum (Commercial) 30 mA 70 mA 150 mA

Maximum (Industrial) 45 mA 105 mA 225 mA

Notes:

1. IDD Includes VCC, VPUMP, VCCI, and VMV currents. Values do not include I/O static contribution, which is

shown in Table 2-8 and Table 2-9 on page 2-7.

2. –F speed grade devices may experience higher standby IDD of up to five times the standard IDD and higher

I/O leakage.

Table 2-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings

VMV

(V)

Static Power

PDC2 (mW)1Dynamic Power

PAC9 (µW/MHz)2

Single-Ended

3.3 V LVTTL/LVCMOS 3.3 – 17.39

3.3 V LVTTL/LVCMOS – Schmitt trigger 3.3 – 25.51

2.5 V LVCMOS 2.5 – 5.76

2.5 V LVCMOS – Schmitt trigger 2.5 – 7.16

1.8 V LVCMOS 1.8 – 2.72

1.8 V LVCMOS – Schmitt trigger 1.8 – 2.80

1.5 V LVCMOS (JESD8-11) 1.5 – 2.08

1.5 V LVCMOS (JESD8-11) – Schmitt trigger 1.5 – 2.00

3.3 V PCI 3.3 – 18.82

3.3 V PCI – Schmitt trigger 3.3 – 20.12

3.3 V PCI-X 3.3 – 18.82

3.3 V PCI-X – Schmitt trigger 3.3 – 20.12

Voltage-Referenced

3.3 V GTL 3.3 2.90 8.23

2.5 V GTL 2.5 2.13 4.78

3.3 V GTL+ 3.3 2.81 4.14

2.5 V GTL+ 2.5 2.57 3.71

HSTL (I) 1.5 0.17 2.03

HSTL (II) 1.5 0.17 2.03

SSTL2 (I) 2.5 1.38 4.48

SSTL2 (II) 2.5 1.38 4.48

SSTL3 (I) 3.3 3.21 9.26

SSTL3 (II) 3.3 3.21 9.26

Notes:

1. PDC2 is the static power (where applicable) measured on VMV.

2. PAC9 is the total dynamic power measured on VCC and VMV.

ProASIC3E DC and Switching Characteristics

v1.2 2-7

Differential

LVDS/B-LVDS/M-LVDS 2.5 2.26 1.50

LVPECL 3.3 5.71 2.17

Table 2-9 • Summary of I/O Output Buffer Power (per pin) – Default I/O Software Settings1

CLOAD

(pF)

VCCI

(V)

Static Power

PDC3 (mW)2Dynamic Power

PAC10 (μW/MHz)3

Single-Ended

3.3 V LVTTL/LVCMOS 35 3.3 – 474.70

2.5 V LVCMOS 35 2.5 – 270.73

1.8 V LVCMOS 35 1.8 – 151.78

1.5 V LVCMOS (JESD8-11) 35 1.5 – 104.55

3.3 V PCI 10 3.3 – 204.61

3.3 V PCI-X 10 3.3 – 204.61

Voltage-Referenced

3.3 V GTL 10 3.3 – 24.08

2.5 V GTL 10 2.5 – 13.52

3.3 V GTL+ 10 3.3 – 24.10

2.5 V GTL+ 10 2.5 – 13.54

HSTL (I) 20 1.5 7.08 26.22

HSTL (II) 20 1.5 13.88 27.22

SSTL2 (I) 30 2.5 16.69 105.56

SSTL2 (II) 30 2.5 25.91 116.60

SSTL3 (I) 30 3.3 26.02 114.87

SSTL3 (II) 30 3.3 42.21 131.76

Differential

LVDS/B-LVDS/M-LVDS – 2.5 7.70 89.62

LVPECL – 3.3 19.42 168.02

Notes:

1. Dynamic power consumption is given for standard load and software default drive strength and output

slew.

2. PDC3 is the static power (where applicable) measured on VCCI.

3. PAC10 is the total dynamic power measured on VCC and VCCI.

Table 2-8 • Summary of I/O Input Buffer Power (per pin) – Default I/O Software Settings (continued)

VMV

(V)

Static Power

PDC2 (mW)1Dynamic Power

PAC9 (µW/MHz)2

Notes:

1. PDC2 is the static power (where applicable) measured on VMV.

2. PAC9 is the total dynamic power measured on VCC and VMV.

ProASIC3E DC and Switching Characteristics

2-8 v1.2

Power Consumption of Various Internal Resources

Table 2-10 • Different Components Contributing to the Dynamic Power Consumption in ProASIC3E Devices

Parameter Definition

Device-Specific Dynamic Contributions

(µW/MHz)

A3PE600 A3PE1500 A3PE3000

PAC1 Clock contribution of a Global Rib 12.77 16.21 19.7

PAC2 Clock contribution of a Global Spine 1.85 3.06 4.16

PAC3 Clock contribution of a VersaTile row 0.88

PAC4 Clock contribution of a VersaTile used as a sequential

module

0.12

PAC5 First contribution of a VersaTile used as a sequential

module

0.07

PAC6 Second contribution of a VersaTile used as a

sequential module

0.29

PAC7 Contribution of a VersaTile used as a combinatorial

module

0.29

PAC8 Average contribution of a routing net 0.70

PAC9 Contribution of an I/O input pin (standard-

dependent)

See Table 2-8 on page 2-6.

PAC10 Contribution of an I/O output pin (standard-

dependent)

See Table 2-9 on page 2-7

PAC11 Average contribution of a RAM block during a read

operation

25.00

PAC12 Average contribution of a RAM block during a write

operation

30.00

PAC13 Static PLL contribution 2.55 mW

PAC14 Dynamic contribution for PLL 2.60

Note: For a different output load, drive strength, or slew rate, Actel recommends using the Actel power

calculator or SmartPower in Actel Libero® Integrated Design Environment (IDE).

ProASIC3E DC and Switching Characteristics

v1.2 2-9

Power Calculation Methodology

This section describes a simplified method to estimate power consumption of an application. For

more accurate and detailed power estimations, use the SmartPower tool in the Libero IDE

software.

The power calculation methodology described below uses the following variables:

• The number of PLLs as well as the number and the frequency of each output clock

generated

• The number of combinatorial and sequential cells used in the design

•The internal clock frequencies

• The number and the standard of I/O pins used in the design

• The number of RAM blocks used in the design

• Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in Table 2-11 on

page 2-11.

• Enable rates of output buffers—guidelines are provided for typical applications in

Table 2-12 on page 2-11.

• Read rate and write rate to the memory—guidelines are provided for typical applications in

Table 2-12 on page 2-11. The calculation should be repeated for each clock domain defined

in the design.

Methodology

Total Power Consumption—PTOTAL

PTOTAL = PSTAT + PDYN

PSTAT is the total static power consumption.

PDYN is the total dynamic power consumption.

Total Static Power Consumption—PSTAT

PSTAT = PDC1 + NINPUTS * PDC2 + NOUTPUTS * PDC3

NINPUTS is the number of I/O input buffers used in the design.

NOUTPUTS is the number of I/O output buffers used in the design.

Total Dynamic Power Consumption—PDYN

PDYN = PCLOCK + PS-CELL + PC-CELL + PNET + PINPUTS + POUTPUTS + PMEMORY + PPLL

Global Clock Contribution—PCLOCK

PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK

NSPINE is the number of global spines used in the user design—guidelines are provided in

Table 2-11 on page 2-11.

NROW is the number of VersaTile rows used in the design—guidelines are provided in

Table 2-11 on page 2-11.

FCLK is the global clock signal frequency.

NS-CELL is the number of VersaTiles used as sequential modules in the design.

PAC1, PAC2, PAC3, and PAC4 are device-dependent.

Sequential Cells Contribution—PS-CELL

PS-CELL = NS-CELL * (PAC5 + α1 / 2 * PAC6) * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design. When a

multi-tile sequential cell is used, it should be accounted for as 1.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-11 on

page 2-11.

FCLK is the global clock signal frequency.

ProASIC3E DC and Switching Characteristics

2-10 v1.2

Combinatorial Cells Contribution—PC-CELL

PC-CELL = NC-CELL* α1 / 2 * PAC7 * FCLK

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-11 on

page 2-11.

FCLK is the global clock signal frequency.

Routing Net Contribution—PNET

PNET = (NS-CELL + NC-CELL) * α1 / 2 * PAC8 * FCLK

NS-CELL is the number of VersaTiles used as sequential modules in the design.

NC-CELL is the number of VersaTiles used as combinatorial modules in the design.

α1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-11 on

page 2-11.

FCLK is the global clock signal frequency.

I/O Input Buffer Contribution—PINPUTS

PINPUTS = NINPUTS * α2 / 2 * PAC9 * FCLK

NINPUTS is the number of I/O input buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-11 on page 2-11.

FCLK is the global clock signal frequency.

I/O Output Buffer Contribution—POUTPUTS

POUTPUTS = NOUTPUTS * α2 / 2 * β1 * PAC10 * FCLK

NOUTPUTS is the number of I/O output buffers used in the design.

α2 is the I/O buffer toggle rate—guidelines are provided in Table 2-11 on page 2-11.

β1 is the I/O buffer enable rate—guidelines are provided in Table 2-12 on page 2-11.

FCLK is the global clock signal frequency.

RAM Contribution—PMEMORY

PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * β2 + PAC12 * NBLOCK * FWRITE-CLOCK * β3

NBLOCKS is the number of RAM blocks used in the design.

FREAD-CLOCK is the memory read clock frequency.

β2 is the RAM enable rate for read operations—guidelines are provided in Table 2-12

on page 2-11.

FWRITE-CLOCK is the memory write clock frequency.

β3 is the RAM enable rate for write operations—guidelines are provided in Table 2-12

on page 2-11.

PLL Contribution—PPLL

PPLL = PAC13 + PAC14 * FCLKOUT

FCLKOUT is the output clock frequency.1

1. The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated

by the PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include

each output clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL

contribution.

ProASIC3E DC and Switching Characteristics

v1.2 2-11

Guidelines

Toggle Rate Definition

A toggle rate defines the frequency of a net or logic element relative to a clock. It is a percentage.

If the toggle rate of a net is 100%, this means that this net switches at half the clock frequency.

Below are some examples:

• The average toggle rate of a shift register is 100% as all flip-flop outputs toggle at half of

the clock frequency.

• The average toggle rate of an 8-bit counter is 25%:

– Bit 0 (LSB) = 100%

– Bit 1 = 50%

– Bit 2 = 25%

–…

– Bit 7 (MSB) = 0.78125%

– Average toggle rate = (100% + 50% + 25% + 12.5% + . . . + 0.78125%) / 8

Enable Rate Definition

Output enable rate is the average percentage of time during which tristate outputs are enabled.

When nontristate output buffers are used, the enable rate should be 100%.

Table 2-11 • Toggle Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

α1Toggle rate of VersaTile outputs 10%

α2I/O buffer toggle rate 10%

Table 2-12 • Enable Rate Guidelines Recommended for Power Calculation

Component Definition Guideline

β1I/O output buffer enable rate 100%

β2RAM enable rate for read operations 12.5%

β3RAM enable rate for write operations 12.5%

ProASIC3E DC and Switching Characteristics

2-12 v1.2

User I/O Characteristics

Timing Model

Figure 2-2 • Timing Model

Operating Conditions: –2 Speed, Commercial Temperature Range (TJ= 70°C), Worst-Case

VCC = 1.425 V

DQ DQ

Combinational Cell

I/O Module

(Registered)

I/O Module

(Non-Registered)

I/O Module

(Registered)

I/O Module

(Non-Registered)

LVPECL

LVDS,

BLVDS,

M-LVDS

GTL+ 3.3V

Combinational Cell

I/O Module

(Non-Registered)

LVTTL/LVCMOS

Output drive strength = 24 mA

High slew rate

I/O Module

(Non-Registered)

LVCMOS 1.5V

Output drive strength = 12 mA

High slew

LVTTL/LVCMOS

Output drive strength = 12 mA

High slew rate

I/O Module

(Non-Registered)

Input LVTTL/LVCMOS

Clock

Input LVTTL/LVCMOS

Clock

Input LVTTL/LVCMOS

Clock

tPD = 0.56 ns tPD = 0.49 ns

tDP = 1.36 ns

tPD = 0.87 ns tDP = 2.74 ns

tPD = 0.51 ns

tPD = 0.47 ns

tDP = 2.39 ns

tDP = 3.30 ns

tCLKQ = 0.59 ns

tDP = 1.53 ns

tSUD = 0.31 ns

tPY = 0.90 ns

tCLKQ = 0.55 ns

tSUD = 0.43 ns

tPY = 0.90 ns

tPD = 0.47 ns

tCLKQ = 0.55 ns

tSUD = 0.43 ns

tPY = 1.36 ns

tPY = 0.90 ns

tICLKQ = 0.24 ns

tISUD = 0.26 ns

tPY = 1.22 ns

ProASIC3E DC and Switching Characteristics

v1.2 2-13

Figure 2-3 • Input Buffer Timing Model and Delays (example)

(R)

PAD

GND

(F)

50%

(R) (F)

(R)

DIN

GND

(F)

50%50%

PAD Y

CLK

I/O Interface

DIN

To Array

tDOUT tDOUT

VCC

tPYS

tPY

tPYS

tPY

VCC

Vtrip Vtrip

VIH

VIL

tPY = MAX(tPY(R), tPY(F))

tDIN = MAX(tDIN(R), tDIN(F))

tPY tDIN

ProASIC3E DC and Switching Characteristics

2-14 v1.2

Figure 2-4 • Output Buffer Model and Delays (example)

tDP

(R)

PAD VOL

tDP

(F)

Vtrip

VOH

VCC

D50% 50%

VCC

0 V

DOUT 50% 50% 0 V

tDOUT

(R)

tDOUT

(F)

From Array

PAD

tDP

Std

Load

CLK

I/O Interface

DOUT

tDOUT

tDP = MAX(tDP(R), tDP(F))

tDOUT = MAX(tDOUT(R), tDOUT(F))

ProASIC3E DC and Switching Characteristics

v1.2 2-15

Figure 2-5 • Tristate Output Buffer Timing Model and Delays (example)

CLK

10% V

CCI

trip

50%

90% V

CCI

trip

50% 50% t

50%

EOUT

PAD

E50%

EOUT (R)

50%

EOUT (F)

PAD

DOUT

EOUT

I/O Interface

EOUT

ZLS

trip

50%

ZHS

trip

50%

EOUT

PAD

E50% 50%

EOUT (R)

EOUT (F)

50%

CCI

, t

ZLS

, t

ZHS

EOUT

= MAX(t

EOUT

(r), t

EOUT

(f))

ProASIC3E DC and Switching Characteristics

2-16 v1.2

Overview of I/O Performance

Summary of I/O DC Input and Output Levels – Default I/O Software

Settings

Table 2-13 • Summary of Maximum and Minimum DC Input and Output Levels

Applicable to Commercial and Industrial Conditions

I/O Standard Drive Strength Slew Rate

VIL VIH VOL VOH IOL IOH

Min, V Max, V Min, V Max, V Max, V Min, V mA mA

3.3 V LVTTL /

3.3 V LVCMOS

12 mA High –0.3 0.8 2 3.6 0.4 2.4 12 12

2.5 V LVCMOS 12 mA High –0.3 0.7 1.7 3.6 0.7 1.7 12 12

1.8 V LVCMOS 12 mA High –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 12 12

1.5 V LVCMOS 12 mA High –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 12 12

3.3 V PCI Per PCI Specification

3.3 V PCI-X Per PCI-X Specification

3.3 V GTL 25 mA2High –0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 – 25 25

2.5 V GTL 25 mA2High –0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 – 25 25

3.3 V GTL+ 35 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 – 51 51

2.5 V GTL+ 33 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 – 40 40

HSTL (I) 8 mA High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCI – 0.4 8 8

HSTL (II) 15 mA2High –0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCI – 0.4 15 15

SSTL2 (I) 15 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6 0.54 VCCI – 0.62 15 15

SSTL2 (II) 18 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6 0.35 VCCI – 0.43 18 18

SSTL3 (I) 14 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6 0.7 VCCI – 1.1 14 14

SSTL3 (II) 21 mA High –0.3 VREF – 0.2 VREF + 0.2 3.6 0.5 VCCI – 0.9 21 21

Notes:

1. Currents are measured at 85°C junction temperature.

2. Output drive strength is below JEDEC specification.

3. Output Slew Rates can be extracted from IBIS Models, located at

http://www.actel.com/download/ibis/default.aspx.

ProASIC3E DC and Switching Characteristics

v1.2 2-17

Table 2-14 • Summary of Maximum and Minimum DC Input Levels

Applicable to Commercial and Industrial Conditions

DC I/O Standards

Commercial1Industrial2

IIL IIH IIL IIH

µA µA µA µA

3.3 V LVTTL / 3.3 V LVCMOS 10 10 15 15

2.5 V LVCMOS 10 10 15 15

1.8 V LVCMOS 10 10 15 15

1.5 V LVCMOS 10 10 15 15

3.3 V PCI 10101515

3.3 V PCI-X 10101515

3.3 V GTL 10101515

2.5 V GTL 10101515

3.3 V GTL+ 10 10 15 15

2.5 V GTL+ 10 10 15 15

HSTL (I) 10101515

HSTL (II) 10 10 15 15

SSTL2 (I) 10101515

SSTL2 (II) 10 10 15 15

SSTL3 (I) 10101515

SSTL3 (II) 10 10 15 15

Notes:

1. Commercial range (0°C < TA < 70°C)

2. Industrial range (–40°C < TA < 85°C)

ProASIC3E DC and Switching Characteristics

2-18 v1.2

Summary of I/O Timing Characteristics – Default I/O Software Settings

Table 2-15 • Summary of AC Measuring Points

Standard

Input Reference Voltage

(VREF_TYP)

Board Termination

Voltage (VTT_REF)

Measuring Trip Point

(Vtrip)

3.3 V LVTTL / 3.3 V LVCMOS – – 1.4 V

2.5 V LVCMOS – – 1.2 V

1.8 V LVCMOS – – 0.90 V

1.5 V LVCMOS – – 0.75 V

3.3 V PCI – – 0.285 * VCCI (RR)

0.615 * VCCI (FF))

3.3 V PCI-X – – 0.285 * VCCI (RR)

0.615 * VCCI (FF)

3.3 V GTL 0.8 V 1.2 V VREF

2.5 V GTL 0.8 V 1.2 V VREF

3.3 V GTL+ 1.0 V 1.5 V VREF

2.5 V GTL+ 1.0 V 1.5 V VREF

HSTL (I) 0.75 V 0.75 V VREF

HSTL (II) 0.75 V 0.75 V VREF

SSTL2 (I) 1.25 V 1.25 V VREF

SSTL2 (II) 1.25 V 1.25 V VREF

SSTL3 (I) 1.5 V 1.485 V VREF

SSTL3 (II) 1.5 V 1.485 V VREF

LVDS – – Cross point

LVPECL – – Cross point

Table 2-16 • I/O AC Parameter Definitions

Parameter Definition

tDP Data to Pad delay through the Output Buffer

tPY Pad to Data delay through the Input Buffer with Schmitt trigger disabled

tDOUT Data to Output Buffer delay through the I/O interface

tEOUT Enable to Output Buffer Tristate Control delay through the I/O interface

tDIN Input Buffer to Data delay through the I/O interface

tPYS Pad to Data delay through the Input Buffer with Schmitt trigger enabled

tHZ Enable to Pad delay through the Output Buffer—HIGH to Z

tZH Enable to Pad delay through the Output Buffer—Z to HIGH

tLZ Enable to Pad delay through the Output Buffer—LOW to Z

tZL Enable to Pad delay through the Output Buffer—Z to LOW

tZHS Enable to Pad delay through the Output Buffer with delayed enable—Z to HIGH

tZLS Enable to Pad delay through the Output Buffer with delayed enable—Z to LOW

ProASIC3E DC and Switching Characteristics

v1.2 2-19

Table 2-17 • Summary of I/O Timing Characteristics—Software Default Settings

–2 Speed Grade, Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI =3.0V

I/O Standard

Drive Strength (mA)

Slew Rate

Capacitive Load (pF)

External Resistor (Ω)

tDOUT (ns)

tDP (ns)

tDIN (ns)

tPY (ns)

tPYS (ns)

tEOUT (ns)

tZL (ns)

tZH (ns)

tLZ (ns)

tHZ (ns)

tZLS (ns)

tZHS (ns)

3.3 V LVTTL /

3.3 V LVCMOS

12 High 35 – 0.49 2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46 3.81

2.5 V LVCMOS 12 High 35 – 0.49 2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28

1.8 V LVCMOS 12 High 35 – 0.49 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98

1.5 V LVCMOS 12 High 35 – 0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37

3.3 V PCI Per PCI spec High 10 25 2 0.49 2.09 0.03 0.78 1.17 0.32 2.13 1.49 2.45 2.70 3.80 3.16

3.3 V PCI-X Per PCI-X spec High 10 25 2 0.49 2.09 0.03 0.78 1.17 0.32 2.13 1.49 2.45 2.70 3.80 3.16

3.3 V GTL 25 High 10 25 0.45 1.55 0.03 2.19 – 0.32 1.52 1.55 – – 3.19 3.22

2.5 V GTL 25 High 10 25 0.45 1.59 0.03 1.83 – 0.32 1.61 1.59 – – 3.28 3.26

3.3 V GTL+ 35 High 10 25 0.45 1.53 0.03 1.19 – 0.32 1.56 1.53 – – 3.23 3.20

2.5 V GTL+ 33 High 10 25 0.45 1.65 0.03 1.13 – 0.32 1.68 1.57 – – 3.35 3.24

HSTL (I) 8 High 20 50 0.49 2.37 0.03 1.59 – 0.32 2.42 2.35 – – 4.09 4.02

HSTL (II) 15 High 20 25 0.49 2.26 0.03 1.59 – 0.32 2.30 2.03 – – 3.97 3.70

SSTL2 (I) 15 High 30 50 0.49 1.59 0.03 1.00 – 0.32 1.62 1.38 – – 3.29 3.05

SSTL2 (II) 18 High 30 25 0.49 1.62 0.03 1.00 – 0.32 1.65 1.32 – – 3.32 2.99

SSTL3 (I) 14 High 30 50 0.49 1.72 0.03 0.93 – 0.32 1.75 1.37 – – 3.42 3.04

SSTL3 (II) 21 High 30 25 0.49 1.54 0.03 0.93 – 0.32 1.57 1.25 – – 3.24 2.92

LVDS/B-LVDS/

M-LVDS

24 High – – 0.49 1.40 0.03 1.36 – – – – – – – –

LVPECL 24 High – – 0.49 1.36 0.03 1.22 – – – – – – – –

Notes:

1. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

2. Resistance is used to measure I/O propagation delays as defined in PCI specifications. See Figure 2-10 on

page 2-35 for connectivity. This resistor is not required during normal operation.

ProASIC3E DC and Switching Characteristics

2-20 v1.2

Detailed I/O DC Characteristics

Table 2-18 • Input Capacitance

Symbol Definition Conditions Min. Max. Units

CIN Input capacitance VIN = 0, f = 1.0 MHz 8 pF

CINCLK Input capacitance on the clock pin VIN = 0, f = 1.0 MHz 8 pF

Table 2-19 • I/O Output Buffer Maximum Resistances1

Standard Drive Strength RPULL-DOWN (Ω)2RPULL-UP (Ω)3

3.3 V LVTTL / 3.3 V LVCMOS 4 mA 100 300

8 mA 50 150

12 mA 25 75

16 mA 17 50

24 mA 11 33

2.5 V LVCMOS 4 mA 100 200

8 mA 50 100

12 mA 25 50

16 mA 20 40

24 mA 11 22

1.8 V LVCMOS 2 mA 200 225

4 mA 100 112

6 mA 50 56

8 mA 50 56

12 mA 20 22

16 mA 20 22

1.5 V LVCMOS 2 mA 200 224

4 mA 100 112

6 mA 67 75

8 mA 33 37

12 mA 33 37

3.3 V PCI/PCI-X Per PCI/PCI-X specification 25 75

3.3 V GTL 25 mA 11 –

2.5 V GTL 25 mA 14 –

3.3 V GTL+ 35 mA 12 –

2.5 V GTL+ 33 mA 15 –

HSTL (I) 8 mA 50 50

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer

resistance values depend on VCCI, drive strength selection, temperature, and process. For

board design considerations and detailed output buffer resistances, use the corresponding

IBIS models located on the Actel website at http://www.actel.com/techdocs/models/ibis.html.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

ProASIC3E DC and Switching Characteristics

v1.2 2-21

HSTL (II) 15 mA 25 25

SSTL2 (I) 15 mA 27 31

SSTL2 (II) 18 mA 13 15

SSTL3 (I) 14 mA 44 69

SSTL3 (II) 21 mA 18 32

Table 2-20 • I/O Weak Pull-Up/Pull-Down Resistances

Minimum and Maximum Weak Pull-Up/Pull-Down Resistance Values

VCCI

R((WEAK PULL-UP)1

(Ω)

R(WEAK PULL-DOWN)2

(Ω)

Min. Max. Min. Max.

3.3 V 10 k 45 k 10 k 45 k

2.5 V 11 k 55 k 12 k 74 k

1.8 V 18 k 70 k 17 k 110 k

1.5 V 19 k 90 k 19 k 140 k

Notes:

1. R(WEAK PULL-DOWN-MAX) = (VOLspec) / IWEAK PULL-DOWN-MIN

2. R(WEAK PULL-UP-MAX) = (VCCImax – VOHspec) / IWEAK PULL-UP-MIN

Table 2-19 • I/O Output Buffer Maximum Resistances1 (continued)

Standard Drive Strength RPULL-DOWN (Ω)2RPULL-UP (Ω)3

Notes:

1. These maximum values are provided for informational reasons only. Minimum output buffer

resistance values depend on VCCI, drive strength selection, temperature, and process. For

board design considerations and detailed output buffer resistances, use the corresponding

IBIS models located on the Actel website at http://www.actel.com/techdocs/models/ibis.html.

2. R(PULL-DOWN-MAX) = (VOLspec) / IOLspec

3. R(PULL-UP-MAX) = (VCCImax – VOHspec) / IOHspec

ProASIC3E DC and Switching Characteristics

2-22 v1.2

The length of time an I/O can withstand IOSH/IOSL events depends on the junction temperature. The

reliability data below is based on a 3.3 V, 36 mA I/O setting, which is the worst case for this type of

analysis.

For example, at 110°C, the short current condition would have to be sustained for more than three

months to cause a reliability concern. The I/O design does not contain any short circuit protection,

but such protection would only be needed in extremely prolonged stress conditions.

Table 2-21 • I/O Short Currents IOSH/IOSL

Drive Strength IOSH (mA)* IOSL (mA)*

3.3 V LVTTL / 3.3 V LVCMOS 4 mA 25 27

8 mA 51 54

12 mA 103 109

16 mA 132 127

24 mA 268 181

2.5 V LVCMOS 4 mA 16 18

8 mA 32 37

12 mA 65 74

16 mA 83 87

24 mA 169 124

1.8 V LVCMOS 2 mA 9 11

4 mA 17 22

6 mA 35 44

8 mA 45 51

12 mA 91 74

16 mA 91 74

1.5 V LVCMOS 2 mA 13 16

4 mA 25 33

6 mA 32 39

8 mA 66 55

12 mA 66 55

*TJ = 100°C

Table 2-22 • Duration of Short Circuit Event before Failure

Temperature Time before Failure

–40°C > 20 years

0°C > 20 years

25°C > 20 years

70°C 5 years

85°C 2 years

100°C 6 months

110°C 3 months

ProASIC3E DC and Switching Characteristics

v1.2 2-23

Single-Ended I/O Characteristics

3.3 V LVTTL / 3.3 V LVCMOS

Low-Voltage Transistor–Transistor Logic is a general-purpose standard (EIA/JESD) for 3.3 V

applications. It uses an LVTTL input buffer and push-pull output buffer. The 3.3 V LVCMOS standard

is supported as part of the 3.3 V LVTTL support.

Table 2-23 • Schmitt Trigger Input Hysteresis

Hysteresis Voltage Value (typ.) for Schmitt Mode Input Buffers

Input Buffer Configuration Hysteresis Value (typ.)

3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode) 240 mV

2.5 V LVCMOS (Schmitt trigger mode) 140 mV

1.8 V LVCMOS (Schmitt trigger mode) 80 mV

1.5 V LVCMOS (Schmitt trigger mode) 60 mV

Table 2-24 • I/O Input Rise Time, Fall Time, and Related I/O Reliability*

Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability

LVTTL/LVCMOS (Schmitt trigger

disabled)

No requirement 10 ns * 20 years (110°C)

LVTTL/LVCMOS (Schmitt trigger

enabled)

No requirement No requirement, but input noise

voltage cannot exceed Schmitt

hysteresis.

20 years (110°C)

HSTL/SSTL/GTL No requirement 10 ns * 10 years (100°C)

LVDS/B-LVDS/M-LVDS/

LVPECL

No requirement 10 ns * 10 years (100°C)

*For clock signals and similar edge-generating signals, refer to ProASIC3/E SSO and Pin Placement Guidelines.

The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low,

then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the

rise/fall times, the more susceptible the input signal is to the board noise. Actel recommends signal integrity

evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals.

Table 2-25 • Minimum and Maximum DC Input and Output Levels

3.3 V LVTTL /

3.3 V LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

4 mA –0.3 0.8 2 3.6 0.4 2.4 4 4 27 25 10 10

8 mA –0.3 0.8 2 3.6 0.4 2.4 8 8 54 51 10 10

12 mA –0.3 0.8 23.6 0.4 2.4 12 12 109 103 10 10

16 mA –0.3 0.8 2 3.6 0.4 2.4 16 16 127 132 10 10

24 mA –0.3 0.8 2 3.6 0.4 2.4 24 24 181 268 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

ProASIC3E DC and Switching Characteristics

2-24 v1.2

Timing Characteristics

Figure 2-6 • AC Loading

Table 2-26 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring Point*

(V) VREF (typ.) (V) CLOAD (pF)

0 3.3 1.4 – 35

*Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

Table 2-27 • 3.3 V LVTTL / 3.3 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.79 9.47 0.05 1.44 1.88 0.51 9.64 8.05 3.23 3.11 12.33 10.74 ns

Std. 0.66 7.88 0.04 1.20 1.57 0.43 8.03 6.70 2.69 2.59 10.26 8.94 ns

–1 0.56 6.71 0.04 1.02 1.33 0.36 6.83 5.70 2.29 2.20 8.73 7.60 ns

–2 0.49 5.89 0.03 0.90 1.17 0.32 6.00 5.01 2.01 1.93 7.67 6.67 ns

8 mA –F 0.79 6.10 0.05 1.44 1.88 0.51 6.21 4.98 3.66 3.86 8.90 7.66 ns

Std. 0.66 5.08 0.04 1.20 1.57 0.43 5.17 4.14 3.05 3.21 7.41 6.38 ns

–1 0.56 4.32 0.04 1.02 1.33 0.36 4.40 3.52 2.59 2.73 6.30 5.43 ns

–2 0.49 3.79 0.03 0.90 1.17 0.32 3.86 3.09 2.28 2.40 5.53 4.76 ns

12 mA –F 0.79 4.41 0.05 1.44 1.88 0.51 4.49 3.45 3.93 4.34 7.17 6.13 ns

Std. 0.66 3.67 0.04 1.20 1.57 0.43 3.74 2.87 3.28 3.61 5.97 5.11 ns

–1 0.56 3.12 0.04 1.02 1.33 0.36 3.18 2.44 2.79 3.07 5.08 4.34 ns

–2 0.49 2.74 0.03 0.90 1.17 0.32 2.79 2.14 2.45 2.70 4.46 3.81 ns

16 mA –F 0.79 4.16 0.05 1.44 1.88 0.51 4.24 3.13 4.00 4.47 6.92 5.82 ns

Std. 0.66 3.46 0.04 1.20 1.57 0.43 3.53 2.61 3.33 3.72 5.76 4.84 ns

–1 0.56 2.95 0.04 1.02 1.33 0.36 3.00 2.22 2.83 3.17 4.90 4.12 ns

–2 0.49 2.59 0.03 0.90 1.17 0.32 2.63 1.95 2.49 2.78 4.30 3.62 ns

24 mA –F 0.79 3.85 0.05 1.44 1.88 0.51 3.92 2.59 4.07 4.96 6.61 5.28 ns

Std. 0.66 3.21 0.04 1.20 1.57 0.43 3.27 2.16 3.39 4.13 5.50 4.39 ns

–1 0.56 2.73 0.04 1.02 1.33 0.36 2.78 1.83 2.88 3.51 4.68 3.74 ns

–2 0.49 2.39 0.03 0.90 1.17 0.32 2.44 1.61 2.53 3.08 4.11 3.28 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

v1.2 2-25

Table 2-28 • 3.3 V LVTTL / 3.3 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.79 13.22 0.05 1.44 1.88 0.51 13.47 10.87 3.23 2.93 16.16 13.56 ns

Std. 0.66 11.01 0.04 1.20 1.57 0.43 11.21 9.05 2.69 2.44 13.45 11.29 ns

–1 0.56 9.36 0.04 1.02 1.33 0.36 9.54 7.70 2.29 2.08 11.44 9.60 ns

–2 0.49 8.22 0.03 0.90 1.17 0.32 8.37 6.76 2.01 1.82 10.04 8.43 ns

8 mA –F 0.79 9.45 0.05 1.44 1.88 0.51 9.62 7.74 3.65 3.68 12.31 10.42 ns

Std. 0.66 7.86 0.04 1.20 1.57 0.43 8.01 6.44 3.04 3.06 10.24 8.68 ns

–1 0.56 6.69 0.04 1.02 1.33 0.36 6.81 5.48 2.58 2.61 8.71 7.38 ns

–2 0.49 5.87 0.03 0.90 1.17 0.32 5.98 4.81 2.27 2.29 7.65 6.48 ns

12 mA –F 0.79 7.24 0.05 1.44 1.88 0.51 7.37 6.03 3.93 4.17 10.06 8.72 ns

Std. 0.66 6.03 0.04 1.20 1.57 0.43 6.14 5.02 3.28 3.47 8.37 7.26 ns

–1 0.56 5.13 0.04 1.02 1.33 0.36 5.22 4.27 2.79 2.95 7.12 6.17 ns

–2 0.49 4.50 0.03 0.90 1.17 0.32 4.58 3.75 2.45 2.59 6.25 5.42 ns

16 mA –F 0.79 6.75 0.05 1.44 1.88 0.51 6.87 5.68 3.99 4.30 9.56 8.36 ns

Std. 0.66 5.62 0.04 1.20 1.57 0.43 5.72 4.72 3.32 3.58 7.96 6.96 ns

–1 0.56 4.78 0.04 1.02 1.33 0.36 4.87 4.02 2.83 3.04 6.77 5.92 ns

–2 0.49 4.20 0.03 0.90 1.17 0.32 4.27 3.53 2.48 2.67 5.94 5.20 ns

24 mA –F 0.79 6.30 0.05 1.44 1.88 0.51 6.42 5.64 4.07 4.76 9.10 8.32 ns

Std. 0.66 5.24 0.04 1.20 1.57 0.43 5.34 4.69 3.39 3.96 7.58 6.93 ns

–1 0.56 4.46 0.04 1.02 1.33 0.36 4.54 3.99 2.88 3.37 6.44 5.89 ns

–2 0.49 3.92 0.03 0.90 1.17 0.32 3.99 3.50 2.53 2.96 5.66 5.17 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

2-26 v1.2

2.5 V LVCMOS

Low-Voltage CMOS for 2.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 2.5 V applications. It uses a 5 V–tolerant input buffer and push-pull output buffer.

Table 2-29 • Minimum and Maximum DC Input and Output Levels

2.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

4 mA –0.3 0.7 1.7 3.6 0.7 1.7 4 4 18 16 10 10

8 mA –0.3 0.7 1.7 3.6 0.7 1.7 8 8 37 32 10 10

12 mA –0.3 0.7 1.7 3.6 0.7 1.7 12 12 74 65 10 10

16 mA –0.3 0.7 1.7 3.6 0.7 1.7 16 16 87 83 10 10

24 mA –0.3 0.7 1.7 3.6 0.7 1.7 24 24 124 169 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 2-7 • AC Loading

Table 2-30 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring Point*

(V) VREF (typ.) (V) CLOAD (pF)

0 2.5 1.2 – 35

*Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC3E DC and Switching Characteristics

v1.2 2-27

Timing Characteristics

Table 2-31 • 2.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.79 10.59 0.05 1.82 1.99 0.51 9.77 10.59 3.26 2.75 12.45 13.28 ns

Std. 0.66 8.82 0.04 1.51 1.66 0.43 8.13 8.82 2.72 2.29 10.37 11.05 ns

–1 0.56 7.50 0.04 1.29 1.41 0.36 6.92 7.50 2.31 1.95 8.82 9.40 ns

–2 0.49 6.58 0.03 1.13 1.24 0.32 6.07 6.58 2.03 1.71 7.74 8.25 ns

8 mA –F 0.79 6.33 0.05 1.82 1.99 0.51 6.33 6.33 3.73 3.64 9.02 9.02 ns

Std. 0.66 5.27 0.04 1.51 1.66 0.43 5.27 5.27 3.10 3.03 7.50 7.51 ns

–1 0.56 4.48 0.04 1.29 1.41 0.36 4.48 4.48 2.64 2.58 6.38 6.38 ns

–2 0.49 3.94 0.03 1.13 1.24 0.32 3.93 3.94 2.32 2.26 5.60 5.61 ns

12 mA –F 0.79 4.50 0.05 1.82 1.99 0.51 4.58 4.19 4.04 4.20 7.27 6.88 ns

Std. 0.66 3.74 0.04 1.51 1.66 0.43 3.81 3.49 3.37 3.49 6.05 5.73 ns

–1 0.56 3.18 0.04 1.29 1.41 0.36 3.24 2.97 2.86 2.97 5.15 4.87 ns

–2 0.49 2.80 0.03 1.13 1.24 0.32 2.85 2.61 2.51 2.61 4.52 4.28 ns

16 mA –F 0.79 4.24 0.05 1.82 1.99 0.51 4.32 3.75 4.11 4.35 7.00 6.43 ns

Std. 0.66 3.53 0.04 1.51 1.66 0.43 3.59 3.12 3.42 3.62 5.83 5.35 ns

–1 0.56 3.00 0.04 1.29 1.41 0.36 3.06 2.65 2.91 3.08 4.96 4.55 ns

–2 0.49 2.63 0.03 1.13 1.24 0.32 2.68 2.33 2.56 2.71 4.35 4.00 ns

24 mA –F 0.79 3.92 0.05 1.82 1.99 0.51 3.99 2.98 4.20 4.93 6.68 5.67 ns

Std. 0.66 3.26 0.04 1.51 1.66 0.43 3.32 2.48 3.49 4.11 5.56 4.72 ns

–1 0.56 2.77 0.04 1.29 1.41 0.36 2.83 2.11 2.97 3.49 4.73 4.01 ns

–2 0.49 2.44 0.03 1.13 1.24 0.32 2.48 1.85 2.61 3.07 4.15 3.52 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

2-28 v1.2

Table 2-32 • 2.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

4 mA –F 0.79 14.42 0.05 1.82 1.99 0.51 14.69 13.95 3.26 2.64 17.37 16.63 ns

Std. 0.66 12.00 0.04 1.51 1.66 0.43 12.23 11.61 2.72 2.20 14.46 13.85 ns

–1 0.56 10.21 0.04 1.29 1.41 0.36 10.40 9.88 2.31 1.87 12.30 11.78 ns

–2 0.49 8.96 0.03 1.13 1.24 0.32 9.13 8.67 2.03 1.64 10.80 10.34 ns

8 mA –F 0.79 10.49 0.05 1.82 1.99 0.51 10.68 9.62 3.73 3.52 13.37 12.31 ns

Std. 0.66 8.73 0.04 1.51 1.66 0.43 8.89 8.01 3.10 2.93 11.13 10.25 ns

–1 0.56 7.43 0.04 1.29 1.41 0.36 7.57 6.82 2.64 2.49 9.47 8.72 ns

–2 0.49 6.52 0.03 1.13 1.24 0.32 6.64 5.98 2.32 2.19 8.31 7.65 ns

12 mA –F 0.79 8.14 0.05 1.82 1.99 0.51 8.29 7.34 4.04 4.08 10.97 10.02 ns

Std. 0.66 6.77 0.04 1.51 1.66 0.43 6.90 6.11 3.37 3.39 9.14 8.34 ns

–1 0.56 5.76 0.04 1.29 1.41 0.36 5.87 5.20 2.86 2.89 7.77 7.10 ns

–2 0.49 5.06 0.03 1.13 1.24 0.32 5.15 4.56 2.51 2.53 6.82 6.23 ns

16 mA –F 0.79 7.58 0.05 1.82 1.99 0.51 7.72 6.88 4.11 4.23 10.40 9.57 ns

Std. 0.66 6.31 0.04 1.51 1.66 0.43 6.42 5.73 3.42 3.52 8.66 7.96 ns

–1 0.56 5.37 0.04 1.29 1.41 0.36 5.46 4.87 2.91 3.00 7.37 6.77 ns

–2 0.49 4.71 0.03 1.13 1.24 0.32 4.80 4.28 2.56 2.63 6.47 5.95 ns

24 mA –F 0.79 7.13 0.05 1.82 1.99 0.51 7.26 6.85 4.20 4.80 9.94 9.54 ns

Std. 0.66 5.93 0.04 1.51 1.66 0.43 6.04 5.70 3.49 4.00 8.28 7.94 ns

–1 0.56 5.05 0.04 1.29 1.41 0.36 5.14 4.85 2.97 3.40 7.04 6.75 ns

–2 0.49 4.43 0.03 1.13 1.24 0.32 4.51 4.26 2.61 2.99 6.18 5.93 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

v1.2 2-29

1.8 V LVCMOS

Low-Voltage CMOS for 1.8 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.8 V applications. It uses a 1.8 V input buffer and a push-pull output buffer.

Table 2-33 • Minimum and Maximum DC Input and Output Levels

1.8 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1μA2μA2

2 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 2 2 11 9 10 10

4 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 4 4 22 17 10 10

6 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 6 6 44 35 10 10

8 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 8 8 51 45 10 10

12 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 12 12 74 91 10 10

16 mA –0.3 0.35 * VCCI 0.65 * VCCI 3.6 0.45 VCCI – 0.45 16 16 74 91 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 2-8 • AC Loading

Table 2-34 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring Point*

(V) VREF (typ.) (V) CLOAD (pF)

0 1.8 0.9 – 35

*Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC3E DC and Switching Characteristics

2-30 v1.2

Timing Characteristics

Table 2-35 • 1.8 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 14.54 0.05 1.74 2.29 0.51 11.52 14.54 3.34 1.97 14.21 17.23 ns

Std. 0.66 12.10 0.04 1.45 1.91 0.43 9.59 12.10 2.78 1.64 11.83 14.34 ns

–1 0.56 10.30 0.04 1.23 1.62 0.36 8.16 10.30 2.37 1.39 10.06 12.20 ns

–2 0.49 9.04 0.03 1.08 1.42 0.32 7.16 9.04 2.08 1.22 8.83 10.71 ns

4 mA –F 0.79 8.47 0.05 1.74 2.29 0.51 7.45 8.47 3.90 3.44 10.14 11.16 ns

Std. 0.66 7.05 0.04 1.45 1.91 0.43 6.20 7.05 3.25 2.86 8.44 9.29 ns

–1 0.56 6.00 0.04 1.23 1.62 0.36 5.28 6.00 2.76 2.44 7.18 7.90 ns

–2 0.49 5.27 0.03 1.08 1.42 0.32 4.63 5.27 2.43 2.14 6.30 6.94 ns

6 mA –F 0.79 5.43 0.05 1.74 2.29 0.51 5.36 5.43 4.29 4.17 8.05 8.12 ns

Std. 0.66 4.52 0.04 1.45 1.91 0.43 4.47 4.52 3.57 3.47 6.70 6.76 ns

–1 0.56 3.85 0.04 1.23 1.62 0.36 3.80 3.85 3.04 2.95 5.70 5.75 ns

–2 0.49 3.38 0.03 1.08 1.42 0.32 3.33 3.38 2.66 2.59 5.00 5.05 ns

8 mA –F 0.79 4.95 0.05 1.74 2.29 0.51 5.04 4.80 4.36 4.35 7.73 7.48 ns

Std. 0.66 4.12 0.04 1.45 1.91 0.43 4.20 3.99 3.63 3.62 6.43 6.23 ns

–1 0.56 3.51 0.04 1.23 1.62 0.36 3.57 3.40 3.09 3.08 5.47 5.30 ns

–2 0.49 3.08 0.03 1.08 1.42 0.32 3.14 2.98 2.71 2.71 4.81 4.65 ns

12 mA –F 0.79 4.56 0.05 1.74 2.29 0.51 4.64 3.71 4.48 5.09 7.33 6.40 ns

Std. 0.66 3.80 0.04 1.45 1.91 0.43 3.87 3.09 3.73 4.24 6.10 5.32 ns

–1 0.56 3.23 0.04 1.23 1.62 0.36 3.29 2.63 3.18 3.60 5.19 4.53 ns

–2 0.49 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98 ns

16 mA –F 0.79 4.56 0.05 1.74 2.29 0.51 4.64 3.71 4.48 5.09 7.33 6.40 ns

Std. 0.66 3.80 0.04 1.45 1.91 0.43 3.87 3.09 3.73 4.24 6.10 5.32 ns

–1 0.56 3.23 0.04 1.23 1.62 0.36 3.29 2.63 3.18 3.60 5.19 4.53 ns

–2 0.49 2.83 0.03 1.08 1.42 0.32 2.89 2.31 2.79 3.16 4.56 3.98 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

v1.2 2-31

Table 2-36 • 1.8 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 19.03 0.05 1.74 2.29 0.51 18.80 19.03 3.34 1.90 21.49 21.71 ns

Std. 0.66 15.84 0.04 1.45 1.91 0.43 15.65 15.84 2.78 1.58 17.89 18.07 ns

–1 0.56 13.47 0.04 1.23 1.62 0.36 13.31 13.47 2.37 1.35 15.22 15.37 ns

–2 0.49 11.83 0.03 1.08 1.42 0.32 11.69 11.83 2.08 1.18 13.36 13.50 ns

4 mA –F 0.79 13.68 0.05 1.74 2.29 0.51 13.94 12.92 3.91 3.33 16.62 15.61 ns

Std. 0.66 11.39 0.04 1.45 1.91 0.43 11.60 10.76 3.26 2.77 13.84 12.99 ns

–1 0.56 9.69 0.04 1.23 1.62 0.36 9.87 9.15 2.77 2.36 11.77 11.05 ns

–2 0.49 8.51 0.03 1.08 1.42 0.32 8.66 8.03 2.43 2.07 10.33 9.70 ns

6 mA –F 0.79 10.78 0.05 1.74 2.29 0.51 10.98 9.73 4.29 4.03 13.66 12.41 ns

Std. 0.66 8.97 0.04 1.45 1.91 0.43 9.14 8.10 3.57 3.36 11.37 10.33 ns

–1 0.56 7.63 0.04 1.23 1.62 0.36 7.77 6.89 3.04 2.86 9.67 8.79 ns

–2 0.49 6.70 0.03 1.08 1.42 0.32 6.82 6.05 2.66 2.51 8.49 7.72 ns

8 mA –F 0.79 10.03 0.05 1.74 2.29 0.51 10.22 9.11 4.37 4.23 12.90 11.80 ns

Std. 0.66 8.35 0.04 1.45 1.91 0.43 8.50 7.59 3.64 3.52 10.74 9.82 ns

–1 0.56 7.10 0.04 1.23 1.62 0.36 7.23 6.45 3.10 3.00 9.14 8.35 ns

–2 0.49 6.24 0.03 1.08 1.42 0.32 6.35 5.66 2.72 2.63 8.02 7.33 ns

12 mA –F 0.79 9.54 0.05 1.74 2.29 0.51 9.72 9.08 4.50 4.93 12.40 11.77 ns

Std. 0.66 7.94 0.04 1.45 1.91 0.43 8.09 7.56 3.74 4.11 10.32 9.80 ns

–1 0.56 6.75 0.04 1.23 1.62 0.36 6.88 6.43 3.18 3.49 8.78 8.33 ns

–2 0.49 5.93 0.03 1.08 1.42 0.32 6.04 5.65 2.79 3.07 7.71 7.32 ns

16 mA –F 0.79 9.54 0.05 1.74 2.29 0.51 9.72 9.08 4.50 4.93 12.40 11.77 ns

Std. 0.66 7.94 0.04 1.45 1.91 0.43 8.09 7.56 3.74 4.11 10.32 9.80 ns

–1 0.56 6.75 0.04 1.23 1.62 0.36 6.88 6.43 3.18 3.49 8.78 8.33 ns

–2 0.49 5.93 0.03 1.08 1.42 0.32 6.04 5.65 2.79 3.07 7.71 7.32 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

2-32 v1.2

1.5 V LVCMOS (JESD8-11)

Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-

purpose 1.5 V applications. It uses a 1.5 V input buffer and a push-pull output buffer.

Table 2-37 • Minimum and Maximum DC Input and Output Levels

1.5 V

LVCMOS VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1μA2μA2

2 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 2 2 16 13 10 10

4 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 4 4 33 25 10 10

6 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 6 6 39 32 10 10

8 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 8 8 55 66 10 10

12 mA –0.3 0.30 * VCCI 0.7 * VCCI 3.6 0.25 * VCCI 0.75 * VCCI 12 12 55 66 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Software default selection highlighted in gray.

Figure 2-9 • AC Loading

Table 2-38 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring Point*

(V) VREF (typ.) (V) CLOAD (pF)

0 1.5 0.75 – 35

*Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Test Point Test Point

Enable Path

Datapath 35 pF

R = 1 k R to VCCI for tLZ/tZL/tZLS

R to GND for tHZ/tZH/tZHS

35 pF for tZH/tZHS/tZL/tZLS

5 pF for tHZ/tLZ

ProASIC3E DC and Switching Characteristics

v1.2 2-33

Timing Characteristics

Table 2-39 • 1.5 V LVCMOS High Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 10.25 0.05 2.04 2.58 0.51 8.72 10.25 4.08 3.35 11.41 12.94 ns

Std. 0.66 8.53 0.04 1.70 2.14 0.43 7.26 8.53 3.39 2.79 9.50 10.77 ns

–1 0.56 7.26 0.04 1.44 1.82 0.36 6.18 7.26 2.89 2.37 8.08 9.16 ns

–2 0.49 6.37 0.03 1.27 1.60 0.32 5.42 6.37 2.53 2.08 7.09 8.04 ns

4 mA –F 0.79 6.50 0.05 2.04 2.58 0.51 6.27 6.50 4.51 4.18 8.95 9.19 ns

Std. 0.66 5.41 0.04 1.70 2.14 0.43 5.22 5.41 3.75 3.48 7.45 7.65 ns

–1 0.56 4.60 0.04 1.44 1.82 0.36 4.44 4.60 3.19 2.96 6.34 6.50 ns

–2 0.49 4.04 0.03 1.27 1.60 0.32 3.89 4.04 2.80 2.60 5.56 5.71 ns

6 mA –F 0.79 5.77 0.05 2.04 2.58 0.51 5.88 5.70 4.60 4.41 8.56 8.39 ns

Std. 0.66 4.80 0.04 1.70 2.14 0.43 4.89 4.75 3.83 3.67 7.13 6.98 ns

–1 0.56 4.09 0.04 1.44 1.82 0.36 4.16 4.04 3.26 3.12 6.06 5.94 ns

–2 0.49 3.59 0.03 1.27 1.60 0.32 3.65 3.54 2.86 2.74 5.32 5.21 ns

8 mA –F 0.79 5.31 0.05 2.04 2.58 0.51 5.41 4.35 4.76 5.25 8.09 7.04 ns

Std. 0.66 4.42 0.04 1.70 2.14 0.43 4.50 3.62 3.96 4.37 6.74 5.86 ns

–1 0.56 3.76 0.04 1.44 1.82 0.36 3.83 3.08 3.37 3.72 5.73 4.98 ns

–2 0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37 ns

12 mA –F 0.79 5.31 0.05 2.04 2.58 0.51 5.41 4.35 4.76 5.25 8.09 7.04 ns

Std. 0.66 4.42 0.04 1.70 2.14 0.43 4.50 3.62 3.96 4.37 6.74 5.86 ns

–1 0.56 3.76 0.04 1.44 1.82 0.36 3.83 3.08 3.37 3.72 5.73 4.98 ns

–2 0.49 3.30 0.03 1.27 1.60 0.32 3.36 2.70 2.96 3.27 5.03 4.37 ns

Notes:

1. Software default selection highlighted in gray.

2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

2-34 v1.2

Table 2-40 • 1.5 V LVCMOS Low Slew

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.4 V

Drive

Strength

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

2 mA –F 0.79 16.95 0.05 2.04 2.58 0.51 17.26 15.78 4.09 3.22 19.95 18.47 ns

Std. 0.66 14.11 0.04 1.70 2.14 0.43 14.37 13.14 3.40 2.68 16.61 15.37 ns

–1 0.56 12.00 0.04 1.44 1.82 0.36 12.22 11.17 2.90 2.28 14.13 13.08 ns

–2 0.49 10.54 0.03 1.27 1.60 0.32 10.73 9.81 2.54 2.00 12.40 11.48 ns

4 mA –F 0.79 13.49 0.05 2.04 2.58 0.51 13.74 11.85 4.53 4.03 16.43 14.54 ns

Std. 0.66 11.23 0.04 1.70 2.14 0.43 11.44 9.87 3.77 3.36 13.68 12.10 ns

–1 0.56 9.55 0.04 1.44 1.82 0.36 9.73 8.39 3.21 2.86 11.63 10.29 ns

–2 0.49 8.39 0.03 1.27 1.60 0.32 8.54 7.37 2.81 2.51 10.21 9.04 ns

6 mA –F 0.79 12.56 0.05 2.04 2.58 0.51 12.79 11.10 4.62 4.26 15.48 13.79 ns

Std. 0.66 10.45 0.04 1.70 2.14 0.43 10.65 9.24 3.84 3.55 12.88 11.48 ns

–1 0.56 8.89 0.04 1.44 1.82 0.36 9.06 7.86 3.27 3.02 10.96 9.76 ns

–2 0.49 7.81 0.03 1.27 1.60 0.32 7.95 6.90 2.87 2.65 9.62 8.57 ns

8 mA –F 0.79 12.04 0.05 2.04 2.58 0.51 12.26 11.09 4.77 5.07 14.94 13.77 ns

Std. 0.66 10.02 0.04 1.70 2.14 0.43 10.20 9.23 3.97 4.22 12.44 11.47 ns

–1 0.56 8.52 0.04 1.44 1.82 0.36 8.68 7.85 3.38 3.59 10.58 9.75 ns

–2 0.49 7.48 0.03 1.27 1.60 0.32 7.62 6.89 2.97 3.15 9.29 8.56 ns

12 mA –F 0.79 12.04 0.05 2.04 2.58 0.51 12.26 11.09 4.77 5.07 14.94 13.77 ns

Std. 0.66 10.02 0.04 1.70 2.14 0.43 10.20 9.23 3.97 4.22 12.44 11.47 ns

–1 0.56 8.52 0.04 1.44 1.82 0.36 8.68 7.85 3.38 3.59 10.58 9.75 ns

–2 0.49 7.48 0.03 1.27 1.60 0.32 7.62 6.89 2.97 3.15 9.29 8.56 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

v1.2 2-35

3.3 V PCI, 3.3 V PCI-X

Peripheral Component Interface for 3.3 V standard specifies support for 33 MHz and 66 MHz PCI

Bus applications.

AC loadings are defined per the PCI/PCI-X specifications for the datapath; Actel loadings for enable

path characterization are described in Figure 2-10.

AC loadings are defined per PCI/PCI-X specifications for the datapath; Actel loading for tristate is

described in Table 2-42.

Timing Characteristics

Table 2-41 • Minimum and Maximum DC Input and Output Levels

3.3 V PCI/PCI-X VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

Per PCI specification Per PCI curves 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 2-10 • AC Loading

Test Point

Enable Path

R to V for t /t /t

CCI LZ ZL ZLS

10 pF for t /t /t /t

ZH ZHS ZLSZL

5 pF for tHZ /tLZ

R to GND for t /t /t

HZ ZH ZH

R = 1 k

Test Point

Datapath

R = 25 R to VCCI for tDP (F)

R to GND for tDP (R)

Table 2-42 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring Point*

(V) VREF (typ.) (V) CLOAD (pF)

0 3.3 0.285 * VCCI for tDP(R)

0.615 * VCCI for tDP(F)

–10

*Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Table 2-43 • 3.3 V PCI/PCI-X

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 3.0 V

Speed

Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.79 3.37 0.05 1.26 2.01 0.51 3.43 2.40 3.93 4.34 6.12 5.08 ns

Std. 0.66 2.81 0.04 1.05 1.67 0.43 2.86 2.00 3.28 3.61 5.09 4.23 ns

–1 0.56 2.39 0.04 0.89 1.42 0.36 2.43 1.70 2.79 3.07 4.33 3.60 ns

–2 0.49 2.09 0.03 0.78 1.25 0.32 2.13 1.49 2.45 2.70 3.80 3.16 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

2-36 v1.2

Voltage-Referenced I/O Characteristics

3.3 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to

3.3 V.

Timing Characteristics

Table 2-44 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

25 mA3–0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 – 25 25 181 268 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Output drive strength is below JEDEC specification.

Figure 2-11 • AC Loading

Table 2-45 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring

Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.05 VREF + 0.05 0.8 0.8 1.2 10

*Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Test Point

10 pF

GTL

VTT

Table 2-46 • 3.3 V GTL

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI =3.0V VREF =0.8V

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.72 2.49 0.05 3.52 0.51 2.45 2.49 5.13 5.18 ns

Std. 0.60 2.08 0.04 2.93 0.43 2.04 2.08 4.27 4.31 ns

–1 0.51 1.77 0.04 2.50 0.36 1.73 1.77 3.63 3.67 ns

–2 0.45 1.55 0.03 2.19 0.32 1.52 1.55 3.19 3.22 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

v1.2 2-37

2.5 V GTL

Gunning Transceiver Logic is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to

2.5 V.

Timing Characteristics

Table 2-47 • Minimum and Maximum DC Input and Output Levels

2.5 GTL VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1μA2μA2

25 mA3–0.3 VREF – 0.05 VREF + 0.05 3.6 0.4 – 25 25 124 169 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Output drive strength is below JEDEC specification.

Figure 2-12 • AC Loading

Table 2-48 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring

Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.05 VREF + 0.05 0.8 0.8 1.2 10

*Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Test Point

10 pF

GTL

VTT

Table 2-49 • 2.5 V GTL

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI =3.0V VREF = 0.8 V

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.72 2.56 0.05 2.95 0.51 2.60 2.56 5.28 5.24 ns

Std. 0.60 2.13 0.04 2.46 0.43 2.16 2.13 4.40 4.36 ns

–1 0.51 1.81 0.04 2.09 0.36 1.84 1.81 3.74 3.71 ns

–2 0.45 1.59 0.03 1.83 0.32 1.61 1.59 3.28 3.26 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

2-38 v1.2

3.3 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to

3.3 V.

Timing Characteristics

Table 2-50 • Minimum and Maximum DC Input and Output Levels

3.3 V GTL+ VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

35 mA –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 – 35 35 181 268 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 2-13 • AC Loading

Table 2-51 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring

Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.1 VREF + 0.1 1.0 1.0 1.5 10

*Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Test Point

10 pF

GTL+

VTT

Table 2-52 • 3.3 V GTL+

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI =3.0V, V

REF = 1.0 V

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.72 2.47 0.05 1.91 0.51 2.51 2.47 5.20 5.15 ns

Std. 0.60 2.06 0.04 1.59 0.43 2.09 2.06 4.33 4.29 ns

–1 0.51 1.75 0.04 1.35 0.36 1.78 1.75 3.68 3.65 ns

–2 0.45 1.53 0.03 1.19 0.32 1.56 1.53 3.23 3.20 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

v1.2 2-39

2.5 V GTL+

Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential

amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to

2.5 V.

Timing Characteristics

Table 2-53 • Minimum and Maximum DC Input and Output Levels

2.5 V GTL+ VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

33 mA –0.3 VREF – 0.1 VREF + 0.1 3.6 0.6 – 33 33 124 169 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 2-14 • AC Loading

Table 2-54 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring

Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.1 VREF + 0.1 1.0 1.0 1.5 10

*Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Test Point

10 pF

GTL+

VTT

Table 2-55 • 2.5 V GTL+

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI =2.3V, V

REF = 1.0 V

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.72 2.65 0.05 1.82 0.51 2.70 2.52 5.38 5.21 ns

Std. 0.60 2.21 0.04 1.51 0.43 2.25 2.10 4.48 4.34 ns

–1 0.51 1.88 0.04 1.29 0.36 1.91 1.79 3.81 3.69 ns

–2 0.45 1.65 0.03 1.13 0.32 1.68 1.57 3.35 3.24 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

2-40 v1.2

HSTL Class I

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).

ProASIC3E devices support Class I. This provides a differential amplifier input buffer and a push-pull

output buffer.

Timing Characteristics

Table 2-56 • Minimum and Maximum DC Input and Output Levels

HSTL Class I VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

8 mA –0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCI – 0.4 8 8 39 32 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 2-15 • AC Loading

Table 2-57 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring Point*

(V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.1 VREF + 0.10.750.750.75 20

*Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Test Point

20 pF

HSTL

Class I

VTT

Table 2-58 • HSTL Class I

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI =.4V, V

REF = 0.75 V

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.79 3.82 0.05 2.55 0.51 3.89 3.78 6.58 6.46 ns

Std. 0.66 3.18 0.04 2.12 0.43 3.24 3.14 5.47 5.38 ns

–1 0.56 2.70 0.04 1.81 0.36 2.75 2.67 4.66 4.58 ns

–2 0.49 2.37 0.03 1.59 0.32 2.42 2.35 4.09 4.02 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

v1.2 2-41

HSTL Class II

High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).

ProASIC3E devices support Class II. This provides a differential amplifier input buffer and a push-

pull output buffer.

Timing Characteristics

Table 2-59 • Minimum and Maximum DC Input and Output Levels

HSTL Class II VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

15 mA3–0.3 VREF – 0.1 VREF + 0.1 3.6 0.4 VCCI-0.4 15 15 55 66 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

3. Output drive strength is below JEDEC specification.

Figure 2-16 • AC Loading

Table 2-60 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring

Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.1 VREF + 0.10.750.750.75 20

*Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Test Point

20 pF

HSTL

Class II

VTT

Table 2-61 • HSTL Class II

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI =1.4V, V

REF = 0.75 V

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.79 3.63 0.05 2.55 0.51 3.70 3.26 6.39 5.95 ns

Std. 0.66 3.02 0.04 2.12 0.43 3.08 2.71 5.32 4.95 ns

–1 0.56 2.57 0.04 1.81 0.36 2.62 2.31 4.52 4.21 ns

–2 0.49 2.26 0.03 1.59 0.32 2.30 2.03 3.97 3.70 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

2-42 v1.2

SSTL2 Class I

Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support

Class I. This provides a differential amplifier input buffer and a push-pull output buffer.

Timing Characteristics

Table 2-62 • Minimum and Maximum DC Input and Output Levels

SSTL2 Class I VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

15 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.54 VCCI – 0.62 15 15 87 83 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 2-17 • AC Loading

Table 2-63 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring

Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.2 VREF + 0.21.251.251.25 30

*Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Test Point

30 pF

SSTL2

Class I

VTT

Table 2-64 • SSTL 2 Class I

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI =2.3V, V

REF = 1.25 V

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.79 2.56 0.05 1.60 0.51 2.60 2.22 5.29 4.90 ns

Std. 0.66 2.13 0.04 1.33 0.43 2.17 1.85 4.40 4.08 ns

–1 0.56 1.81 0.04 1.14 0.36 1.84 1.57 3.74 3.47 ns

–2 0.49 1.59 0.03 1.00 0.32 1.62 1.38 3.29 3.05 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

v1.2 2-43

SSTL2 Class II

Stub-Speed Terminated Logic for 2.5 V memory bus standard (JESD8-9). ProASIC3E devices support

Class II. This provides a differential amplifier input buffer and a push-pull output buffer.

Timing Characteristics

Table 2-65 • Minimum and Maximum DC Input and Output Levels

SSTL2 Class II VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

18 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.35 VCCI – 0.43 18 18 124 169 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 2-18 • AC Loading

Table 2-66 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring

Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.2 VREF + 0.21.251.251.25 30

*Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Test Point

30 pF

SSTL2

Class II

VTT

Table 2-67 • SSTL 2 Class II

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI =2.3V, V

REF = 1.25 V

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.79 0.79 2.60 0.05 1.60 0.51 2.65 2.13 5.34 ns

Std. 0.66 0.66 2.17 0.04 1.33 0.43 2.21 1.77 4.44 ns

–1 0.56 0.56 1.84 0.04 1.14 0.36 1.88 1.51 3.78 ns

–2 0.49 0.49 1.62 0.03 1.00 0.32 1.65 1.32 3.32 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

2-44 v1.2

SSTL3 Class I

Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support

Class I. This provides a differential amplifier input buffer and a push-pull output buffer.

Timing Characteristics

Table 2-68 • Minimum and Maximum DC Input and Output Levels

SSTL3 Class I VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

14 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.7 VCCI – 1.1 14 14 54 51 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 2-19 • AC Loading

Table 2-69 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring

Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.2 VREF + 0.2 1.5 1.5 1.485 30

*Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Test Point

30 pF

SSTL3

Class I

VTT

Table 2-70 • SSTL3 Class I

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI =3.0V, V

REF = 1.5 V

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.79 2.77 0.05 1.50 0.51 2.82 2.21 5.51 4.89 ns

Std. 0.66 2.31 0.04 1.25 0.43 2.35 1.84 4.59 4.07 ns

–1 0.56 1.96 0.04 1.06 0.36 2.00 1.56 3.90 3.46 ns

–2 0.49 1.72 0.03 0.93 0.32 1.75 1.37 3.42 3.04 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

v1.2 2-45

SSTL3 Class II

Stub-Speed Terminated Logic for 3.3 V memory bus standard (JESD8-8). ProASIC3E devices support

Class II. This provides a differential amplifier input buffer and a push-pull output buffer.

Timing Characteristics

Table 2-71 • Minimum and Maximum DC Input and Output Levels

SSTL3 Class II VIL VIH VOL VOH IOL IOH IOSL IOSH IIL IIH

Drive

Strength Min., V Max., V Min., V Max., V Max., V Min., V mA mA Max., mA1Max., mA1µA2µA2

21 mA –0.3 VREF – 0.2 VREF + 0.2 3.6 0.5 VCCI – 0.9 21 21 109 103 10 10

Notes:

1. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.

2. Currents are measured at 85°C junction temperature.

Figure 2-20 • AC Loading

Table 2-72 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V)

Measuring

Point* (V) VREF (typ.) (V) VTT (typ.) (V) CLOAD (pF)

VREF – 0.2 VREF + 0.2 1.5 1.5 1.485 30

*Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

Test Point

30 pF

SSTL3

Class II

VTT

Table 2-73 • SSTL3 Class II

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V,

Worst-Case VCCI =3.0V, V

REF = 1.5 V

Speed

Grade tDOUT tDP tDIN tPY tEOUT tZL tZH tLZ tHZ tZLS tZHS Units

–F 0.79 2.48 0.05 1.50 0.51 2.53 2.01 5.21 4.69 ns

Std. 0.66 2.07 0.04 1.25 0.43 2.10 1.67 4.34 3.91 ns

–1 0.56 1.76 0.04 1.06 0.36 1.79 1.42 3.69 3.32 ns

–2 0.49 1.54 0.03 0.93 0.32 1.57 1.25 3.24 2.92 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

2-46 v1.2

Differential I/O Characteristics

Physical Implementation

Configuration of the I/O modules as a differential pair is handled by the Actel Designer software

when the user instantiates a differential I/O macro in the design.

Differential I/Os can also be used in conjunction with the embedded Input Register (InReg), Output

bidirectional I/Os or tristates with the LVPECL standards.

LVDS

Low-Voltage Differential Signaling (ANSI/TIA/EIA-644) is a high-speed, differential I/O standard. It

requires that one data bit be carried through two signal lines, so two pins are needed. It also

requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in

Figure 2-21. The building blocks of the LVDS transmitter-receiver are one transmitter macro, one

receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.

The values for the three driver resistors are different from those used in the LVPECL

implementation because the output standard specifications are different.

Along with LVDS I/O, ProASIC3E also supports Bus LVDS structure and Multipoint LVDS (M-LVDS)

configuration (up to 40 nodes).

Figure 2-21 • LVDS Circuit Diagram and Board-Level Implementation

140 Ω100 Ω

Z0 = 50 Ω

165 Ω

–

INBUF_LVDS

OUTBUF_LVDS

FPGA FPGA

Bourns Part Number: CAT16-LV4F12

ProASIC3E DC and Switching Characteristics

v1.2 2-47

Table 2-74 • LVDS Minimum and Maximum DC Input and Output Levels

DC Parameter Description Min. Typ. Max. Units

VCCI Supply Voltage 1 2.375 2.5 2.625 V

VOL Output Low Voltage 0.9 1.075 1.25 V

VOH Output High Voltage 1.25 1.425 1.6 V

IOL 4 Output Lower Current 0.65 0.91 1.16 mA

IOH 4 Output High Current 0.65 0.91 1.16 mA

VI Input Voltage 0 2.925 V

IIH 3Input High Leakage Current 10 µA

IIL 3Input Low Leakage Current 10 µA

VODIFF Differential Output Voltage 250 350 450 mV

VOCM Output Common Mode Voltage 1.125 1.25 1.375 V

VICM Input Common Mode Voltage 0.05 1.25 2.35 V

VIDIFF Input Differential Voltage 2 100 350 mV

Notes:

1. ±5%

2. Differential input voltage = ±350 mV.

3. Currents are measured at 85°C junction temperature.

4. IOL/I

OH defined by VODIFF/(Resistor Network).

Table 2-75 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V)

1.075 1.325 Cross point –

*Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

ProASIC3E DC and Switching Characteristics

2-48 v1.2

Timing Characteristics

B-LVDS/M-LVDS

Bus LVDS (B-LVDS) and Multipoint LVDS (M-LVDS) specifications extend the existing LVDS standard

to high-performance multipoint bus applications. Multidrop and multipoint bus configurations

may contain any combination of drivers, receivers, and transceivers. Actel LVDS drivers provide the

higher drive current required by B-LVDS and M-LVDS to accommodate the loading. The drivers

require series terminations for better signal quality and to control voltage swing. Termination is

also required at both ends of the bus since the driver can be located anywhere on the bus. These

configurations can be implemented using the TRIBUF_LVDS and BIBUF_LVDS macros along with

appropriate terminations. Multipoint designs using Actel LVDS macros can achieve up to 200 MHz

with a maximum of 20 loads. A sample application is given in Figure 2-22. The input and output

buffer delays are available in the LVDS section in Table 2-76.

Example: For a bus consisting of 20 equidistant loads, the following terminations provide the

required differential voltage, in worst-case Industrial operating conditions, at the farthest receiver:

RS=60Ω and RT=70Ω, given Z0=50Ω (2") and Zstub =50Ω (~1.5").

Table 2-76 • LVDS

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.3 V

Speed Grade tDOUT tDP tDIN tPY Units

–F 0.79 2.25 0.05 2.18 ns

Std. 0.66 1.87 0.04 1.82 ns

–1 0.56 1.59 0.04 1.55 ns

–2 0.49 1.40 0.03 1.36 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

Figure 2-22 • B-LVDS/M-LVDS Multipoint Application Using LVDS I/O Buffers

...

BIBUF_LVDS

-T

-R

-T

EN EN EN EN EN

Receiver Transceiver Receiver TransceiverDriver

RSRSRSRSRSRSRSRS

RSRS

Zstub Zstub Zstub Zstub Zstub Zstub Zstub Zstub

ProASIC3E DC and Switching Characteristics

v1.2 2-49

LVPECL

Low-Voltage Positive Emitter-Coupled Logic (LVPECL) is another differential I/O standard. It

requires that one data bit be carried through two signal lines. Like LVDS, two pins are needed. It

also requires external resistor termination.

The full implementation of the LVDS transmitter and receiver is shown in an example in

Figure 2-23. The building blocks of the LVPECL transmitter-receiver are one transmitter macro, one

receiver macro, three board resistors at the transmitter end, and one resistor at the receiver end.

The values for the three driver resistors are different from those used in the LVDS implementation

because the output standard specifications are different.

Timing Characteristics

Figure 2-23 • LVPECL Circuit Diagram and Board-Level Implementation

Table 2-77 • Minimum and Maximum DC Input and Output Levels

DC Parameter Description Min. Max. Min. Max. Min. Max. Units

VCCI Supply Voltage 3.0 3.3 3.6 V

VOL Output LOW Voltage 0.96 1.27 1.06 1.43 1.30 1.57 V

VOH Output HIGH Voltage 1.8 2.11 1.92 2.28 2.13 2.41 V

VIL, VIH Input LOW, Input HIGH Voltages 0 3.3 0 3.6 0 3.9 V

VODIFF Differential Output Voltage 0.625 0.97 0.625 0.97 0.625 0.97 V

VOCM Output Common-Mode Voltage 1.762 1.98 1.762 1.98 1.762 1.98 V

VICM Input Common-Mode Voltage 1.01 2.57 1.01 2.57 1.01 2.57 V

VIDIFF Input Differential Voltage 300 300 300 mV

Table 2-78 • AC Waveforms, Measuring Points, and Capacitive Loads

Input LOW (V) Input HIGH (V) Measuring Point* (V) VREF (typ.) (V)

1.64 1.94 Cross point –

*Measuring point = Vtrip. See Table 2-15 on page 2-18 for a complete table of trip points.

187 W 100 Ω

= 50 Ω

100 Ω

–

INBUF_LVPECL

OUTBUF_LVPECL

FPGA FPGA

Bourns Part Number: CAT16-PC4F12

Table 2-79 • LVPECL

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI =3.0V

Speed Grade tDOUT tDP tDIN tPY Units

–F 0.79 2.19 0.05 1.96 ns

Std. 0.66 1.83 0.04 1.63 ns

–1 0.56 1.55 0.04 1.39 ns

–2 0.49 1.36 0.03 1.22 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

2-50 v1.2

I/O Register Specifications

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous

Preset

Figure 2-24 • Timing Model of Registered I/O Buffers with Synchronous Enable and Asynchronous Preset

INBUF

INBUF INBUF

TRIBUF

CLKBUF

INBUF

CLKBUF

Data Input I/O Register with:

Active High Enable

Active High Preset

Positive-Edge Triggered

Data Output Register and

Enable Output Register with:

Active High Enable

Active High Preset

Postive-Edge Triggered

Pad Out

CLK

Enable

Preset

Data_out

Data

EOUT

DOUT

Enable

CLK

DFN1E1P1

PRE

DFN1E1P1

PRE

DFN1E1P1

PRE

D_Enable

Core

Array

ProASIC3E DC and Switching Characteristics

v1.2 2-51

Table 2-80 • Parameter Definition and Measuring Nodes

Parameter Name Parameter Definition

Measuring Nodes

(from, to)*

tOCLKQ Clock-to-Q of the Output Data Register H, DOUT

tOSUD Data Setup Time for the Output Data Register F, H

tOHD Data Hold Time for the Output Data Register F, H

tOSUE Enable Setup Time for the Output Data Register G, H

tOHE Enable Hold Time for the Output Data Register G, H

tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register L, DOUT

tOREMPRE Asynchronous Preset Removal Time for the Output Data Register L, H

tORECPRE Asynchronous Preset Recovery Time for the Output Data Register L, H

tOECLKQ Clock-to-Q of the Output Enable Register H, EOUT

tOESUD Data Setup Time for the Output Enable Register J, H

tOEHD Data Hold Time for the Output Enable Register J, H

tOESUE Enable Setup Time for the Output Enable Register K, H

tOEHE Enable Hold Time for the Output Enable Register K, H

tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register I, EOUT

tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register I, H

tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register I, H

tICLKQ Clock-to-Q of the Input Data Register A, E

tISUD Data Setup Time for the Input Data Register C, A

tIHD Data Hold Time for the Input Data Register C, A

tISUE Enable Setup Time for the Input Data Register B, A

tIHE Enable Hold Time for the Input Data Register B, A

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register D, E

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register D, A

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register D, A

*See Figure 2-24 on page 2-50 for more information.

ProASIC3E DC and Switching Characteristics

2-52 v1.2

Fully Registered I/O Buffers with Synchronous Enable and Asynchronous

Clear

Figure 2-25 • Timing Model of the Registered I/O Buffers with Synchronous Enable and Asynchronous Clear

Enable

CLK

Pad Out

CLK

Enable

CLR

Data_out

Data

EOUT

DOUT

Core

Array

DFN1E1C1

CLR

DFN1E1C1

CLR

DFN1E1C1

CLR

D_Enable

CLKBUF

INBUF

TRIBUF

INBUF INBUF CLKBUF

INBUF

Data Input I/O Register with

Active High Enable

Active High Clear

Positive-Edge Triggered Data Output Register and

Enable Output Register with

Active High Enable

Active High Clear

Positive-Edge Triggered

ProASIC3E DC and Switching Characteristics

v1.2 2-53

Table 2-81 • Parameter Definition and Measuring Nodes

Parameter Name Parameter Definition

Measuring Nodes

(from, to)*

tOCLKQ Clock-to-Q of the Output Data Register HH, DOUT

tOSUD Data Setup Time for the Output Data Register FF, HH

tOHD Data Hold Time for the Output Data Register FF, HH

tOSUE Enable Setup Time for the Output Data Register GG, HH

tOHE Enable Hold Time for the Output Data Register GG, HH

tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register LL, DOUT

tOREMCLR Asynchronous Clear Removal Time for the Output Data Register LL, HH

tORECCLR Asynchronous Clear Recovery Time for the Output Data Register LL, HH

tOECLKQ Clock-to-Q of the Output Enable Register HH, EOUT

tOESUD Data Setup Time for the Output Enable Register JJ, HH

tOEHD Data Hold Time for the Output Enable Register JJ, HH

tOESUE Enable Setup Time for the Output Enable Register KK, HH

tOEHE Enable Hold Time for the Output Enable Register KK, HH

tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register II, EOUT

tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register II, HH

tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register II, HH

tICLKQ Clock-to-Q of the Input Data Register AA, EE

tISUD Data Setup Time for the Input Data Register CC, AA

tIHD Data Hold Time for the Input Data Register CC, AA

tISUE Enable Setup Time for the Input Data Register BB, AA

tIHE Enable Hold Time for the Input Data Register BB, AA

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register DD, EE

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register DD, AA

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register DD, AA

*See Figure 2-25 on page 2-52 for more information.

ProASIC3E DC and Switching Characteristics

2-54 v1.2

Input Register

Timing Characteristics

Figure 2-26 • Input Register Timing Diagram

50%

Preset

Clear

Out_1

CLK

Data

Enable

tISUE

50%

tISUD

tIHD

50% 50%

tICLKQ

tIHE

tIRECPRE tIREMPRE

tIRECCLR tIREMCLR

tIWCLR

tIWPRE

tIPRE2Q

tICLR2Q

tICKMPWH tICKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 2-82 • Input Data Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tICLKQ Clock-to-Q of the Input Data Register 0.24 0.27 0.32 0.38 ns

tISUD Data Setup Time for the Input Data Register 0.26 0.30 0.35 0.42 ns

tIHD Data Hold Time for the Input Data Register 0.00 0.00 0.00 0.00 ns

tISUE Enable Setup Time for the Input Data Register 0.37 0.42 0.50 0.60 ns

tIHE Enable Hold Time for the Input Data Register 0.00 0.00 0.00 0.00 ns

tICLR2Q Asynchronous Clear-to-Q of the Input Data Register 0.45 0.52 0.61 0.73 ns

tIPRE2Q Asynchronous Preset-to-Q of the Input Data Register 0.45 0.52 0.61 0.73 ns

tIREMCLR Asynchronous Clear Removal Time for the Input Data Register 0.00 0.00 0.00 0.00 ns

tIRECCLR Asynchronous Clear Recovery Time for the Input Data Register 0.22 0.25 0.30 0.36 ns

tIREMPRE Asynchronous Preset Removal Time for the Input Data Register 0.00 0.00 0.00 0.00 ns

tIRECPRE Asynchronous Preset Recovery Time for the Input Data Register 0.22 0.25 0.30 0.36 ns

tIWCLR Asynchronous Clear Minimum Pulse Width for the Input Data

0.22 0.25 0.30 0.36 ns

tIWPRE Asynchronous Preset Minimum Pulse Width for the Input Data

0.22 0.25 0.30 0.36 ns

tICKMPWH Clock Minimum Pulse Width HIGH for the Input Data Register 0.36 0.41 0.48 0.57 ns

tICKMPWL Clock Minimum Pulse Width LOW for the Input Data Register 0.32 0.37 0.43 0.52 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

v1.2 2-55

Output Register

Timing Characteristics

Figure 2-27 • Output Register Timing Diagram

Preset

Clear

DOUT

CLK

Data_out

Enable

tOSUE

50%

tOSUD tOHD

50% 50%

tOCLKQ

tOHE

tORECPRE

tOREMPRE

tORECCLR tOREMCLR

tOWCLR

tOWPRE

tOPRE2Q

tOCLR2Q

tOCKMPWH tOCKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 2-83 • Output Data Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tOCLKQ Clock-to-Q of the Output Data Register 0.59 0.67 0.79 0.95 ns

tOSUD Data Setup Time for the Output Data Register 0.31 0.36 0.42 0.50 ns

tOHD Data Hold Time for the Output Data Register 0.00 0.00 0.00 0.00 ns

tOSUE Enable Setup Time for the Output Data Register 0.44 0.50 0.59 0.70 ns

tOHE Enable Hold Time for the Output Data Register 0.00 0.00 0.00 0.00 ns

tOCLR2Q Asynchronous Clear-to-Q of the Output Data Register 0.80 0.91 1.07 1.29 ns

tOPRE2Q Asynchronous Preset-to-Q of the Output Data Register 0.80 0.91 1.07 1.29 ns

tOREMCLR Asynchronous Clear Removal Time for the Output Data Register 0.00 0.00 0.00 0.00 ns

tORECCLR Asynchronous Clear Recovery Time for the Output Data Register 0.22 0.25 0.30 0.36 ns

tOREMPRE Asynchronous Preset Removal Time for the Output Data Register 0.00 0.00 0.00 0.00 ns

tORECPRE Asynchronous Preset Recovery Time for the Output Data Register 0.22 0.25 0.30 0.36 ns

tOWCLR Asynchronous Clear Minimum Pulse Width for the Output Data

0.22 0.25 0.30 0.36 ns

tOWPRE Asynchronous Preset Minimum Pulse Width for the Output Data

0.22 0.25 0.30 0.36 ns

tOCKMPWH Clock Minimum Pulse Width HIGH for the Output Data Register 0.36 0.41 0.48 0.57 ns

tOCKMPWL Clock Minimum Pulse Width LOW for the Output Data Register 0.32 0.37 0.43 0.52 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

2-56 v1.2

Output Enable Register

Timing Characteristics

Figure 2-28 • Output Enable Register Timing Diagram

50%

Preset

Clear

EOUT

CLK

D_Enable

Enable

tOESUE

50%

tOESUD tOEHD

50% 50%

tOECLKQ

tOEHE

tOERECPRE

tOEREMPRE

tOERECCLR tOEREMCLR

tOEWCLR

tOEWPRE

tOEPRE2Q tOECLR2Q

tOECKMPWH tOECKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 2-84 • Output Enable Register Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tOECLKQ Clock-to-Q of the Output Enable Register 0.59 0.67 0.79 0.95 ns

tOESUD Data Setup Time for the Output Enable Register 0.31 0.36 0.42 0.50 ns

tOEHD Data Hold Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns

tOESUE Enable Setup Time for the Output Enable Register 0.44 0.50 0.58 0.70 ns

tOEHE Enable Hold Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns

tOECLR2Q Asynchronous Clear-to-Q of the Output Enable Register 0.67 0.76 0.89 1.07 ns

tOEPRE2Q Asynchronous Preset-to-Q of the Output Enable Register 0.67 0.76 0.89 1.07 ns

tOEREMCLR Asynchronous Clear Removal Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns

tOERECCLR Asynchronous Clear Recovery Time for the Output Enable Register 0.22 0.25 0.30 0.36 ns

tOEREMPRE Asynchronous Preset Removal Time for the Output Enable Register 0.00 0.00 0.00 0.00 ns

tOERECPRE Asynchronous Preset Recovery Time for the Output Enable Register 0.22 0.25 0.30 0.36 ns

tOEWCLR Asynchronous Clear Minimum Pulse Width for the Output Enable

0.22 0.25 0.30 0.36 ns

tOEWPRE Asynchronous Preset Minimum Pulse Width for the Output Enable

0.22 0.25 0.30 0.36 ns

tOECKMPWH Clock Minimum Pulse Width HIGH for the Output Enable Register 0.36 0.41 0.48 0.57 ns

tOECKMPWL Clock Minimum Pulse Width LOW for the Output Enable Register 0.32 0.37 0.43 0.52 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

v1.2 2-57

DDR Module Specifications

Input DDR Module

Figure 2-29 • Input DDR Timing Model

Table 2-85 • Parameter Definitions

Parameter Name Parameter Definition Measuring Nodes (from, to)

tDDRICLKQ1 Clock-to-Out Out_QR B, D

tDDRICLKQ2 Clock-to-Out Out_QF B, E

tDDRISUD Data Setup Time of DDR input A, B

tDDRIHD Data Hold Time of DDR input A, B

tDDRICLR2Q1 Clear-to-Out Out_QR C, D

tDDRICLR2Q2 Clear-to-Out Out_QF C, E

tDDRIREMCLR Clear Removal C, B

tDDRIRECCLR Clear Recovery C, B

Input DDR

Data

CLK

CLKBUF

INBUF

Out_QF

(to core)

FF2

FF1

INBUF

CLR

DDR_IN

Out_QR

(to core)

ProASIC3E DC and Switching Characteristics

2-58 v1.2

Timing Characteristics

Figure 2-30 • Input DDR Timing Diagram

tDDRICLR2Q2

tDDRIREMCLR

tDDRIRECCLR

tDDRICLR2Q1

12 3 4 5 6 7 8 9

CLK

Data

CLR

Out_QR

Out_QF

tDDRICLKQ1

246

357

tDDRIHD

tDDRISUD

tDDRICLKQ2

Table 2-86 • Input DDR Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tDDRICLKQ1 Clock-to-Out Out_QR for Input DDR 0.39 0.44 0.52 0.62 ns

tDDRICLKQ2 Clock-to-Out Out_QF for Input DDR 0.27 0.31 0.37 0.44 ns

tDDRISUD Data Setup for Input DDR 0.28 0.32 0.38 0.45 ns

tDDRIHD Data Hold for Input DDR 0.00 0.00 0.00 0.00 ns

tDDRICLR2Q1 Asynchronous Clear to Out Out_QR for Input DDR 0.57 0.65 0.76 0.92 ns

tDDRICLR2Q2 Asynchronous Clear-to-Out Out_QF for Input DDR 0.46 0.53 0.62 0.74 ns

tDDRIREMCLR Asynchronous Clear Removal Time for Input DDR 0.00 0.00 0.00 0.00 ns

tDDRIRECCLR Asynchronous Clear Recovery Time for Input DDR 0.22 0.25 0.30 0.36 ns

tDDRIWCLR Asynchronous Clear Minimum Pulse Width for Input DDR 0.22 0.25 0.30 0.36 ns

tDDRICKMPWH Clock Minimum Pulse Width HIGH for Input DDR 0.36 0.41 0.48 0.57 ns

tDDRICKMPWL Clock Minimum Pulse Width LOW for Input DDR 0.32 0.37 0.43 0.52 ns

FDDRIMAX Maximum Frequency for Input DDR 1404 1232 1048 871 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

v1.2 2-59

Output DDR Module

Figure 2-31 • Output DDR Timing Model

Table 2-87 • Parameter Definitions

Parameter Name Parameter Definition Measuring Nodes (from, to)

tDDROCLKQ Clock-to-Out B, E

tDDROCLR2Q Asynchronous Clear-to-Out C, E

tDDROREMCLR Clear Removal C, B

tDDRORECCLR Clear Recovery C, B

tDDROSUD1 Data Setup Data_F A, B

tDDROSUD2 Data Setup Data_R D, B

tDDROHD1 Data Hold Data_F A, B

tDDROHD2 Data Hold Data_R D, B

Data_F

(from core)

CLK

CLKBUF

Out

FF2

INBUF

CLR

DDR_OUT

Output DDR

FF1

OUTBUF

Data_R

(from core)

ProASIC3E DC and Switching Characteristics

2-60 v1.2

Timing Characteristics

Figure 2-32 • Output DDR Timing Diagram

116

910

28 3 9

tDDROREMCLR

tDDROHD1

tDDROREMCLR

tDDROHD2

tDDROSUD2

tDDROCLKQ

tDDRORECCLR

CLK

Data_R

Data_F

CLR

Out

tDDROCLR2Q

7104

Table 2-88 • Output DDR Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tDDROCLKQ Clock-to-Out of DDR for Output DDR 0.70 0.80 0.94 1.13 ns

tDDROSUD1 Data_F Data Setup for Output DDR 0.38 0.43 0.51 0.61 ns

tDDROSUD2 Data_R Data Setup for Output DDR 0.38 0.43 0.51 0.61 ns

tDDROHD1 Data_F Data Hold for Output DDR 0.00 0.00 0.00 0.00 ns

tDDROHD2 Data_R Data Hold for Output DDR 0.00 0.00 0.00 0.00 ns

tDDROCLR2Q Asynchronous Clear-to-Out for Output DDR 0.80 0.91 1.07 1.29 ns

tDDROREMCLR Asynchronous Clear Removal Time for Output DDR 0.00 0.00 0.00 0.00 ns

tDDRORECCLR Asynchronous Clear Recovery Time for Output DDR 0.22 0.25 0.30 0.36 ns

tDDROWCLR1 Asynchronous Clear Minimum Pulse Width for Output DDR 0.22 0.25 0.30 0.36 ns

tDDROCKMPWH Clock Minimum Pulse Width HIGH for the Output DDR 0.36 0.41 0.48 0.57 ns

tDDROCKMPWL Clock Minimum Pulse Width LOW for the Output DDR 0.32 0.37 0.43 0.52 ns

FDDOMAX Maximum Frequency for the Output DDR 1404 1232 1048 871 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

v1.2 2-61

VersaTile Characteristics

VersaTile Specifications as a Combinatorial Module

The ProASIC3E library offers all combinations of LUT-3 combinatorial functions. In this section,

timing characteristics are presented for a sample of the library. For more details, refer to the

Fusion, IGLOO®/e, and ProASIC3/E Macro Library Guide.

Figure 2-33 • Sample of Combinatorial Cells

MAJ3

MUX2

XOR2 Y

NOR2

YOR2

INV

AND2

NAND3

XOR3

NAND2

ProASIC3E DC and Switching Characteristics

2-62 v1.2

Figure 2-34 • Timing Model and Waveforms

tPD

tPD = MAX(tPD(RR), tPD(RF),

tPD(FF), tPD(FR)) where edges are

applicable for the particular

combinatorial cell

NAND2 or

Any Combinatorial

Logic

tPD

50%

VCC

50%

GND

A, B, C

50% 50%

50%

(RR)

(RF) GND

OUT

GND

50%

(FF)

(FR)

tPD

ProASIC3E DC and Switching Characteristics

v1.2 2-63

Timing Characteristics

VersaTile Specifications as a Sequential Module

The ProASIC3E library offers a wide variety of sequential cells, including flip-flops and latches. Each

has a data input and optional enable, clear, or preset. In this section, timing characteristics are

presented for a representative sample from the library. For more details, refer to the Fusion,

IGLOO/e, and ProASIC3/E Macro Library Guide.

Table 2-89 • Combinatorial Cell Propagation Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Combinatorial Cell Equation Parameter –2 –1 Std. –F Units

INV Y = !A tPD 0.40 0.46 0.54 0.65 ns

AND2 Y = A · B tPD 0.47 0.54 0.63 0.76 ns

NAND2 Y = !(A · B) tPD 0.47 0.54 0.63 0.76 ns

OR2 Y = A + B tPD 0.49 0.55 0.65 0.78 ns

NOR2 Y = !(A + B) tPD 0.49 0.55 0.65 0.78 ns

XOR2 Y = A ⊕ Bt

PD 0.74 0.84 0.99 1.19 ns

MAJ3 Y = MAJ(A , B, C) tPD 0.70 0.79 0.93 1.12 ns

XOR3 Y = A ⊕ B ⊕ Ct

PD 0.87 1.00 1.17 1.41 ns

MUX2 Y = A !S + B S tPD 0.51 0.58 0.68 0.81 ns

AND3 Y = A · B · C tPD 0.56 0.64 0.75 0.90 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

Figure 2-35 • Sample of Sequential Cells

DFN1

Data

CLK

Out

DFN1C1

Data

CLK

Out

CLR

DFI1E1P1

Data

CLK

Out

PRE

DFN1E1

Data

CLK

Out

ProASIC3E DC and Switching Characteristics

2-64 v1.2

Timing Characteristics

Figure 2-36 • Timing Model and Waveforms

PRE

CLR

Out

CLK

Data

tSUE

50%

tSUD

tHD

50% 50%

tCLKQ

tHE

tRECPRE tREMPRE

tRECCLR tREMCLRtWCLR

tWPRE

tPRE2Q tCLR2Q

tCKMPWH tCKMPWL

50% 50%

50% 50% 50%

50% 50%

50% 50% 50% 50% 50% 50%

50%

Table 2-90 • Register Delays

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tCLKQ Clock-to-Q of the Core Register 0.55 0.63 0.74 0.89 ns

tSUD Data Setup Time for the Core Register 0.43 0.49 0.57 0.69 ns

tHD Data Hold Time for the Core Register 0.00 0.00 0.00 0.00 ns

tSUE Enable Setup Time for the Core Register 0.45 0.52 0.61 0.73 ns

tHE Enable Hold Time for the Core Register 0.00 0.00 0.00 0.00 ns

tCLR2Q Asynchronous Clear-to-Q of the Core Register 0.40 0.45 0.53 0.64 ns

tPRE2Q Asynchronous Preset-to-Q of the Core Register 0.40 0.45 0.53 0.64 ns

tREMCLR Asynchronous Clear Removal Time for the Core Register 0.00 0.00 0.00 0.00 ns

tRECCLR Asynchronous Clear Recovery Time for the Core Register 0.22 0.25 0.30 0.36 ns

tREMPRE Asynchronous Preset Removal Time for the Core Register 0.00 0.00 0.00 0.00 ns

tRECPRE Asynchronous Preset Recovery Time for the Core Register 0.22 0.25 0.30 0.36 ns

tWCLR Asynchronous Clear Minimum Pulse Width for the Core Register 0.22 0.25 0.30 0.36 ns

tWPRE Asynchronous Preset Minimum Pulse Width for the Core Register 0.22 0.25 0.30 0.36 ns

tCKMPWH Clock Minimum Pulse Width HIGH for the Core Register 0.32 0.37 0.43 0.52 ns

tCKMPWL Clock Minimum Pulse Width LOW for the Core Register 0.36 0.41 0.48 0.57 ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

v1.2 2-65

Global Resource Characteristics

A3PE600 Clock Tree Topology

Clock delays are device-specific. Figure 2-37 is an example of a global tree used for clock routing.

The global tree presented in Figure 2-37 is driven by a CCC located on the west side of the A3PE600

device. It is used to drive all D-flip-flops in the device.

Global Tree Timing Characteristics

Global clock delays include the central rib delay, the spine delay, and the row delay. Delays do not

include I/O input buffer clock delays, as these are I/O standard–dependent, and the clock may be

driven and conditioned internally by the CCC module. For more details on clock conditioning

capabilities, refer to the "Clock Conditioning Circuits" section on page 2-68. Table 2-91 on

page 2-66, Table 2-92 on page 2-66, and Table 2-93 on page 2-67 present minimum and maximum

global clock delays within the device. Minimum and maximum delays are measured with minimum

and maximum loading.

Figure 2-37 • Example of Global Tree Use in an A3PE600 Device for Clock Routing

Central

Global Rib

VersaTile

Rows

Global Spine

CCC

ProASIC3E DC and Switching Characteristics

2-66 v1.2

Timing Characteristics

Table 2-91 • A3PE600 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 0.83 1.04 0.94 1.18 1.11 1.39 1.33 1.67 ns

tRCKH Input HIGH Delay for Global Clock 0.81 1.06 0.93 1.21 1.09 1.42 1.31 1.71 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock ns

tRCKSW Maximum Skew for Global Clock 0.25 0.28 0.33 0.40 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

Table 2-92 • A3PE1500 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 1.07 1.29 1.22 1.47 1.43 1.72 1.72 2.07 ns

tRCKH Input HIGH Delay for Global Clock 1.06 1.32 1.21 1.50 1.42 1.76 1.71 2.12 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock ns

tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.34 0.41 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3E DC and Switching Characteristics

v1.2 2-67

Table 2-93 • A3PE3000 Global Resource

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description

–2 –1 Std. –F

UnitsMin.1Max.2Min.1Max.2Min.1Max.2Min.1Max.2

tRCKL Input LOW Delay for Global Clock 1.41 1.62 1.60 1.85 1.88 2.17 2.26 2.61 ns

tRCKH Input HIGH Delay for Global Clock 1.40 1.66 1.59 1.89 1.87 2.22 2.25 2.66 ns

tRCKMPWH Minimum Pulse Width HIGH for Global Clock ns

tRCKMPWL Minimum Pulse Width LOW for Global Clock ns

tRCKSW Maximum Skew for Global Clock 0.26 0.29 0.35 0.41 ns

FRMAX Maximum Frequency for Global Clock MHz

Notes:

1. Value reflects minimum load. The delay is measured from the CCC output to the clock pin of a sequential

element, located in a lightly loaded row (single element is connected to the global net).

2. Value reflects maximum load. The delay is measured on the clock pin of the farthest sequential element,

located in a fully loaded row (all available flip-flops are connected to the global net in the row).

3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

ProASIC3E DC and Switching Characteristics

2-68 v1.2

Clock Conditioning Circuits

CCC Electrical Specifications

Timing Characteristics

Table 2-94 • ProASIC3E CCC/PLL Specification

Parameter Minimum Typical Maximum Units

Clock Conditioning Circuitry Input Frequency fIN_CCC 1.5 350 MHz

Clock Conditioning Circuitry Output Frequency fOUT_CCC 0.75 350 MHz

Delay Increments in Programmable Delay Blocks 2, 3 160 ps

Serial Clock (SCLK) for Dynamic PLL1125 MHz

Number of Programmable Values in Each

Programmable Delay Block

Input Period Jitter 1.5 ns

CCC Output Peak-to-Peak Period Jitter FCCC_OUT Max Peak-to-Peak Period Jitter

1 Global

Network

Used

3 Global

Networks

Used

0.75 MHz to 24 MHz 0.50% 0.70%

24 MHz to 100 MHz 1.00% 1.20%

100 MHz to 250 MHz 1.75% 2.00%

250 MHz to 350 MHz 2.50% 5.60%

Acquisition Time LockControl = 0 300 µs

LockControl = 1 6.0 ms

Tracking Jitter 4 LockControl = 0 1.6 ns

LockControl = 1 0.8 ns

Output Duty Cycle 48.5 51.5 %

Delay Range in Block: Programmable Delay 1 2, 3 0.6 5.56 ns

Delay Range in Block: Programmable Delay 2 2, 3 0.025 5.56 ns

Delay Range in Block: Fixed Delay1, 2 2.2 ns

Notes:

1. Maximum value obtained for a –2 speed-grade device in worst-case commercial conditions. For specific

junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.

2. This delay is a function of voltage and temperature. See Table 2-6 on page 2-5 for deratings.

3. TJ = 25°C, VCC = 1.5 V.

4. Tracking jitter is defined as the variation in clock edge position of PLL outputs with reference to the PLL

input clock edge. Tracking jitter does not measure the variation in PLL output period, which is covered by

the period jitter parameter.

ProASIC3E DC and Switching Characteristics

v1.2 2-69

Note: Peak-to-peak jitter measurements are defined by Tpeak-to-peak = Tperiod_max – Tperiod_min.

Figure 2-38 • Peak-to-Peak Jitter Definition

period_max

period_min

Output Signal

ProASIC3E DC and Switching Characteristics

2-70 v1.2

Embedded SRAM and FIFO Characteristics

SRAM

Figure 2-39 • RAM Models

ADDRA11 DOUTA8

DOUTA7

DOUTA0

DOUTB8

DOUTB7

DOUTB0

ADDRA10

ADDRA0

DINA8

DINA7

DINA0

WIDTHA1

WIDTHA0

PIPEA

WMODEA

BLKA

WENA

CLKA

ADDRB11

ADDRB10

ADDRB0

DINB8

DINB7

DINB0

WIDTHB1

WIDTHB0

PIPEB

WMODEB

BLKB

WENB

CLKB

RAM4K9

RADDR8 RD17

RADDR7 RD16

RADDR0 RD0

WD17

WD16

WD0

WW1

WW0

RW1

RW0

PIPE

REN

RCLK

RAM512X18

WADDR8

WADDR7

WADDR0

WEN

WCLK

RESET

ProASIC3E DC and Switching Characteristics

v1.2 2-71

Timing Waveforms

Figure 2-40 • RAM Read for Pass-Through Output

Figure 2-41 • RAM Read for Pipelined Output

CLK

ADD

BLK_B

WEN_B

A0A1A2

D0D1D2

tCYC

tCKH tCKL

tAS tAH

tBKS

tENS tENH

tDOH1

tBKH

tCKQ1

CLK

ADD

BLK_B

WEN_B

A0A1A2

D0D1

tCYC

tCKH tCKL

tAS tAH

tBKS

tENS tENH

tDOH2

tCKQ2

tBKH

ProASIC3E DC and Switching Characteristics

2-72 v1.2

Figure 2-42 • RAM Write, Output Retained (WMODE = 0)

Figure 2-43 • RAM Write, Output as Write Data (WMODE = 1)

tCYC

tCKH tCKL

A0A1A2

DI0DI1

tAS tAH

tBKS

tENS tENH

tDS tDH

CLK

BLK_B

WEN_B

ADD

tBKH

CYC

CKH

CKL

BKS

ENS

CLK

BLK_B

WEN_B

ADD

BKH

(pass-through) DI

(pipelined) DI

ProASIC3E DC and Switching Characteristics

v1.2 2-73

Figure 2-44 • Write Access after Write onto Same Address

CLK1

CLK2

WEN_B1

WEN_B2

ADD1

ADD2

DI1

DI2

DO2

(pass-through)

DO2

(pipelined)

tAH

tAS

tAH

tAS

tDH

tCCKH

tDS

tCKQ1

tCKQ2

DnD0

A0A4

ProASIC3E DC and Switching Characteristics

2-74 v1.2

Figure 2-45 • Read Access after Write onto Same Address

CLK1

CLK2

WEN_B1

WEN_B2

ADD1

ADD2

DI1

DO2

(pass-through)

DO2

(pipelined)

tAH

tAS

tAH

tAS

tDH

tDS

tWRO

tCKQ1

tCKQ2

A0A1A4

DnD0

D0D1

ProASIC3E DC and Switching Characteristics

v1.2 2-75

Figure 2-46 • Write Access after Read onto Same Address

Figure 2-47 • RAM Reset

tAH

tAS

tAH

tAS

tCKQ1 tCKQ1

tCKQ2

tCCKH

CLK1

ADD1

WEN_B1

DO1

(pass-through)

DO1

(pipelined)

CLK2

ADD2

DI2

WEN_B2

CLK

RESET_B

DO Dn

tCYC

tCKH tCKL

tRSTBQ

ProASIC3E DC and Switching Characteristics

2-76 v1.2

Timing Characteristics

Table 2-95 • RAM4K9

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tAS Address Setup Time 0.25 0.28 0.33 0.40 ns

tAH Address Hold Time 0.00 0.00 0.00 0.00 ns

tENS REN_B, WEN_B Setup Time 0.14 0.16 0.19 0.23 ns

tENH REN_B, WEN_B Hold Time 0.10 0.11 0.13 0.16 ns

tBKS BLK_B Setup Time 0.23 0.27 0.31 0.37 ns

tBKH BLK_B Hold Time 0.02 0.02 0.02 0.03 ns

tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns

tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to New Data Valid on DO (output retained, WMODE = 0) 1.79 2.03 2.39 2.87 ns

Clock HIGH to New Data Valid on DO (pass-through, WMODE = 1) 2.36 2.68 3.15 3.79 ns

tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.89 1.02 1.20 1.44 ns

tWRO Address collision clk-to-clk delay for reliable read access after write

on same address

TBDTBDTBDTBD ns

tCCKH Address collision clk-to-clk delay for reliable write access after

write/read on same address

TBDTBDTBDTBD ns

tRSTBQ RESET_B LOW to Data Out LOW on DO (pass-through) 0.92 1.05 1.23 1.48 ns

RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns

tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns

FMAX Maximum Frequency 310 272 231 193 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

v1.2 2-77

Table 2-96 • RAM512X18

Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tAS Address Setup Time 0.25 0.28 0.33 0.40 ns

tAH Address Hold Time 0.00 0.00 0.00 0.00 ns

tENS REN_B, WEN_B Setup Time 0.18 0.20 0.24 0.28 ns

tENH REB_B, WEN_B Hold Time 0.06 0.07 0.08 0.09 ns

tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns

tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to New Data Valid on DO (output retained, WMODE = 0) 2.16 2.46 2.89 3.47 ns

tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.90 1.02 1.20 1.44 ns

tWRO Address collision clk-to-clk delay for reliable read access after write

on same address

TBDTBDTBDTBD ns

tCCKH Address collision clk-to-clk delay for reliable write access after

write/read on same address

TBDTBDTBDTBD ns

tRSTBQ RESET_B LOW to Data Out LOW on DO (pass-through) 0.92 1.05 1.23 1.48 ns

RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns

tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns

FMAX Maximum Frequency 310 272 231 193 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

2-78 v1.2

FIFO

Figure 2-48 • FIFO Model

FIFO4K18

RW2

RD17

RW1

RD16

RW0

WW2

WW1

WW0 RD0

ESTOP

FSTOP

FULL

AFULL

EMPTY

AFVAL11

AEMPTY

AFVAL10

AFVAL0

AEVAL11

AEVAL10

AEVAL0

REN

RBLK

RCLK

WEN

WBLK

WCLK

RPIPE

WD17

WD16

WD0

RESET

ProASIC3E DC and Switching Characteristics

v1.2 2-79

Timing Waveforms

Figure 2-49 • FIFO Reset

Figure 2-50 • FIFO EMPTY Flag and AEMPTY Flag Assertion

MATCH (A

)

MPWRSTB

RSTFG

RSTCK

RSTAF

RCLK/

WCLK

RESET_B

EMPTY

AEMPTY

WA/RA

(Address Counter)

RSTFG

RSTAF

FULL

AFULL

RCLK

NO MATCH NO MATCH Dist = AEF_TH MATCH (EMPTY)

CKAF

tRCKEF

EMPTY

AEMPTY

tCYC

WA/RA

(Address Counter)

ProASIC3E DC and Switching Characteristics

2-80 v1.2

Figure 2-51 • FIFO FULL Flag and AFULL Flag Assertion

Figure 2-52 • FIFO EMPTY Flag and AEMPTY Flag Deassertion

Figure 2-53 • FIFO FULL Flag and AFULL Flag Deassertion

NO MATCH NO MATCH Dist = AFF_TH MATCH (FULL)

tCKAF

tWCKFF

tCYC

WCLK

FULL

AFULL

WA/RA

(Address Counter)

WCLK

WA/RA

(Address Counter) MATCH

(EMPTY) NO MATCH NO MATCH NO MATCH Dist = AEF_TH + 1

NO MATCH

RCLK

EMPTY

1st Rising

Edge

After 1st

Write

2nd Rising

Edge

After 1st

Write

tRCKEF

tCKAF

AEMPTY

Dist = AFF_TH – 1

MATCH (FULL) NO MATCH NO MATCH NO MATCH NO MATCH

tWCKF

tCKAF

1st Rising

Edge

After 1st

Read

1st Rising

Edge

After 2nd

Read

RCLK

WA/RA

(Address Counter)

WCLK

FULL

AFULL

ProASIC3E DC and Switching Characteristics

v1.2 2-81

Timing Characteristics

Table 2-97 • FIFO

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description –2 –1 Std. –F Units

tENS REN_B, WEN_B Setup Time 1.38 1.57 1.84 2.21 ns

tENH REN_B, WEN_B Hold Time 0.02 0.02 0.02 0.03 ns

tBKS BLK_B Setup Time 0.19 0.22 0.26 0.31 ns

tBKH BLK_B Hold Time 0.00 0.00 0.00 0.00 ns

tDS Input Data (DI) Setup Time 0.18 0.21 0.25 0.29 ns

tDH Input Data (DI) Hold Time 0.00 0.00 0.00 0.00 ns

tCKQ1 Clock HIGH to New Data Valid on DO (pass-through) 2.36 2.68 3.15 3.79 ns

tCKQ2 Clock HIGH to New Data Valid on DO (pipelined) 0.89 1.02 1.20 1.44 ns

tRCKEF RCLK HIGH to Empty Flag Valid 1.72 1.96 2.30 2.76 ns

tWCKFF WCLK HIGH to Full Flag Valid 1.63 1.86 2.18 2.62 ns

tCKAF Clock HIGH to Almost Empty/Full Flag Valid 6.19 7.05 8.29 9.96 ns

tRSTFG RESET_B LOW to Empty/Full Flag Valid 1.69 1.93 2.27 2.72 ns

tRSTAF RESET_B LOW to Almost Empty/Full Flag Valid 6.13 6.98 8.20 9.85 ns

tRSTBQ RESET_B LOW to Data Out LOW on DO (pass-through) 0.92 1.05 1.23 1.48 ns

RESET_B LOW to Data Out LOW on DO (pipelined) 0.92 1.05 1.23 1.48 ns

tREMRSTB RESET_B Removal 0.29 0.33 0.38 0.46 ns

tRECRSTB RESET_B Recovery 1.50 1.71 2.01 2.41 ns

tMPWRSTB RESET_B Minimum Pulse Width 0.21 0.24 0.29 0.34 ns

tCYC Clock Cycle Time 3.23 3.68 4.32 5.19 ns

FMAX Maximum Frequency 310 272 231 193 MHz

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

2-82 v1.2

Embedded FlashROM Characteristics

Timing Characteristics

JTAG 1532 Characteristics

JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays

to the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O

Characteristics" section on page 2-12 for more details.

Timing Characteristics

Figure 2-54 • Timing Diagram

HOLD

CKQ2

CLK

Address

Data D

Table 2-98 • Embedded FlashROM Access Time

Parameter Description –2 –1 Std. Units

tSU Address Setup Time 0.53 0.61 0.71 ns

tHOLD Address Hold Time 0.00 0.00 0.00 ns

tCK2Q Clock to Out 16.23 18.48 21.73 ns

FMAX Maximum Clock Frequency 15 15 15 MHz

Table 2-99 • JTAG 1532

Commercial-Case Conditions: TJ = 70°C, VCC = 1.425 V

Parameter Description –2 –1 Std. Units

tDISU Test Data Input Setup Time 0.50 0.57 0.67 ns

tDIHD Test Data Input Hold Time 1.00 1.13 1.33 ns

tTMSSU Test Mode Select Setup Time 0.50 0.57 0.67 ns

tTMDHD Test Mode Select Hold Time 1.00 1.13 1.33 ns

tTCK2Q Clock to Q (data out) 6.00 6.80 8.00 ns

tRSTB2Q Reset to Q (data out) 20.00 22.67 26.67 ns

FTCKMAX TCK Maximum Frequency 25.00 22.00 19.00 MHz

tTRSTREM ResetB Removal Time 0.00 0.00 0.00 ns

tTRSTREC ResetB Recovery Time 0.20 0.23 0.27 ns

tTRSTMPW ResetB Minimum Pulse TBD TBD TBD ns

Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating

values.

ProASIC3E DC and Switching Characteristics

v1.2 2-83

Part Number and Revision Date

Part Number 51700098-002-2

Revised June 2008

List of Changes

The following table lists critical changes that were made in the current version of the chapter.

Previous Version Changes in Current Version (v1.2) Page

v1.1

(January 2008)

The title of Table 2-4 · Overshoot and Undershoot Limits 1 was modified to

remove "as measured on quiet I/Os." Table note 2 was revised to remove

"estimated SSO density over cycles." Table note 3 was deleted.

2-3

Table 2-74 · LVDS Minimum and Maximum DC Input and Output Levels was

updated.

2-47

v1.0

(January 2008)

In Table 2-3 · Flash Programming Limits – Retention, Storage and Operating

Temperature 1, Maximum Operating Junction Temperature was changed from

110°C to 100°C for both commercial and industrial grades.

2-2

The "PLL Behavior at Brownout Condition" section is new. 2-4

In the "PLL Contribution—PPLL" section, the following was deleted:

FCLKIN is the input clock frequency.

2-10

In Table 2-14 · Summary of Maximum and Minimum DC Input Levels, the note

was incorrect. It previously said TJ and it was corrected and changed to TA.

2-17

In Table 2-94 · ProASIC3E CCC/PLL Specification, the SCLK parameter and note

1 are new.

2-68

Table 2-99 · JTAG 1532 was populated with the parameter data, which was not

in the previous version of the document.

2-82

v2.1

(July 2007)

This document was previously in datasheet v2.1. As a result of moving to the

handbook format, Actel has restarted the version numbers so the new version

number is v1.0.

N/A

v2.0

(April 2007)

The caption "Main (chip)" in Figure 2-9 • Overview of Automotive ProASIC3

VersaNet Global Network was changed to "Chip (main)."

2-9

The TJ parameter in Table 3-2 • Recommended Operating Conditions was

changed to TA, ambient temperature, and table notes 4–6 were added.

3-2

The "PLL Macro" section was updated to add information on the VCO and PLL

outputs during power-up.

2-15

Advance v0.6

(January 2007)

The "PLL Macro" section was updated to include power-up information. 2-15

Table 2-13 • ProASIC3E CCC/PLL Specification was updated. 2-30

Figure 2-19 • Peak-to-Peak Jitter Definition is new. 2-18

The "SRAM and FIFO" section was updated with operation and timing

requirement information.

2-21

The "RESET" section was updated with read and write information. 2-25

The "Introduction" in the "Advanced I/Os" section was updated to include

information on input and output buffers being disabled.

2-28

In the Table 2-15 • Levels of Hot-Swap Support, the ProASIC3 compliance

descriptions were updated for levels 3 and 4.

2-34

ProASIC3E DC and Switching Characteristics

2-84 v1.2

Advance v0.6

(continued)

Table 2-45 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in ProASIC3E

Devices was updated.

2-64

Notes 3, 4, and 5 were added to Table 2-17 • Comparison Table for 5 V–

Compliant Receiver Scheme. 5 x 52.72 was changed to 52.7 and the Maximum

current was updated from 4 x 52.7 to 5 x 52.7.

2-40

The "VCCPLF PLL Supply Voltage" section was updated. 2-50

The "VPUMP Programming Supply Voltage" section was updated. 2-50

The "GL Globals" section was updated to include information about direct

input into quadrant clocks.

2-51

VJTAG was deleted from the "TCK Test Clock" section. 2-51

In Table 2-22 • Recommended Tie-Off Values for the TCK and TRST Pins, TSK

was changed to TCK in note 2. Note 3 was also updated.

2-51

Ambient was deleted from Table 3-2 • Recommended Operating Conditions.

VPUMP programming mode was changed from "3.0 to 3.6" to "3.15 to 3.45".

3-2

Note 3 is new in Table 3-4 • Overshoot and Undershoot Limits (as measured

on quiet I/Os).

3-2

In EQ 3-2, 150 was changed to 110 and the result changed to 5.88. 3-5

Table 3-6 • Temperature and Voltage Derating Factors for Timing Delays was

updated.

3-5

Table 3-5 • Package Thermal Resistivities was updated. 3-5

Table 3-10 • Different Components Contributing to the Dynamic Power

Consumption in ProASIC3E Devices was updated.

3-8

tWRO and tCCKH were added to Table 3-94 • RAM4K9 and Table

3-95 • RAM512X18.

3-74 to

3-74

The note in Table 3-24 • I/O Input Rise Time, Fall Time, and Related I/O

Reliability was updated.

3-23

Figure 3-43 • Write Access After Write onto Same Address, Figure

3-44 • Read Access After Write onto Same Address, and Figure 3-45 • Write

Access After Read onto Same Address are new.

3-71 to

3-73

Figure 3-53 • Timing Diagram was updated. 3-80

Advance v0.4

(October 2005)

B-LVDS and M-LDVS are new I/O standards added to the datasheet. N/A

The term flow-through was changed to pass-through. N/A

Figure 2-8 • Very-Long-Line Resources was updated. 2-8

The footnotes in Figure 2-27 • CCC/PLL Macro were updated. 2-28

The Delay Increments in the Programmable Delay Blocks specification in

Figure 2-24 • ProASIC3E CCC Options.

2-24

The "SRAM and FIFO" section was updated. 2-21

The "RESET" section was updated. 2-25

The "WCLK and RCLK" section was updated. 2-25

The "RESET" section was updated. 2-25

The "RESET" section was updated. 2-27

The "Introduction" of the "Introduction" section was updated. 2-28

Previous Version Changes in Current Version (v1.2) Page

ProASIC3E DC and Switching Characteristics

v1.2 2-85

Advance v0.4

(continued)

PCI-X 3.3 V was added to the Compatible Standards for 3.3 V in Table 2-

11 • VCCI Voltages and Compatible Standards

2-29

Table 2-35 • ProASIC3E I/O Features was updated. 2-54

The "Double Data Rate (DDR) Support" section was updated to include

information concerning implementation of the feature.

2-32

The "Electrostatic Discharge (ESD) Protection" section was updated to include

testing information.

2-35

Level 3 and 4 descriptions were updated in Table 2-43 • I/O Hot-Swap and 5 V

Input Tolerance Capabilities in ProASIC3 Devices.

2-64

The notes in Table 2-45 • I/O Hot-Swap and 5 V Input Tolerance Capabilities in

ProASIC3E Devices were updated.

2-64

The "Simultaneous Switching Outputs (SSOs) and Printed Circuit Board

Layout" section is new.

2-41

A footnote was added to Table 2-37 • Maximum I/O Frequency for Single-

Ended and Differential I/Os in All Banks in ProASIC3E Devices (maximum drive

strength and high slew selected).

2-55

Table 2-48 • ProASIC3E I/O Attributes vs. I/O Standard Applications 2-81

Table 2-55 • ProASIC3 I/O Standards—SLEW and Output Drive (OUT_DRIVE)

Settings

2-85

The "x" was updated in the "Pin Descriptions" section. 2-50

The "VCC Core Supply Voltage" pin description was updated. 2-50

The "VMVx I/O Supply Voltage (quiet)" pin description was updated to include

information concerning leaving the pin unconnected.

2-50

EXTFB was removed from Figure 2-24 • ProASIC3E CCC Options. 2-24

The CCC Output Peak-to-Peak Period Jitter FCCC_OUT was updated in Table

2-13 • ProASIC3E CCC/PLL Specification.

2-30

EXTFB was removed from Figure 2-27 • CCC/PLL Macro. 2-28

The LVPECL specification in Table 2-45 • I/O Hot-Swap and 5 V Input

Tolerance Capabilities in ProASIC3E Devices was updated.

2-64

Table 2-15 • Levels of Hot-Swap Support was updated. 2-34

The "Cold-Sparing Support" section was updated. 2-34

"Electrostatic Discharge (ESD) Protection" section was updated. 2-35

The VJTAG and I/O pin descriptions were updated in the "Pin Descriptions"

section.

2-50

The "VJTAG JTAG Supply Voltage" pin description was updated. 2-50

The "VPUMP Programming Supply Voltage" pin description was updated to

include information on what happens when the pin is tied to ground.

2-50

The "I/O User Input/Output" pin description was updated to include

information on what happens when the pin is unused.

2-50

The "JTAG Pins" section was updated to include information on what happens

when the pin is unused.

2-51

The "Programming" section was updated to include information concerning

serialization.

2-53

The "JTAG 1532" section was updated to include SAMPLE/PRELOAD

information.

2-54

Previous Version Changes in Current Version (v1.2) Page

ProASIC3E DC and Switching Characteristics

2-86 v1.2

Actel Safety Critical, Life Support, and High-Reliability

Applications Policy

The Actel products described in this advance status datasheet may not have completed Actel’s