TM Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Datasheet The Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver (LXT908 PHY) is designed for IEEE 802.3 physical layer applications. It provides all the active circuitry to interface most standard 802.3 controllers to either the 10BASE-T media or Attachment Unit Interface (AUI). In addition to standard 10 Mbps Ethernet, the LXT908 PHY also supports full-duplex operation at 20 Mbps. LXT908 PHY functions include Manchester encoding/decoding, receiver squelch and transmit pulse shaping, jabber, link testing and reversed polarity detection/correction. The LXT908 PHY can be used to drive either the AUI drop cable or the 10BASE-T twisted-pair cable with only a simple isolation transformer. Integrated filters simplify the design work required for FCC-compliant EMI performance. The LXT908 PHY is fabricated with an advanced CMOS process and requires only a single 3.3 V power supply. Applications Access devices (DSL, Cable Modems, and Set-top Boxes) Routers/Bridges/Switches/Hubs Telecom Backplane USB to Ethernet Converters Features Functional Features Diagnostic Features Convenience Features Improved Filters - Simplifies FCC Compliance Integrated Manchester Encoder/Decoder 10BASE-T compliant Transceiver AUI Transceiver Supports Standard and Full-Duplex Ethernet Four LED Drivers AUI/RJ-45 Loopback Automatic/Manual AUI/RJ-45 Selection Automatic Polarity Correction SQE Disable/Enable function Power Down Mode with tristated outputs Four loopback modes Single 3.3 V operation Available in 64-pin LQFP and 44-pin PLCC package Commercial (0 to +70C) and Extended (-40 to +85C) temperature range 249049, Revision 4.0 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Legal Disclaimers INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH CORTINA SYSTEMS(R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN CORTINA'S TERMS AND CONDITIONS OF SALE OF SUCH PRODUCTS, CORTINA ASSUMES NO LIABILITY WHATSOEVER, AND CORTINA DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE AND/OR USE OF CORTINA PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Cortina products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. CORTINA SYSTEMS(R), CORTINATM, and the Cortina Earth Logo are trademarks or registered trademarks of Cortina Systems, Inc. or its subsidiaries in the US and other countries. Any other product and company names are the trademarks of their respective owners. Copyright (c) 20012009 Cortina Systems, Inc. All rights reserved. Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 2 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Contents Contents 1.0 Pin Assignments and Signal Descriptions ................................................................................. 9 2.0 Functional Description................................................................................................................ 12 2.1 3.0 Application Information .............................................................................................................. 19 3.1 3.2 4.0 External Components ......................................................................................................... 19 3.1.1 Crystal Information................................................................................................. 19 3.1.2 Magnetic Information ............................................................................................. 19 Layout Requirements.......................................................................................................... 19 3.2.1 Auto Port Select with External Loopback Control .................................................. 19 3.2.2 Full Duplex Support ............................................................................................... 21 3.2.3 Dual Network Support-10Base T and Token Ring................................................. 22 3.2.4 Manual Port Select & Link Test Function............................................................... 23 3.2.5 Three Media Application ........................................................................................ 24 3.2.6 AUI Encoder/Decoder Only ................................................................................... 25 Test Specifications...................................................................................................................... 27 4.1 4.2 4.3 4.4 4.5 5.0 Introduction ......................................................................................................................... 12 2.1.1 Controller Compatibility Modes.............................................................................. 12 2.1.2 Transmit Function .................................................................................................. 12 2.1.3 Jabber Control Function ........................................................................................ 13 2.1.4 Receive Function ................................................................................................... 14 2.1.5 SQE Function ........................................................................................................ 14 2.1.6 Polarity Reverse Function...................................................................................... 15 2.1.7 Loopback Function ................................................................................................ 15 2.1.8 Collision Detection Function .................................................................................. 16 2.1.9 Link Pulse Transmission........................................................................................ 17 2.1.10 Link Integrity Test Function.................................................................................... 17 Timing Diagrams for Mode 1 (MD2, 1, 0 = Low, Low, Low) Figure 16 through Figure 21 ............................................................................................... 31 Timing Diagrams for Mode 2 (MD2, 1, 0 = Low, Low, High) Figure 22 through Figure 27 ............................................................................................... 33 Timing Diagrams for Mode 3 (MD2, 1, 0 = Low, High, Low) Figure 28 through Figure 33 ............................................................................................... 35 Timing Diagrams for Mode 4 (MD2, 1, 0 = Low, High, High) Figure 34 through Figure 39 ............................................................................................... 37 Timing Diagrams for Mode 5 (MD2, 1, 0 = High, High, Low) Figure 40 through Figure 45 ............................................................................................... 39 Mechanical Specifications.......................................................................................................... 41 Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 3 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Figures Figures 1 LXT908 PHY Block Diagram ........................................................................................................... 8 2 LXT908 Pin Assignments-44-pin and 64-pin Packages ................................................................. 9 3 LXT908 PHY TPO Output Waveform ............................................................................................ 13 4 Jabber Control Function ................................................................................................................ 14 5 SQE Function ............................................................................................................................... 15 6 Collision Detection Function ......................................................................................................... 16 7 Transmitted Link Integrity Pulse Timing ........................................................................................ 17 8 Link Integrity Test Function ........................................................................................................... 18 9 LAN Adapter Board - Auto Port Select with External Loopback Control....................................... 20 10 Full-Duplex Operation.................................................................................................................... 21 11 LXT908 PHY/380C26 Interface for Dual Network Support of 10BASE-T and Token Ring ........... 22 12 LAN Adapter Board - Manual Port Select with Link Test Function ............................................... 23 13 Manual Port Select with Seeq* 8005 Controller ............................................................................ 24 14 Three Media Application................................................................................................................ 25 15 AUI Encoder/Decoder Only Application......................................................................................... 26 16 Mode 1 RCLK/Start-of-Frame Timing............................................................................................ 31 17 Mode 1 RCLK/End-of-Frame Timing ............................................................................................. 31 18 Mode 1 Transmit Timing................................................................................................................ 32 19 Mode 1 Collision Detect Timing..................................................................................................... 32 20 Mode 1 COL/SQE Output Timing/CI Output Timing...................................................................... 32 21 Mode 1 Loopback Timing .............................................................................................................. 32 22 Mode 2 RCLK/Start-of-Frame Timing............................................................................................ 33 23 Mode 2 RCLK/End-of-Frame Timing ............................................................................................. 33 24 Mode 2 Transmit Timing................................................................................................................ 34 25 Mode 2 Collision Detect Timing..................................................................................................... 34 26 Mode 2 COL/SQE Output Timing .................................................................................................. 34 27 Mode 2 Loopback Timing .............................................................................................................. 34 28 Mode 3 RCLK/Start-of-Frame Timing............................................................................................ 35 29 Mode 3 RCLK/End-of-Frame Timing ............................................................................................. 35 30 Mode 3 Transmit Timing................................................................................................................ 36 31 Mode 3 Collision Detect Timing..................................................................................................... 36 32 Mode 3 COL/SQE Output Timing .................................................................................................. 36 33 Mode 3 Loopback Timing .............................................................................................................. 36 34 Mode 4 RCLK/Start-of-Frame Timing............................................................................................ 37 Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 4 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Figures 35 Mode 4 RCLK/End-of-Frame Timing ............................................................................................. 37 36 Mode 4 Transmit Timing................................................................................................................ 38 37 Mode 4 Collision Detect Timing..................................................................................................... 38 38 Mode 4 COL/SQE Output Timing .................................................................................................. 38 39 Mode 4 Loopback Timing .............................................................................................................. 38 40 Mode 5 RCLK/Start-of-Frame Timing............................................................................................ 39 41 Mode 5 RCLK/End-of-Frame Timing ............................................................................................. 39 42 Mode 5 Transmit Timing................................................................................................................ 40 43 Mode 5 Collision Detect Timing..................................................................................................... 40 44 Mode 5 COL/SQE Output Timing .................................................................................................. 40 45 Mode 5 Loopback Timing .............................................................................................................. 40 46 44-Pin PLCC Package Specifications ........................................................................................... 41 47 64-Pin LQFP Package Specifications............................................................................................ 42 Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 5 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Tables Tables 1 LXT908 PHY Signal Descriptions.................................................................................................. 10 2 Controller Compatibility Mode Options .......................................................................................... 13 3 Suitable Crystals............................................................................................................................ 19 4 Absolute Maximum Values ............................................................................................................ 27 5 Recommended Operating Conditions ........................................................................................... 27 6 I/O Electrical Characteristics ......................................................................................................... 27 7 AUI Electrical Characteristics ........................................................................................................ 28 8 Twisted-Pair Electrical Characteristics .......................................................................................... 28 9 Switching Characteristics .............................................................................................................. 29 10 RCLK/Start-of-Frame Timing......................................................................................................... 29 11 RCLK/End-of-Frame Timing .......................................................................................................... 29 12 Transmit Timing............................................................................................................................. 30 13 Collision, COL/CI Output and Loopback Timing............................................................................ 30 Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 6 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Revision History Revision History Revision 4.0 Revision Date: 10 March 2009 First release of this document from Cortina Systems, Inc. Revision 003 Revision Date: 29 October 2005 * Added Section 5.1, "Top-Label Marking": * Added Table 48 "Sample LQFP Package - Intel(R) LXT908 Transceiver" * Added Table 49 "Sample Pb-Free (RoHS-Compliant) LQFP Package - Intel(R) LXT908 Transceiver" * Modified Table 14 "Product Information" for RoHS information. * Modified Figure 52 "Ordering Information - Sample" Revision 2001 Revision Date: June 2001 * Added new set of applications * Added 01 F label to capacitor at bottom of Figure 9 * Added 01 F label to capacitor at bottom of Figure 10 * Added 01 F label to capacitor at bottom of Figure 11 * Added 01 F label to capacitor at bottom of Figure 12 * Added 01 F label to capacitor at bottom of Figure 13 * Added second para. under "Test Specifications" regarding Quality and Reliability issues * Removed "Ambient operating temperature" from Absolute Maximum Ratings table * Added Appendix: Product Ordering Information Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 7 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Figure 1 LXT908 PHY Block Diagram AUTOSEL MD0 MD1 MD2 MODE SELECT LOGIC Controller Compatibility/ Port Select / Loopback / Link test PAUI LBK LI TCLK CLKI CLKO TEN XTAL OSC TWISTED PAIR INTERFACE Select: PLS Only or PLS / MAU WATCHDOG TIMER RC CMOS TX AMP PULSE SHAPER AND FILTER TPOPB TPOPA TPONA TPONB RC DO COLLISION/ POLARITY DETECT CORRECT MANCHESTER ENCODER RX SLICER TPIP TPIN TXD DROP CABLE INTERFACE CD LEDL ECL TX AMP SQUELCH / LINK DETECT + DOP - DON LPBK RXD DI MANCHESTER DECODER RCLK RX SLICER CI COLLISION LOGIC COL LEDR LEDT/PDN LEDC/FDE DSQE NTH JAB COLLISION RECEIVER DIP DIN CIP CIN PLR Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 8 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 1.0 Pin Assignments and Signal Descriptions MD0 NTH CIN CIP VCC1 DON DOP DIN DIP PAUI 4 3 2 1 44 43 42 41 40 LXT908 Pin Assignments-44-pin and 64-pin Packages MD1 Figure 2 5 Pin Assignments and Signal Descriptions 6 1.0 n/c 7 39 TPIN LI 8 38 TPIP JAB 9 37 DSQE TEST 10 36 TPONB TCLK 11 35 TPONA TXD 12 34 VCC2 TEN 13 33 GND2 CLKO 14 32 TPOPA CLKI 15 31 TPOPB COL 16 30 PLR AUTOSEL 17 29 n/c 23 24 25 26 27 28 GND1 RBIAS MD2 RXD CD RCLK 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 n/c n/c TPIN TPIP n/c DSQE TPONB TPONA VCC2 GND2 TPOPA TPOPB PLR n/c n/c n/c 22 21 LEDC/FDE LBK 19 20 18 LEDR LEDT/PDN LEDL 44-pin PLCC Package 64-pin LQFP Package 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 n/c RCLK CD RXD MD2 n/c RBIAS n/c GNDA GND1 LBK LEDC/FDE LEDL LEDT/PDN LEDR n/c 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 n/c n/c LI n/c JAB TEST TCLK TXD TEN CLKO CLKI COL AUTOSEL n/c n/c n/c n/c n/c PAUI DIP DIN n/c DOP DON VCCA VCC1 CIP CIN NTH MD0 MD1 n/c Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 9 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Table 1 1.0 Pin Assignments and Signal Descriptions LXT908 PHY Signal Descriptions (Sheet 1 of 2) Pin# PLCC LQFP Symbol I/O Description 1 10 VCC1 - 34 56 VCC2 - - 9 VCCA - Analog Supply. (+3.3 V) AUI Collision Pair. Differential input pair connected to the AUI transceiver CI circuit. The input is collision signaling or SQE. Power 1 and 2. Connect to positive power supply terminal (+3.3 V DC). 2 11 CIP I 3 12 CIN I 4 13 NTH I 5 14 MD0 I 6 15 MD1 I 25 44 MD2 I N/C - No Connect. These pins may be left unconnected or tied to ground. Normal Threshold. When NTH is High, the normal TP squelch threshold is in effect. When NTH is Low, the normal TP squelch threshold is reduced by 4.5 dB. Mode Select 0 (MD0), Mode Select 1 (MD1) and Mode Select 2 (MD2). Mode select pins determine the controller compatibility mode as specified in Table 2. 1, 2, 6 16, 17 18, 20 30, 31 7, 29 32, 33 41, 43 48, 49, 50, 51, 60, 63, 64 8 19 LI I Link Test Enable. Controls Link Integrity Test; enabled when High, disabled when Low. 9 21 JAB O Jabber Indicator. Output goes High to indicate Jabber state. 10 22 TEST I Test. This pin must be tied High. 11 23 TCLK O Transmit Clock. A 10 MHz clock output. This clock signal should be directly connected to the transmit clock input of the controller. TCLK goes to high impedance (tri-state) when LEDT/PDN is pulled Low externally. 12 24 TXD I Transmit Data. Input signal containing NRZ data to be transmitted on the network. TXD is connected directly to the transmit data output of the controller. 13 25 TEN I Transmit Enable. Enables data transmission and starts the Watch-Dog Timer. Synchronous to TCLK (see Test Specifications for details). 14 26 CLKO O 15 27 CLKI I 16 28 COL O Collision Detect. Output driving the collision detect input of the controller. COL goes to high impedance (tri-state) when LEDT/PDN is pulled Low externally. 17 29 AUTOSEL I Automatic Port Select. When High, automatic port selection is enabled (the LXT908 PHY defaults to the AUI port only if TP link integrity = Fail). When Low, manual port selection is enabled (the PAUI pin determines the active port). 18 34 LEDR O Receive LED. Open drain driver for the receive indicator LED. Output is pulled Low during receive, except when data is being looped back to DIN/DIP from a remote transceiver (external MAU). LED "On" time (Low output) is extended by approximately 100 ms. O I Transmit LED (LEDT)/Power Down (PDN). Open drain driver for the transmit indicator LED. Output is pulled Low during transmit. Do not allow this pin to float. If unused, tie High. LED "On" time (Low output) is extended by approximately 100 ms. If externally tied Low, the LXT908 PHY goes to power down state. In power down state, TCLK, COL, RXD, CD, and RCLK (pins 11, 16, 26, 27, and 28, respectively) are tri-stated. 19 35 LEDT/ PDN Crystal Oscillator. A 20 MHz crystal must be connected across these pins, or a 20 MHz clock applied at CLKI with CLKO left open. Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 10 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Table 1 1.0 Pin Assignments and Signal Descriptions LXT908 PHY Signal Descriptions (Continued) (Sheet 2 of 2) Pin# Symbol PLCC LQFP 20 36 LEDL I/O Description O Link LED. Open drain driver for link integrity indicator LED. Output is pulled Low during link test pass. If externally tied Low, internal circuitry is forced to "Link Pass" state and the LXT908 PHY will continue to transmit link test pulses. I 21 37 LEDC/ FDE O I Collision LED (LEDC)/Full Duplex Enable (FDE). Open drain driver for the collision indicator LED pulls Low during collision. LED "On" time (Low output) is extended by approximately 100 ms. If externally tied Low, the LXT908 PHY disables the internal TP loopback and collision detection circuits to allow full-duplex operation or external TP loopback. 22 38 LBK I Loopback. Enables internal loopback mode. Refer to Functional Description and Test Specifications for details. 23 39 GND1 - 33 55 GND2 - - 40 GNDA - Analog Ground. Ground for analog plane. 27 46 CD O Carrier Detect. An output to notify the controller of activity on the network. CD goes to high impedance (tri-state) when LEDT/PDN is pulled Low externally. 28 47 RCLK O Receive Clock. A recovered 10 MHz clock that is synchronous to the received data and connected to the controller receive clock input. RCLK goes to high impedance (tri-state) when LEDT/PDN is pulled Low externally. 30 52 PLR O Polarity Reverse. Output goes High to indicate reversed polarity at the TP input. 32 35 31 36 54 57 53 58 TPOPA O TPONA O TPOPB O TPONB O DSQE I 37 59 38 61 TPIP I 39 62 TPIN I 40 3 PAUI I 41 4 DIP I 42 5 DIN I 43 7 DOP O 44 8 DON O Ground Returns 1 and 2. Connect to negative power supply terminal (ground). Twisted-Pair Transmit Pairs A & B. Two differential driver pair outputs (A and B) to the twisted-pair cable. The outputs are pre-equalized. Each pair must be shorted together with an 11.5 1% resistor to match an impedance of 100 . Disable SQE. When DSQE is High, the SQE function is disabled. When DSQE is Low, the SQE function is enabled. SQE must be disabled for normal operation in Hub/Switch applications. Twisted-Pair Receive Pair. A differential input pair from the TP cable. Receive filter is integrated on chip. No external filters are required. Port/AUI Select. In Manual Port Select mode (AUTOSEL Low), PAUI selects the active port. When PAUI is High, the AUI port is selected. When PAUI is Low, the TP port is selected. In Auto Port Select mode, PAUI must be tied to ground. AUI Receive Pair. Differential input pair from the AUI transceiver DI circuit. The input is Manchester encoded. AUI Transmit Pair. A differential output driver pair for the AUI transceiver cable. The output is Manchester encoded. Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 11 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 2.0 Functional Description 2.1 Introduction 2.0 Functional Description The LXT908 PHY performs the physical layer signaling (PLS) and Media Attachment Unit (MAU) functions as defined by the IEEE 802.3 specification. It functions as an AUI (PLS-Only device) for use with 10BASE-2 or 10BASE-5 coaxial cable networks, or as an Integrated PLS/MAU for use with 10BASE-T twisted-pair (TP) networks. In addition to standard 10 Mbps operation, the LXT908 PHY also supports full-duplex 20 Mbps operation. The LXT908 PHY interfaces a back-end controller to either an AUI drop cable or a TP cable. The controller interface includes transmit and receive clock and NRZ data channels, as well as mode control logic and signaling. The AUI interface comprises three circuits: Data Output (DO), Data Input (DI), and Collision (CI). The TP interface comprises two circuits: Twisted-Pair Input (TPI) and Twisted-Pair Output (TPO). In addition to the three basic interfaces, the LXT908 PHY contains an internal crystal oscillator and four LED drivers for visual status reporting. Functions are defined from the back end controller side of the interface. The LXT908 PHY Transmit function refers to data transmitted by the back end to the AUI cable (PLS-Only mode) or to the TP network (Integrated PLS/MAU mode). The LXT908 PHY Receive function refers to data received by the back end from the AUI cable (PLS-Only) or from the TP network (Integrated PLS/MAU mode). In the integrated PLS/MAU mode, the LXT908 PHY performs all required MAU functions defined by the IEEE 802.3 10BASE-T specification such as collision detection, link integrity testing, signal quality error messaging, jabber control, and loopback. In the PLS-Only mode, the LXT908 PHY receives incoming signals from the AUI DI circuit with 18 ns of jitter and drives the AUI DO circuit. 2.1.1 Controller Compatibility Modes The LXT908 PHY is compatible with most industry-standard controllers including devices produced by Advanced Micro Devices* (AMD*), Motorola*, Intel*, Fujitsu*, National Semiconductor*, Seeq*, and Texas Instruments*, as well as custom controllers. Five different control signal timing and polarity schemes (Modes 1 through 5) are required to achieve this compatibility. Mode select pins (MD2:0) determine Controller compatibility modes as listed in Table 2. Refer to Test Specifications for a complete set of timing diagrams for each mode. 2.1.2 Transmit Function The LXT908 PHY receives NRZ data from the controller at the TXD input as shown in the block diagram on the first page of this Data Sheet, and passes it through a Manchester encoder. The encoded data is then transferred to either the AUI cable (the DO circuit) or the TP network (the TPO circuit). The advanced integrated pulse shaping and filtering network produces the output signal on TPON and TPOP, shown in Figure 3. The TPO output is pre-distorted and pre-filtered to meet the 10BASE-T jitter template. An internal continuous resistor-capacitor filter is used to remove any high-frequency clocking noise from the pulse shaping circuitry. Integrated filters simplify the design work required for FCC-compliant EMI performance. During idle periods, the LXT908 PHY transmits link integrity test pulses on the TPO circuit (if LI is enabled and integrated PLS/ MAU mode is selected). External resistors control the termination impedance. Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 12 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Figure 3 2.1 Introduction LXT908 PHY TPO Output Waveform 4V 2V 0V -2V -4V Table 2 Controller Compatibility Mode Options Controller Mode MD2 MD1 MD0 Mode 1 - For AMD* AM7990, Motorola* 68EN360, MPC860 or compatible controllers Low Low Low Mode 2 - For Intel 82596 or compatible controllers Low Low High Low High Low 1 Mode 3 - For Fujitsu* MB86950, MB86960 or compatible controllers (Seeq* 8005) Mode 4 - For National Semiconductor* 8390 or compatible controllers (TI TMS380C26) Low High High Mode 5 - For custom controllers (Mode 3 with TCLK, RCLK and COL inverted) High High Low 1. Seeq* controllers require inverters on CLKI, LBK, RCLK, and COL in Mode 3; or on CLKI, LBK, and TCLK in Mode 5. 2.1.3 Jabber Control Function Figure 4 is a state diagram of the LXT908 PHY Jabber control function. The LXT908 PHY on-chip Watch-Dog Timer prevents the DTE from locking into a continuous transmit mode. When a transmission exceeds the time limit, the Watch-Dog Timer disables the transmit and loopback functions, and activates the JAB pin. Once the LXT908 PHY is in the jabber state, the TXD circuit must remain idle for a period of 0.25 to 0.75 s before it will exit the jabber state. Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 13 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Figure 4 2.1 Introduction Jabber Control Function Power On No Output DO=Active Nonjabber Output Start_XMIT_MAX_Timer DO=Idle DO=Active * XMIT_Max_Timer_Done Jab XMIT=Disable LPBK=Disable CI=SQE DO=Idle Unjab Wait Start_Unjab_Timer XMIT=Disable LPBK=Disable CI=SQE Unjab_ Timer_Done 2.1.4 DO=Active * Unjab_Timer_Not_Done Receive Function The LXT908 PHY receive function acquires timing and data from the TP network (the TPI circuit) or from the AUI (the DI circuit). Valid received signals are passed through the on-chip filters and Manchester decoder then output as decoded NRZ data and recovered clock on the RXD and RCLK pins, respectively. An internal RC filter and an intelligent squelch function discriminate noise from link test pulses and valid data streams. The receive function is activated only by valid data streams above the squelch level and with proper timing. If the differential signal at the TPI or the DI circuit inputs falls below 75% of the threshold level (unsquelched) for 8 bit times (typical), the LXT908 PHY receive function enters the idle state. If the polarity of the TPI circuit is reversed, LXT908 PHY detects the polarity reverse and reports it via the PLR output. The LXT908 PHY automatically corrects reversed polarity. 2.1.5 SQE Function In the integrated PLS/MAU mode, the LXT908 PHY supports the signal quality error (SQE) function as shown in Figure 4, although the SQE function can be disabled. After every successful transmission on the 10BASE-T network when SQE is enabled, the LXT908 PHY transmits the SQE signal for 10BT 5BT over the internal CI circuit, which is indicated on the COL pin of the device. SQE must be disabled for normal operation in hub and switch Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 14 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 2.1 Introduction applications. In TP applications, the SQE function is disabled when DSQE is set High, and enabled when DSQE is Low. When using the 10BASE-2 port of the LXT908 PHY, the SQE function is determined by the external MAU attached. Figure 5 SQE Function Power On Output Idle DO=Active Output Detected DO=Idle SQE Wait Test Start_SQE_Test__Wait_Timer XMIT=Disable SQE_Test__Wait_Timer_Done * XMIT=Enable SQE Test Start_SQE_Test_Timer CI=SQE SQE_Test_Timer_Done 2.1.6 Polarity Reverse Function The LXT908 PHY polarity reverse function uses both link pulses and end-of-frame data to determine polarity of the received signal. A reversed polarity condition is detected when eight opposite receive link pulses are detected without receipt of a link pulse of the expected polarity. Reversed polarity is also detected if four frames are received with a reversed start-of-idle. Whenever a correct polarity frame or a correct link pulse is received, these two counters are reset to zero. If the LXT908 PHY enters the link fail state and no valid data or link pulses are received within 96 to 128 ms, the polarity is reset to the default non-flipped condition. If Link Integrity Testing is disabled, polarity detection is based only on received data. Polarity correction is always enabled. 2.1.7 Loopback Function The LXT908 PHY provides the normal loopback function specified by the 10BASE-T standard for the twisted-pair port. The loopback function operates in conjunction with the transmit function. Data transmitted by the back-end is internally looped back within the LXT908 PHY from the TXD pin through the Manchester encoder/decoder to the RXD pin and returned to the back-end. This "normal" loopback function is disabled when a data collision occurs, clearing the RXD circuit for the TPI data. Normal loopback is also disabled during link fail and jabber states. Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 15 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 2.1 Introduction The LXT908 PHY also provides three additional loopback functions. An external loopback mode, useful for system-level testing, is controlled by pin 21 (LEDC). When LEDC is tied Low, the LXT908 PHY disables the collision detection and internal loopback circuits, to allow external loopback or full-duplex operation. "Normal" TP loopback is controlled by pin 22 (LBK). When the TP port is selected and LBK is High, TP loopback is "forced", overriding collisions on the TP circuit. When LBK is Low, normal loopback is in effect. AUI loopback is also controlled by the LBK pin. When the AUI port is selected and LBK is High, data transmitted by the back-end is internally looped back from the TXD pin through the Manchester encoder/decoder to the RXD pin. When LBK is Low, no AUI loopback occurs. 2.1.8 Collision Detection Function The collision detection function operates on the twisted pair side of the interface. For standard (half-duplex) 10BASE-T operation, a collision is defined as the simultaneous presence of valid signals on both the TPI circuit and the TPO circuit. The LXT908 PHY reports collisions to the back-end via the COL pin. If the TPI circuit becomes active while there is activity on the TPO circuit, the TPI data is passed to the back-end over the RXD circuit, disabling normal loopback. Figure 6 is a state diagram of the LXT908 PHY collision detection function. Refer to Test Specifications for collision detection and COL/CI output timing. NOTE: For full-duplex operation, the collision detection circuitry must be disabled. Figure 6 Collision Detection Function A DO=Active * TPI=Idle * XMIT=Enable Power On Idle TPI=Active Output Input TPO=DO DI=DO DI=TPI DO=Active * TPI=Active * XMIT=Enable DO=Active * TPI=Active * XMIT=Enable Collision A DO=Idle + XMIT=Disable DO=Active * TPI=Idle TPO=DO DI=TPI CI=SQE A TPI=Idle DO=Idle Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 16 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 2.1.9 2.1 Introduction Link Pulse Transmission The LXT908 PHY transmits standard link pulses which meet the 10BASE-T specifications. Figure 7 shows the link integrity pulse timing. Figure 7 Transmitted Link Integrity Pulse Timing 10-20 ms 2.1.10 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms 10-20 ms Link Integrity Test Function Figure 8 is a state diagram of the LXT908 PHY Link Integrity test function. The link integrity test is used to determine the status of the receive side twisted-pair cable. Link integrity testing is enabled when pin 8 (LI) is tied High. When enabled, the receiver recognizes link integrity pulses which are transmitted in the absence of receive traffic. If no serial data stream or link integrity pulses are detected within 50 - 150 ms, the chip enters a link fail state and disables the transmit and normal loopback functions. The LXT908 PHY ignores any link integrity pulse with interval less than 2 - 7 ms. The LXT908 PHY will remain in the link fail state until it detects either a serial data packet or two or more link integrity pulses. Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 17 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Figure 8 2.1 Introduction Link Integrity Test Function Power On Idle Test Start_Link_Loss_Timer Start_Link_Test_Min_Timer Link_Loss_Timer_Done * TPI=Idle * Link_Test_Rcvd=False TPI=Active + (Link_Test_Rcvd=True * Link_Test_Min_Timer_Done) Link Test Fail Reset Link Test Fail Wait Link_Count=0 XMIT=Disable RCVR=Disable LPBK=Disable TPI=Active Link_Test_Rcvd=False * TPI=Idle XMIT=Disable RCVR=Disable LPBK=Disable Link_Count=Link_Count + 1 TPI=Active Link_Test_Rcvd=Idle * TPI=Idle Link Test Fail Start_Link_Test_Min_Timer Start_Link_Test_Max_Timer XMIT=Disable RCVR=Disable LPBK=Disable TPI=Active + Link_Count=LC_Max Link_Test_Min_Timer_Done * Link_Test_Rcvd=True Link Test Fail Extended XMIT=Disable RCVR=Disable LPBK=Disable (TPI=Idle * Link_Test_Max_Timer_Done) + (Link_Test_Min_Timer_Not_Done * Link_Test_Rcvd=True) TPI=Idle * DO=Idle Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 18 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 3.0 3.0 Application Information Application Information Figure 9 through Figure 15 show some typical LXT908 PHY applications. 3.1 External Components 3.1.1 Crystal Information Suitable crystals are available from various manufacturers. Table 3 lists some suitable crystals based on limited evaluation. Designers should test and validate all crystals before using them in production. Table 3 Suitable Crystals Manufacturer Part Number MTRON* 3.1.2 MP-1 MP-2 Magnetic Information The TP interface requires a 1:1 ratio for the receive transformer and a 1:2 ratio for the transmit transformer. The AUI interface requires a 1:1 ratio for the data-in, data-out, and collision-pair transformers. Designers should test and validate all magnetics before committing to a specific component. 3.2 Layout Requirements 3.2.1 Auto Port Select with External Loopback Control Figure 9 is a typical LXT908 PHY application. The diagram is arranged to group similar pins together; it does not represent the actual LXT908 PHY pin-out. The controller interface pins (TXD, RXD, TEN, TCLK, RCLK, CD, COL, and LBK) are shown at the top left. Programmable option pins are grouped center left. The PAUI pin is tied Low and all other option pins are tied High. This setup selects the following options: * Automatic Port Selection (PAUI Low and AUTOSEL High) * Normal Receive Threshold (NTH High) * Mode 4, compatible with National NS8390 controllers (MD2:0 = Low, High, High) * SQE Disabled (DSQE High) * Link Testing Enabled (LI High) Status outputs are grouped at lower left. Line status outputs drive LED indicators and the Jabber and Polarity status indicators are available as required. Power and ground pins are shown at the bottom of the diagram. A single power supply is used for both VCC1 and VCC2 with a decoupling capacitor installed between the power and ground busses. Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 19 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 3.2 Layout Requirements An additional power and ground pin (VCCA and GNDA) is supported in designs using the 64-pin LQFP package. A single power supply is used for all three power and ground pins (VCC1, VCC2, VCCA) and (GND1, GND2, GNDA). Install a decoupling capacitor between each power and ground buss. The TP and AUI interfaces are shown at upper and lower right, respectively. Impedance matching resistors for 100 UTP are installed in each I/O pair but no external filters are required. LAN Adapter Board - Auto Port Select with External Loopback Control TXD TXE TXC NS8390 BACK-END CONTROLLER INTERFACE RXC RXD CRS COL LOOPBACK ENABLE LBK 20 M Hz CLKI 20 pF CLKO TXD TEN TCLK RCLK RXD CD COL LBK RJ45 TPIN TPIP TPONB AUTOSEL NTH MD0 JAB PLR LINE STATUS 330 330 330 330 Green Red Red Red TPOPB TPOPA LXT908 M D2 M D1 MODE SELECT 11.5 220pF 11.5 78 CIN 14 5 1 6 1:2 3 11 2 8 16 9 1 1 9 2 10 CIP DON LEDC/FDE LEDR LEDT/PDN LEDL 3 6 4 PAUI DSQE LI 1 : 1 16 100 TPONA PROGRAMMING OPTIONS 1 2 78 4 3 15 11 4 13 12 5 DOP DIN 5 12 78 7 10 To 10 BASE-T TWISTEDPAIR NETWORK 20 pF D - CONNECTOR to AUI DROP CABLE Figure 9 13 6 14 7 15 8 TEST +3.3V VCC1 RBIAS VCC2 Fuse 9 12.4 k 1% GND1 GND2 1 8 DIP 1 Chassis Gnd + 12 V Bias resistor RBIAS should be located close to the pin and isolated from other signals. Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 20 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 3.2.2 3.2 Layout Requirements Full Duplex Support Figure 10 shows the LXT908 PHY with a Texas Instruments* 380C24 CommProcessor. The 380C24* is compatible with Mode 4 (MD2:0 = Low, High, High). When used with the 380C24* or other full duplex-capable controller, the LXT908 PHY supports full-duplex Ethernet, effectively doubling the available bandwidth of the network. In this application the SQE function is enabled (DSQE tied Low), and the LXT908 PHY AUI port is not used. Full-Duplex Operation CLKI 3 TXD TXEN TXC RXC RXD CSN COLL LPBK *TEST0 OUTSEL0 1N914 1 TXD TEN TCLK RCLK RXD CD COL LBK LEDC/FDE 10 K AUTOSEL *Open Collector Driver NTH 4.7 K PROGRAMMING OPTIONS 20 pF 20 MHz CLKO RJ45 TPIN 1 1 : 1 16 3 14 6 100 TPIP 5 4 TPONB TPONA 11.5 6 1:2 11 2 220pF TPOPB TPOPA 11.5 8 3 9 To 10 BASE-T TWISTEDPAIR NETWORK 20 pF TMS380C24 LXT908 Figure 10 1 LI DSQE PAUI MODE SELECT LINE STATUS 330 330 330 Green Red Red CIN MD2 MD1 MD0 JAB PLR DON PAUI DOP LEDR LEDT/PDN LEDL CIP 1 Half/Full Duplex Selection controlled by TMS380C24 Pins Test0 and OUTSEL0. 2 Bias resistor RBIAS should be located close to the pin and isolated from other signals. 3 The TMS380C26 may be substituted for dual network support of 10BASE-T and Token Ring. DIN DIP TEST +3.3 V VCC1 RBIAS VCC2 2 12.4 k 1% GND1 GND2 Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 21 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 3.2.3 3.2 Layout Requirements Dual Network Support-10Base T and Token Ring Figure 11 shows the LXT908 PHY with a Texas Instruments* 380C26 CommProcessor. The 380C26 is compatible with Mode 4 (MD2:0 = Low, High, High). When used with the 380C26, both the LXT908 PHY and a TMS38054 Token Ring transceiver can be tied to a single RJ-45 allowing dual network support from a single connector. The LXT908 PHY AUI port is not used. LXT908 PHY/380C26 Interface for Dual Network Support of 10BASE-T and Token Ring From TI TMS38054 Token Ring Transceiver To TI TMS38054 Token Ring Transceiver 20 pF 380C26 CLKI TXD TEN TCLK RCLK RXD CD COL LBK TXD TXE TXC RXC RXD CRS COL LBK JAB PLR LINE STATUS Green Red 330 CLKO 2 TPIN 1 1 : 1 16 3 14 100 TPIP RJ45 6 5 4 TPONB 11.5 6 TPONA 1:2 11 11.5 8 TPOPA 3 2 220pF 9 1 TPOPB 18 pF LXT908 MD2 MD1 MD0 MODE SELECT 330 20 pF AUTOSEL NTH DSQE PAUI LI PROGRAMMING OPTIONS 330 20 MHz To 10 BASE-T TWISTEDPAIR NETWORK Figure 11 CIN CIP 330 Red Red 1 LEDC/FDE LEDR LEDT/PDN LEDL DON 2 DOP Bias resistor RBIAS should be located close to the pin and isolated from other signals. Additional magnetics and switching logic (not shown) is required to implement the dual network solution. DIN DIP TEST +3.3 V 12.4k VCC1 RBIAS VCC2 GND1 GND2 1% 1 Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 22 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 3.2.4 3.2 Layout Requirements Manual Port Select & Link Test Function With MD2:0 = Low, High, Low, the LXT908 PHY logic and framing are set to Mode 3 (compatible with Fujitsu* MB86950 and MB86960, and Seeq* 8005 controllers). Figure 12 shows the setup for Fujitsu* controllers. Figure 13 on page 24 shows the four inverters required to interface with the Seeq* 8005 controller. As in Figure 9 on page 20, both these Mode 3 applications show the LI pin tied High, enabling Link Testing; and the NTH and DSQE pins are both tied High, selecting the standard receiver threshold and disabling SQE. However, in these applications AUTOSEL is tied Low, allowing external port selection through the PAUI pin. Figure 12 LAN Adapter Board - Manual Port Select with Link Test Function 20 pF 20 pF MODE SELECT MD2 MD1 MD0 LINE STATUS JAB PLR TEN TCKN MB86950 or MB86960 BACK-END/ CONTROLLER INTERFACE RCKN RXD XCD XCOL LBC Port Selection PROGRAMMING OPTIONS 330 Green 330 Red 330 Red RJ45 1 TPIN 1:1 6 100 5 14 3 TPIP 4 TPONB 11.5 6 TPONA 1:2 3 11 2 220pF 11.5 8 TPOPA TPOPB 78 CIN 1 16 9 1 1 9 2 10 330 Red 16 LEDC/FDE LEDR LEDT/PDN LEDL 2 CIP 78 DON 3 15 11 4 4 13 12 5 DOP 78 DIN 5 12 7 10 To 10 BASE-T TWISTEDPAIR NETWORK CLKO TXD D - CONNECTOR to AUI DROP CABLE CLKI TXD TEN TCLK RCLK RXD CD COL LBK PAUI AUTOSEL NTH DSQE LI LXT908 20 MHz 13 6 14 7 15 8 TEST +3.3 V VCC1 8 DIP 9 12.4 k RBIAS VCC2 1% GND1 GND2 1 1 Fuse Chassis Gnd + 12 V Bias resistor RBIAS should be located close to the pin and isolated from other signals. Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 23 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Manual Port Select with Seeq* 8005 Controller External 20 MHz Source CLKI CLKO CLKI LBK CD RXD RCLK COL TEN TCLK TXD PAUI AUTOSEL NTH DSQE LI LPBK CSN 8005 Left Open RxD RxC COLL TxEN TxC TxD Port Selection PROGRAMMING OPTIONS RJ45 1 TPIN 1:1 16 6 100 3 TPIP 5 14 4 TPONB 11.5 6 TPONA 1:2 3 11 2 220pF 11.5 8 TPOPA 9 To 10 BASE-T TWISTEDPAIR NETWORK Figure 13 3.2 Layout Requirements 1 MODE SELECT LINE STATUS JAB PLR 330 Green 330 Red 330 78 CIN 1 16 2 10 330 Red Red 1 9 CIP LEDC/FDE LEDR LEDT/PDN LEDL 2 78 DON 3 15 11 4 4 13 12 5 5 DOP TEST 78 ? DIN 7 12 10 D - CONNECTOR to AUI DROP CABLE MD2 MD1 MD0 LXT908 TPOPB 13 6 14 7 15 8 8 DIP VCC1 +3.3V RBIAS VCC2 9 12.4k 1% GND1 GND2 1 1 3.2.5 Fuse Chassis Gnd + 12 V Bias resistor RBIAS should be located close to the pin and isolated from other signals. Three Media Application Figure 14 shows the LXT908 PHY in Mode 2 (compatible with Intel 82596 controllers) with additional media options for the AUI port. Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 24 3.2.6 Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver 0.1 F +3.3 V 10 k Power Down 10 k LINE STATUS MODE SELECT LINK TEST ENABLE PROGRAMMING OPTIONS LBK CDT CRS RXD RXC RTS TXC TXD CLK 1 CLKI CLKO 12.4 k 1% GND1 LXT908 RBIAS VCC2 VCC1 TEST LEDL LEDT/PDN LEDR LEDC/FDE PLR JAB MD0 MD1 MD2 LI PAUI DSQE NTH AUTOSEL LBK COL CD RXD RCLK TCLK TEN TXD GND2 DIP DIN DOP DON CIP CIN TPOPB TPOPA TPONA TPONB TPIP TPIN 11.5 11.5 100 8 6 3 1 1:2 9 11 14 1 : 1 16 78 78 78 1 2 3 4 5 6 9 8 10 9 8 12 13 15 7 5 4 2 16 10 7 1 12 5 13 15 2 4 16 To 10 BASE-T TWISTEDPAIR NETWORK 1 RJ45 8 7 6 5 4 3 2 Chassis Gnd 15 14 13 12 11 10 9 1 1.5 k + 12 V Fuse D - CONNECTOR to AUI DROP CABLE (Thick Coax) HBE GND RXRX+ RR+ RR- VEE TX+ VEE VEE RXI TXD CD+ TX- CDS CD- DP8392 0.01 F 1 M 1/2 W -9V 1 k 1N916 0V 9 13 12 V- N/C V+ 24 23 3 1 2 75 F / 1 kV GND GND EN 5V 5V PM6044 BHC to THIN COAX NETWORK +5 V Figure 14 82566 BACK-END/ CONTROLLER INTERFACE 20 MHz System Clock Left Open LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 3.2 Layout Requirements Two transformers are used to couple the AUI port to either a D-connector or a BNC connector. (A DP8392 coax transceiver with PM6044 power supply are required to drive the thin coax network through the BNC. Three Media Application AUI Encoder/Decoder Only In the application shown in Figure 15, the DTE is connected to a coaxial network through the AUI. AUTOSEL is tied Low and PAUI is tied High, manually selecting the AUI port. The twisted-pair port is not used. With MD2:0 all tied Low, the LXT908 PHY logic and framing Page 25 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 3.2 Layout Requirements are set to Mode 1 (compatible with AMD* and Motorola* controllers). The LI pin is tied Low, disabling the link test function. The DSQE pin is also Low, enabling the SQE function. The LBK input controls loopback. A 20 MHz system clock is supplied at CLKI with CLKO left open. AUI Encoder/Decoder Only Application SYSTEM CLOCK Left Open 20 MHz TX TENA TCLK RCLK AM7990 BACK-END/ CONTROLLER INTERFACE RX RENA CLSN LOOPBACK CONTROL LBK CLKI CLKO TXD TEN TCLK RCLK RXD CD COL LBK AUTOSEL 78 PAUI NTH DSQE LI MD2 MD1 MD0 MODE SELECT JAB PLR LINE STATUS 330 330 1 16 1 9 2 10 CIP LXT908 PROGRAMMING OPTIONS 330 CIN DON 2 78 4 3 15 11 4 13 12 5 DOP DIN 5 12 78 7 10 330 13 6 14 7 15 8 GREEN Red Red Red LEDC/FDE LEDR LEDT/PDN LEDL 8 DIP 9 Chassis Gnd TEST +3.3 V VCC1 Fuse + 12 V 1 RBIAS VCC2 GND1 GND2 1 D - CONNECTOR to AUI DROP CABLE Figure 15 12.4 k 1% Bias resistor RBIAS should be located close to the pin and isolated from the other signals Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 26 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 4.0 Test Specifications 4.0 Test Specifications Note: Table 4 through Table 13 and Figure 16 through Figure 45 represent the performance specifications of the LXT908 PHY. These specifications are guaranteed by test except where noted "by design." Minimum and maximum values listed in Table 6 through Table 13 apply over the recommended operating conditions specified in Table 5. Table 4 Absolute Maximum Values Parameter Symbol Min Max Units VCC -0.3 6 V Supply voltage Ambient operating temperature (Commercial) TA 0 +70 C Ambient operating temperature (Extended) TA -40 +85 C TSTG -65 +150 C Storage temperature Caution: Table 5 Exceeding these values may cause permanent damage. Functional operation under these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Min Typ Max Units Recommended supply voltage VCC 3.13 3.3 3.47 V Recommended operating temperature (Commercial) TOP 0 - +70 C Recommended operating temperature (Extended) TOP -40 - +85 C 1 1. Voltages with respect to ground unless otherwise specified. Table 6 I/O Electrical Characteristics (Sheet 1 of 2) Parameter 2 Input Low voltage 2 Input High voltage Output Low voltage Output Low voltage (Open drain LED driver) Output High voltage Sym Min 1 Typ Max Units Test Conditions VIL - - 0.8 V -- VIH 2.0 - - V -- VOL - - 0.4 V IOL = 1.6 mA VOL - - 10 %VCC IOL < 10 A VOLL - - 0.7 V IOLL = 10 mA VOH 2.4 - - V IOH = 40 A VOH 90 - - %VCC IOH < 10 A Output rise time CMOS - - 3 12 ns CLOAD = 20 pF TCLK & RCLK TTL - - 2 8 ns -- Output fall time CMOS - - 3 12 ns CLOAD= 20 pF TCLK & RCLK TTL - - 2 8 ns -- 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Limited functional tests are performed at these input levels. The majority of functional tests are performed at levels of 0 V and 3 V. Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 27 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Table 6 4.0 Test Specifications I/O Electrical Characteristics (Sheet 2 of 2) Parameter Sym 1 Typ Min Max Units Test Conditions CLKI rise time (externally driven) - - - 10 ns -- CLKI duty cycle (externally driven) - - - 40/60 % -- ICC - 65 85 mA Idle Mode Normal Mode ICC - 95 120 mA Transmitting on TP ICC - 90 120 mA Transmitting on AUI Power Down Mode ICC - 0.75 2 mA -- Supply current 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Limited functional tests are performed at these input levels. The majority of functional tests are performed at levels of 0 V and 3 V. Table 7 AUI Electrical Characteristics Symbol Min 1 Typ Max Units Input Low current IIL - - -700 A -- Input High Current II H - - 500 A -- Differential output voltage VOD 550 - 1200 mV -- Differential squelch threshold VDS 150 260 350 mV 5 MHz square wave input Parameter Test Conditions 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Table 8 Twisted-Pair Electrical Characteristics Symbol Min 1 Typ Max Units ZOUT - 5 - -- Transmit timing jitter addition - - 5 6.4 ns 0 line length for internal MAU Transmit timing jitter added by the MAU and PLS sections2, 3 - - 3.5 5.5 ns After line model specified by IEEE 802.3 for 10BASE-T internal MAU ZIN - 20 - k Between TPIP/TPIN, CIP/CIN & DIP/DIN Parameter Transmit output impedance Receive input impedance Test Conditions Differential Squelch Threshold Normal Threshold NTH = High VDS 300 395 585 mV 5 MHz square wave input -- Reduced Threshold NTH = Low VDS 180 250 345 mV 5 MHz square wave input 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. Parameter is guaranteed by design; not subject to production testing. 3. IEEE 802.3 specifies maximum jitter additions at 1.5/ns for the AUI cable, 0.5 ns from the encoder, and 3.5 ns from the MAU. Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 28 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Table 9 4.0 Test Specifications Switching Characteristics Parameter Jabber Timing Link Integrity Timing Symbol Minimum Maximum transmit time - 20 Unjab time - Time link loss receive Link min receive Typical 1 Maximum Units - 150 ms 250 - 750 ms - 50 - 150 ms - 2 - 7 ms Link max receive - 50 - 150 ms Link transmit period - 8 10/20 24 ms 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Table 10 RCLK/Start-of-Frame Timing Parameter Minimum AUI tDATA - 900 1100 ns TP tDATA - 1200 1500 ns AUI tCD - 25 200 ns TP tCD - 420 550 ns Receive data setup from RCLK Mode 1 tRDS 60 70 - ns Modes 2 through 5 tRDS 30 45 - ns Receive data hold from RCLK Mode 1 tRDH 10 20 - ns Modes 2 through 5 tRDH 30 45 - ns tsws - 100 - ns Decoder acquisition time CD turn-on delay RCLK shut off delay from CD assert (Mode 3 and Mode 5) 1. Typical 1 Symbol Maximum Units Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Table 11 RCLK/End-of-Frame Timing Parameter Type Sym Mode 1 Mode 2 Mode 3 Mode 4 Mode 5 Units RCLK after CD off Min tRC 5 1 - 5 - BT RXD throughput delay Max tRD 400 375 375 375 375 ns Max tCDOFF 500 475 475 475 475 ns 2 CD turn off delay 1 Receive block out after TEN off Typ tIFG 5 50 - - - BT RCLK switching delay after CD off (Mode 3 and 5) Typ1 tSWE - - 120(80) - 120(80) ns 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. 2. CD turn-off delay measured from middle of last bit: timing specification is unaffected by the value of the last bit. Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 29 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Table 12 4.0 Test Specifications Transmit Timing Parameter Symbol Minimum TEN setup from TCLK tEHCH 22 TXD setup from TCLK tDSCH TEN hold after TCLK TXD hold after TCLK Typical 1 Maximum Units - - ns 22 - - ns tCHEL 5 - - ns tCHDU 5 - - ns Transmit start-up delay - AUI tSTUD - 220 450 ns Transmit start-up delay - TP tSTUD - 430 450 ns Transmit through-put delay - AUI tTPD - - 300 ns Transmit through-put delay - TP tTPD - 305 350 ns 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Table 13 Collision, COL/CI Output and Loopback Timing Parameter Symbol Minimum COL turn-on delay tCOLD - COL turn-off delay tCOLOFF - Typical 1 Maximum Units 40 500 ns 420 500 ns COL (SQE) Delay after TEN off tSQED 0.65 1.2 1.6 s COL (SQE) Pulse Duration tSQEP 500 1000 1500 ns LBK setup from TEN tKHEH 10 25 - ns LBK hold after TEN tKHEL 10 0 - ns 1. Typical values are at 25 C and are for design aid only; not guaranteed and not subject to production testing. Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 30 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 4.1 Timing Diagrams for Mode 1 (MD2, 1, 0 = Low, Low, Low) Figure 16 through Figure 21 4.1 Timing Diagrams for Mode 1 (MD2, 1, 0 = Low, Low, Low) Figure 16 through Figure 21 Figure 16 Mode 1 RCLK/Start-of-Frame Timing 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 0 1 0 1 1 1 TPIP/TPIN or DIP/DIN tCD CD RCLK t RDS t RDH t DATA RXD 1 Note: Figure 17 0 1 0 1 0 1 RXD changes 25 ns after the rising edge of RCLK. Mode 1 RCLK/End-of-Frame Timing 1 0 1 0 1 0 1 0 0 TPIP/TPIN or DIP/DIN t CDOFF CD tRD tRC RCLK RXD 1 Note: 0 1 0 1 0 1 0 0 RXD changes 25 ns after the rising edge of RCLK. Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 31 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Figure 18 4.1 Timing Diagrams for Mode 1 (MD2, 1, 0 = Low, Low, Low) Figure 16 through Figure 21 Mode 1 Transmit Timing TEN t CHEL t EHCH TCLK t DSCH t CHDU TXD t STUD t TPD TPO Figure 19 Mode 1 Collision Detect Timing CI t COLOFF t COLD COL Figure 20 Mode 1 COL/SQE Output Timing/CI Output Timing TEN t SQED COL Figure 21 t SQEP Mode 1 Loopback Timing LBK t KHEH t KHEL TEN Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 32 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 4.2 Timing Diagrams for Mode 2 (MD2, 1, 0 = Low, Low, High) Figure 22 through Figure 27 4.2 Timing Diagrams for Mode 2 (MD2, 1, 0 = Low, Low, High) Figure 22 through Figure 27 Figure 22 Mode 2 RCLK/Start-of-Frame Timing 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 0 0 1 0 1 1 1 TPIP/TPIN or DIP/DIN tCD CD RCLK t RDS t RDH t DATA RXD 1 Note: 0 1 0 1 0 1 RXD changes at the rising edge of RCLK. The controller should sample at the falling edge. Figure 23 Mode 2 RCLK/End-of-Frame Timing 1 0 1 0 1 0 1 0 0 TPIP/TPIN or DIP/DIN CD t CDOFF tRD RCLK RXD 1 Note: 0 1 0 1 0 1 0 0 RXD changes at the rising edge of RCLK. The controller should sample at the falling edge. Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 33 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Figure 24 4.2 Timing Diagrams for Mode 2 (MD2, 1, 0 = Low, Low, High) Figure 22 through Figure 27 Mode 2 Transmit Timing TEN t CHEL t EHCH TCLK t DSCH t CHDU TXD t STUD t TPD TPO Figure 25 Mode 2 Collision Detect Timing CI t COLD t COLOFF COL Figure 26 Mode 2 COL/SQE Output Timing tIFG TEN t SQED COL t SQEP Figure 27 Mode 2 Loopback Timing LBK t KHEH t KHEL TEN Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 34 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 4.3 Timing Diagrams for Mode 3 (MD2, 1, 0 = Low, High, Low) Figure 28 through Figure 33 4.3 Timing Diagrams for Mode 3 (MD2, 1, 0 = Low, High, Low) Figure 28 through Figure 33 Figure 28 Mode 3 RCLK/Start-of-Frame Timing 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 TPIP/TPIN or DIP/DIN tCD CD t SWS Recovered from Input Data Stream RCLK t RDS Generated from TCLK t DATA RXD 1 Note: t RDH 0 1 0 1 0 1 0 1 1 1 0 1 RXD changes at the rising edge of RCLK. The controller should sample at the falling edge. Figure 29 Mode 3 RCLK/End-of-Frame Timing 1 0 1 0 1 0 1 0 0 TPIP/TPIN or DIP/DIN t CDOFF CD tRD t SWE RCLK Recovered Clock Generated from TCLK RXD 1 Note: 0 1 0 1 0 1 0 0 RXD changes at the rising edge of RCLK. The controller should sample at the falling edge. Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 35 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Figure 30 4.3 Timing Diagrams for Mode 3 (MD2, 1, 0 = Low, High, Low) Figure 28 through Figure 33 Mode 3 Transmit Timing TEN t CHEL t EHCH TCLK t DSCH t CHDU TXD t STUD t TPD TPO Figure 31 Mode 3 Collision Detect Timing CI t COLOFF t COLD COL Figure 32 Mode 3 COL/SQE Output Timing TEN t SQED t SQEP COL Figure 33 Mode 3 Loopback Timing LBK t KHEH t KHEL TEN Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 36 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 4.4 Timing Diagrams for Mode 4 (MD2, 1, 0 = Low, High, High) Figure 34 through Figure 39 4.4 Timing Diagrams for Mode 4 (MD2, 1, 0 = Low, High, High) Figure 34 through Figure 39 Figure 34 Mode 4 RCLK/Start-of-Frame Timing 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 TPIP/TPIN or DIP/DIN tCD CD RCLK t RDS t RDH t DATA RXD 1 Note: 0 1 0 1 0 1 0 1 1 1 0 1 RXD changes at the rising edge of RCLK. The controller should sample at the falling edge. Figure 35 Mode 4 RCLK/End-of-Frame Timing 1 0 1 0 1 0 1 0 0 TPIP/TPIN or DIP/DIN t CDOFF CD tRD RCLK RXD 1 Note: 0 1 0 1 0 1 0 0 RXD changes at the rising edge of RCLK. The controller should sample at the falling edge. Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 37 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Figure 36 4.4 Timing Diagrams for Mode 4 (MD2, 1, 0 = Low, High, High) Figure 34 through Figure 39 Mode 4 Transmit Timing TEN t CHEL t EHCH TCLK t DSCH t CHDU TXD t TPD t STUD TPO Figure 37 Mode 4 Collision Detect Timing CI t COLD t COLOFF COL Figure 38 Mode 4 COL/SQE Output Timing TEN t SQED COL Figure 39 t SQEP Mode 4 Loopback Timing LBK t KHEH t KHEL TEN Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 38 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 4.5 Timing Diagrams for Mode 5 (MD2, 1, 0 = High, High, Low) Figure 40 through Figure 45 4.5 Timing Diagrams for Mode 5 (MD2, 1, 0 = High, High, Low) Figure 40 through Figure 45 Figure 40 Mode 5 RCLK/Start-of-Frame Timing 1 0 1 0 1 0 1 0 1 1 1 0 1 0 0 0 1 0 1 TPIP/ TPIN tCD CD t SWS Recovered from Input Data Stream RCLK t RDS Generated from TCLK t DATA RXD 1 Note: t RDH 0 1 0 1 0 1 0 1 1 1 0 1 RXD changes at the rising edge of RCLK. The controller should sample at the falling edge. Figure 41 Mode 5 RCLK/End-of-Frame Timing 1 0 1 0 1 0 1 0 0 TPIP/ TPIN t CDOFF CD tRD t SWE RCLK Recovered Clock Generated from TCLK RXD 1 Note: 0 1 0 1 0 1 0 0 RXD changes at the rising edge of RCLK. The controller should sample at the falling edge. Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 39 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Figure 42 4.5 Timing Diagrams for Mode 5 (MD2, 1, 0 = High, High, Low) Figure 40 through Figure 45 Mode 5 Transmit Timing TEN t CHEL t EHCH TCLK t DSCH t CHDU TXD t STUD t TPD TPO Figure 43 Mode 5 Collision Detect Timing CI t COLOFF t COLD COL Figure 44 Mode 5 COL/SQE Output Timing TEN t SQED t SQEP COL Figure 45 Mode 5 Loopback Timing LBK t KHEH t KHEL TEN Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 40 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 5.0 Mechanical Specifications 5.0 Mechanical Specifications Figure 46 44-Pin PLCC Package Specifications 44-Pin Plastic Leaded Chip Carrier * Part Number LXT908PC - Commercial temperature range (0 C to +70 C) * Part Number LXT908PE - Extended temperature range (-40 C to +85 C) CL Inches Millimeters Dim Min Max Min Max A 0.165 0.180 4.191 4.572 A1 0.090 0.120 2.286 3.048 A2 0.062 0.083 1.575 2.108 B 0.050 - 1.270 - C 0.026 0.032 0.660 0.813 D 0.685 0.695 17.399 17.653 D1 0.650 0.656 16.510 16.662 F 0.013 0.021 0.330 0.533 C B D1 D A2 D A A1 F Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver Page 41 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Figure 47 5.0 Mechanical Specifications 64-Pin LQFP Package Specifications 64-Pin Low-Profile Quad Flat Package * Part Number LXT908LC (Commercial Temperature Range) * Part Number LXT908LE (Extended Temperature Range) Dim Dim Inches Inches Min Min Max Max Min Min Max Max A A - - 0.063 0.063 - - 1.60 1.60 A1 A1 0.002 0.002 0.006 0.006 0.05 0.05 0.15 0.15 A2 A2 0.053 0.053 0.057 0.057 1.35 1.35 1.45 1.45 B B 0.007 0.007 .011 .011 0.17 0.17 0.27 0.27 D D 0.472 0.472 BSC BSC 12.00 12.00 BSC BSC D1 D1 0.394 0.394 BSC BSC 10.00 10.00 BSC BSC E E 0.472 0.472 BSC BSC 12.00 12.00 BSC BSC E1 E1 0.394 0.394 BSC BSC 10.00 10.00 BSC BSC e e 0.020 0.020 BSC BSC 0.50 0.50 BSC BSC L L L1 L1 0.018 0.018 D Millimeters Millimeters 0.030 0.030 0.45 0.45 0.039 0.039 REF REF D1 E1 E 0.75 0.75 1.00 1.00 REF REF 33 o 11 11o o 13 13o o 11 11o o 13 13o o 0 0o o 7 7o o 0 0o o 7 7o e e/ 2 3 L1 A A1 L Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver A2 B 3 Page 42 LXT908 PHY Datasheet 249049, Revision 4.0 10 March 2009 Contact Information Contact Information Cortina Systems, Inc. 840 W. California Ave Sunnyvale, CA 94086 408-481-2300 For additional product and ordering information: www.cortina-systems.com To provide comments on this document: documentation@cortina-systems.com Cortina Systems(R) LXT908 Universal 3.3 V 10BASE-T and AUI Transceiver ~ End of Document ~ Page 43