ANALOG LC?MOS High Speed jxP-Compatible DEVICES 8-Bit ADC with Track/Hold Function AD7820 1.1 Scope. This specification covers the detail requirements for a monolithic CMOS, microprocessor compatible 8-bit analog-to-digital converter which was a half-flash conversion technique to achieve a conversion time of 1.6us. The converter has a OV to +5V analog input voltage range with a single + 5V supply. 1.2 Part Number. The complete part number per Table | of this specification is as follows: Device Part Number! ] AD7820T(XV/883B ~2 AD7820U(X)/883B NOTE 'See paragraph 1.2.3 for package identifier. 1.2.3 Case Outline. See Appendix | of General Specification ADI-M-1000: package outline: () Package Description Q Q-20 20-Pin Cerdip E E-20A 20-Contact LCC 1.3 Absolute Maximum Ratings. (T, = + 25C unless otherwise noted) Vpp toDGND . 2... te tee tees OV, +7V Digital Input Voltage to GND (Pins 6-8, 13) 2... ee ee -0.3V; Vpp Digital Output Voltage to GND (Pins 2-5, 14-18) 2... ee ee 0.3V, Vpp Vrer(+)toGND .. 0... ee es Veer (),; Vop Vrer () to GND 2.0. ee ee ov, VREF (+) Vin toGND 2.0... ee ee es -0.3V, Vop Operating Temperature Range .... 0.0.0. ee ee ee es 55C to + 125C Storage Temperature 2.2... ee ee es 65C to + 150C Lead Temperature (Soldering 10sec) . 0... 2. ee te tt + 300C Power Dissipation (Any Package) to +75 2 ww et 450mW Derates above +75C by 22... et ee 6mW/C 1.5 Thermal Characteristics. Thermal Resistance 8j- = 35C/W for Q-20 and E-20A @y4 = 120C/W for Q-20 and E-20A REV. A ANALOG-TO-DIGITAL CONVERTERS 6-133 ANALOG-TO-DIGITAL CONVERTERS aAD7820SPECIFICATIONS Table 1. Design (Sub | Sub | Sub Limit Group | Group/ Group Test Symbol| Device | Taie~Taex| 1 2,3 14 Test Condition!? Units Resolution RES | -1,2 [8 This is the minimum resolu- [Bits tion for which no missing codes are guaranteed. Total Unadjusted Error? TUE | -1 1 1 1 + LSB max -2 12 1 12 1/2 Analog Input Leakage Current In -1,2 |3 3 3 + pA max Analog Input Capacitance Cc -1,2 | 45 pF typ Reference Input Resistance Ry -1,2 [1 1 1 [kf min 4 4 4 kf max Digital Input High Level Vin -1,2 12.4 24 | 2.4 CS, WR, RD V min 3.5 3.5 | 3.5 Mode (Pin 7) Digital Input Low Level Vin -1,2 | 0.8 0.8 0.8 CS, WR, RD 'V max 1.5 15 1.5 Mode (Pin 7) Digital Input High Current Im -1,2 | 1.0 1.0 1.0 S,RD pA max 3.0 3.0 | 3.0 WR 200.0 200.0 | 200.0 Mode (Pin 7) Digital Input Low Current In -1,2 | 1.0 1.0 1.0 CS, WR, RD Mode(Pin7) | Amax Digital Input Capacitance Cc ~-1,2 | 8.0 CS, WR, RD Mode(Pin7) [pF max Digital Output High Level Von | -1,2 | 4.0 4.0 4.0 DBO-DB7, OFL, INT Vmin Tsounce = 360pA Digital Output Low Level Vor | -1,2 | 0.4 0.4 0.4 DBO-DB7, OFL, INT Vmox Isnex = 1.6mA Digital Output Low Level Vor | -1,2 | 0.4 RDY; Ismx = 2.6mA Vmax Floating State LeakageCurrent |Iour | 1,2 | 3.0 3.0 | 3.0 DB0-DB7 pA max Digital Output Capscitance Cour | 1,2 | 8.0 (Typically SpF) pF maz Slew Rate, Tracking ~1,2 | 0.1 Vins Supply Current from Vpp Ipp 1,2 | 15.0 20.0 | 20.0 CS = RD= 0v mA max Power Supply Sensitivity 1,2 | 14 wm =| Vpp = 5V 5% = LSB max CS to RD/WR Setup Time tcs -1,2 | 0 ns min CS to RD/WR Hold Time tou -1,2 | 0 ns min CS w RDY Delay. Pull-Up Resistor 2k* troy | -1,2 | 100 70ns max at + 25C ns max Conversion Time (RD Mode) terp | -1,2 | 2.5 16 | 2.5 ys max Data Access Time (RD Mode) | tacco | 1,2 | tenn +50 (tcrp +20) nsmaxat +25C| ns max RDtoINT Delay (RD Mode)* | tyre | ~1,2 | 225 175ns max at + 25C ns max Data Hold Time ton -1,2 | 100 60ns max at + 25C ns max Delay Time Between Conversions| tp -1,2 | 600 500ns min at + 25C ns min Write Pulse Width twr -1,2 | 600 ns max 50 ns max Delay Time Between WR and RD Pulses trp ~1,2 | 700 600ns max at + 25C ns min Dats Access Time (WR/RD Mode, See Fig. 4) tacce: | 1,2 | 250 160ns max at + 25C ns max RD twoINT Delay tri 1,2 | 225 140ns max at + 25C ns max WR to INT Delay* tort | 1,2 | 1700 1000ns max at + 25C ps max 6-134 ANALOG-TO-DIGITAL CONVERTERS REV. AAD7820 Design Sub Sub Sub Limit Group | Group| Group Test Symbol | Device | Tyje-T man} 1 2,3 Test Condition Units Data Access Time (WR/RD Mode, See Fig. 3) tacc2 ~1,2 | 110 70ns max at + 25C ns max WR INT Delay (Stand- Alone Operation)* turwr | 1,2 ] 150 100ns max at + 25C ns max Data Access Time after INT (Stand-Alone Operation) tp ~1,2 | 75 $0ns max at + 25C ns max NOTES Von = +5V;Vrue(+) = +5V; Vaze() = GND = OV unless otherwise specified . Specifications apply for RD mode (Pin? = OV). Allinput contro signals are specified with = t = 20ns (10% 10 90% of + 5V) and timed from s voltage level of + 1.6V. 3Includes gain error, offset error and linearity error. C, = SOpF. 5 Measured with load circuits of Figure | and defined as the time required for an output to cross 0.8V of 2.4V. Defined as the time required for the data lines to change 0.5V when loaded with the circuits of Figure 2. 5V 5v 3k 3kn DBN DBN DBN OBN 3ka 100pF 100pF akn L 10pF L 10pF DGND L J DGND OGND a. High-Z to Vow b. High-Z to Vox a. Von to High-Z b. Voy to High-Z Figure 1. Load Circuits for Data Access Time Test Figure 2. Load Circuits for Data Hold Time Test 3.2.1 Functional Block Diagram and Terminal Assignments. E Package (LCC) Veer (+) Veer (1 Va DBO-OB7 DATAOUT PINS 2-5, 14-17 4-8IT FLASH oC Al (4LSB} TIMING AND CONTROL NC CIRCUITRY 9 GND MODE WR/RDY int alte 3.2.4 Microcircuit Technology Group. This microcircuit is covered by technology group (81). REV. A 18 GFL 17 DB7 (MSB) 16 DBS 15 DBS 14 DB4 13 8 Vase (-) Veer (+1 8 ANALOG-TO-DIGITAL CONVERTERS 6-135 ANALOG-TO-DIGITAL CONVERTERS aAD7820 4.2.1 Life Test/Burn-In Circuit. Steady state life test is per MIL-STD-883 Method 1005. Burn-in is per MIL-STD-883 Method 1015 test condition (B). Voo $ F3 $ a1 $ ks 7 = $ 100 | i Vinw Veco [20 a 2 EI DB0 NC 73] 5v- tH EE pB1 OFL ia) yop o- [e] ose pa7 [77] 5vV~ a - somo en Fa] was ST Vy {&] Wanov pes [715] ; + $1m | ra on El MODE pes [14] POWER-UP CONVERT. START ain Sar {e] aD ts 13}+ Ee INT Vaer (+) liz} 9Lie] oxo Veer (~) [1 INITIALIZATION SEQUENCE Voo = 5V R1,R2 FOR PROTECTION ONLY R31S A PULL-UP RESISTOR 5.0 Digital Interface. The AD7820 has two basic interface modes which are determined by the status of the MODE pin. When this pin is low the converter is in the RD mode, with this pin high the AD7820 is set up for the WR-RD mode. 5.1 WR-RD Mode. In the WR-RD mode, pin 6 is configured as the WRITE input for the AD7820. With CS low, conversion is initiated on the falling edge of WR. Two options exist for reading data from the converter. In the first of these options the processor waits for the INT status line to go low before reading the data (see Figure 3). INT typically goes low 700ns after the rising edge of WR. It indicates that conversion is complete and that the data result is in the output latch. With CS low, the data outputs (DB0-DB7) are activated when RD goes low. INT is reset by the rising edge of RD or CS. f | } INT / | ten | t x 0B? ee VALIO D80-0B7 + DATA 7 mete Figure 3. WR-RD Mode (trap>tinr) 6-136 ANALOG-TO-DIGITAL CONVERTERS REV. AAD7820 REV. A The alternative option can be used to shorten the conversion time. To achieve this, the status of the INT line is ignored and RD can be brought low 600ns after the rising edge of WR. In this case RD going low transfers the data result into the output latch and activates the data outputs (DBO-DB7). INT also goes low on the falling edge of RD and is reset on the rising edge of RD or CS. The timing for this interface is shown in Figure 4. a ee | Late a f' / V/ teas t ty RD \ # =} te iNT tNTH 080-D87 wae ~--- tacct am] bat mee} ton jo Figure 4. WR-RD Mode (tpp>tint) 5.2 RD Mode. The timing diagram for the RD mode is shown in Figure 5. In the RD mode configuration, conversion is initiated by taking RD low. The RD line is then kept low until output data appears. It is very useful with microprocessors which can be forced into a WAIT state, with the microprocessor starting a conversion, waiting, and then reading data with a single READ instruction. In this mode, pin 6 of the AD7820 is configured as a status output, RDY. This RDY output can be used to drive the processor READY or WAIT input. It is an open drain output (no internal pull-up device) which goes low after the falling edge of CS and goes high impedance at the end of conversion. An INT line is also 0 provided which goes low at the completion of conversion, INT returns high on the rising edge of CS or RD. The AD7820 can also be used in stand-alone operation in the WR-RD mode. CS and RD are tied low and a conversion is initiated by bringing WR low. Output data is valid typically 700ns after the rising edge of WR. The timing diagram for this mode is shown in Figure 6. _ aah FS Lf toss 1 . tne ROY WITH EXTERNAL PULL-UP teoy Ls twe, -~| tan Int TF if. te Wi wo a) Ty VALID 4 DB0-087 = 4 DATA SS So Lo | tou po Figure 6. WR-RD Mode Stand-Alone Operation, CS=RD=0 . Figure 5. RD Mode ANALOG-TO-DIGITAL CONVERTERS 6-137