October 2003
Copyright © Alliance Semiconductor. All rights reserved.
AS7C33128PFS16B
AS7C33128PFS18B
3.3V 128K × 16/18 pipeline burst synchronous SRAM
®
10/29/03; v.1.0 Alliance Semiconductor P. 1 of 14
Features
•Organization: 131,072 words × 16 or 18 bits
•Fast clock speeds to 200 MHz in LVTTL/LVCMOS
•Fast clock to data access: 3.0/3.5/4.0 ns
•Fast OE access time: 3.0/3.5/4.0 ns
•Fully synchronous register-to-register operation
•“Flow-through” or “Pipeline” mode
•Single-cycle deselect
Dual-cycle deselect also available (AS7C33128PFD16B/
AS7C33128PFD18B)
•Pentium®1 compatible architecture and timing
•Asynchronous output enable control
•Economical 100-pin TQFP package
•Byte write enables
•Multiple chip enables for easy expansion
•3.3V core power supply
•2.5V or 3.3V I/O operation with separate VDDQ
•30 mW typical standby power in power down mode
•NTD™1 pipeline architecture available
(AS7C33128NTD16B/AS7C33128NTD18B)
1. Pentium® is a registered trademark of Intel Corporation. NTD™ is a
trademark of Alliance Semiconductor Corporation. All trademarks men-
tioned in this document are the property of their respective owners.
Selection guide
–200 –166 –133 Units
Minimum cycle time 5 6 7.5 ns
Maximum pipelined clock frequency 200 166 133 MHz
Maximum pipelined clock access time 3 3.5 4 ns
Maximum operating current 400 350 325 mA
Maximum standby current 120 100 90 mA
Maximum CMOS standby current (DC) 30 30 30 mA
Logic block diagram
Burst logic
ADV
ADSC
ADSP
CLK
LBO
CLK
CLR
CS
17
15
17
A
[16:0]
17 Address
DQ
CS
CLK
register
128K × 16/18
Memory
array
16/18
16/18
DQb
CLK
DQ
Byte Write
registers
DQa
CLK
DQ
Byte Write
registers
Enable
CLK
DQ
register
Enable
CLK
DQ
delay
register
CE
Output
registers
Input
registers
Power
down
2
CE0
CE1
CE2
BWb
BWa
OE
ZZ
OE
FT
CLK CLK
BWE
GWE
16/18
DQ [a,b]
Pin arrangement
LBO
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE0
CE1
NC
NC
BWb
BWa
CE2
VDD
VSS
CLK
GWE
BWE
OE
ADSC
ADSP
ADV
A
A
NC
NC
NC
NC
VDDQ
VSSQ
NC
NC
DQb
DQb
VSSQ
VDDQ
DQb
DQb
FT
VDD
NC
VSS
DQb
DQb
VDDQ
VSSQ
DQb
DQb
DQpb/NC
NC
VSSQ
VDDQ
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSSQ
NC
DQpa/NC
DQa
DQa
VSSQ
VDDQ
DQa
DQa
VSS
ZZ
DQa
DQa
VDDQ
VSSQ
DQa
DQa
NC
NC
VSSQ
VDDQ
NC
NC
NC
NC
VDD
TQFP 14 × 20mm
Note: pins 24, 74 are NC for ×16.
AS7C33128PFS16B
AS7C33128PFS18B
®
10/29/03; v.1.0 Alliance Semiconductor P. 2 of 14
Functional description
The AS7C33128PFS16B and AS7C33128PFS18B are high performance CMOS 2 Mbit synchronous Static Random
Access Memory (SRAM) devices organized as 131,072 words × 16 or 18 bits and incorporate a pipeline for highest
frequency on any given technology.
Timing for this device is compatible with existing Pentium® synchronous cache specifications. This architecture is
suited for ASIC, DSP (TMS320C6X), and PowerPC™1-based systems in computing, datacom, instrumentation, and
telecommunications systems.
Fast cycle times of 5.0/6.0/7.5 ns with clock access times (tCD) of 3.0/3.5/4.0 ns enable 200, 166 and 133 MHz bus
frequencies. Three chip enable inputs permit easy memory expansion. Burst operation is initiated in one of two
ways: the controller address strobe (ADSC), or the processor address strobe (ADSP). The burst advance pin (ADV)
allows subsequent internally generated burst addresses.
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the
on-chip address register. When ADSP is sampled LOW, the chip enables are sampled active, and the output buffer
is enabled with OE. In a read operation the data accessed by the current address, registered in the address registers
by the positive edge of CLK, are carried to the data-out registers and driven on the output pins on the next positive
edge of CLK. ADV is ignored on the clock edge that samples ADSP asserted but is sampled on all subsequent clock
edges. Address is incremented internally for the next access of the burst when ADV is sampled LOW and both
address strobes are HIGH. Burst mode is selectable with the
LBO
input. With
LBO
unconnected or driven HIGH,
burst operations use a Pentium® count sequence. With
LBO
driven LOW the device uses a linear count sequence
suitable for PowerPC™ and many other applications.
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global
write enable GWE writes all 16/18 bits regardless of the state of individual BW[a:b] inputs. Alternately, when
GWE is HIGH, one or more bytes may be written by asserting BWE and the appropriate individual byte BWn
signal(s).
BWn is ignored on the clock edge that samples ADSP LOW, but is sampled on all subsequent clock edges. Output
buffers are disabled when BWn is sampled LOW (regardless of OE). Data is clocked into the data input register
when BWn is sampled LOW. Address is incremented internally to the next burst address if BWn and ADV are
sampled LOW.
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated
with ADSC and ADSP follow.
ADSP must be sampled HIGH when ADSC is sampled LOW to initiate a cycle with ADSC.
WE
signals are sampled on the clock edge that samples ADSC LOW (and ADSP HIGH).
Master chip select CE0 blocks ADSP, but not ADSC.
The AS7C33128PFS16B and AS7C33128PFS18B operate from a 3.3V supply. I/Os use a separate power supply that
can operate at 2.5V or 3.3V. These devices are available in a 100-pin 14×20 mm TQFP packaging.
1. PowerPC™ is a trademark International Business Machines Corporation
®
AS7C33128PFS16B
AS7C33128PFS18B
10/29/03; v.1.0 Alliance Semiconductor P. 3 of 14
Capacitance
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN Address and control pins VIN = 0V 5 pF
I/O capacitance CI/O I/O pins VIN = VOUT = 0V 7 pF
Write enable truth table (per byte)
GWE BWE BWn WEn
LXXT
HLLT
HHXF*
HLHF
*
Key: *= valid read; n = a,b X = Don’t Care, L = Low, H = High, T=True, F=False;
WE
,
WEn
= internal write signal.
Burst Order
Interleaved Burst Order
LBO
=1
Linear Burst Order
LBO
=0
Starting Address 00 01 10 11 Starting Address 00 01 10 11
First increment 01 00 11 10 First increment 01 10 11 00
Second increment 10 11 00 01 Second increment 10 11 00 01
Third increment 11 10 01 00 Third increment 11 00 01 10
AS7C33128PFS16B
AS7C33128PFS18B
®
10/29/03; v.1.0 Alliance Semiconductor P. 4 of 14
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other condi-
tions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect reliability.
Signal descriptions
Signal I/O Properties Description
CLK I CLOCK Clock. All inputs except OE,
FT
, ZZ,
LBO
are synchronous to this clock.
A0–A16 I SYNC Address. Sampled when all chip enables are active and ADSC or ADSP are
asserted.
DQ[a,b] I/O SYNC Data. Driven as output when the chip is enabled and OE is active.
CE0 ISYNC
Master chip enable. Sampled on clock edges when ADSP or ADSC is
active. When CE0 is inactive, ADSP is blocked. Refer to the Synchronous
Truth Table for more information.
CE1,
CE2
ISYNC
Synchronous chip enables. Active HIGH and active LOW, respectively.
Sampled on clock edges when ADSC is active or when CE0 and ADSP are
active.
ADSP ISYNC Address strobe (processor). Asserted LOW to load a new address or to
enter standby mode.
ADSC ISYNC Address strobe (controller). Asserted LOW to load a new address or to
enter standby mode.
ADV I SYNC Burst advance. Asserted LOW to continue burst read/write.
GWE ISYNC Global write enable. Asserted LOW to write all 16/18 bits. When HIGH,
BWE and BW[a,b] control write enable.
BWE ISYNC Byte write enable. Asserted LOW with GWE = HIGH to enable effect of
BW[a,b] inputs.
BW[a,b] ISYNC
Write enables. Used to control write of individual bytes when GWE =
HIGH and BWE = LOW. If any of BW[a,b] is active with GWE = HIGH and
BWE = LOW the cycle is a write cycle. If all BW[a,b] are inactive, the cycle
is a read cycle.
OE IASYNC Asynchronous output enable. I/O pins are driven when OE is active and
the chip is in read mode.
LBO I STATIC
Selects Burst mode. When tied to VDD or left floating, device follows interleaved
Burst order. When driven Low, device follows linear Burst order. This signal is
internally pulled High.
FT I STATIC
Selects Pipeline or Flow-through mode.When tied to VDD or left floating, enables
Pipeline mode. When driven Low, enables single register Flow-through mode.
This signal is internally pulled High.
ZZ I ASYNC Snooze. Places device in low power mode; data is retained. Connect to
GND if unused.
Absolute maximum ratings
Parameter Symbol Min Max Unit
Power supply voltage relative to GND VDD, VDDQ –0.5 +4.6 V
Input voltage relative to GND (input pins) VIN –0.5 VDD + 0.5 V
Input voltage relative to GND (I/O pins) VIN –0.5 VDDQ + 0.5 V
Power dissipation PD–1.8W
DC output current IOUT –50mA
Storage temperature (plastic) Tstg –65 +150 °C
Temperature under bias Tbias –65 +135 °C
®
AS7C33128PFS16B
AS7C33128PFS18B
10/29/03; v.1.0 Alliance Semiconductor P. 5 of 14
Key: X = Don’t Care, L = Low, H = High.
1See “Write enable truth table” on page 3 for more information.
2Q in flow through mode
3For write operation following a READ,
OE must be HIGH before the input data set up time and held HIGH throughout the input hold time.
Synchronous truth table
CE0 CE1 CE2 ADSP ADSC ADV
WEn
1OE
Address
accessed CLK Operation DQ
H X X X L X X X NA L to H Deselect Hi−Z
L L X L X X X X NA L to H Deselect Hi−Z
L L X H L X X X NA L to H Deselect Hi−Z
L X H L X X X X NA L to H Deselect Hi−Z
L X H H L X X X NA L to H Deselect Hi−Z
L H L L X X X L External L to H Begin read Hi−Z2
L H L L X X X H External L to H Begin read Hi−Z
L H L H L X F L External L to H Begin read Hi−Z2
L H L H L X F H External L to H Begin read Hi−Z
X X X H H L F L Next L to H Cont. read Q
X X X H H L F H Next L to H Cont. read Hi−Z
X X X H H H F L Current L to H Suspend read Q
X X X H H H F H Current L to H Suspend read Hi−Z
H X X X H L F L Next L to H Cont. read Q
H X X X H L F H Next L to H Cont. read Hi−Z
H X X X H H F L Current L to H Suspend read Q
H X X X H H F H Current L to H Suspend read Hi−Z
L H L H L X T X External L to H Begin write D3
X X X H H L T X Next L to H Cont. write D
H X X X H L T X Next L to H Cont. write D
X X X H H H T X Current L to H Suspend write D
H X X X H H T X Current L to H Suspend write D
Recommended operating conditions
Parameter Symbol Min Nominal Max Unit
Supply voltage VDD 3.135 3.3 3.6 V
VSS 0.0 0.0 0.0
3.3V I/O supply voltage VDDQ 3.135 3.3 3.6 V
VSSQ 0.0 0.0 0.0
2.5V I/O supply voltage VDDQ 2.35 2.5 2.9 V
VSSQ 0.0 0.0 0.0
Input voltages1
1 Input voltage ranges apply to 3.3V I/O operation. For 2.5V I/O operation, contact factory for input specifications.
VIH 2.0 – VDD + 0.3 V
VIL –0.52
2 VIL min = –2.0V for pulse width less than 0.2 × tRC.
–0.8
VIH 2.0 – VDDQ + 0.3 V
VIL –0.52–0.8
Ambient operating
temperature TA0–70°C
AS7C33128PFS16B
AS7C33128PFS18B
®
10/29/03; v.1.0 Alliance Semiconductor P. 6 of 14
TQFP thermal resistance
Description Conditions Symbol Typical Units
Thermal resistance
(junction to ambient)1Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
θJA 46 °C/W
Thermal resistance
(junction to top of case)1θJC 2.8 °C/W
1 This parameter is sampled.
DC electrical characteristics
Parameter Symbol Test conditions
–200 –166 –133
UnitMin Max Min Max Min Max
Input leakage
current1|ILI|V
DD = Max, VIN = GND to VDD –2–2 –2 µA
Output leakage
current |ILO|
OE
≥ VIH, VDD = Max,
VOUT = GND to VDD –2–2 –2 µA
Operating power
supply current ICC2
CE0
= VIL, CE1 = VIH,
CE2
=
VIL,
f = fMax, IOUT = 0 mA
– 400 - 350 – 325 mA
Standby power
supply current
ISB Deselected, f = fMax, ZZ ≤ VIL – 120 – 100 – 90
mA
ISB1 Deselected, f = 0, ZZ ≤ 0.2V
all VIN ≤ 0.2V or ≥ VDD – 0.2V –30–30–30
ISB2
Deselected, f = f
Max
, ZZ
≥
V
DD
–
0.2V
All VIN ≤ VIL or ≥ VIH
–30–30–30
Output voltage VOL IOL = 8 mA – 0.4 – 0.4 – 0.4 V
VOH IOH = –4 mA 2.4 – 2.4 – 2.4 –
1 LBO pin has an internal pull-up and input leakage = ±10 µA.
2 ICC give with no output loading. ICC increases with faster cycle times and greater output loading.
DC electrical characteristics for 2.5V I/O operation
Parameter Symbol Test conditions
–200 –166 –133
UnitMin Max Min Max Min Max
Output leakage
current |ILO|
OE
>VIH, VDD = Max,
VOUT = GND to VDD –1 1 –1 1 –1 1 µA
Output voltage VOL IOL = 2 mA – 0.7 – 0.7 – 0.7 V
VOH IOH = –2 mA 1.7 – 1.7 – 1.7 –
®
AS7C33128PFS16B
AS7C33128PFS18B
10/29/03; v.1.0 Alliance Semiconductor P. 7 of 14
Timing characteristics over operating range
Parameter Sym
–200 –166 –133
Unit Notes1
1 See “Notes” on page 11..
Min Max Min Max Min Max
Clock frequency fMax – 200 – 166 – 133 MHz
Cycle time (pipelined mode) tCYC 5–6 –7.5–ns
Cycle time (flow-through mode) tCYCF 7.5 – 9 – 12 – ns
Clock access time (pipelined mode) tCD – 3.0 – 3.5 – 4.0 ns
Clock access time (flow-through
mode) tCDF –6.5– 8.0 – 10 ns
Output enable LOW to data valid tOE – 3.0 – 3.5 – 4.0 ns
Clock HIGH to output Low Z tLZC 0 – 0 – 0 – ns 2,3,4
Data output invalid from clock HIGH tOH 1.5 – 1.5 – 1.5 – ns 2
Output enable LOW to output Low Z tLZOE 0 – 0 – 0 – ns 2,3,4
Output enable HIGH to output High Z tHZOE – 3.0 – 3.5 – 4.0 ns 2,3,4
Clock HIGH to output High Z tHZC – 3.0 – 3.5 – 4.0 ns 2,3,4
Output enable HIGH to invalid output tOHOE 0–0 – 0 –ns
Clock HIGH pulse width tCH 2.2 – 2.4 – 2.5 – ns 5
Clock LOW pulse width tCL 2.2 – 2.4 – 2.5 – ns 5
Address setup to clock HIGH tAS 1.4 – 1.5 – 1.5 – ns 6
Data setup to clock HIGH tDS 1.4 – 1.5 – 1.5 – ns 6
Write setup to clock HIGH tWS 1.4 – 1.5 – 1.5 – ns 6,7
Chip select setup to clock HIGH tCSS 1.4 – 1.5 – 1.5 – ns 6,8
Address hold from clock HIGH tAH 0.4 – 0.5 – 0.5 – ns 6
Data hold from clock HIGH tDH 0.4 – 0.5 – 0.5 – ns 6
Write hold from clock HIGH tWH 0.4 – 0.5 – 0.5 – ns 6,7
Chip select hold from clock HIGH tCSH 0.4 – 0.5 – 0.5 – ns 6,8
ADV setup to clock HIGH tADVS 1.4 – 1.5 – 1.5 – ns 6
ADSP setup to clock HIGH tADSPS 1.4 – 1.5 – 1.5 – ns 6
ADSC setup to clock HIGH tADSCS 1.4 – 1.5 – 1.5 – ns 6
ADV hold from clock HIGH tADVH 0.4 – 0.5 – 0.5 – ns 6
ADSP hold from clock HIGH tADSPH 0.4 – 0.5 – 0.5 – ns 6
ADSC hold from clock HIGH tADSCH 0.4 – 0.5 – 0.5 – ns 6
AS7C33128PFS16B
AS7C33128PFS18B
®
10/29/03; v.1.0 Alliance Semiconductor P. 8 of 14
Key to switching waveforms
Timing waveform of read cycle
Note: Ý = XOR when
LBO
= HIGH/No Connect; Ý = ADD when
LBO
= LOW.
BW[a:b] is don’t care.
Undefined/don’t careFalling inputRising input
t
CYC
t
CH
t
CL
t
ADSPS
t
ADSPH
t
AS
t
AH
t
WS
t
ADVS
t
OH
CLK
ADSP
ADSC
Address
GWE, BWE
CE0, CE2
ADV
OE
D
OUT
t
CSS
t
CSH
t
HZC
t
CD
t
WH
t
ADVH
t
HZOE
t
ADSCS
t
ADSCH
LOAD NEW ADDRESS
ADV INSERTS WAIT STATES
Q(A2Ý10)
Q(A2Ý11) Q(A3)
Q(A2)
Q(A2Ý01) Q(A3Ý01) Q(A3Ý10)
Q(A1)
A2A1 A3
CE1
(pipelined mode)
D
OUT
Q(A2Ý10)
Q(A2Ý11)
Q(A3)
Q(A2Ý01) Q(A3Ý01) Q(A3Ý10)
Q(A3Ý11)
Q(A1)
(flow-through mode)
t
HZC
t
OE
t
LZOE
®
AS7C33128PFS16B
AS7C33128PFS18B
10/29/03; v.1.0 Alliance Semiconductor P. 9 of 14
Timing waveform of write cycle
Note: Ý = XOR when
LBO
= HIGH/No Connect; Ý = ADD when
LBO
= LOW.
t
CYC
t
CL
t
ADSPS
t
ADSPH
t
ADSCS
t
ADSCH
t
AS
t
AH
t
WS
t
WH
t
CSS
t
ADVS
t
DS
t
DH
CLK
ADSP
ADSC
Address
BWE
CE0, CE2
ADV
OE
Data In
t
CSH
t
ADVH
D(A2Ý01) D(A2Ý10) D(A3)D(A2) D(A2Ý01) D(A3Ý01) D(A3Ý10)
D(A1) D(A2Ý11)
ADV SUSPENDS BURST
ADSC LOADS NEW ADDRESS
A1 A2 A3
t
CH
CE1
BWa,b
AS7C33128PFS16B
AS7C33128PFS18B
®
10/29/03; v.1.0 Alliance Semiconductor P. 10 of 14
Timing waveform of read/write cycle
Note: Ý = XOR when
LBO
= HIGH/No Connect; Ý = ADD when
LBO
= LOW.
t
CH
t
CYC
t
CL
t
ADSPS
t
ADSPH
t
AS
t
AH
t
WS
t
WH
t
ADVS
t
DS
t
DH
t
OH
CLK
ADSP
Address
GWE
CE0, CE2
ADV
OE
D
IN
D
OUT
t
LZC
t
ADVH
t
LZOE
t
OE
t
CD
Q(A1)
Q(A3Ý01)
D(A2)
Q(A3)
Q(A3Ý10) Q(A3Ý11)
A1 A2 A3
CE1
t
HZOE
(pipeline mode)
D
OUT
Q(A1)
Q(A3Ý01) Q(A3Ý10)
(flow-through mode)
t
CDF
Q(A3Ý11)
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AC test conditions
Z
0
= 50
Ω
D
OUT
50
Ω
Figure B: Output load (A)
30 pF*
Figure A: Input waveform
10%
90%
GND
90%
10%
+3.0V
• Output load: see Figure B, except for tLZC, tLZOE, tHZOE, tHZC, see Figure
C.
• Input pulse level: GND to 3V. See Figure A.
• Input rise and fall time (measured at 0.3V and 2.7V): 2 ns. See Figure A.
V
L
= 1.5V
for 3.3V I/O;
= V
DDQ
/2
for 2.5V I/O
353
Ω / 1538Ω
5 pF*
319
Ω / 1667Ω
D
OUT
GND
Figure C: Output load (B)
*including scope
and jig capacitan
c
Thevenin equivalent:
+3.3V for 3.3V I/O;
/+2.5V for 2.5V I/O
Notes
1 For test conditions, see AC Test Conditions, Figures A, B, C.
2 This parameter measured with output load condition in Figure C.
3 This parameter is sampled, but not 100% tested.
4t
HZOE is less than tLZOE; and tHZC is less than tLZC at any given temperature and voltage.
5 tCH measured as HIGH above VIH and tCL measured as LOW below VIL.
6 This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK. All other synchronous inputs
must meet the setup and hold times for all rising edges of CLK when chip is enabled.
7 Write refers to
GWE
,
BWE
,
BW[a,b].
8 Chip select refers to
CE0
,
CE1
,
CE2
AS7C33128PFS16B
AS7C33128PFS18B
®
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Package Dimensions
100-pin quad flat pack (TQFP)
TQFP
Min Max
A1 0.05 0.15
A2 1.35 1.45
b 0.22 0.38
c 0.09 0.20
D 13.90 14.10
E 19.90 20.10
e 0.65 nominal
Hd 15.85 16.15
He 21.80 22.20
L 0.45 0.75
L1 1.00 nominal
α0° 7°
Dimensions in millimeters
He E
Hd
D
b
e
A1 A2
L1
L
c
α
®
AS7C33128PFS16B
AS7C33128PFS18B
10/29/03; v.1.0 Alliance Semiconductor P. 13 of 14
1. Alliance Semiconductor SRAM Prefix
2.Operating voltage: 33=3.3V
3.Organization: 128=128K
4.Pipeline-Flowthrough (each device works in both modes)
5.Deselect: S=Single cycle deselect
6.Organization: 16=x16; 18=x18
7.Production version: B= product revision
8.Clock speed (MHz)
9.Package type: TQ=TQFP
10.Operating temperature: C=Commercial (
0° C to 70° C); I=Industrial (
-40
° C to 85° C)
Ordering information
Package Width –200 MHz –166 MHz –133 MHz
TQFP x16 AS7C33128PFS16B-200TQC AS7C33128PFS16B-166TQC AS7C33128PFS16B-133TQC
TQFP x16 AS7C33128PFS16B-200TQI AS7C33128PFS16B-166TQI AS7C33128PFS16B-133TQI
TQFP x18 AS7C33128PFS18B-200TQC AS7C33128PFS18B-166TQC AS7C33128PFS18B-133TQC
TQFP x18 AS7C33128PFS18B-200TQI AS7C33128PFS18B-166TQI AS7C33128PFS18B-133TQI
Part numbering guide
AS7C 33 128 PF S16/18 B–XXX TQ C/I
12345678910
AS7C33128PFS16B
AS7C33128PFS18B
®
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Part Number: AS7C33128PFS16B-18B
Document Version: v.1.0
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