DATA SHEET O K I A S I C P R O D U C T S MSM12R/13R/98R 0.5 mm Mixed 3-V/5-V Sea of Gates and Customer Structured Arrays July 2001 ------------------------------------------------------------------------------------------- CONTENTS Description ................................................................................................................................................................1 Features .....................................................................................................................................................................1 MSM12R/13R/98R Family Listing .......................................................................................................................2 Array Architecture ...................................................................................................................................................3 MSM98R000 CSA Layout Methodology ........................................................................................................3 Electrical Characteristics .........................................................................................................................................5 Macro Library .........................................................................................................................................................10 Macrocells for Driving Clock Trees ..............................................................................................................11 Oki Advanced Design Center CAD Tools ..........................................................................................................12 Design Process .................................................................................................................................................13 Automatic Test Pattern Generation ..............................................................................................................14 Floorplanning Design Flow ...........................................................................................................................14 IEEE JTAG Boundary Scan Support .............................................................................................................15 Package Options ....................................................................................................................................................16 Oki Semiconductor MSM12R/13R/98R 0.5m Mixed 3-V/5-V Sea of Gates and Customer Structured Arrays DESCRIPTION OKI's 0.5m ASIC products, specially designed for mixed 3-V/5-V applications, are now available in both Sea Of Gates (SOG) and Customer Structured Array (CSA) architectures. Both the SOG-based MSM13R Series and the CSA-based MSM98R Series use a three-layer-metal process on 0.5m drawn (0.4m L-effective) CMOS technology. The MSM12R SOG series uses two-layer metal process. The semiconductor process is adapted from OKI's production-proven 16-Mbit DRAM manufacturing process. The MSM12R/13R and MSM98R series feature high speed, low power, and high density logic with either a 5-V or 3-V interface. The MSM12R/13R and MSM98R Series employ a 3-V core and flexible I/O architecture to support both 3-V and 5-V voltage levels. The MSM12R SOG series is available in 5 sizes with up to 240 I/O pads and over 40k usable gates. The MSM13R SOG Series is available in 10 sizes with up to 624 I/O pads and over 464k gates. The SOG array sizes are designed to fit the most popular quad flat pack (QFP) packages, such as 100-, 144-, 176-, 208-, 240-, and 304-pin QFPs. MSM12R/13R SOG-based designs are therefore ideal for pad-limited circuits that require rapid prototyping turnaround times. The MSM98R CSA Series is an all-mask-level superset of the SOG series, available in 36 sizes. The CSA offerings combine the SOG architecture's logic flexibility with the higher integration yielded by optimized diffusion for faster and more compact memory blocks. The MSM98R is ideal for core-limited applications or circuits with large and/or multiple memory functions. Customer modification to the structure of any of the 36 predefined masterslices, rather than creation of a new masterslice every time, improves the prototyping turnaround time over cell-based manufacturing techniques. Each product family is supported by OKI's proprietary MEMGEN tool which quickly and easily generates SOG memories (for the MSM12R/13R) as well as optimized memories for the MSM98R Series. The families also feature floorplanning to control pre-layout timing, clock-skew management software that guarantees worst-case clock skew of 0.5 ns or less, and scan-path design techniques that support ATPG for fault coverage approaching 100%. FEATURES * * * * 0.5m drawn two- and three-layer metal CMOS Optimized 3.3-V core with 3-V or 5-V interface SOG and CSA architecture availability 110-ps typical gate propagation delay (for a 2-input 4x-drive NAND gate, operating at 3.3 V, with a fanout of 2 and 0 mm of wire) * Up to 464K usable gates and 624 pads * User-configurable I/O with VSS, VDD, CMOS, TTL, 3-state, and 2 mA ~ 24 mA options * Slew-rate-controlled outputs for low-radiated noise * Clock tree cells with 0.5-ns clock skew, worst-case (fan-out 9000 at 75 MHz) * User-configurable single and dual-port memories * Specialized 3-V and 5-V macrocells, including phaselocked loop, PCI, and USB cells * Floorplanning for front-end simulation, back-end layout controls, and links to synthesis * JTAG boundary scan and scan-path ATPG * Support for popular CAE systems including Cadence, Exemplar, Model Technology, Inc. (MTI), Zycad, and Synopsys Oki Semiconductor 1 ------------------------------------------------------------------------------------------- MSM12R/13R/98R FAMILY LISTING CSA Part# CSA Master# SOG Part# I/O Pads Rows [1] Columns MSM98R020X020 B98RB01 -- 80 58 164 9,512 7,610 MSM98R024X024 B98RB02 -- 96 72 204 14,688 11,750 Raw Gates Usable Gates [2] -- -- MSM12R0170 104 78 224 17,472 8,387 MSM98R026X026 B98RB03 MSM13R0170 104 78 224 17,472 13,978 MSM98R030X030 B98RB04 -- 120 92 264 24,288 19,430 MSM98R032X032 B98RB05 -- 128 99 280 27,720 22,176 -- -- MSM12R0350 144 112 320 35,840 17,203 MSM98R036X036 B98RB06 MSM13R0350 144 112 320 35,840 26,880 MSM98R038X038 B98RB07 -- 152 119 340 40,460 30,345 MSM98R040X040 B98RB08 -- 160 126 360 45,360 34,020 MSM98R042X042 B98RB09 -- 168 133 380 50,540 37,905 -- -- MSM12R0560 176 140 400 56,000 25,200 MSM98R044X044 B98RB10 MSM13R0560 176 140 400 56,000 39,200 MSM98R048X048 B98RB11 -- 192 153 436 66,708 46,696 MSM98R050X050 B98RB12 -- 200 160 456 72,960 51,072 -- -- MSM12R0790 208 167 476 79,492 31,797 MSM98R052X052 B98RB13 MSM13R0790 208 167 476 79,492 55,644 MSM98R056X056 B98RB14 -- 224 180 516 92,880 65,016 -- -- MSM12R1070 240 194 552 107,088 40,693 MSM98R060X060 B98RB15 MSM13R1070 240 194 552 107,088 74,962 MSM98R064X064 B98RB16 -- 256 208 592 123,136 81,270 MSM98R068X068 B98RB17 -- 272 221 632 139,672 92,184 MSM98R072X072 B98RB18 -- 288 235 672 157,920 104,227 MSM98R076X076 B98RB19 MSM13R1750 304 248 708 175,584 115,885 MSM98R080X080 B98RB20 -- 320 262 748 195,976 125,425 MSM98R084X084 B98RB21 -- 336 276 788 217,488 139,192 MSM98R088X088 B98RB22 -- 352 289 824 238,136 152,407 MSM98R092X092 B98RB23 -- 368 303 864 261,792 167,547 MSM98R096X096 B98RB24 MSM13R2850 384 316 904 285,664 177,112 MSM98R100X100 B98RB25 -- 400 330 944 311,520 193,142 MSM98R104X104 B98RB26 -- 416 344 980 337,120 209,014 MSM98R108X108 B98RB27 -- 432 357 1,020 364,140 225,767 MSM98R112X112 B98RB28 MSM13R3930 448 371 1,060 393,260 235,956 MSM98R118X118 B98RB29 -- 472 391 1,116 436,356 261,814 MSM98R122X122 B98RB30 -- 488 405 1,156 468,180 280,908 MSM98R126X126 B98RB31 MSM13R4990 504 418 1,196 499,928 299,957 MSM98R132X132 B98RB32 -- 528 439 1,252 549,628 329,777 MSM98R138X138 B98RB33 -- 552 459 1,312 602,208 361,325 MSM98R144X144 B98RB34 -- 576 480 1,368 656,640 393,984 MSM98R150X150 B98RB35 -- 600 500 1,428 714,000 428,400 MSM98R156X156 B98RB36 -- 624 520 1,488 773,760 464,256 1. Row and column numbers are used to evaluate the number and size of mega macrocells that may be included into each array. For example, a 7,600-gate mega macrocell with a size and aspect ratio of 36 rows by 245 columns can be used on the MSM98R030x030 or any larger array base, but not on the MSM98R026x026. 2. Usable gate count is design dependent and varies based upon the number of fan-outs per net, internal busses, floor plan, RAM/ROM blocks, etc. 2 Oki Semiconductor ------------------------------------------------------------------------------------------ ARRAY ARCHITECTURE The primary components of a 0.5m MSM12R/13R/98R circuit include: * * * * * * * I/O base cells Configurable I/O pads for VDD, VSS, or I/O (I/O in both 3V and 5V) VDD and VSS pads dedicated to wafer probing Separate power bus for output buffers Separate power bus for internal core logic and input buffers Core base cells containing N-channel and P-channel pairs, arranged in column of gates Isolated gate structure for reduced input capacitance and increased routing flexibility Each array has 24 dedicated corner pads for power and ground use during wafer probing, with four pads per corner. The arrays also have separate power rings for the internal core functions (VDDC and VSSC) and output drive transistors (VDDO and VSSO). I/O cells include level shifter Separate power bus for internal core logic Column of Gates Configurable I/O pads for VDD (3.3 V), VDD (5 V), VSS, I/O (3.3 V), or I/O (5 V) Core Area VDD = 3.3V Four-transistor basic core cell (same dimensions as MSM10R) VDD, VSS pads in each corner for wafer probing only VDDO (3.3 V) VDDO (5 V) VSSO Separate power bus over I/O cell for output buffers (VDDO (3.3 V), VDDO (5 V), VSSO) Figure 7. MSM13R0000 Array Architecture MSM98R000 CSA Layout Methodology The procedure to design, place, and route a CSA follows. 1. Select suitable base array frame from the available predefined sizes. To select an array size: - Identify the macrocell functions required and the minimum array size to hold the macrocell functions. Oki Semiconductor 3 ------------------------------------------------------------------------------------------- - Add together all the area occupied by the required random logic and macrocells and select the optimum array. 2. Make a floor plan for the design's megacells. - OKI Design Center engineers verify the master slice and review simulation. - OKI Design Center engineers floorplan the array using OKI's proprietary floorplanner and customer performance specifications. - Using OKI CAD software, Design Center engineers remove the SOG transistors and replace them with diffused memory macrocells to the customer's specifications. Figure 8 shows an array base after placement of the optimized memory macrocells. Early mask high-density ROM Mega macrocell High-density RAM Multi-port RAM Figure 8. Optimized Memory Macrocell Floor Plan 3. Place and route logic into the array transistors. - OKI Design Center engineers use layout software and customer performance specifications to connect the random logic and optimized memory macrocells. Figure 9 marks the area in which placement and routing is performed with light shading. Figure 9. Random Logic Place and Route 4 Oki Semiconductor ------------------------------------------------------------------------------------------ ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (VSS = 0 V, Tj = 25 C) [1] Parameter Symbol Power supply voltage Conditions Rated Value VDD (3.3 V) -0.3 ~ +4.6 VDD (5 V) -0.5 ~ +6.5 V - Input voltage VI Output voltage VO -0.3 ~ VDD+0.3 II -10 ~ +10 Input current Output current per I/O [2] IO (3.3 V) IO (5 V) Storage temperature Tstg Unit -0.3 ~ VDD+0.3 IO = 1, 2, 4, 6, 8, 12 mA -25 ~ +25 IO = 2, 4, 8, 12 mA -25 ~ +25 V mA mA IO = 16, 24 mA -50 ~ + 50 IO = 48 mA -100 ~ +100 - -65 ~ +150 mA C 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions in the other specifications of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. One I/O cell can be configured for maximum, 24 mA buffer. Oki Semiconductor 5 ------------------------------------------------------------------------------------------- Recommended Operating Conditions (VSS = 0 V) Parameter Power supply voltage Symbol Rated Value VDD (3 V) +3.0 ~ +3.6 VDD (5 V) +4.5 ~ +5.5 Tj -40 ~ +85 Junction temperature Unit V C DC Characteristics (VDD = 2.7 V ~ 3.3 V, VSS = 0 V, Tj = -40 C ~ +85 C) Rated Value Parameter High-level input voltage Low-level input voltage TTL- level Schmitt Trigger input threshold voltage Conditions Min Typ VIH TTL input 1.8 - VDD+0.3 VIH CMOS input 0.7*VDD - VDD+0.3 TTL input -0.3 - -0.6 VIL CMOS input -0.3 - 0.3*VDD - 1.4 1.8 0.6 1 - 0.1 0.4 - Vt+ Vt+ - Vt- Vt+ Vt 1 - VDD-0.2 - - IOH = -1, -2, -4, -6, -8, -12 mA 2.2 - - IOL = 100 A - - 0.2 [2] IDDQ - - 0.4 IOL = 12 mA - - 0.5 VIH = VDD - 0.01 1 VIH = VDD (75 k pull-down) 10 45 160 VIL = VSS -1 -0.01 - VIL = VSS (75 k pull-up) -160 -45 -10 VIL = VSS (4.5 k pull-up) -2.66 -0.73 -0.16 VOH = VDD - 0.01 10 VOH = VDD (75 k pull-down) 10 45 160 VOL = VSS -1 -0.01 - VOL = VSS (75 k pull-up) -160 -45 -10 VOL = VSS (4.5 k pull-up) -2.66 -0.73 -0.16 Output open VIH = VDD, VIL = VSS 1. Typical condition is 3.3 V and Tj = 25 oC on a typical process. 2. RAM/ROM should be in power-down mode. 6 Oki Semiconductor V V V IOL = 1, 2, 4, 6, 8 mA 3-state output leakage current IOZL - 0.1*VDD Low-level input current IOZH 0.76*VDD 0.8 Vt+ - Vt- High-level input current IIL 1.8 IOH = -100 A Low-level output voltage IIH - 0.24*VDD CMOS input Vt- VOL V TTL input Vt- VOH Unit V High- level output voltage Stand-by current Max VIL Vt CMOS-level Schmitt Trigger input threshold voltage [1] Symbol Design dependent V A A mA A A mA A ------------------------------------------------------------------------------------------ DC Characteristics (VDD = 3.0 V ~ 3.6 V, VSS = 0 V, Tj = -40 C ~ +85 C) Rated Value [1] Parameter Symbol High- level input voltage VIH Low- level input voltage VIL TTL-level Schmitt Trigger input threshold voltage Vt+ Typ TTL input 2.0 - VDD+0.3 CMOS input 0.7*VDD - VDD+0.3 TTL input -0.3 - 0.8 -0.3 - 0.3*VDD - 1.6 2.0 0.8 1.2 - Vt+ - Vt- IDDQ 1 - 0.1*VDD 1 - - - - - IOL = 100 A - - 0.2 IOL = 1, 2, 4, 6, 8 mA - - 0.4 V 0.5 - - VIH = VDD - 0.01 1 VIH = VDD (75 k pull-down) 10 45 160 VIL = VSS -1 -0.01 - VIL = VSS (75 k pull-up) -160 -45 -10 VIL = VSS (4.5 k pull-up) -2.66 -0.73 -0.16 VOH = VDD - 0.01 10 VOH = VDD (75 k pull-down) 10 45 160 VOL = VSS -1 -0.01 - VOL = VSS (75 k pull-up) -160 -45 -10 VOL = VSS (4.5 k pull-up) -2.66 -0.73 -0.16 Output open VIH = VDD, VIL = VSS V V V IOL = 12 mA 3-state output leakage current [3] 0.24*VDD Vt+ - Vt- 2.4 Low-level input current IOZL 0.76*VDD VDD-0.2 High-level input current IOZH - 2.0 IOH = -100 A Low-level output voltage IIL 0.4 - IOH = -1, -2, -4, -6, -8, -12 mA High-level output voltage IIH 0.1 CMOS input Vt- VOL Unit TTL input Vt+ VOH Max CMOS input Vt- Vt Stand-by current Min V Vt CMOS-level Schmitt Trigger input threshold voltage [2] Condition Design dependent V A A mA A A mA A 1. JEDEC compatible; JESD8-1A LVTTL. 2. Typical condition is 3.3 V and Tj = 25 C for a typical process. 3. RAM/ROM should be in power-down mode. Oki Semiconductor 7 ------------------------------------------------------------------------------------------- DC Characteristics (I/O VDD = 4.5 V ~ 5.5 V, Core VDD = 3.3 V, VSS = 0 V, Tj = -40 C ~ +85 C) Rated Value Parameter Symbol High-level input voltage VIH Low-level input voltage VIL TTL-level Schmitt Trigger input threshold voltage Min Typ TTL input 2.2 - VDD+0.5 Vt+ CMOS input 0.7*VDD - VDD+0.5 TTL input -0.5 - 0.8 CMOS input -0.5 - 0.3*VDD - 1.7 2.2 0.8 1.4 - Vt+ - Vt- Vt+ Vt 0.24*VDD 1.7 - Vt+ - Vt- 0.4 1.4 - - - 3.7 - - IOL = 100 A - - 0.2 IOL = 2, 4, 8, 12, 16 mA - - 0.4 0.5 IOL = 24, 48 mA - - 0.01 10 VIH = VDD (50 k pull-down) 20 100 250 VIL = VSS -10 -0.01 - VIL = VSS (50 k pull-up) -250 -100 -20 VIL = VSS (3 k pull-up) -5 -1.6 -0.5 VOH = VDD - 0.01 10 VOH = VDD (50 k pull-down) 20 100 250 VOL = VSS -10 -0.01 - VOL = VSS (50 k pull-up) -250 -100 -20 VOL = VSS (3 k pull-up) -5 -1.6 -0.5 [3] IDDQ 1. Typical condition is 5 V and Tj = 25o C for a typical process. 2. 48 mA is only available for open-drain outputs. 3. RAM/ROM should be in power-down mode. 8 Oki Semiconductor [2] - 3-state output leakage current Stand-by current V Output open VIH = VDD, VIL = VSS V V V VIH = VDD High-level input current IOZL 0.76*VDD VDD-0.2 High-level input current IOZH - 3.1 IOH = -100 A Low-level output voltage IIL 0.3 - IOH = -2, -4, -8, -12, -16, -24 mA High-level output voltage IIH 0.2 CMOS input Vt- VOL Unit TTL input Vt- VOH Max V Vt CMOS-level Schmitt Trigger input threshold voltage [1] Condition Design dependent V A A mA A A mA A ------------------------------------------------------------------------------------------ AC Characteristics (I/O VDD = 3.3 V, Core VDD = 3.3 V, VSS = 0 V, Tj = 25 C) Parameter Driving Type Internal gate propagation delay 1. 2. 3. 4. Rated Value Inverter 2-input NAND 1x 2x 4x 2-input NOR 1x 2x 4x 0.18 0.15 0.16 Inverter 1x 2x 4x 0.33 0.24 0.15 2-input NAND 1x 2x 4x 2-input NOR 1x 2x 4x [3] Unit 0.11 0.09 0.07 0.16 0.12 0.11 Fan-out = 2, L = 0 mm, VDD = 3.3V Fan-out = 2, L = 2 mm, VDD = 3.3 V ns 0.43 0.26 0.17 ns 0.53 0.36 0.30 Fan-out = 1, L = 0 mm 720 MHz TTL level input buffer Fan-out = 2, L = 2 mm 0.39 ns CMOS level input buffer Fan-out = 2, L = 2 mm 0.24 ns Push-pull 4 mA 8 mA 12 mA CL = 20 pF CL = 50 pF CL = 100 pF 1.41 1.82 2.81 ns Push-pull 12 mA CL = 75 pF 3.00 (r) 1.78 (f) ns Output buffer propagation delay Output buffer transition times [1] [2] 1x 2x 4x Toggle frequency Input buffer propagation delay Conditions [4] Input transition time is 0.2 ns / 3.3 V. Typical condition is VDD = 3.3 V and Tj = 25 C. Rated value is calculated as an average of the L-H and H-L delay times of each macro type on a typical process. Output rising and falling times are both specified over a 20%-80% range. AC Characteristics (I/O VDD = 5 V, Core VDD = 3.3 V, VSS = 0 V, Tj = 25 C) Parameter Input buffer propagation delay [3] Output buffer propagation delay Output buffer transition times [4] 1. 2. 3. 4. 5. Driving Type Conditions [1] Rated Value [2] Uni t TTL level input buffer Fan-out= 2, L= 2 mm 0.42 ns CMOS level input buffer Fan-out= 2, L= 2 mm 0.38 ns Push-pull 4 mA 8 mA 16 mA 24 mA CL = 20 pF CL = 50 pF CL = 100 pF CL = 150 pF 2.22 2.73 2.77 3.39 ns Push-pull 24 mA CL = 150 pF 4.08 (r) 2.48 (f) ns [4] [5] Typical condition is VDD = 5 V and Tj = 25 C. Rated value is calculated as an average of the LH and HL delay times of each macro type; typical process. Input transition time is 0.18 ns / 3 V for TTL input buffers and 0.3 ns / 5 V for CMOS input buffers. Input transition time is 0.2 ns / 3.3 V for output buffers. Output rising and falling times are both specified over a 20%-80% range. Oki Semiconductor 9 ------------------------------------------------------------------------------------------- MACRO LIBRARY Oki Semiconductor supports a wide range of macrocells and macrofunctions, ranging from simple hard macrocells for basic Boolean operations to large, user-parameterizable macrofunctions. The following figure illustrates the main classes of macrocells and macrofunctions available. Examples Basic Macrocells NANDs NORs Basic Macrocells with Scan test Flip-Flops EXORs Latches Flip-Flops Combinational Logic Clock Tree Driver Macrocells Macrocells Mixed 3V/5V Output Macrocells MSI Macrocells Mega/Special Macrocells [1] 3-State Outputs Push-Pull Outputs Open Drain Outputs Slew Rate Control Outputs PCI Outputs Counters Shift Registers UART PLL 82C37 82C54 82C59 PCI Controller Ethernet Controller Macro Library Mixed 3V/5V Input Macrofunctions Inputs Inputs with Pull-Downs Inputs with Pull-Ups GTL Inputs Mixed 3V/5V Bi-Directional Macrofunctions I/O PCI I/O I/O with Pull-Downs I/O with Pull-Ups MSI Macrofunctions 74199 74163 74151 Oscillator Macrofunctions Gated Oscillators Memory Macrocells SOG RAMs: Single-Port RAMs Dual-Port RAMs Macrofunctions Optimized Diffused RAMs: Single-Port RAMs Dual-Port RAMs [1] Under development Figure 10. Oki Macrocell and Macrofunction Library 10 Oki Semiconductor ------------------------------------------------------------------------------------------ Macrocells for Driving Clock Trees Oki offers clock-tree drivers that guarantee a skew time of less than 0.5 ns. The advanced layout software uses dynamic driver placement and sub-trunk allocation to optimize the clock-tree implementation for a particular circuit. Features of the clock-tree driver-macrocells include: * * * * * * * * Clock skew 0.5 ns Automatic fan-out balancing Dynamic sub-trunk allocation Single clock tree driver logic symbol Single-level clock drivers Automatic branch length minimization Dynamic driver placement Up to four clock trunks The clock-skew management scheme is described in detail in Oki's 0.5m Technology Clock Skew Management Application Note. Main Trunk Clocked Cell Sub Trunk Branch Clock Drivers Pad Input Buffer Clock Tree Driver Macrocell Figure 11. Clock Tree Structure Oki Semiconductor 11 ------------------------------------------------------------------------------------------- OKI ADVANCED DESIGN CENTER CAD TOOLS Oki's advanced design center CAD tools include support for the following: * * * * Floorplanning for front-end simulation and back-end layout control Clock tree structures improve first-time silicon success by eliminating clock skew problems JTAG Boundary scan support Power calculation which predicts circuit power under simulation conditions to accurately model package requirements Design Kits Vendor Platform (R) [2] Operating System [1] Vendor Software/Revision [1] Description Solaris Ambit Buildgates NC-VerilogTM Verilog XL VerifaultTM Design Synthesis Design Simulation Design Simulation Fault Simulation Cadence Sun Synopsys Sun [2] Solaris Design Compiler Ultra + Tetramax/ATPG Primetime DFT Compiler/Test Compiler RTL Analyzer VCS Design synthesis ATPG Static Timing Analysis (STA) Test synthesis RTL check Design Simulation Model Technology Inc. (MTI) Sun [2] NT Solaris WinNT4.0 MTI-VHDL MTI-Verilog Design Simulation Design Simulation Exemplar Sun [2] NT Solaris WinNT4.0 Leonardo Spectrum Design Synthesis Oki Sun [2] Solaris Floorplanner Floor planning Verplex Sun [2] Solaris Tuxedo Formal verification Zycad Sun [2] Solaris XPLUS Fault Simulation 1. Contact Oki Application Engineering for current software versions. 2. Sun or Sun-compatible. 12 Oki Semiconductor ------------------------------------------------------------------------------------------ Design Process The following figure illustrates the overall IC design process, also indicating the three main interface points between external design houses and Oki ASIC Application Engineering. Level 1 [4] VHDL/HDL Description Synopsys Timing Script (optional) Functional Test Vectors Synthesis CAE Front-End Floorplanning Gate-Level Simulation Level 2 Netlist Conversion (EDIF 200) Test Vector Conversion (Oki TPL [3]) Scan Insertion (Optional) TDC [2] CDC [1] Formal Verification Floorplanning Pre-Layout Simulation Level 2.5 [4] Layout / Timing Driven Layout (optional) [6] Static Timing Analysis Fault Simulation [5] Oki Interface Automatic Test Pattern Generation Verification (Design Rule Check/Formal Verification) Post-Layout Simulation Level 3 [4] Manufacturing Prototype Test Program Conversion [1] Oki's Circuit Data Check program (CDC) verifies logic design rules [2] Oki's Test Data Check program (TDC) verifies test vector rules [3] Oki's Test Pattern Language (TPL) [4] Alternate Customer-Oki design interfaces available in addition to standard level 2 [5] Standard design process includes fault simulation [6] Requires Synopsys timing script for Oki timing driven layout Figure 12. Oki's Design Process Oki Semiconductor 13 ------------------------------------------------------------------------------------------- Automatic Test Pattern Generation Oki's 0.5m ASIC technologies support Automatic Test Pattern Generation (ATPG) using full scan-path design techniques, including the following: * * * * * * * * * Increases fault coverage 95% Uses Synopsys Test Compiler Automatically inserts scan structures Connects scan chains Traces and reports scan chains Checks for rule violations Generates complete fault reports Allows multiple scan chains Supports vector compaction ATPG methodology is described in detail in Oki's 0.5m Scan Path Application Note. Combinational Logic A FD1AS Scan Data In D C SD SS B FD1AS Q QN D C SD SS Q Scan Data Out QN Scan Select Figure 13. Full Scan Path Configuration Floorplanning Design Flow Oki's floorplanner can be classified as both a front-end floorplanner and a back-end floorplanner. During front-end floorplanning, logic designers use the floorplanner to generate two files: a capacitance file for pre-layout simulation, and a floorplanner interface file for layout. During back-end floorplanning, the layout engineer transfers the floorplanner interface file to Oki's proprietary layout software, code-named Pegasus. The floorplanner interface file contains information about the placement of blocks and groups of blocks. The back-end floorplanner is automated and is transparent to logic designers. Figure 14 shows a diagram of front-end floorplanning. Figure 15 shows a diagram of back-end floorplanning. 14 Oki Semiconductor ------------------------------------------------------------------------------------------ Floorplanner Set Design EDIF EDIF Netlist rcEst Simulation Interface File Pre-Floor Plan Floorplan PLT Pinlist File FPI Floorplanner Interface File Figure 14. Front-End Floorplanning Pegasus Pre-Layout EDIF EDIF Netlist FPI Floorplanner Interface File GCD Layout FIF Layout Interface File Figure 15. Back-End Floorplanning IEEE JTAG Boundary Scan Support Boundary scan offers efficient board-level and chip-level testing capabilities. Benefits resulting from incorporating boundary-scan logic into a design include: * * * * * * Improved chip-level and board-level testing and failure diagnostic capabilities Support for testing of components with limited probe access Easy-to-maintain testability and system self-test capability with on-board software Capability to fully isolate and test components on the scan path Built-in test logic that can be activated and monitored An optional Boundary Scan Identification (ID) Register Oki's boundary scan methodology meets the JTAG Boundary Scan standard, IEEE 1149.1-1990. Oki supports boundary scan on both Sea of Gates (SOG) and Customer Structured Array (CSA) ASIC technologies. Either the customer or Oki can perform boundary-scan insertion. More information is available in Oki's JTAG Boundary Scan Application Note. Contact the Oki Application Engineering Department for interface options. Oki Semiconductor 15 ------------------------------------------------------------------------------------------- PACKAGE OPTIONS MSM12R/13R/98R Package Menu Prod Name I/O QFP TQFP TQFP PBGA MSM98R Pads [1] 44 64 80 100 128 160 208 240 304 44 64 80 100 128 144 176 208 256 352 420 MSM98RB0 80 MSM98RB0 96 MSM12R0170 104 MSM13R0170 MSM98RB0 104 MSM98RB0 120 MSM98RB0 128 MSM12R0350 144 MSM13R0350 MSM98RB0 144 MSM98RB0 152 MSM98RB0 160 MSM98RB0 168 MSM12R0560 176 MSM13R0560 MSM98RB1 176 MSM98RB1 192 MSM98RB1 200 MSM12R0790 208 MSM13R0790 MSM98RB1 208 MSM98RB1 224 MSM12R1070 240 MSM13R1070 MSM98RB1 240 MSM98RB1 256 MSM98RB1 272 MSM98RB1 288 MSM13R1750 MSM98RB1 304 MSM98RB2 320 MSM98RB2 336 MSM98RB2 352 MSM98RB2 368 MSM13R2850 MSM98RB2 384 MSM98RB2 400 MSM98RB2 416 MSM98RB2 432 MSM13R3930 MSM98RB2 448 MSM98RB2 472 MSM98RB3 488 MSM13R4990 MSM98RB3 504 MSM98RB3 528 MSM98RB3 552 MSM98RB3 576 MSM98RB3 600 MSM98RB3 624 Body Size (mm) 9x10 14x14 14x20 14x20 28x28 28x28 28x28 32x32 40x40 10x10 10x10 12x12 14x14 14x14 20x20 24x24 28x28 27x27 35x35 35x35 Lead Pitch (mm) 0.8 0.8 0.8 0.65 0.8 0.65 0.5 0.5 0.5 0.8 0.5 0.5 0.5 0.5 0.5 0.5 0.5 1.27 1.27 1.27 Ball Count 256 352 420 Signal I/O 231 304 352 Power Balls 12 16 32 Ground Balls 13 32 36 SOG Base 1. I/O Pads can be used for input, output, bi-directional, power, or ground. l = Available now; m = In development 16 Oki Semiconductor The information contained herein can change without notice owing to product and/or technical improvements. Please make sure before using the product that the information you are referring to is up-to-date. The outline of action and examples of application circuits described herein have been chosen as an explanation of the standard action and performance of the product. When you actually plan to use the product, please ensure that the outside conditions are reflected in the actual circuit and assembly designs. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters outside the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right,etc.is granted by us in connection with the use of product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges, including but not limited to operating voltage, power dissipation, and operating temperature. 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