GA100SICP12-227 - GeneSiC Semiconductor

GA100SICP12-227

Dec 2015 Latest version of this datasheet at: http://www.genesicsemi.com/commercial-sic/sic-modules-copack/ Pg 1 of 13

Silicon Carbide Junction

Transistor/Schot tk y Diode C o-pack

Features

Package

• 175 °C Maximum Operating Temperature

• Gate Oxide Free SiC Switch

• Optional Gate Return Pin

• Exceptional Safe Operating Area

• Integrated SiC Schottky Rectifier

• Excellent Gain Linearity

• Temperature Independent Switching Performance

• Low Output Capacitance

• Positive Temperature Coefficient of RDS,ON

• Suitable for Connecting an Anti-parallel Diode

• RoHS Compliant

Isolated Baseplate

SOT-227

Advantages

Applications

• Compatible with Si MOSFET/IGBT Gate Drive ICs

• > 20 µs Short-Circuit Withstand Capability

• Lowest-in-class Conduction Losses

• High Circuit Efficiency

• Minimal Input Signal Distortion

• High Amplifier Bandwidth

• Reduced cooling requirements

•

Reduced system size

• Down Hole Oil Drilling, Geothermal Instrumentation

• Hybrid Electric Vehicles (HEV)

• Solar Inverters

• Switched-Mode Power Supply (SMPS)

• Power Factor Correction (PFC)

• Induction Heating

• Uninterruptible Power Supply (UPS)

•

Motor Drives

Table of Conte nts

Section I: Absolute Maximum Ratings .......................................................................................................... 1

Section II: Static Electrical Characteristics ................................................................................................... 2

Section III: D ynamic Electrical Characteristics ............................................................................................ 2

Section IV: Figures .......................................................................................................................................... 4

Section V: Driving the GA100SICP12-227 ..................................................................................................... 8

Section VI: Packag e Di mensions ................................................................................................................. 12

Section VII: SPICE Model Parameters ......................................................................................................... 14

Section I: Absolute Maximum Ratings

Parameter Symbol Conditions Value Unit Notes

SiC Junction Transistor

Drain – Source Voltage

VDS

= 0 V

1200

Continuous Drain Current I

TC = 25°C 160 A Fig. 17

Continuous Drain Current

TC = 115°C

100

Fig. 17

Continuous Gate Current

Continuous Gate Return Current

IGR

Turn-Off Safe Operating Area RBSOA TVJ = 175

Clamped Inductive Load

D,max

= 100

@ VDS ≤ VDSmax

A Fig. 19

Short Circuit Safe Operating Area SCSOA

= 175 oC, I

= 1 A, V

= 800 V,

Non Repetitive

>20 µs

Reverse Gate – Source Voltage

Reverse Drain – Source Voltage

Power Dissipation Ptot TC = 25 °C / 115 °C, tp > 100 ms 535 / 214 W Fig. 16

Operating and storage temperature Tstg -55 to 175 °C

VDS = 1200 V

RDS(ON) = 10 mΩ

ID (@ 25°C) = 160 A

ID (@ 115°C) = 100 A

hFE (@ 25°C) = 85

Please note: The Source and Gate Return

pins are not exchangeable. Their exchange

might lead to malfunction.

Pin D - Drain

Pin S - Source

Pin GR - Gate Return

Pin G - Gate

GA100SICP12-227

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Parameter Symbol Conditions Value Unit Notes

Free-Wheeling SiC Diode

Repetitive peak reverse voltage

RRM

1200

Continuous forward current

IF TC

≤ 135 °C 100 A

RMS forward current

IF(RMS)

≤ 135 °C

174

Surge non-repetitive forward current,

Half Sine Wave

IF,SM TC = 25 °C, tP = 10 ms

= 135 °C, tP = 10 ms

700

626

Non-repetitive peak forward current

IF,max

= 25 °C, t

= 10 µs

3250

I2t value ∫i2 dt TC = 25 °C, tP = 10 ms

= 135 °C, tP = 10 ms

900

600

A2s

Thermal Characteristics

Thermal resistance, junction - case RthJC SiC Junctio n Tra n sis tor 0.28 °C/W Fig. 20

Thermal resistance, junction - case

thJC

SiC Diode

0.26

°C/W

Fig. 21

Section II: Static Electrical Characteristics

A: On State

B: Off State

Section III: Dynamic Electrical Characteristics

A: Capacitance and Gate Charge

Parameter Symbol Conditions

Value

Unit Notes

Min.

Typical

Max.

Drain – Source On Resistance RDS(ON) ID = 100 A, Tj = 25 °C

ID = 100 A, Tj = 150 °C

ID = 100 A, Tj = 175 °C

mΩ Fig. 5

Gate – Source Saturation Voltage VGS,SAT ID = 100 A, ID/IG = 40, Tj = 25 °C

ID = 100 A, ID/IG = 30, Tj = 175 °C 3.42

3.23

V Fig. 7

DC Current Gain hFE VDS = 8 V, ID = 100 A, Tj = 25 °C

VDS = 8 V, ID = 100 A, Tj = 125 °C

VDS = 8 V, ID = 100 A, Tj = 175 °C

– Fig. 4

FWD forward voltage VF IF = 100 A, T j = 25 °C

IF = 100 A, Tj = 175 °C

1.4

2.1

1.8

3.0

Drain Leakage Current IDSS VDS = 1200 V, VGS = 0 V, T j = 25 °C

VDS = 1200 V, VGS = 0 V, Tj = 150 °C

VDS = 1200 V, VGS = 0 V, Tj = 175 °C

100

300

600

μA Fig. 8

Gate Leakage Current I

VSG = 20 V, Tj = 25 °C 40 nA

Parameter Symbol Conditions

Value

Unit Notes

Min.

Typical

Max.

Input Capacitance

iss

VGS = 0 V, VDS = 800 V, f = 1 MHz

16.1

Fig. 9

Reverse Transfer/Output Capacitance Crss/Coss VDS = 1 V, f = 1 M Hz

VDS = 400 V, f = 1 MH z

VDS = 800 V, f = 1 MHz

6480

570

440 pF Fig. 9

Total Output Capacitance Charge Qoss VDS = 400 V

VDS = 800 V

375

570 nC

Output Capacitance Stored Energy

EOSS

= 0 V, V

= 800 V, f = 1 MHz

170

µJ

Fig. 10

Effective Output Capacitance,

time related

Coss,tr ID = constant, VGS = 0 V, V DS = 0…800 V 715 pF

Effective Output Capacitance,

energy related

Coss,er VGS = 0 V, VDS = 0…800 V 535 pF

Gate-Source Charge

QGS

VGS = -5…3 V

130

Gate-Drain Charge

QGD

= 0 V, V

= 0…800 V

570

Gate Charge - Total QG 700 nC

GA100SICP12-227

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B: SJT Switching1

1 – All times are relative to the Drain-Source Voltage VDS

Parameter Symbol Conditions

Value

Unit Notes

Min.

Typical

Max.

Internal Gate Resistance – ON

RG(INT-ON)

VGS > 2.5 V, VDS = 0 V, Tj = 175 ºC

0.1

Turn On Delay Time td(on) Tj = 25 ºC, VDS = 800 V,

ID = 50 A, Resistive Load

Refer to Section V for additional

driving information.

Fall Time, V

Fig. 11, 13

Turn Off Delay Time

td(off)

Rise Time, VDS

Fig. 12, 14

Turn On Delay Time

td(on)

Tj = 175 ºC, VDS = 800 V,

ID = 50 A, Resistive Load

Fall Time, VDS

Fig. 11

Turn Off Delay Time

td(off)

Rise Time, V

Fig. 12

Turn-On Energy Per Pulse

Tj = 25 º C, VDS = 800 V,

ID = 50 A, Inductive Load

Refer to Section V.

1.8

Fig. 11, 13

Turn-Off Energy Per Pulse

Eoff

1.4

Fig. 12, 14

Total Switching Energy

Etot

3.2

Turn-On Energy Per Pulse

Eon

Tj = 175 ºC, VDS = 800 V,

ID = 50 A, Inductive Load

1.85

Fig. 11

Turn-Off Energy Per Pulse

Eoff

1.3

Fig. 12

Total Switching Energy E

tot

3.15 mJ

GA100SICP12-227

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Section IV: Figures

A: Static Characteristics

Figure 1: Typical Output Characteristics at 25 °C Figure 2: Typical Output Characteristics at 150 °C

Figure 3: Typical Output Characteristics at 175 °C Figure 4: DC Current Gain vs. Drain Current

Figure 5: On-Resistance vs. Gate Current Figure 6: Normalized On-Resistance vs. Tempe ratur e

GA100SICP12-227

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Figure 7: Typical Gate – Source Saturation Voltage Figure 8: Typical Blocking Characteristics

B: Dynamic Cha racteristi cs

Figure 9: Input, Output, and Reverse Transfer Capacitance Figure 10: Energy Stored in Output Capacitance

Figure 11: Typical Switching Times and Turn O n Energy

Losses vs. Temperature

Figure 12: Typical Switching Times and Turn O ff Energy

Losses vs. Temperature

GA100SICP12-227

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Figure 13: Typical Switching Times and Turn O n Energy

Losses vs. Drain Current

Figure 14: Typical Switching Times and Turn O ff Energy

Losses vs. Drain Current

C: Current and Power Derating

Figure 15: Typical Hard Switched Device Power Loss vs.

Switching Fr eq uen cy

Figure 16: Power Derating Curve

Figure 17: Drain Current Derating vs. Temperature Figure 18: Forward Bias Safe Operating Area at Tc= 25

2 – Representative values based on device conduction and switching loss. Actual losses will depend on gate drive conditions, device load, and circuit topology.

GA100SICP12-227

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Figure 19: Turn-Off Safe Operating Area

Figure 20: SJT Transient Thermal Impedance

Figure 21: FWD Transient Thermal Impedance Figure 22: Typical FWD Forward Characteristics

GA100SICP12-227

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Section V: Driving the GA100SICP12-227

Drive Topology Gate Drive Power

Consumption Switching

Frequency Application Emphasis Availability

TTL Logic

High

Low

Wide Temperature Range

Coming Soon

Constant Current Medium Medium Wide Temperature Range Coming Soon

High Speed – Boost Capacitor

Medium

High

Fast Switching

Production

High Speed – Boost Inductor

Low

High

Ultra Fast Switching

Coming Soon

Proportional

Lowest

High

Wide Drain Current Range

Coming Soon

Pulsed Power Medium N/A Pulse Power Coming Soon

A: Static TTL Logic Driving

The GA100SICP12-227 may be driven with direct (5 V) TTL logic and current amplification. The amplified current level of the supply must

meet or exceed the steady state gate current (IG,steady) required to operate the GA100SICP12-227. Minimum IG,steady is dependent on the

anticipated drain current ID through the SJT and the DC current gain hFE, it may be calculated from the following equation. An accurate value of

the hFE may be read from Fi gure 4. An optional re s is tor RG ma y be used i n series with the gate pi n t o trim IG,steady, also an optional c ap aci tor CG

may be added in parallel with RG to facilitate faster SJT switching if desired, further details on these options are given in the following section.

, 

(,)1.5

Figure 23: TTL Gate Dr ive Schematic

B: High Speed Driving

The SJT is a current controlled transi stor which requires a pos itive gate current for turn-on and to remain i n on-state. An ideal ized gate current

waveform for ultra-fast switching of the SJT while maintaini ng low gate drive losses is shown in Figure 24, it features a positive current peak

during turn-on, a negative current peak during turn-off, and continuous gate current during on-state.

Figure 24: An idealized gate current waveform for fast switching of an SJT.

An SJT is rapidly switched from its blocking state to on-state when the necessary gate charge, QG, for turn-on is supplied by a burst of high

gate current, IG,on, until the SJT gate-source capacitance, CGS, and gate-drain capacitance, CGD, are fully charged.

 =,  1

   +

TTL

Gate Signal

5 / 0 V

TTL i/p

5 V

G,steady

GA100SICP12-227

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Ideally, IG,on should terminate when the drain v oltage falls to its on-state value i n order to avoid unnecessary drive l osses during the steady on-

state. In practice, the rise time of the IG,on puls e is affected by the parasitic inductances, Lpar in the device package and drive circuit. A v oltage

developed across the parasiti c inductance in the source path, Ls, can de-bias the gate-source juncti on, when high drain currents begi n to flow

through the device. The voltage applied to the gate pin should be maintai ned high enough, above the VGS,sat (see Figure 7) level to counter

these effects.

A high negative peak current, -IG,off is recommend ed at the s tart of the turn -off t ransi tion, i n order to r apidl y sweep out the i njec ted carri ers from

the gate, and achieve rapid turn-off. Turn off can be achieved with VGS = 0 V, however a negative gate voltage V GS may be used in order to

speed up the turn-off transition.

Gate Return Pin

The optional gate return (GR) pin allows for a reduction of source path inductive and resistive coupling in the gate driver connection to the

GA100SICP12-227. Drain current s through the source pi n during transi ent and steady state operati on induce an undesi rable source voltage in

all power transistors due to unavoidable source pin inductance and resistance. This voltage can negatively affect gate driving performance,

however the gate return pin all ows for dec oupling f rom these sou rce current path effec ts which resul ts in faster s witching and higher ef fic iency

gate driving.

B:1: High Speed, Low Loss Drive with Boost Capacitor, GA15IDDJT22-FR4

The GA100SICP12-227 may be driven using a High Speed, Low Los s Drive with Boost Capacitor topology in which multiple voltage l evels, a

gate resistor, and a gate c apacito r are used t o pro vide fas t switchin g current peaks at turn -on and tu rn-off and a conti nuous gate current while

in on-state. An eval uation gate driv e board ( GA15IDDJT22-FR4) utili zing this topology is comm ercially avai lable low-s ide driv ing, its da tasheet

provides additional details.

Figure 25: Topo logy of the GA15IDDJT22-FR4 Two Voltage Source gate driver.

The GA15IDDJT22-FR4 evaluation board comes equipped with two on board gate drive resistors (RG1, RG2) pre-installed for an effective

gate resistance3 of RG = 0.7 Ω. It may be necessary for the user to reduce RG1 and/or RG2 under high drain current conditions for safe

operation of the GA100SICP12-227. The steady state c urrent supplied to the gate p in of the GA100SICP12-227 with on-board RG = 0.7 Ω, is

shown in Figure 26. The maximum allowable safe value of RG for the user’s required drain current can be read from Figure 27.

For the GA100SICP12-227, RG must be reduced or shorted for ID ≥ ~40 A for safe operation with the GA15IDDJT22-FR4.

For operation at ID ≥ ~40 A, RG may be calculated from the following equation, which contains the DC current gain hFE and the gate-source

saturation voltage VGS,sat (Figure 7).

, =4.7  ,    (,)

1.5 0.1

GA15IDDJT22-FR4

Gate Driver Board

CG2

Gate

Signal

VGH

R1 U4

VGL

VEE

VGL

VGH

VEE

VGL

VEE

CG1

RG1

RG2

C21

+12 V

VCC High

VCC High RTN

VCC Low

VCC Low RTN

Signal

Signal RTN

VGL

VEE C10

GA100SICP12-227

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Figure 26: Typical steady state gate current supplied by the

GA15IDDJT22-FR4 board for the GA100SICP12-227 with the

on board resistance of 0.7 Ω

Figure 27: Maximum gate resistance for safe operation of

the GA100SICP12-227 at different drain currents using the

GA15IDDJT22-FR4 board.

B:2: High Speed, Low Loss Drive with Boost Inductor

A High Speed, Low-Loss Driver with Boost Inductor is also capable of driving the GA100SICP12-227 at high-speed. It utilizes a gate drive

inductor instead of a capacitor to provide the high-current gate current pulses IG,on and IG,off. During operation, inductor L is charged to a

specified IG,on current value then made to discharge IL into the SJT gate pin using logic control of S1, S2, S3, and S4, as shown in Figure 28.

After turn on, while the dev ice re m ai ns on the nec e ss ary stead y stat e gate curre nt IG,steady is suppli ed f rom sourc e VCC t hrough RG. Plea s e refer

to the article “A current-source concept for fast and efficient driving of silicon carbide transistors” by Dr. Jacek Rąbkowski for additional

information on this driving topology.4

Figure 28: Simplified Inductive Pulsed Drive Topology

3 – RG = (1/RG1 +1/RG2)-1. Driver is pre-installed wit h R G1 = 2.2 Ω, RG2 = 1.0 Ω

4 – Archives of Electrical Engineering. Volume 62, Issue 2, Pages 333–343, ISSN (Print) 0004-0746, DOI: 10.2478/aee-2013-0026, June 2013

GA100SICP12-227

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C: Proportional Gate Current Driving

For applications in which the GA100SICP12-227 will operate over a wide range of drain current conditions, it may be beneficial to drive the

device using a proportional gate drive topolog y to optimize gate drive power consumption. A proportional gate driver relies on instantaneous

drain current ID feedback to vary the steady state gate current IG,steady supplied to the GA100SICP2-227

C:1: Voltage Controlled Proportional Driver

The voltage controlled proportion al driver reli es on a gate dri ve IC t o detec t the GA100SICP12-227 drain-source volta ge VDS duri ng on -state to

sense ID. The gate drive IC will then increase or decrease IG,steady in response to ID. This allows IG,steady, and thus the gate drive power

consumption, to be reduced whi le ID is relativel y low or for IG,steady to increase when is ID hi gher. A high voltage diode connected between the

drain and sense protects the IC from high-voltage when the dri ver and GA100SICP12-227 are in off-state. A si mplified versi on of this t opolog y

is shown in Figure 29, additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junction-

transistors/

Figure 29: Simplified Voltage Controlled Proportional Driver

C:2: Current Controlled Proportional Driver

The current controlled proportional driver relies on a low-loss transformer in the drain or source path to provide feedback ID of the

GA100SICP12-227 during on-state to supply IG,steady into the device gate. IG,steady will then increase or decrease in response to ID at a fixed

forced current gain which is set be the turns ratio of the transformer, hforce = ID / IG = N2 / N1. GA100SICP12-227 is initially turned-on using a

gate current pulse supplied into an RC drive circuit to allow ID current to begin flowing. This topology allows IG,steady, and thus the gate drive

power consumption, to be reduce d while ID is relatively low or for IG,steady to increase when is ID higher . A simplified version of this topolog y is

shown in Figure 30, additional information will be available in the future at http://www.genesicsemi.com/commercial-sic/sic-junction-

transistors/.

Figure 30: Simplified Current Controlled Propor tional D river

Proportional

Gate Current

Driver

Gate Signal

G,steady

HV Diode

Sense

Signal Output

Gate Signal

GA100SICP12-227

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Section VI: Package Dimensions

SOT-227 PACKAGE OUTLINE

NOTE

1. CONTROLLED DIMENSION IS INCH. DIMENSION IN BRACKET IS MILLIMETER.

2. DIMENSIONS DO NOT INCLUDE END FLAS H, MOLD FLASH, MATERIAL PROTRUSIONS

Revision History

Date Revision Comments Supersedes

2015/12/07 1 Updated Electrical Characteristics

2015/03/30 0 Initial release

Published by

GeneSiC Semiconductor, Inc.

43670 Trade Center Place Suite 155

Dulles, VA 20166

GeneSiC Semiconductor, Inc. reserves right to make changes to the product specifications and data in this document without notice.

GeneSiC disclaims all and any warranty and liability arising out of use or application of any product. No license, express or implied to any

intellectual property rights is granted by this document.

Unless otherwise expressly indicated, GeneSiC products are not designed, tested or authorized for use in life-saving, medical, aircraft

navigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal

injury and/or property damage.

1.240 (31.5)

1.255 (31.88)

0.310 (7.87)

0.322 (8.18)

R 3.97

0.163 (4.14)

0.169 (4.29)

Ø 0.163 (4.14)

0.169 (4.29)

0.186 (4.72)

0.191 (4.85)

0.165 (4.19)

0.169 (4.29)

0.588 (14.9)

0.594 (15.09)

1.186 (30.1)

1.192 (30.28)

1.494 (37.9)

1.504 (38.20)

0.108 (2.74)

0.124 (3.15)

0.372 (9.45)

0.378 (9.60)

0.472 (11.9)

0.480 (12.19)

0.030 (0.76)

0.033 (0.84)

0.495 (12.5)

0.506 (12.85)

0.990 (25.1)

1.000 (25.40)

1.049 (26.6)

1.059 (26.90)

0.080 (2.03)

0.084 (2.13) 0.164 (4.16)

0.174 (4.42)

0.172 (4.37)

0.234 (5.94)

GA100SICP12-227

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Section VII: SPICE Model Parameters

This is a secure document. Please copy this code from the SPICE model PDF file on our website

(http://www.genesicsemi.com/images/products_sic/igbt_copack/GA100SICP12-227_SPICE.pdf) into

LTSPICE (version 4) software for simulation of the GA100SICP12-227.

* MODEL OF GeneSiC Semiconductor Inc.

* $Revision: 2.0 $

* $Date: 07-DEC-2015 $

* GeneSiC Semiconductor Inc.

* 43670 Trade Center Place Ste. 155

* Dulles, VA 20166

* These models are provided "AS IS, WHERE IS, AND WITH NO WARRANTY

* OF ANY KIND EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED

* TO ANY IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A

* PARTICULAR PURPOSE."

* Models accurate up to 2 times rated drain current.

* Start of GA100SICP12-227 SPICE Model

.SUBCKT GA100SIPC12 DRAIN GATE SOURCE

QA1 DRAIN GATE SOURCE GA100SIPC12_Q

DA1 SOURCE DRAIN GA100SIPC12_D1

DA2 SOURCE DRAIN GA100SIPC12_D2

QB1 DRAIN GATE SOURCE GA100SIPC12_Q

DB1 SOURCE DRAIN GA100SIPC12_D1

DB2 SOURCE DRAIN GA100SIPC12_D2

.model GA100SIPC12_Q NPN

+ IS 9.833E-48 ISE 1.073E-26 EG 3.23

+ BF 89 BR 0.55 IKF 9000

+ NF 1 NE 2 RB 0.95

+ RE 0.004 RC 0.0125 CJC 2.398E-9

+ VJC 2.8346 MJC 0.4846 CJE 6.026E-09

+ VJE 3.1791 MJE 0.5295 XTI 3

+ XTB -1.5 TRC1 9.0E-03 MFG GeneSiC_Semi

+ IRB 0.005 RBM 0.073

.MODEL GA100SIPC12_D1 D

+ IS 1.99E-16 RS 0.015652965 N 1

+ IKF 1000 EG 1.2 XTI 3

+ TRS1 0.0042 TRS2 1.3E-05 CJO 3.86E-09

+ VJ 1.362328465 M 0.48198551 FC 0.5

+ TT 1.00E-10 IAVE 50

.MODEL GA100SIPC12_D2 D

+ IS 1.54E-19 RS 0.1 N 3.941

+ EG 3.23 TRS1 -0.004 IKF 19

+ XTI 0 FC 0.5 TT 0

.ENDS