TDA7313 - STMicroelectronics

TDA7313

DIGITAL CONTROLLED STEREO AUDIO PROCESSOR

WITH LOUDNESS

INPUTMULTIPLEXER:

- 3 STEREO INPUTS

- SELECTABLEINPUT GAINFOR OPTIMAL

ADAPTIONTO DIFFERENT SOURCES

INPUT AND OUTPUT FOR EXTERNAL

EQUALIZER OR NOISE REDUCTION SYS-

TEM

LOUDNESS FUNCTION

VOLUMECONTROL IN 1.25dB STEPS

TREBLEAND BASSCONTROL

FOURSPEAKERATTENUATORS:

- 4 INDEPENDENT SPEAKERSCONTROL

IN 1.25dB STEPS FOR BALANCE AND

FADERFACILITIES

- INDEPENDENT MUTE FUNCTION

ALL FUNCTIONS PROGRAMMABLE VIA SE-

RIAL I2C BUS

DESCRIPTION

The TDA7313 is a volume, tone (bass and treble)

balance (Left/Right) and fader (front/rear) processor

for quality audio applications in car radio and Hi-Fi

systems.

Selectable input gain and externalloudness function

are provided. Control is accomplished by serial I2C

busmicroprocessorinterface.

TheAC signalsettingis obtainedbyresistornetworks

andswitchescombinedwithoperationalamplifiers.

Thanks to the used BIPOLAR/CMOS Tecnology,

LowDistortion, Low Noise andLowDCsteppingare

obtained.

November 1999



DIP28 SO28

ORDERING NUMBERS:

TDA7313 TDA7313D

PIN CONNECTION (Topview)

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THERMAL DATA

Symbol Description SO28 DIP28 Unit

Rthj-pins Thermal Resistance Junction-pins max 85 65 °C/W

QUICK REFERENCE DATA

Symbol Parameter Min. Typ. Max. Unit

VSSupply Voltage 6 9 10 V

VCL Max. input signal handling 2 Vrms

THD Total Harmonic DistortionV = 1Vrms f = 1KHz 0.01 0.1 %

S/N Signal to Noise Ratio 106 dB

SCChannel Separation f = 1KHz 103 dB

Volume Control 1.25dB step -78.75 0 dB

Bass and Treble Control 2db step -14 +14 dB

Fader and Balance Control 1.25dB step -38.75 0 dB

Input Gain 3.75dB step 0 11.25 dB

Mute Attenuation 100 dB

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

VSOperating Supply Voltage 10.2 V

Tamb Operating Ambient Temperature -40 to 85 °C

Tstg Storage Temperature Range -55 to +150 °C

TEST CIRCUIT

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L1 15 L1

L2 14 L2

L3 13 L3

INPUT

SELECTOR

+ GAIN

LEFT

INPUTS

2.2µF

SUPPLY

R3 9 R3

R2 10 R2

R1 11 R1

2.2µF

RIGHT

INPUTS

231

CC AGND CREF

C9 2.2µF

OUT(L) IN(L)

17 16

VOL

+ LOUD

LOUD(L)

100nF

C14

BASS

5.6K R2

BOUT(L)

BIN(L)

100nF

C15

TREBLE

C17

2.7nF

TREBLE(L)

MUTE

D94AU180

SERIAL BUS DECODER + LATCHES

SPKR

ATT 25

VOL

+ LOUD BASS TREBLE

OUT(R) IN(R)

C8 2.2µF

100nF

C12 100nF

C13

5.6K R1

BOUT(R) BIN(R)

21 20

2.7nF

C16

TREBLE(R)

MUTE

SPKR

ATT

SCL

SDA

DIGGND

BUS

OUT

RIGHT

REAR

OUT LEFT

FRONT

22µFC7

LOUD(R)

C11

100nF

C10

MUTE

SPKR

ATT OUT LEFT

REAR

MUTE

SPKR

ATT OUT

RIGHT

FRONT

BLOCK DIAGRAM

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ELECTRICAL CHARACTERISTICS (refer to the test circuit Tamb =25°C, VS= 9V,RL=10KΩ,

RG= 600Ω, all controls flat (G = 0), f = 1KHz unless otherwise specified)

Symbol Parameter Test Condition Min. Typ. Max. Unit

SUPPLY

VSSupply Voltage 6 9 10 V

ISSupply Current 8 11 mA

SVR Ripple Rejection 60 80 dB

INPUTSELECTORS

RII Input Resistance Input 1, 2, 3 35 50 70 KΩ

VCL Clipping Level 2 2.5 Vrms

SIN Input Separation (2) 80 100 dB

RLOutput Load resistance pin 7, 17 2 KΩ

GINmin Min. Input Gain -1 0 1 dB

GINmax Max. Input Gain 11.25 dB

GSTEP Step Resolution 3.75 dB

eIN Input Noise G = 11.25dB 2 µV

VDC DC Steps adjacent gainsteps 4 20 mV

G = 18.75 to Mute 4 mV

VOLUMECONTROL

RIV Input Resistance 20 33 50 kΩ

CRANGE Control Range 70 75 80 dB

AVMIN Min. Attenuation -1 0 1 dB

AVMAX Max. Attenuation 70 75 80 dB

ASTEP Step Resolution 0.5 1.25 1.75 dB

EAAttenuation Set Error Av = 0 to -20dB

Av = -20 to -60dB -1.25

-3 0 1.25

2dB

ETTracking Error 2dB

DC DC Steps adjacent attenuationsteps

From 0dB to Av max 0

0.5 3

7.5 mV

SPEAKERATTENUATORS

Crange Control Range 35 37.5 40 dB

SSTEP Step Resolution 0.5 1.25 1.75 dB

EAAttenuation set error 1.5 dB

AMUTE Output Mute Attenuation 80 100 dB

VDC DC Steps adjacent att.steps

from 0 to mute 0

10 mV

BASS CONTROL (1)

Gb Control Range Max. Boost/cut +12 +14 +16 dB

BSTEP Step Resolution 1 2 3 dB

RBInternal Feedback Resistance 34 44 58 KΩ

TREBLE CONTROL (1)

Gt Control Range Max. Boost/cut +13 +14 +15 dB

TSTEP Step Resolution 1 2 3 dB

TDA7313

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ELECTRICAL CHARACTERISTICS (continued)

Symbol Parameter Test Condition Min. Typ. Max. Unit

AUDIO OUTPUTS

VOCL Clipping Level d = 0.3% 2 2.5 Vrms

RLOutput LoadResistance 2 KΩ

CLOutput LoadCapacitance 10 nF

ROUT Output resistance 30 75 120 Ω

VOUT DC Voltage Level 4.2 4.5 4.8 V

GENERAL

eNO Output Noise BW = 20-20KHz, flat

output muted

all gains = 0dB 2.5

515

µV

A curve all gains = 0dB 3 µV

S/N Signal to Noise Ratio all gains = 0dB; VO= 1Vrms 106 dB

d Distortion AV=0,V

IN = 1Vrms

AV= -20dB VIN = 1Vrms

VIN = 0.3Vrms

0.01

0.09

0.04

0.1

0.3 %

Sc Channel Separation left/right 80 103 dB

Total Tracking error AV= 0 to -20dB

-20 to -60 dB 0

2dB

BUS INPUTS

VIL Input Low Voltage 1V

IH Input High Voltage 3 V

IIN Input Current -5 +5 µA

VOOutput VoltageSDA

Acknowledge IO= 1.6mA 0.4 V

Notes:

(1) Bass and Trebleresponse see attached diagram(fig.16). The center frequency and quality of the resonance behaviour can be choosen by

the external circuitry. A standardfirst order bass response can be realized by a standard feedback network

(2) The selected input is grounded thru the 2.2µF capacitor.

Figure2: Loudnessvs. Frequency(CLOUD =

100nF) vs. Volume Attenuation

Figure 1: Loudnessvs. VolumeAttenuation

TDA7313

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Figure6: Distortion& Noisevs. Frequency

Figure 7: Distortion & Noise vs. Frequency Figure8: Distortionvs. Load Resistance

Figure4: Noise vs. Volume/GainSettings

Figure 5: Signal to Noise Ratio vs. Volume

Setting

Figure 3: Loudnessvs. External Capacitors

TDA7313

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Figure12: OutputClipping Level vs. Supply

Voltage

Figure14: SupplyCurrent vs. Temperature

Figure 13: QuiescentCurrent vs. SupplyVoltage

Figure10: InputSeparation(L1 →L2, L3, L4) vs.

Frequency

Figure 9: ChannelSeparation(L →R) vs.

Frequency

Figure 11: Supply Voltage Rejection vs.

Frequency

TDA7313

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I2C BUS INTERFACE

Data transmission from microprocessor to the

TDA7313 and viceversa takes place thru the 2

wires I2C BUS interface, consisting of the two

lines SDA and SCL (pull-up resistors to positive

supply voltage must be connected).

Data Validity

As shown in fig. 17, the data on the SDA line

must be stable during the high period of the clock.

The HIGH and LOW state of the data line can

only change when the clock signal on the SCL

line is LOW.

Start and Stop Conditions

As shown in fig.18 a start condition is a HIGH to

LOW transition of the SDA line while SCL is

HIGH. The stop condition is a LOW to HIGH tran-

sition of the SDA line while SCL is HIGH.

Byte Format

Every byte transferredon the SDA line must con-

tain 8 bits. Each byte must be followed by an ac-

knowledgebit. The MSB is transferredfirst.

Acknowledge

The master (µP) puts a resistive HIGH level on the

SDA line during the acknowledgeclock pulse (see

fig. 19). The peripheral (audioprocessor) that ac-

knowledges has to pull-down (LOW) the SDA line

during the acknowledge clock pulse, so that the

SDAlineis stableLOWduringthisclockpulse.

The audioprocessor which has been addressed

has to generate an acknowledge after the recep-

tion of each byte, otherwise the SDA line remains

at the HIGH level during the ninth clock pulse

time. In this case the master transmitter can gen-

erate the STOP information in order to abort the

transfer.

Transmissionwithout Acknowledge

Avoiding to detect the acknowledge of the audio-

processor, the µP can use a simplier transmis-

sion: simply it waits one clock without checking

the slave acknowledging, and sends the new

data.

This approach of course is less protected from

misworking and decreasesthe noise immunity.

Figure 17: Data Validity on the I2CBUS

Figure16: TypicalTone Response (with the ext.

components indicatedin the test

circuit)

Figure 15: BassResistancevs. Temperature

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SOFTWARE SPECIFICATION

Interface Protocol

The interfaceprotocol comprises:

A startcondition (s)

A chip address byte, containing the TDA7313

address(the 8th bit of the bytemust be 0). The

TDA7313must always acknowledgeat theend

of each transmitted byte.

A sequenceof data (N-bytes + acknowledge)

A stopcondition (P)

TDA7313 ADDRESS

MSB first byte LSB MSB LSB MSB LSB

S10001000

ACK DATA ACK DATA ACK P

Data Transferred (N-bytes + Acknowledge)

ACK = Acknowledge

S = Start

P = Stop

MAX CLOCK SPEED 100kbits/s

SOFTWARE SPECIFICATION

Chip address

MSB 0001000

LSB

DATA BYTES

MSB LSB FUNCTION

Volume control

Speaker ATT LR

Speaker ATT RR

Speaker ATT LF

Speaker ATT RF

Audio switch

Bass control

Treble control

Ax = 1.25dB steps; Bx = 10dB steps; Cx = 2dB steps; Gx = 3.75dBsteps

Figure 18: TimingDiagramof I2CBUS

Figure 19: Acknowledgeon the I2CBUS

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SOFTWARE SPECIFICATION (continued)

DATA BYTES(detailed description)

Volume

MSB LSB FUNCTION

0 0 B2 B1 B0 A2 A1 A0 Volume 1.25dB steps

-1.25

-2.5

-3.75

-5

-6.25

-7.5

-8.75

0 0 B2 B1 B0 A2 A1 A0 Volume 10dB steps

-10

-20

-30

-40

-50

-60

-70

For example a volume of -45dB is givenby:

00100100

Speaker Attenuators

MSB LSB FUNCTION

Speaker LF

Speaker RF

Speaker LR

Speaker RR

-1.25

-2.5

-3.75

-5

-6.25

-7.5

-8.75

-10

-20

-30

11111 Mute

For example attenuationof 25dB on speakerRF is given by:

10110100

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Audio Switch

MSB LSB FUNCTION

0 1 0 G1 G0 S2 S1 S0 Audio Switch

Stereo 1

Stereo 2

Stereo 3

Stereo 4 (*)

LOUDNESS ON

LOUDNESS OFF

+11.25dB

+7.5dB

+3.75dB

0dB

For example to select the stereo 2 input with a gain of +7.5dBLOUDNESS ON the 8bit string is:

01001001

(*) Stereo 4 is connectedinternally, but not availableon pins.

Bass andTreble

1C3

C3 C2

C2 C1

C1 C0

C0 Bass

Treble

-14

-12

-10

-8

-6

-4

-2

C3 = Sign

For example Bass at -10dB is obtained by the following8 bit string:

01100010

Purchase of I2C Components of STMicroelectronics, conveys a license under the Philips I2C Patent

Rights to use these components in an I2C system, provided that the system conforms to the I2C

StandardSpecificationsas definedby Philips.

TDA7313

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SO28

DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

A 2.65 0.104

a1 0.1 0.3 0.004 0.012

b 0.35 0.49 0.014 0.019

b1 0.23 0.32 0.009 0.013

C 0.5 0.020

c1 45°(typ.)

D 17.7 18.1 0.697 0.713

E 10 10.65 0.394 0.419

e 1.27 0.050

e3 16.51 0.65

F 7.4 7.6 0.291 0.299

L 0.4 1.27 0.016 0.050

S8°(max.)

OUTLINE AND

MECHANICAL DATA

TDA7313

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DIM. mm inch

MIN. TYP. MAX. MIN. TYP. MAX.

a1 0.63 0.025

b 0.45 0.018

b1 0.23 0.31 0.009

0.012

b2 1.27 0.050

D 37.34 1.470

E 15.2 16.68 0.598 0.657

e 2.54 0.100

e3 33.02 1.300

F 14.1 0.555

I 4.445 0.175

L 3.3 0.130 DIP28

OUTLINE AND

MECHANICAL DATA

TDA7313

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Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is

granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are

subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products

are not authorized for use as criticalcomponents in life support devices or systems without express written approval of STMicroelectronics.

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TDA7313

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