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FEATURES
Real-Time Clock Keeps Track of Hundredths
of Seconds, Seconds, Minutes, Hours, Days,
Date of the Month, Months, and Years
8K x 8 NV SRAM Directly Replaces
Volatile Static RAM or EEPROM
Embedded Lithium Energy Cell Maintains
Calendar Operation and Retains RAM Data
Watch Function is Transparent to RAM
Operation
Automatic Leap Year Compensation Valid
Up to 2100
Lithium Energy Source is Electrically
Disconnected to Retain Freshness Until
Power is Applied for the First Time
Standard 28-Pin JEDEC Pinout
Full ±10% Operating Range
Accuracy is Better than ±1 Minute/Month at
+25°C
Over 10 Years of Data Retention in the
Absence of Power
Available in 120ns Access Time
Underwriters Laboratories (UL) Recognized
(www.maxim-ic.com/qa/info/ul)
PIN CONFIGURATION
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS1243Y-120+
0°C to +70°C
28 EDIP (0.720a)
+ Denotes a lead(Pb)-free/RoHS-compliant package.
Encapsulated Package
(720-Mil Extended)
A7
A5
A3
A2
A1
A0
DQ0
DQ1
GND
DQ2
VCC
WE
N.C.
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ3
DQ4
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
15
16
A12
A6
A4
RST
DS1243Y
TOP VIEW
DS1243Y
64K
NV SRAM with Phantom Clock
19-6076; Rev 11/11
DS1243Y
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PIN DESCRIPTION
PIN
NAME
FUNCTION
1 RST
Active-Low Reset Input. This pin has an internal pullup resistor
connected to VCC.
2
A12
Address Inputs
3
A7
4
A6
5
A5
6
A4
7
A3
8
A2
9
A1
10
A0
23
A11
21
A10
24
A9
25
A8
11
DQ0
Data In/Data Out
12
DQ1
13
DQ2
15
DQ3
16
DQ4
17
DQ5
18
DQ6
19
DQ7
20
CE
Active-Low Chip-Enable Input
22
OE
Active-Low Output-Enable Input
26
N.C.
No Connection
27
WE
Active-Low Write-Enable Input
28
VCC
Power-Supply Input
14
GND
Ground
DESCRIPTION
The DS1243Y 64K NV SRAM with Phantom Clock is a fully static nonvolatile RAM (organized as 8192
words by 8 bits) with a built-in real time clock. The DS1243Y has a self-contained lithium energy source
and control circuitry, which constantly monitors VCC for an out-of-tolerance condition. When such a
condition occurs, the lithium energy source is automatically switched on and write protection is
unconditionally enabled to prevent corrupted data in both the memory and real time clock. The Phantom
Clock provides timekeeping information including hundredths of seconds, seconds, minutes, hours, day,
date, month, and year information. The date at the end of the month is automatically adjusted for months
with fewer than 31 days, including correction for leap years. The Phantom Clock operates in either
24-hour or 12-hour format with an AM/PM indicator.
DS1243Y
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RAM READ MODE
The DS1243Y executes a read cycle whenever
WE
(Write Enable) is inactive (high) and
CE
(Chip
Enable) is active (low). The unique address specified by the 13 address inputs (A0–A12) defines which of
the 8192 bytes of data is to be accessed. Valid data will be available to the eight data output drivers
within tACC (Access Time) after the last address input signal is stable, providing that
CE
and
OE
(Output
Enable) access times and states are also satisfied. If
OE
and
CE
access times are not satisfied, then data
access must be measured from the later occurring signal (
CE
or
OE
) and the limiting parameter is either
tCO for
CE
or tOE for
OE
rather than address access.
RAM WRITE MODE
The DS1243Y is in the write mode whenever the
WE
and
CE
signals are in the active (low) state after
address inputs are stable. The latter occurring falling edge of
CE
or
WE
will determine the start of the
write cycle. The write cycle is terminated by the earlier rising edge of
CE
or
WE
. All address inputs must
be kept valid throughout the write cycle.
WE
must return to the high state for a minimum recovery time
(tWR) before another cycle can be initiated. The
OE
control signal should be kept inactive (high) during
write cycles to avoid bus contention. However, if the output bus has been enabled (
CE
and
OE
active)
then
WE
will disable the outputs in t ODW from its falling edge.
DATA RETENTION MODE
The DS1243Y provides full functional capability for VCC greater than VTP and write protects by 4.25V.
Data is maintained in the absence of VCC without any additional support circuitry. The nonvolatile static
RAM constantly monitors VCC. Should the supply voltage decay, the RAM automatically write protects
itself. All inputs to the RAM become “don’t care” and all outputs are high impedance. As VCC falls below
approximately 3.0V, the power switching circuit connects the lithium energy source to RAM to retain
data. During power-up, when VCC rises above approximately 3.0V, the power switching circuit connects
external VCC to the RAM and disconnects the lithium energy source. Normal RAM operation can resume
after VCC exceeds 4.5V.
See “Conditions of Acceptability” at www.maxim-ic.com/TechSupport/QA/ntrl.htm
FRESHNESS SEAL
Each DS1243Y is shipped from Maxim with its lithium energy source disconnected, insuring full energy
capacity. When VCC is first applied at a level greater than VTP, the lithium energy source is enabled for
battery backup operation.
DS1243Y
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PHANTOM CLOCK OPERATION
Communication with the Phantom Clock is established by pattern recognition on a serial bit stream of 64
bits which must be matched by executing 64 consecutive write cycles containing the proper data on DQ0.
All accesses which occur prior to recognition of the 64–bit pattern are directed to memory.
After recognition is established, the next 64 read or write cycles either extract or update data in the
Phantom Clock, and memory access is inhibited.
Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control
of Chip Enable (
CE
), Output Enable (
OE
), and Write Enable (
WE
). Initially, a read cycle to any memory
location using the
CE
and
OE
control of the Phantom Clock starts the pattern recognition sequence by
moving a pointer to the first bit of the 64–bit comparison register. Next, 64 consecutive write cycles are
executed using the
CE
and
WE
control of the SmartWatch. These 64 write cycles are used only to gain
access to the Phantom Clock. Therefore, any address to the memory in the socket is acceptable. However,
the write cycles generated to gain access to the Phantom Clock are also writing data to a location in the
mated RAM. The preferred way to manage this requirement is to set aside just one address location in
RAM as a Phantom Clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of
the 64–bit comparison register. If a match is found, the pointer increments to the next location of the
comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance
and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition,
the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues
for a total of 64 write cycles as described above until all the bits in the comparison register have been
matched (this bit pattern is shown in Figure 1). With a correct match for 64 bits, the Phantom Clock is
enabled and data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause
the Phantom Clock to either receive or transmit data on DQ0, depending on the level of the
OE
pin or the
WE
pin. Cycles to other locations outside the memory block can be interleaved with
CE
cycles without
interrupting the pattern recognition sequence or data transfer sequence to the Phantom Clock.
PHANTOM CLOCK REGISTER INFORMATION
The Phantom Clock information is contained in 8 registers of 8 bits, each of which is sequentially
accessed 1 bit at a time after the 64–bit pattern recognition sequence has been completed. When updating
the Phantom Clock registers, each register must be handled in groups of 8 bits. Writing and reading
individual bits within a register could produce erroneous results. These read/write registers are defined in
Figure 2.
Data contained in the Phantom Clock register is in binary coded decimal format (BCD). Reading and
writing the registers is always accomplished by stepping through all 8 registers, starting with bit 0 of
register 0 and ending with bit 7 of register 7.
DS1243Y
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PHANTOM CLOCK REGISTER DEFINITION Figure 1
NOTE: THE PATTERN RECOGNITION IN HEX IS C5, 3A, A3, 5C, C5, 3A, A3, 5C. THE ODDS OF THIS
PATTERN BEING ACCIDENTALLY DUPLICATED AND CAUSING INADVERTENT ENTRY TO THE PHANTOM
CLOCK IS LESS THAN 1 IN 10
19
. THIS PATTERN IS SENT TO THE PHANTOM CLOCK LSB TO MSB.
DS1243Y
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PHANTOM CLOCK REGISTER DEFINITION Figure 2
AM-PM/12/24 MODE
Bit 7 of the hours register is defined as the 12- or 24-hour mode select bit. When high, the 12-hour mode
is selected. In the 12-hour mode, bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode,
bit 5 is the 20-hour bit (20–23 hours).
OSCILLATOR AND RESET BITS
Bits 4 and 5 of the day register are used to control the
RESET
and oscillator functions. Bit 4 controls the
RESET
(pin 1). When the
RESET
bit is set to logic 1, the
RESET
input pin is ignored. When the
RESET
bit is set to logic 0, a low input on the
RESET
pin will cause the Phantom Clock to abort data transfer
without changing data in the watch registers. Bit 5 controls the oscillator. When set to logic 1, the
oscillator is off. When set to logic 0, the oscillator turns on and the watch becomes operational. These
bits are shipped from the factory set to a logic 1, oscillator off.
ZERO BITS
Registers 1, 2, 3, 4, 5, and 6 contain one or more bits that always read logic 0. When writing these
locations, either a logic 1 or 0 is acceptable.
DS1243Y
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ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground……………………………………………..-0.3V to +6.0V
Operating Temperature Range……………………………………………...0°C to +70°C (noncondensing)
Storage Temperature Range……………………………………………...-40°C to +85°C (noncondensing)
Lead Temperature (soldering, 10s)……… . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +260°C
Note: EDIP is wave or hand-soldered only.
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect
reliability.
RECOMMENDED OPERATING CONDITIONS
(TA = 0°C to +70°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Power Supply Voltage
VCC
4.5
5.0
5.5
V
Input Logic 1
VIH
2.2
VCC+0.3
V
Input Logic 0
VIL
-0.3
+0.8
V
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V ±10%, TA = 0°C to +70°C.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Leakage Current
IIL
-1.0
+1.0
µA
12
I/O Leakage Current
CE
≥
VIH
≤
VCC
IIO -1.0 +1.0 µA
Output Current @ 2.4V
IOH
-1.0
mA
Output Current @ 0.4V
IOL
2.0
mA
Standby Current
CE
= 2.2
I
CCS1
5.0
10
mA
Standby Current
CE
= VCC – 0.5V
ICCS2 3.0 5.0 mA
Operating Current tCYC = 200ns
ICC01
85
mA
Write Protection Voltage
VTP
4.25
4.5
V
DC TEST CONDITIONS
Outputs are open; all voltages are referenced to ground.
CAPACITANCE
(TA = +25°C)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Input Capacitance
CIN
5
10
pF
Input/Output Capacitance
CI/O
5
10
pF
DS1243Y
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MEMORY AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V ±10%, TA = 0°C to +70°C.)
PARAMETER SYMBOL
DS1243Y-120
UNITS NOTES
MIN
MAX
Read Cycle Time
tRC
120
ns
Access Time
tACC
120
ns
OE
to Output Valid
tOE 60 ns
CE
to Output Valid
t
CO
120
ns
OE
or
CE
to Output
Active
tCOE 5 ns 5
Output High-Z from
Deselection
tOD 40 ns 5
Output Hold from
Address Change
toH 5 ns
Write Cycle Time
tWC
120
ns
Write Pulse Width
tWP
90
ns
3
Address Setup Time
tAW
0
ns
Write Recovery Time
tWR
20
ns
Output High-Z from
WE
tODW 40 ns 5
Output Active from
WE
tOEW 5 ns 5
Data Setup Time
tDS
50
ns
4
Data Hold Time from
WE
tDH 20 ns 4
AC TEST CONDITIONS
Output Load: 50pF + 1TTL Gate
Input Pulse Levels: 0 to 3V
Timing Measurement Reference Levels
Input: 1.5V
Output: 1.5V
Input Pulse Rise and Fall Times: 5ns
DS1243Y
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PHANTOM CLOCK AC ELECTRICAL CHARACTERISTICS
(VCC = 4.5V to 5.5V, TA = 0°C to +70°C.)
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
Read Cycle Time tRC 120 ns
CE
Access Time
tCO 100 ns
OE
Access Time
tOE 100 ns
CE
to Output Low-Z
tCOE 10 ns
OE
to Output Low-Z
tOEE 10 ns
CE
to Output High-Z
tOD 40 ns 5
OE
to Output High-Z
tODO 40 ns 5
Read Recovery tRR 20 ns
Write Cycle Time tWC 120 ns
Write Pulse Width tWP 100 ns
Write Recovery tWR 20 ns 10
Data Setup Time tDS 40 ns 11
Data Hold Time tDH 10 ns 11
CE
Pulse Width
tCW 100 ns
RESET
Pulse Width
tRST 200 ns
CE
High to Power-Fail
tPF 0 ns
POWER-DOWN/POWER-UP TIMING
PARAMETER SYMBOL MIN TYP MAX UNITS NOTES
CE
at VIH before Power-Down
tPD 0 µs
VCC Slew from 4.5V to 0V (
CE
at VIH)
tF 300 µs
VCC Slew from 0V to 4.5V (
CE
at VIH)
tR 0 µs
CE
at VIH after Power-Up
tREC 2 ms
(TA = +25°C)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
Expected Data-Retention Time tDR 10 years 9
WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when
device is in battery-backup mode.
DS1243Y
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MEMORY READ CYCLE (NOTE 1)
MEMORY WRITE CYCLE 1 (NOTES 2, 6, AND 7)
DS1243Y
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MEMORY WRITE CYCLE 2 (NOTES 2 AND 8)
RESET FOR PHANTOM CLOCK
READ CYCLE TO PHANTOM CLOCK
DS1243Y
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WRITE CYCLE TO PHANTOM CLOCK
POWER-DOWN/POWER-UP CONDITION
DS1243Y
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NOTES:
1.
WE
is high for a read cycle.
2.
OE
= VIH or VIL. If
OE
= VIH during write cycle, the output buffers remain in a high impedance state.
3. tWP is specified as the logical AND of
CE
and
WE
. tWP is measured from the latter of
CE
or
WE
going low to the earlier of
CE
or
WE
going high.
4. tDH, tDS are measured from the earlier of
CE
or
WE
going high.
5. These parameters are sampled with a 50pF load and are not 100% tested.
6. If the
CE
low transition occurs simultaneously with or later than the
WE
low transition in Write
Cycle 1, the output buffers remain in a high impedance state during this period.
7. If the
CE
high transition occurs prior to or simultaneously with the
WE
high transition, the output
buffers remain in a high impedance state during this period.
8. If
WE
is low or the
WE
low transition occurs prior to or simultaneously with the
CE
low transition,
the output buffers remain in a high impedance state during this period.
9. The expected tDR is defined as cumulative time in the absence of VCC with the clock oscillator
running.
10. tWR is a function of the latter occurring edge of
WE
or
CE
.
11. tDH and tDS are a function of the first occurring edge of
WE
or
CE
.
12. RST (Pin1) has an internal pullup resistor.
13. Real-Time Clock Modules can be successfully processed through conventional wave-soldering
techniques as long as temperature exposure to the lithium energy source contained within does not
exceed +85°C. Post-solder cleaning with water washing techniques is acceptable, provided that
ultrasonic vibration is not used.
PACKAGE INFORMATION
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages.
Note that a “+”, “#”, or “-” in the package code indicates RoHS status only. Package drawings may show a
different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
28 EDIP MDT28+1 21-0245 —
DS1243Y
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Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim
reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2011 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
REVISION HISTORY
REVISION
DATE
DESCRIPTION
PAGES
CHANGED
11/11
Updated the Features, Ordering Information, AM-PM/12/24 MODE, and
Absolute Maximum Ratings sections
1, 6, 7