© Semiconductor Components Industries, LLC, 2017
April, 2020 − Rev. 12
1Publication Order Number:
NCP81295/D
Hot Swap Smart Fuse
NCP81295, NCP81296
The NCP81295 and NCP81296 are 50 A, electronically re−settable,
in−line fuses for use in 12 V, high current applications such as servers,
storage and base stations. The NCP81295/6 offers a very low 0.65 mW
integrated MOSFET to reduce solution size and minimize power loss.
It also integrates a highly accurate current sensor for monitoring and
overload protection.
Power Features
•Co−packaged Power Switch, Hotswap Controller and Current Sense
•Up to 60 A Peak Current Output, 50 A Continuous
•Vin Range: 4.5 V to 18 V
•0.65 mW, no RSENSE Required
Control Features
•Enable Input
•Optional Enable−controlled Output Pulldown when Disabled
•Programmable Soft−Start
•Programmable, Multi−level Current Limit
Reporting Features
•Accurate Analog Load Current Monitor
•Programmable Over Current Alert Output
•Analog Temperature Output
•Status Fault OK Output
Other Features
•5 mm x 5 mm QFN32 Package
•Operating Temperature: −40°C to 125°C
•Can be Paralleled for Higher Current Applications
•Built−in Insertion Delay for Hotswap Applications
•NCP81295: Latch off for Following Protection Features
NCP81296: Auto−Retry Mode for Following Protection Features
♦Current−limit after Delay
♦Fast Short−circuit Protection
♦Over−Temperature Shutdown
♦Excessive Soft−start Duration
•Internal Switch Fault Diagnostics
•Low−power Auxiliary Output Voltage
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LQFN32 5x5, 0.5P
CASE 487AA
PINOUT
For more details see Figure 1.
MARKING
DIAGRAM
ORDERING INFORMATION
NCP8129x = Specific Device Code
x = 5 or 6
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G= Pb−Free Package
= (may or may not be present)
(Note: Microdot may be in either location)
1
8
7
6
5
4
3
2
9
12
16
15
14
13
11
10
24
17
18
19
20
21
22
23
32
31
30
29
28
27
26
25
NCP81295/6
(TOP VIEW)
33
See detailed ordering and shipping information on page 2 of
this data sheet.
VIN
NCP8129x
AWLYYWWG
G
1
32
1
NCP81295, NCP81296
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2
NC4 1
NC2
VINF
NC1
GOK
ON
D_OC
NC5
8
7
6
5
4
3
2
9
12
16
15
14
13
11
10
GATE
CLREF
CS
IMON
VDD
GND
SS
VTEMP
24
17
18
19
20
21
22
23
32
31
30
29
28
27
26
VOUT25
VOUT27
VOUT28
VOUT29
VOUT30
VOUT31
VOUT32
VOUT26
NCP81295 /6
(TOP VIEW)
33
25
Figure 1. Pin Configuration
VIN
VIN9
VIN10
VIN11
VIN12
VIN13
VIN14
VIN15
VIN16
Ordering Information
Table 1. AVAILABLE DEVICES
Device Package Shipping
†
NCP81295MNTXG QFN32 2500 / Tape & Reel
NCP81296MNTXG QFN32 2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
NCP81295, NCP81296
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3
Figure 2. Typical Application
NCP81295/ 6
GND
VIN VINF
VDD
VOUT
CS
SS
CLREF
IMON
VTEMP
ON
GOK
D_OC
System VIN
Fuse−protected
System VIN
GATE
Figure 3. Typical Application Diagram
Input
Voltage
E−Fuse
Control/
Monitor
E−Fuse
IMON Standby
System
Power Standby
System
Main System
Main Efuse
Main Efuse
E−Fuse
Control/
Monitor
E−Fuse
Control/
Monitor
PMBSUS Control and
Monitor
Main
System
Power
Standby Efuse
mController
NCP81295, NCP81296
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4
Figure 4. Application Schematic − Parallel Fuse Operation with Controller
S
ystem
VIN
Fuse−protected
System VIN
NCP81295
GND
VIN VINF
VDD
VOUT
CS
SS
CLREF
IMON
VTEMP
ON
GOK
D_OC
NCP81295
GND
VIN VINF
VDD
VOUT
CS
SS
CLREF
IMON
VTEMP
ON
GOK
D_OC
NCP81295
GND
VIN VINF
VDD
VOUT
CS
SS
CLREF
IMON
VTEMP
ON
GOK
D_OC
mController
FAULT IN
OVERCURRENT IN
ENABLE OUT
TEMP MONITOR A/D IN
CURRENT MONITOR A/D IN
CURRENT LIMIT D/A OUT
GATE
GATE
GATE
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5
Figure 5. Application Schematic − Single EFuse with Controller
System VIN
GOK
D_OC
ON
VTEMP VOUT
GND
SS
CLREF
IMON
VDD
CS
VIN VINF
Fuse Protected
CURRENT MONITOR A/D IN
CURRENT LIMIT D/A OUT
TEMP MONITOR A/D IN
ENABLE OUT
OVERCURRENT IN
FAULT IN
System VIN
mController
NCP81295/6
GATE
Figure 6. Application Schematic − Stand−alone Single EFuse
System VIN
GOK
D_OC
ON
VTEMP
VIN
VOUT
GND
VINF
SS
CLREF
IMON
VDD
CS
Fuse Protected
System VIN
NCP81295/6
GATE
NCP81295, NCP81296
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7
-32
Figure 8. Block Diagram
EN
SENSEFET
1:5000
5V
LDO
21
7
VDD_UVR
OUTPUT
MONITOR
VDD
VINF
VIN VOUT > 90 % VIN
VOUT > 80 % VIN
VOUT > 40 % VIN
25−32 VOUT
PD
19 SS
VDD
CHARGE
PUMP
VINF+2XVDD
AIMON
ACS
22
23
IMON
CS
24 CLREF
3D_OC
VOC_TH(85% CLREF)
VCL_MAX
VCL_HI
VCL_LO
VOUT>80%VIN
VOUT>40%VIN
OVERCURRENT
TIMER
LOGIC
ISC
5
VOUT>90%VIN
VOUT>70%VIN
DRAIN MON
GATE MON
4
ON
V
SWON
V
SWOFF
DIE TEMP
MONITOR
18
VTEMP
20
GND
VDD
50 mA
VDD
5mA
500
VDD
10 mA
GOK
VOUT > 70 % VIN
9−16
5 mA
NCP81295, NCP81296
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Table 2. PIN DESCRIPTION
Pin No. Symbol Description
1 NC4 No electrical connection internally. May connect to any potential
2 NC5 No electrical connection internally. May connect to any potential
3 D_OC Overcurrent indicator output (open drain). Low indicates the NCP81295 is limiting current. The D_OC
output does not report current limiting during soft−start.
4 ON Enable input and output pulldown resistance control.
5 GOK OK status indicator output (open drain). Low indicates that the NCP81295 was turned off by a fault.
6 NC1 Test pin. Do not connect to this pin. Leave floating
7 VINF Control circuit power supply input. Connect to VIN pins through an RC filter. (1 W / 0.1 mF)
8 NC2 Internal FET sense pin. Do not connect to this pin. Leave floating
9 VIN09 Input of high current output switch
10 VIN10 Input of high current output switch
11 VIN11 Input of high current output switch
12 VIN12 Input of high current output switch
13 VIN13 Input of high current output switch
14 VIN14 Input of high current output switch
15 VIN15 Input of high current output switch
16 VIN16 Input of high current output switch
17 GATE Internal FET gate pin. Connect to the cathode of an anode grounded diode such as BAS16P2T5G. A
4.7 nF ceramic capacitor is reserved between this pin and GND for NCP81295 to mitigate the oscilla-
tion risk when small amount of output capacitance (< 100 mF) or long input/output cable (large LIN /
LOUT) happens.
18 VTEMP Analog temperature monitor output.
19 SS Soft Start time programming pin. Connect a capacitor to this pin to set the softstart time.
20 GND Ground
21 VDD Linear regulator output
22 IMON Analog current monitor output
23 CS Current sense feedback output (current). Scaling the voltage developed at this pin with a resistor to
ground makes this also an input for several current limiting functions and overcurrent indicator D_OC.
24 CLREF Current limit setpoint input for normal operation (after soft−start).
25 VOUT25 Output of high current output switch
26 VOUT26 Output of high current output switch
27 VOUT27 Output of high current output switch
28 VOUT28 Output of high current output switch
29 VOUT29 Output of high current output switch
30 VOUT30 Output of high current output switch
31 VOUT31 Output of high current output switch
32 VOUT32 Output of high current output switch
33 VIN33 Input of high current output switch
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Table 3. MAXIMUM RATINGS
Rating Symbol Min Max Unit
Pin Voltage Range (Note 1) Vout enabled VINx, VINF −0.3 20 V
Pin Voltage Range (Note 1) Vout disabled (Note 2) VINx, VINF −0.3 30 V
Pin Voltage Range (Note 1) VOUTx −0.3
−1(<500 ms)
20 V
Pin Voltage Range (Note 1) VDD −0.3 6.0 V
Pin Voltage Range (Note 3) All Other Pins −0.3 VDD + 0.3 V
Operating Junction Temperature TJ(max) 150 °C
Storage Temperature Range TSTG −55 150 °C
Lead Temperature Soldering
Reflow (SMD Styles Only), Pb−Free Versions (Note 4)
TSLD 260 °C
Electrostatic Discharge − Charged Device Model ESDCDM 2.0 kV
Electrostatic Discharge − Human Body Model ESDHBM 2.5 kV
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. All signals referenced to GND unless noted otherwise.
2. Vout disable is the state of output OFF when internal FET has turned off by disable ON or FAULTs protection.
3. Pin ratings referenced to VDD apply with VDD at any voltage within the VDD Pin Voltage Range.
4. For information, please refer to our Soldering and Mounting Techniques Reference Manual, SOLDERRM/D
Table 4. THERMAL CHARACTERISTICS
Rating Symbol Value Unit
Thermal Resistance, Junction−to−Ambient (Note 5) RθJA 30 °C/W
Thermal Resistance, Junction−to−Top −Case RθJCT 50 °C/W
Thermal Resistance, Junction−to−Bottom−Case RθJCB 1.5 °C/W
Thermal Resistance, Junction−to−Board (Note 6) RθJB 1.5 °C/W
Thermal Resistance, Junction−to−Case (Note 7) RθJC 1.5 °C/W
5. RqJA is obtained by simulating the device mounted on a 500 mm2, 1−oz Cu pad on a 80 mm x 80 mm, 1.6 mm thick 8−layer FR4 board.
6. RqJB value based on hottest board temperature within 1 mm of the package.
7. RqJC ≈ RqJCT // RqJCB (Two−Resistor Compact Thermal Model, JESD15−3).
Table 5. RECOMMENDED OPERATING RANGES
Parameter Symbol Min Max Unit
VIN, VINF Pin Voltage Range 4.5 18 V
Maximum Continuous Output Current IAVE 50 A
Peak Output Current IPEAK 60 A
VDD Output Load Capacitance Range CVDD 2.2 10 mF
VTEMP Output Load Capacitance Range CVTEMP 0.1 mF
Softstart Duration TSS 10 100 ms
CS Load Resistance Range RCS 1.8 4 kW
CLREF Voltage Range VCLREF 0.2 1.4 V
Operating Junction Temperature TJ(OP) −40 125 °C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
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Table 6. ELECTRICAL CHARACTERISTICS (VINx = VINF = 12.0 V, VON = 3.3 V, CVINF = 0.1 mF, CVDD = 4.7 mF, C VTEMP = 0.1 mF,
RVTEMP = 1 kW, CSS = 100 nF (unless specified otherwise) Min/Max values are valid for the temperature range −40°C ≤ TA = TJ ≤ 125°C
unless noted otherwise, and are guaranteed by design and characterization through statistical correlation.
Parameter Symbol Test Conditions Min Typ Max Units
VINF INPUT
Quiescent Current VON > 1.4 V, no load 3.23 5.0 mA
VON > 1.4 V, fault 5.0 mA
VON < 0.8 V 2.38 4.0 mA
VON < 0.8 V, VINF = 16 V 4.0 mA
VDD REGULATOR
VDD Output Voltage VDD_NL IVDD = 0 mA, VINF = 6 V 4.7 5.09 5.3 V
VDD Load Capability IDDLOAD VINF = 5.5 V 30 mA
VDD Current Limit IDD_CL VINF = 12 V and VINF = 6 V 50 70 mA
VDD Dropout Voltage IVDD = 25 mA, VINF = 4.5 V 85 200 mV
UVLO threshold − rising VDD_UVR 4.1 4.3 4.5 V
UVLO threshold − falling VDD_UVF 3.8 4.0 4.2 V
ON INPUT
Bias Current ION From pin into a 0 V or 1.5 V source 4.0 5.0 6.0 mA
Switch ON Threshold VSWON 1.33 1.4 1.47 V
Switch OFF/ Pulldown Upper
Threshold
VSWOFF 1.13 1.2 1.27 V
Pulldown Lower Threshold VPDOFF 0.8 V
Switch ON Delay Timer tON From ON transitioning above VSWON to SS
start
0.6 1.0 2.5 ms
Switch OFF Delay Time
(Note 8)
tOFF From ON transitioning below VSWOFF to GATE
pulldown
1.7 ms
ON Current Source Clamp
Voltage
VON_CLMP Max pullup voltage of current source 3.0 V
Load Pulldown Delay Timer tPD_DEL From ON transitioning into the range between
VSWOFF and VPDOFF
2.0 ms
Output Pulldown Resistance RPD VOUT = 12 V, PD mode = 1 0.77 kW
SS PIN
Bias Current ISS From pin into a 0 V or 1 V source 4.62 5.15 5.62 mA
Gain to VOUT AVSS 9.6 10 10.4 V/V
SS Pulldown Voltage VOL_SS 0.1 mA into pin during ON delay 22 mV
GOK OUTPUT
Output Low Voltage VOL_GOK IGOK = 1 mA 0.1 V
Off−state Leakage Current ILK_GOK VGOK= 5 V 1.0 mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Guaranteed by design or characterization data. Not tested in production.
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11
Table 6. ELECTRICAL CHARACTERISTICS (VINx = VINF = 12.0 V, VON = 3.3 V, CVINF = 0.1 mF, C VDD = 4.7 mF, CVTEMP = 0.1 mF,
RVTEMP = 1 kW, CSS = 100 nF (unless specified otherwise) Min/Max values are valid for the temperature range −40°C ≤ TA = TJ ≤ 125°C
unless noted otherwise, and are guaranteed by design and characterization through statistical correlation.
Parameter UnitsMaxTypMinTest ConditionsSymbol
IMON/CS OUTPUT
IMON or CS Current
(single EFuse)
Based on 10 mA/A+5 mA
IIMON/ICS TJ = 0 to 85°CIOUT = 5 A (Note 8) 55 mA
IOUT = 10 A (Note 8) 105 mA
IOUT = 25 A (Note 8) 255 mA
IOUT = 50 A (Note 8) 505 mA
Accuracy (single EFuse) TJ = 0 to 85°CIOUT = 5 A (Note 8) −6 +6 %
IOUT = 10 A (Note 8) −4 +4 %
IOUT = 25 A (Note 8) −4 +4 %
IOUT = 50 A (Note 8) −4 +4 %
IMON or CS Current Source
Clamp Voltage
VIM_CLMP/
VCS_CLMP
Max pullup voltage of current source 3.0 V
Pre−Biased Offset Current
Load for Auto−Zero Op−Amp
IAZ_BIAS 5.0 mA
CURRENT LIMIT & CLREF PIN
Current Limit Voltage VCL_TH If VCS > VCL_TH current limiting regulation
occurs via gate
95 98 101 %VCLREF
Current Limit Enact Offset
Voltage
VENACT 0.2 V < VCLREF < 1.4 V −70 −24 12 mV
Current Limit Clamp Voltage VCL_LO VOUT < 40% VIN, VCLREF > 0.15 V 135 152 165 mV
VCL_HI 40% VIN < VOUT < 80% VIN
VCLREF > 0.5 V
480 504 520 mV
Max Current Limit Reference
Voltage
VCL_MX VOUT > 80% VIN, VCLREF > 1.6 V 1.55 1.6 1.65 V
Response Time (Note 8) tCL_REG VCS > VCLREF until current limiting 200 ms
CLREF Bias Current ICL From pin into a 1.2 V source 9.6 10 10.4 mA
CLREF Current Source
Clamp Voltage
VCL_CLMP Max pullup voltage of current source 3.0 V
FET Turn−off Timer tCL_LA Delay between current limit detection and FET
turn−off (GOK = 0)
250 ms
D_OC OUTPUT
Overcurrent Threshold VOC_TH If VCS > VOC_TH D_OC pin pulls low 83 86 90 %VCLREF
Output Low Voltage VOL_DOC IDOC = 1 mA 0.1 V
Off−state Leakage Current ILK_DOC VDOC= 5 V −1.0 mA
Delay (rising) (Note 8) VCS < limit until D_OC rising −1.0 ms
Delay (falling) (Note 8) VCS > limit until D_OC falling −1.0 ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Guaranteed by design or characterization data. Not tested in production.
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Table 6. ELECTRICAL CHARACTERISTICS (VINx = VINF = 12.0 V, VON = 3.3 V, CVINF = 0.1 mF, C VDD = 4.7 mF, CVTEMP = 0.1 mF,
RVTEMP = 1 kW, CSS = 100 nF (unless specified otherwise) Min/Max values are valid for the temperature range −40°C ≤ TA = TJ ≤ 125°C
unless noted otherwise, and are guaranteed by design and characterization through statistical correlation.
Parameter UnitsMaxTypMinTest ConditionsSymbol
SHORT CIRCUIT PROTECTION
Current Threshold (Note 8) ISC NCP81295 100 A
NCP81296 80 A
Response Time (Note 8) tSC From IOUT > ILIMSC until gate pulldown 500 ns
VTEMP OUTPUT
Bias Voltage VVTEMP25 At 25°C 450 mV
Gain (Note 8) AVTEMP 0
°
C ≤ TJ ≤ 125
°
C 10 mV/°C
Load Capability RVTEMP At 25°C 1 kW
Pulldown Current IVTEMP At 25°C 50 mA
THERMAL SHUTDOWN
Temperature Shutdown
(Note 8)
TTSD GOK pulls dow 140 °C
OUTPUT SWITCH (FET)
On Resistance RDSon TJ = 25°C 0.65 1.0 mW
Off−state leakage current IDSoff VIN = 16 V, VON < 1.2 V, TJ = 25°C 1.0 mA
FAULT detection
VDS Short Threshold VDS_TH Startup postponed if VOUT > VDS_TH at VON
> VSWON transition
88.8 %VIN
VDS Short OK Threshold VDS_OK Startup resumed if VOUT < VDS_OK anytime
after postponed
68.6 %VIN
VGD Short Threshold VDG_TH Startup postponed if VG > VDG_TH at VON >
VSWON transition
3.1 V
VGD Short OK Threshold VDG_OK Startup resumed if VG < VDG_OK anytime af-
ter postponed
3.0 V
VG Low Threshold VG_TH Latch/Restart if VGD < VG_TH after tSSF_END
or tGATE_FLT
5.4 V
VOUT Low Threshold VOUTL_TH Latch/Restart if VOUT < VOUTL_TH after
tSSF_END
90 %VIN
Gate Fault Timer (Note 8) tGATE_FLT Time from VGD < VG_TH transition after
tSSF_END completed
200 ms
Startup Timer Failsafe
(Note 8)
tSSF_END Time from VON > VSWON transition,
Max programmable softstart time
200 ms
AUTO−RETRY (NCP81296)
Auto−Retry Delay tDLY_RETRY Delay from power−down to retry of startup 1000 ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Guaranteed by design or characterization data. Not tested in production.
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TYPICAL CHARACTERISTICS
Test Conditions: Vin = 12 V, Rcs = 2 kW, Css = 200 nF, RCLREF = 121 kW, RIMON = 2 kW
Figure 9. Ics vs. Load Current Figure 10. Imon vs. Load Current
LOAD CURRENT (A) LOAD CURRENT (A)
6050403020100
0
100
200
300
400
500
600
6050403020100
0
100
200
300
400
500
600
Figure 11. Ics vs. Temperature Figure 12. Imon vs. Temperature
TEMPERATURE (°C) TEMPERATURE (°C)
1251007550250−25−50
0
100
200
300
400
500
600
1251007550250−25−50
0
100
200
300
400
500
600
Figure 13. Output Switch RDS(on) @ 22 A vs.
Temperature
Figure 14. Vtemp vs. Temperature (no load)
TEMPERATURE (°C) TEMPERATURE (°C)
10080604020−20−40−60
0
0.1
0.3
0.4
0.5
0.7
0.8
1.0
12010060400−20−40−60
0
200
400
600
800
1200
1400
1600
Ics (mA)
Imon (mA)
Ics (mA)RDS(on) (mW)
Vtemp (mV)
150150
0 120 140
0.2
0.6
0.9
20 80 140
1000
30 A
50 A
30 A
50 A
Imon (mA)
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TYPICAL CHARACTERISTICS
Test Conditions: Vin = 12 V, Rcs = 2 kW, Css = 200 nF, RCLREF = 121 kW, RIMON = 2 kW
Figure 15. Output Switch Off−state Leakage
vs. Temperature
TEMPERATURE (°C)
1008060200−20−40−60
−6
−5
−4
−3
−2
−1
0
OFF−STATE LEAKAGE (mA)
40 120 140
Figure 16. Power Loss vs. Load Current
OUTPUT CURRENT (A)
4020100
0
500
1000
1500
2000
2500
POWER LOSS (mW)
30 50
Figure 17. Internal FET’s Safe Operating Area (SOA)
VDS, DRAIN−SOURCE VOLTAGE (V)
10.1
0.01
0.1
1
10
100
1000
ID, DRAIN CURRENT (A)
10
Power Loss
20
100 ms
250 ms
1 ms
10 ms
100 ms
10 s
1 s
Dotted Lines: Measured SOA
Solid Lines: Calculated SOA
Single Pulse
RqJA = 24.8 °C/W
TA = 25°C
RDS(ON) Limit
60
Figure 18. Single Pulse Power Rating (10 ms −
1000 s, Junction−to−Ambient, Note 4)
PULSE WIDTH (s)
POWER (W)
100k
10k
1k
100
10
1
0.00001 0.0001 0.001 0.01 0.1 1.0 100 1k10
TA = 25°C
TA = 85°C
Figure 19. Single Pulse Power Rating (10 ms −
100 ms, Junction−to−Ambient, Note 4)
PULSE WIDTH (s)
POWER (W)
250
200
150
100
50
0
0.01 0.10.2 0.3 0.90.80.70.4 0.5 0.6
TA = 25°C
TA = 85°C
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TYPICAL CHARACTERISTICS
Test Conditions: Vin = 12 V, Rcs = 2 kW, Css = 200 nF, RCLREF = 121 kW, RIMON = 2 kW
Figure 20. Start Up by VIN (Iout = 0 A) Figure 21. Shut Down by VIN (Iout = 0 A)
Figure 22. Start Up by VIN (Iout = 15 A) Figure 23. Shut Down by VIN (Iout = 15 A)
Figure 24. Start Up by EN (Iout = 0 A) Figure 25. Shut Down by EN (Iout = 0 A)
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TYPICAL CHARACTERISTICS
Test Conditions: Vin = 12 V, Rcs = 2 kW, Css = 200 nF, RCLREF = 121 kW, RIMON = 2 kW
Figure 26. Start Up by EN (Iout = 15 A) Figure 27. Shut Down by EN (Iout = 15 A)
Figure 28. Short Circuit during Normal
Operation (Iout = 0 A)
Figure 29. Short Circuit during Normal
Operation (Iout = 50 A)
Figure 30. Short FET’s Gate During Normal
Operation (Iout = 2.5 A)
Figure 31. DOC Index for Current Limit during
Normal Operation (Iout = 51.8 A)
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General Information
The NCP81295/6 is an N−channel MOSFET
co−packaged with a smart hotswap controller. It is suited for
high−side current limiting and fusing in hot−swap
applications. It can be used either alone, or in a paralell
configuration for higher current applications.
VDD Output (Auxiliary Regulated Supply)
An internal linear regulator draws current from the VINF
pin to produce and regulate voltage at the VDD pin. This
auxiliary output supply is current−limited to IDD_CL. A
ceramic capacitor in the range of 2.2 mF to 10 mF must be
placed between the VDD and GND pins, as close to the
NCP81295/6 as possible. The voltage difference between
VIN and VINF pin voltage should be within 0.4 V for better
CS/IMON performance. Small time constant R/C filter such
as 1 W/0.1 mF on the VINF pin is recommended.
ON Input (Device Enable)
When the ON pin voltage (VON) is higher than VSWON,
and no undervoltage (UVLO) or output switch faults are
present, the output switch turns on. When VON is lower than
VSWOFF, the output switch is off. If VON is between VPDOFF
and VSWOFF for longer than tPD_DEL, the output switches
off, and a pulldown resistance to ground, of RPD, is applied
to VOUT. In other words, there is behavior as follows:
•When VON < 0.8 V, FET turns off.
•When 0.8 V < VON < 1.2 V, VOUT will discharge with
15 mA.
•When VON > 1.2 V, FET turns on.
For standalone applications, the ON pin sources current
ION, which can be used to delay output switch turn−on for
some time after the appearance of input voltage by
connecting a capacitor from the ON pin to ground.
A bi−level control signal driving to ground can be biased
up with a resistive divider to produce ON input levels
between VPDOFF < VON < VSWON and VON > VSWON in
order to always apply the output pulldown when the output
switch is off.
SS Output (Soft−Start)
When the output switch first turns on, it does so in a
controlled manner. The output voltage (VOUT) follows the
voltage at the SS pin, produced by current ISS into a capacitor
from SS to ground. The duration of soft−start can be
programmed by selection of the capacitor value. In parallel
fuse applications, the SS pins of all fuses should be shorted
together to one shared SS capacitor. Internal soft−start load
balancing circuity will ensure the soft−start current is shared
between paralleled devices, so as not to stress one device
more than another or hit a soft start−current limit.
The soft−start capacitor value can be calculated by:
CSS = (tSS * ISS * AVSS)/VIN (where tSS is the target
soft−start time). The recommended range of tSS is 10 −
100 ms (see Table 5).
The typical CSS values for different tSS are listed below:
tSS (ms) CSS (nF) tSS (ms) CSS (nF)
10 47 60 270
20 82 70 330
30 120 80 330
40 180 90 470
50 220 100 470
The maximum load capacitor value NCP81295/6 can
power up depends on the device soft−start time. When
VIN =12V, R
CS = 2 kW, RLOAD = 2.4 W, their relationship
for different paralleled operations are shown as below chart
(above line device shuts down safely due to protection,
below line device powers up successfully without trigger
protection):
GOK Output (Gate OK)
The GOK pin is an open−drain output that is pulled low to
report the fault under the following conditions:
•VDD voltage is below UVLO voltage at any time.
•VON disabled and VDS_OK is false
(indicates a short from VIN to VOUT).
•VON disabled and VDG_OK is false
(indicates a short from GATE to VIN).
•VON enabled and VSS_OK is false at tSSF_END
(indicates VOUT < 90% after soft−start completes
− FET latches off for NCP81295/auto−retries for
NCP81296).
•VON enabled and VG is below VG_TH at tSSF_END
(indicates leakage on GATE in startup – FET latches off
for NCP81295/auto−retries for NCP81296).
•VON enabled and VG is below VG_TH after tGATE_FLT
(indicates leakage on GATE during normal operation
– FET latches off for NCP81295/auto−retries for
NCP81296).
•VON enabled and a current−limiting condition lasts
longer than tOC_LA
(FET latches off for NCP81295/auto−retries for
NCP81296).
NCP81295, NCP81296
www.onsemi.com
19
•VON enabled and device temperature is above TTSD
(indicates an over−temperature is detected − FET
latches off for NCP81295/auto−retries for NCP81296).
Usually GOK can’t be used as power good to indicate the
output voltage is in the normal range. Bringing VDD below
the UVLO voltage is required to release a latching condition.
IMON Output (Current Monitor)
The IMON pin sources a current that is AIMON (10 mA/A)
times the VOUT output current and plus IAZ_BIAS. A resistor
connected from the IMON pin to ground can be used to
monitor current information as a voltage up to VIM_CLMP
. A
capacitor of any value in parallel with the IMON resistor can
be used to low−pass filter the IMON signal without affecting
any internal operation of the device.
CLREF Pin (Current Limit and Over−Current Reference)
The CLREF pin voltage determines the current−limit
regulation point and over−current indication point via its
interaction with the CS pin voltage. The CLREF voltage can
be applied by an external source, such as a hot−swap
controller or D−to−A converter, or developed across a
programming resistor to ground by the CLREF bias current,
ICL. The recommended range of CLREF voltage is 0.2 −
1.4 V (see Table 5).
CS Input/Output (Current Set)
The CS pin is both an input and an output. The CS pin
sources a current that is ACS (10 mA/A) times the VOUT
current and plus IAZ_BIAS. This produces a voltage on the CS
pin that is the product of the CS pin current and an external
CS pin resistance to ground.
The voltage generated on VCS determines the D_OC
over−current indicator trip point and the current−limit
regulation point, via its interaction with the voltage on
CLREF pin.
When the voltage on the CS pin is higher than VOC_TH ,
D_OC is pulled low. If the CS pin voltage drops below
VOC_TH, the D_OC pin is released to and gets pulled high by
the external pullup resistor. D_OC transitions based on the
following formula:
(eq. 1)
IOUT +
VOC_TH)VENACT
RCS
*IAZ_BIAS
10 m
The VOC_TH trip point is based on a percentage of VCLREF
(86%).
During normal operation (VON > VSWON for longer than
tSS_END), if the voltage on the CS pin is above VCL_TH
(VCL_TH is clamped at VCL_MX if VCL_TH > VCL_MX), then
the gate voltage of the FET is modulated to limit current into
the output based on the following formula:
(eq. 2)
IOUT +
VCL_TH)VENACT
RCS
*IAZ_BIAS
10 m
The VCL_TH regulation point is equal to VCLREF.
During startup (VON > VSWON for less than tSS_END), the
current limit reference voltage is clamped according to the
following:
•When VOUT < 40% of VIN, VCL_TH = VCL_LO or
VCLREF (whichever is lower).
•When VOUT is between 40% and 80% of VIN,
VCL_TH = VCL_HI or VCLREF (whichever is lower).
•When VOUT exceeds 80% of VIN, VCL_TH = VCL_MX
or VCLREF (whichever is lower).
If a current limiting condition exists anytime for a
continuous duration > tCL_LA, then the device latches off
(NCP81295) or restarts (NCP81296).
The CS pin must have no capacitive loading other than
parasitic device/board capacitance to function correctly. The
recommended range of RCS is 1.8 − 4kW (see Table 5).
CS AMP OFFSET BIAS
NCP81295/6 use an auto−zero Op−Amp with low input
offset to sense current in FET with high−accuracy, and an
pre−biased offset current load, IAZ_BIAS is need for this
Op−Amp to always keep it to maintain this low input offset
(<100 mV). The internal IMON and CS current source
follow below relationship:
IOUT +
ICS *IAZ_BIAS
10 m(eq. 3)
and
(eq. 4)
IOUT +
IMON *IAZ_BIAS
10 m
For typical 5 mA IAZ_BIAS, there has 0.5 A positive off−set
in IOUT sense.
D_OC Output (Over−current Indicator)
The D_OC pin is an open−drain output that indicates
when an over−current condition exists after soft−start is
complete. When the voltage on the CS pin is higher than
VOC_TH, D_OC is pulled low. If output current drops below
VOC_TH, the D_OC pin is released and gets pulled high by
an external pullup resistor.
VTEMP Output (Temperature Indicator)
VTEMP is a voltage output proportional to device
temperature, with an offset voltage. The VTEMP output can
source much more current than it can sink, so that if multiple
VTEMP outputs are connected together, the voltage of all
VTEMP outputs will be driven to the voltage produced by
the hottest NCP81295/6. A 100 nF capacitor or greater must
be connected from the VTEMP pin to ground.
NCP81295, NCP81296
www.onsemi.com
20
Auto−Retry Restart (NCP81296)
Under certain fault conditions, the FET is turned off and
another soft−start procedure takes place. Between the fault
and the new soft−start, there is a delay of tDLY_RETRY
. The
protection features that use this hiccup mode restart are:
•Over−Current
•Short−Circuit Detection
•Over−Temperature
•Excessive Soft−Start Duration
•Gate Leakage
Protection Features
For the following protection features, the FET either
latches off (NCP81295) or the FET turns off and initiates a
restart (NCP81296), unless noted otherwise.
Excessive Current Limiting
If a current limiting condition exists anytime for a
continuous duration > tCL_LA, then the FET latches/restarts.
Excessive Soft−Start Duration
If VOUT < VOUTL_TH when tSSF_END expires, then the
FET latches/restarts.
Short Circuit Detection
If switch current exceeds ISC, the device reacts within tSC,
and the FET latches/restarts. The short−circuit current
monitor is independent of CS, CLREF, IMON and current
limit setting (cannot be changed externally).
Over−Temperature Shutdown
If the FET controller temperature > TTSD, then the FET
latches/restarts.
FET Fault Detection
The device contains various FET monitoring circuits:
•VIN to VOUT short, non−latching/non−auto−retry
condition. If the device is disabled and
VOUT > VDS_TH then GOK is pulled low and the
device is prevented from powering up. The device is
allowed to power up once VOUT < VDS_OK.
•GATE to VIN short, non−latching/non−auto−retry
condition. If the device is disabled and
GATE (Pin 8) > VDG_TH, then GOK is pulled low and
device is prevented from powering up. The device
allowed to power up once GATE < VDG_OK.
•GATE leakage − startup.
If (GATE – VINF) < VG_TH at tSSF_END, then GOK is
pulled low and FET latches/restarts.
•GATE leakage − normal operation.
If (GATE – VINF) < VG_TH for tGATE_FLT time after
the soft−start timer completes, then GOK is pulled low
and device latches/restarts.
FET SOA Limits
In−built timed current limits and fault−monitoring circuits
ensure the copackaged FET is always kept within SOA
limits.
Multiple Fuse Power Up
When multiple NPC81295 are paralleled together as
shown in Figure 4, the NPC81295s will turn on together.
Keeping the current through each switch within 1 A (typical)
helps to prevent overstress on each switching during
soft−start.
Due to NCP81296 is featured by Auto−Retry Mode
protection, please follow the below reference schematic
of NCP81296 for paralleled operation.
LQFN32 5x5, 0.5P
CASE 487AA
ISSUE A
DATE 03 OCT 2017
ÉÉÉ
ÉÉÉ
ÉÉÉ
SCALE 2:1
SEATING
NOTE 4
K
0.10 C
(A3)
A
A1
D2
b
1
17
32
E2
32X
9
24
L
32X
BOTTOM VIEW
TOP VIEW
SIDE VIEW
DA
B
E
0.10 C
PIN ONE
REFERENCE
0.10 C
0.05 C
C
25
e
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.30 MM FROM THE TERMINAL TIP.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
32
1
PLANE
DIM MIN MAX
MILLIMETERS
A1.20 1.40
A1 −−− 0.05
A3 0.20 REF
b0.18 0.30
D5.00 BSC
D2 3.30 3.50
E5.00 BSC
E2
e0.50 BSC
L0.30 0.50
3.30 3.50
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
0.50
3.60
0.30
3.60
32X
0.63
32X
5.30
5.30
NOTE 3
DIMENSIONS: MILLIMETERS
DETAIL A
ALTERNATE
CONSTRUCTION
L
DETAIL B
DETAIL A
e/2 A
M
0.10 BC
M
0.05 C
PITCH
RECOMMENDED
XXXXXXXX
XXXXXXXX
AWLYYWWG
G
1
GENERIC
MARKING DIAGRAM*
XXXXX = Specific Device Code
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
G= Pb−Free Package
*This information is generic. Please refer
to device data sheet for actual part
marking.
Pb−Free indicator, “G” or microdot “ G”,
may or may not be present. Some prod-
ucts may not follow the Generic Marking.
(Note: Microdot may be in either location)
DETAIL B
ALTERNATE
CONSTRUCTION
ÉÉÉ
ÉÉÉ
ÇÇÇ
A1
A3
L2 0.13 REF
DETAIL C
L2
DETAIL C
4 PLACES
L2
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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LQFN32, 5x5, 0.5P
© Semiconductor Components Industries, LLC, 2019 www.onsemi.com
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