Lattice Semiconductor Corporation * December 2003 * Volume 9, Number 2 In This Issue Lattice and Tyco Electronics Demonstrate 10Gbps SERDES at the CEATEC Exhibition Cascaded ispPAC(R) Power Manager ICs Manage Distributed Power Supplies New Service Pack Available for ispLEVER(R) v.3.1 FPSC Demonstrates 4G Fibre Channel Capability Lattice Offers Lead-Free Product Options Lattice Listens New Lattice Literature Lattice Introduces Low-Power, Field Programmable System-on-a-Chip for SPI4.2 Solutions New ORCA(R) ORSPI4 FPSC Offers Embedded SPI4.2 Core, 3.7Gbps SERDES, High-Speed Memory Controller + FPGA Lattice has announced the availability of the ORSPI4, a Field Programmable System-on-a-Chip (FPSC) that efficiently integrates ASIC and FPGA technologies. By combining the two approaches, Lattice has developed a more highly integrated, higher performance, lower cost and lower power SPI4.2 solution when compared to a full FPGA implementation. The pre-engineered ASIC block on the ORSPI4 contains two SPI4.2 interface blocks, a high-speed Quad Data Rate (QDR II) SRAM memory controller, 4 channels of 600 Mbps to 3.7 Gigabits per second (Gbps) SERDES, 8b/10b encoding/ Lattice's ORSPI4 FPSC is the lowest power decoding and other supporting logic. programmable SPI4.2 solution available today! Connected to the ASIC block is a high performance FPGA with over 16,000 FPGA SPI4.2 (System-Packet Interface, Level 4, logic elements plus embedded block RAM. Phase 2) is a recent system-level interface The ORSPI4 FPSC is the world's most highly standard that enables the development of integrated field programmable System-onflexible, scalable systems for a converged a-Chip targeted at line card applications for data and telecommunications infrastructure. high-speed communications systems in the Published in 2001 by the Optical InternetworkMetro space. ing Forum (OIF), the SPI4.2 standard supThe ORSPI4 FPSC is the tenth FPSC prod- ports the transmission of multiple protocols uct Lattice has introduced into the market, but at variable, high-speed data rates, including: the first targeted specifically at a growing line Packet-over-SONET/SDH (POS), OC-192, card segment. Analysts expect line card shipEthernet, Fast Ethernet, Gigabit Ethernet, ments to rise from 1.9 million ports in 2002 to 10 Gigabit Ethernet, and 10 Gigabit Fibre4.8 million ports in 2006, a 27% compound Channel SAN. SPI4.2 eliminates proprietary annual growth rate.1 Lattice will be there with ASIC-based or specialized network processor a highly-integrated device that will bridge interfaces traditionally used to support a broad network processors, MACs and framers to range of data rates and services. The benhigh-speed serial backplanes. (Please See Page 2) 1. Semiconductors: Technology and Market Primer 1.0, CIBC World Markets Inc., May 30, 2003 December 2003/Page 2 Bringing the Best Together (ORSPI4, Continued) efits are a common standards-based interface facilitating inter-connection between diverse devices from multiple manufacturers. Designed for packet transfer between a MAC device and a network processor or switch fabric, the SPI4.2 interface supports the aggregate bandwidths required of ATM and Packetover-SONET/SDH (POS) applications. SPI4.2 provides a common interface for 10 Gbps Wide Area Network (WAN), Local Area Network (LAN), Metro Area Network (MAN), and Storage Area Network (SAN) technologies, and it is ideal for systems that aggregate low-data rate channels into a single 10 Gbps uplink for long haul or backbone transmission. Lattice's ORSPI4 FPSC is unique in the programmable market as it embeds the SPI4.2 core in pre-characterized ASIC gates, unlike competitors who ship soft SPI4.2 IP cores which must be integrated into the overall design and face the uncertainties of FPGA place and route timing. Advantages Over FPGA-Only Approaches Unlike other SPI4.2 implementations for FPGAs, the ORSPI4 FPSC CML I/Os embeds all the high-speed functions in an ASIC core of over 1 million gates, allowing the FPGA gates to be used for design-specific bridging functions. Embedding these functions within a hard core assures performance, predictability and interoperability. This implementation also provides a big advantage in terms of total power consumption. Typical programmable-only FPGA IP cores consume upwards of 10W for one SPI4.2 interface implementation. In comparison, the ORSPI4 dissipates less than 2W per SPI4.2 implementation at 900 Mbps operation. This is a big advantage for power hungry 10 Gbps line cards. Line cards are getting "smarter" all the time, with the incorporation of NPUs and traffic management capabilities. This intelligence adds to board complexity with the potential for signal skew and strenuous layout constraints. The SPI4.2 spec defines a de-skew technique that relies on a built-in training sequence with userselectable repetition rate and duration. Referred to as dynamic alignment, this timing mode eliminates phase errors due to PCB traces of unequal lengths by continuously monitoring the data and adjusting the phase of the clock to align with it. This can be a challenging HSTL I/Os Quad SERDES with 8B/10B Encoder/Decoder LVDS I/Os Memory Controller SPI4.2 Transmit and SPI4.2 Receive Core Quad Channel MUX/deMUX 4 x 2K 4 x 2K DPRAM DPRAM System Bus Multi-Chan. Alignment + FIFO SPI4.2 Transmit and SPI4.2 Receive Core 4 x 2K 4 x 2K DPRAM DPRAM Clock Low-Speed Data 25-78 Mbits/s MicroProcessor Interface 128-bit Data + Control Paths ORCA Series 4 FPGA Gates User-Configurable I/Os ORCA ORSPI4 block diagram www.latticesemi.com problem for programmable devices, but Lattice's FPSC technology affords the opportunity to manage dynamic alignment with predictable and reliable ASIC technology. SPI4.2 Core Features The SPI4 interface blocks in the ORSPI4 FPSC contains these industry-best features: Multiple SPI4.2 Interface Cores * Two independent full-featured OIFcompliant SPI4.2 interfaces for >20 Gbps bandwidth. * Supports quarter-rate mode for 2.5 Gbps operation Data Alignment * Supports both static and dynamic alignment schemes * Supports dynamic bit de-skew over 16 phases of clock * Supports receive clock aligned or clock centered transmit data in static mode. Parity Generation and Checking * DIP-2 and DIP-4 parity generation and checking embedded in ASIC Calendar Support * Embedded 1K deep main and shadow calendar built-in, supports scheduling up to 256 ports and hitless bandwidth provisioning User Design Interface * User friendly FIFO interface from ASIC to FPGA logic for clock domain transfer and ease of design * Support of up to four user clock domains and 32 FIFOs per Tx and Rx Signal Integrity * Dedicated LVDS drivers and receivers with center tap option increases performance and reduces jitter Flow Control Flexibility * An embedded set of write and read port descriptor memories supports a flexible flow control interface for each SPI4.2 port Low Power * Less than 2W of power for each SPI4.2 interface at 900 Mbps operation with dynamic alignment * 1.5W for each SPI4.2 interface at 700 Mbps operation with static alignment (Please See Page 3) December 2003/Page 3 Bringing the Best Together www.latticesemi.com (ORSPI4, Continued) Packet Buffering * Embedded high-speed memory controller for interface to external QDR II SRAM for line-rate packet buffering The SPI4.2 cores on the ORSPI4 FPSC provide dual 10 Gbps Physical-to-Link Layer interfaces in conformance to the OIF-SPI4-02.0 specification. Each block provides a bi-directional interface with an aggregate bandwidth of 14.4 Gbps. This is achieved by using 16 LVDS pairs each for transmit and receive channel operating at a data rate of 900 Mbps with a 450 MHz DDR clock. Both static and dynamic alignment are supported at the receive interface. DIP-4 and DIP-2 parity generation and checking are also supported. 8K bytes of data buffering is provided by embedded DualPort RAM for both transmit and receive in each SPI-4.2 core. Internal 1K deep main and shadow calendars supports scheduling of up to 256 ports. The Transmit and Receive Status FIFOs can also store flow control information for up to 256 ports, the maximum specified in the SPI-4.2 specification. In order to provide wire-speed packet processing, the ORSPI4 also contains an independent Memory Controller Block that provides data buffering between the FPGA logic and external memory and supports a throughput of greater than 20 Gbps. Data is transferred to and from memory through two sets of 36-bit unidirectional data lines (one read, one write) operating at up to 200 MHz DDR (400Mbps). A set of 72 data signals is available to transfer data across the core-FPGA interface and allows the system to utilize the bandwidth available with second-generation QDR II SRAMs. Of the 72 data signals, 8 signals can be used either for parity or data. A second memory controller can also be added in the FPGA section to provide two independent line-rate buffers if needed. High Speed SERDES I/O The high-speed SERDES block supports four serial links, each operating at up to 3.7 Gbps (2.96 Gbps data rate with 8b/10b encoding and decoding), to provide four full-duplex synchronous interfaces with built-in receiver Clock and Data Recovery (CDR) and transmitter pre-emphasis. The SERDES block is identical to that proven in Lattice's ORT82G5 and ORT42G5 FPSCs, supporting embedded 8b/ 10b encoding/decoding as well as link state machines for both 10 Gbps Ethernet and Fibre Channel. The state machines are IEEE P802.3ae/D4.01 XAUI compliant and also support FC (ANSI X3.230: 1994) link synchronization. The SERDES in the ORSPI4 FPSC contains industry-best performance with the following features: Widest Range of Programmable Data Rates * 4 channels with industry-leading performance from 0.6 Gbps to 3.7 Gbps Multiple Standards Compliance * Fibre Channel (1G, 2G), XAUIEthernet (10G) and XAUI-FC (10G) Rx Jitter Tolerance * 0.75UI p-p typical, 0.65 UI p-p worst case, exceeds XAUI and Fibre Channel specifications (@ 3.125 Gbps) Tx Total Jitter * 0.17UI p-p typical, 0.24 UI p-p worst case, exceeds XAUI and Fibre Channel specifications (@ 3.125 Gbps) Low Power per SERDES Channel * 225 mW worst case, including I/O buffers @ 3.125 Gbps Fast Locking Times * Bit Realignment 300 nanoseconds (938 bit times @ 3.125 Gbps) nominal Transmitter Output (CML) * Full-amplitude mode: 0.8V p-p Minimum * Half-amplitude mode: 0.4V p-p Minimum Demonstrated Drive Length * Over 40 inches (100cm) of FR-4 backplane The ORSPI4 FPSC also contains a dedicated microprocessor interface, a 32-bit internal system bus (and 4 bits parity), and built-in system registers that act as the control and status center for the SPI4.2, SERDES, and memory controller blocks. The FPGA portion of the device can also be configured through this interface. Availability The ORSPI4 FPSC in the 1036 fpSBGA (1mm ball pitch, thermally enhanced fine pitch ball grid array) package is currently shipping. The device will also be offered in an 1156 fpSBGA package without the SERDES channels. The device is supported by Lattice's ispLEVER v.3.1 design software, a dedicated design kit, and popular third-party synthesis, simulation, and verification tools. ORSPI4 Attributes Device ORSPI4 FPGA Usable Gates PFUs LUTs EBR RAM Bits 471-899K 2,024 16,192 148K Packaging/ User I/Os I/O Compatibility 1036 fpSBGA / 496 I/Os 1.5/1.8/2.5/3.3 1156 fpBGA / 352 I/Os SERDES Channels Max. SERDES Rates SPI4.2 Cores 4 3.7Gbits/s 2 December 2003/Page 4 Bringing the Best Together www.latticesemi.com Lattice and Tyco Electronics Demonstrate 10 Gbps SERDES Across High Speed Cable Interconnect and FR-4 Backplane Solutions Lattice and Tyco Electronics joined forces recently at the Combined Exhibition of Advanced Technologies (CEATEC) in Tokyo to demonstrate the interoperability of Lattice's XPIOTM 110GXS physical layer electronic transceiver with Tyco's FR-4 backplane and High-Speed long cables. The demonstration utilized Lattice's XPIO 110GXS 16-bit, 9.953 to 10.709 Gbps transceivers and Tyco's HM-Zd based QuadRouteTM backplane and ZFP-I/O high speed cables in conjunction with passive equalizer and active equalizer device. "Using Tyco Electronics' interconnect solutions with our XPIO 110GXS to actually demonstrate signals driving over 16 inches (~406mm) and 30 inches (~762mm) of FR-4 backplane and/or at least 7 meters of ZFP-I/O cable assembly at speeds up to 10 Gbps NRZ is the best way to prove to customers the quality and reliability of our high-speed physical layer solutions," said Stan Kopec, Vice President of Marketing for Lattice. "This demonstration is a key step in bringing cost-effective 10 Gbps cable interconnect and electrical backplane solutions to market," added Kopec. Tyco Electronics Circuit and Design engineers have optimized the channel losses of a backplane based on highspeed Z-PACKTM HM-Zd connectors with Lattice's XPIO 110GXS as an active interconnect using combined passive and active equalization technique. In addition, a high-speed cable assembly based on the ZFP-I/O connector was optimized to achieve reliable transmission over a distance of 7 meters using similar combined passive and active equalization technique. Demo Configuration A 9.953 Gbps serial NRZ-PRBS 211-1 bit stream was injected into the Lattice XPIO SERDES using a Pulse Pattern Generator. The XPIO then hooked to one end of a 7 meter long "ZFP-I/O" cable assembly through interface boards. A second XPIO SERDES was hooked to the other end of the cable through combined passive and active equalization. The XPIO outputs were individually connected to the DSO and BERT as single ended signals. "We demonstrated a reliable and error free (BER better than 10-14) system interconnect at 9.953 Gbps that ran during the entire 5 days of the show," said Doron Lapidot, Director, Circuit and Design, Tyco Electronics, Asia/Pacific and EMEA. "This is a breakthrough in 10G serial link NRZ-coded system interconnect since the solution also demonstrated full interoperability," added Lapidot. "In today's competitive market, this cost effective and reliable solution is an excellent example of how our customers can utilize a flexible solution for system interconnect based on a combined solution," stated Minoru Okamoto, Vice President, Communications, Computer & Consumer Electronics of Tyco. providing similar performance and FPGA density. The ORSO82G5 includes eight backplane transceiver channels, each operating at up to 2.7 Gbps data rate providing a full-duplex synchronous interface with built-in Clock/Data Recovery (CDR) and more than 400K FPGA gates. The ORSO82G5 contains an embedded core for SONET data scrambling and descrambling, streamlined SONET framing, transport overhead handling, cell insertion and extraction, idle cell insertion/deletion plus the programmable logic to terminate the network into proprietary systems. All SONET functionality is hidden from the user and no prior networking knowledge is required. CEATEC, the largest electronics and IT show in Asia Pacific, was held October 7-11, 2003. Lattice ORCA FPGAs Lattice has developed the industry's broadest and fastest programmable device family for high-speed serial backplane data transmission. The ORT82G5 integrates eight backplane transceiver channels, each operating over a range from 600 Mbps to 3.7 Gbps with a full duplex synchronous interface with built-in Clock and Data Recovery (CDR). Also included are embedded XAUI and Fibre-Channel state machines, bypassable 8B/10B encoding/decoding support plus multi-channel alignment capability without using any FPGA gates. The device features more than 400K FPGA gates and up to 372 general-purpose programmable I/O pins. The new ORT42G5 contains four backplane transceiver channels Lattice and Tyco Electronics demonstrated 10Gbps SERDES at the CEATEC Exhibition in Tokyo December 2003/Page 5 Bringing the Best Together www.latticesemi.com Cascaded ispPAC Power Manager ICs Manage Distributed Power Supplies Today's circuit board power supply architectures are moving away from the traditional approach that uses isolated power supplies to source all board power supply voltages. Traditional power supplies are bulky and costly due to the magnetics used for isolation. As a result, newer architectures have resorted to two-stage power conversion. The first stage provides isolation between the backplane and a local circuit board supply bus. The second stage, powered by the local bus, generates the required power supply voltages. Because the second stage does not provide isolation, this architecture is smaller for a given output current. This method of distributing the power supply functions is known as the Distributed Power Architecture (DPA). coordinated manner) becomes more complex since the designer must not only control the power supply sequence for a device, but must also ensure that supplies of equal voltages on the circuit board are turned on and off at the same time. Distributed Power Supply Sequence Synchronization: Designers often use multiple, same voltage POLs powering different ICs to minimize coupling of power supply noise. At the circuit board level, all these samevoltage supplies need to be turned on together while conforming to each device's power-up sequence specification. For example, the I/O voltage of the CPU, an ASIC, etc., needs to be turned on simultaneously while not violating the CPU and the ASIC's sequence specification. This is further complicated by the fact that some devices require their lowest supply to be turned on first followed by the higher voltage while another device might require its highest voltage to be turned on before the lower voltages. Additionally, most devices require the power supply be removed in the Managing Power Supplies in a Distributed Power Architecture While the use of DPA provides cost effective solutions, the management of these supplies (e.g., monitoring for faults, controlling the sequence in a - 48V Backplane 3.3V POL Intermediate Bus (12V) Isolatted Power Supply pp y 3.3V 2.5V POL 2.5V POL 1.2V 3.3V 2.5V ASIC Good_3V3 Good_2V5 1.3V Good_1V2 En_3V3 En_1V2n3 FPGA & Other ICs on Circuit Board 2.5V Good_1V3 1.3V POL En_2V5 3.3V CPU 1.2V Good_3V3 Good_2V5 Good_1V5 En_1V5 En_2V5 CARD_Reset En_3V3 1.5V Digital Control Bus Expandable to Mezzanine Card CLLK_250k RESET Watchdog_Trigger PWR 0 PWR 1 Power1208 CPU_Reset Brown_Out_Interrupt Power_Good Cascaded ispPAC Power Manager devices in an intermediate bus architecture reverse order of application. The actual sequence of power supply turn-off can depend on the event that initiated the power supply turn-off sequence. Power supply sequencing is further complicated when the main card also has a plug-in mezzanine card, which is powered by the intermediate bus. Mezzanine card sequencing should be synchronized with the main card and the power management function on the main card should automatically include monitoring voltages of the mezzanine card. Supervisory Signal Generation Centralized Monitoring: All the supplies on the circuit board should be monitored continuously for low-voltage or high-voltage conditions. If a supply becomes faulty, the processor should be interrupted to save critical data and proceed to Phase 5 to turn off the power supplies. Centralized Reset Control: Often the CPU reset signal is stretched (for about 100 ms) after its supplies are turned on to facilitate the execution of built-in self-test. Also, in-order to prevent the processor mis-execution of instructions, the CPU reset signal should also be generated when a fault develops in any supply powering the devices connected to its data bus. This requires the reset signal be generated from the supervisor chip that monitors all the supplies. Additionally, during Phase 4, the input reset signal activation or watchdog timer failure results in resetting the processor. Scaling: The power supply monitoring function and supervisory signal generation should not only cover the supplies on the main circuit board, but should also monitor the supplies on the mezzanine cards. The operation in Phases 3 and 4 should be extended to include the mezzanine cards. Power Management Using ispPAC Power Manager The figure at left shows an example Intermediate Bus Architecture (IBA) arrangement. Power management is implemented using the ispPAC(Please See Page 6) December 2003/Page 6 (ispPAC Power Manager, Continued) POWR1208 (Power1208) and ispPACPOWR604 (Power604) devices from Lattice in a master-slave configuration with the Power1208 as master and the Power604 as slave. The isolated power supply, powered by the backplane -48V, sources a 12V Intermediate Bus (IB). There are two types of supplies: Point-Of-Load supplies shown as POLs (3.3V, 2.5V, 1.2V, and 1.3V) located close to the ASIC and the CPU and centralized supplies (3.3V, 2.5V, and 1.5V). The design uses separate POLs to power 2.5V and 3.3V to provide clean and monotonic supplies, as required by the CPU and ASIC devices. The Power604 is positioned close to the ASIC to monitor 1.3V to improve precision in monitoring. This article, for convenience refers to the supplies monitored by Power604 as POLs, and those monitored by Power1208 as central supplies. The master and slave Power Manager devices operate from the 12V supply. Card-level power management functions are coordinated by means of a Digital Control Bus between the Power1208 (master) and Power604 (slave). This architecture can be expanded to manage additional supplies by adding more ispPAC Power Manager devices on this Digital Control bus. For example, the mezzanine card can use this bus to synchronize its power supply management with the main card. No modifications are required for either the Digital Control Bus or the master Power1208 device. The Digital Control bus signals consist of Clock, Reset, PWR0, and PWR1 sourced by the master Power1208 and Response generated by the slave Power604 device. The master Power1208 synchronizes power supply sequencing across the circuit board, through the Digital control bus, while monitoring all supplies both during supply sequencing and normal operation. Centralized supervisory signal generation is controlled by the master Power1208 by logically combining the Card_reset signal, watchdog timer input and the status of all power supplies on the circuit board. Bringing the Best Together The design can be expanded to manage a larger number of power supplies either by using another Power1208 device as a slave or by using additional slave devices (either Power1208 or Power604), all controlled by the digital control bus. The algorithm on the master remains the same irrespective of the number of slave devices. However, the slave device's algorithm can be changed depending on the power supply domain. For example, with a slave Power1208, full 5-phase power management can be implemented for a mezzanine card with its own CPU reset, brownout interrupt, etc., while powering up/down synchronously with the main card. The entire design is implemented using the PAC-Designer(R) software, Lattice's interactive, intuitive, PCbased point-and-click software tool. This tool is available for download from www.latticesemi.com, free of charge. www.latticesemi.com Conclusion The ispPAC Power Manager's unique architecture combines PLDs and programmable analog circuits that can be cascaded to provide reliable power management solutions for a distributed power architecture. The resulting power management solution is both flexible and scalable. This arrangement operates reliably under noisy power supply conditions and across various plug-in mezzanine cards. This reliability is due to the ruggedness of the Power1208 and Power604 devices, their voltage monitoring precision, and reliable handshake mechanisms through the digital control bus. The LogiBuilder section of the PACDesigner software further simplifies designs by providing a wide variety of power management functions through a simple and intuitive point-and-click mechanism. ispPAC Power Manager Attributes Feature Programmable Sense Inputs Power604 Power1208 6 12 1V to 5.7V 1V to 5.7V Supervisory Inputs 4 4 FET Drivers/Digital Inputs -- 4 Reprogrammable Timers 2 4 CPLD Macrocells 8 16 2.25 to 5.5V 2.25 to 5.5V 44 TQFP 44 TQFP Sense Voltage Range Power Supply Voltage Packaging New Service Pack Available for ispLEVER v3.1 Lattice provides regular service pack updates to the ispLEVER design tool to ensure users always have access to the latest design tools and silicon products. A new update for ispLEVER v.3.1, called Service Pack 01, is now available for download. The easiest way to download and/or install Service Pack 01 is to use the ispUPDATETM utility, included with ispLEVER v.3.1. Simply run ispUPDATE, and follow the on-screen instructions. Alternatively, you can download Service Pack 01 directly from the Lattice web site at www.latticesemi.com/software. Select the ispLEVER configuration you're using, and choose "Downloads" from the resource box. Service Pack 01 updates device libraries and databases for new Lattice product families such as the ispXPLDTM 5000MX, ispGDX2TM, ispXPGA(R) and ORCA FPSC design kits. Service Pack 01 also includes a number of updates and enhancements to features and algorithms used in many parts of the ispLEVER design tool set. December 2003/Page 7 Bringing the Best Together www.latticesemi.com Lattice Field Programmable System-on-a-Chip Demonstrates 4G Fibre Channel Capability Lattice has introduced its ORT82G5 Field Programmable System-ona-Chip (FPSC) that demonstrates the ability to pass error-free data at 4.25Gigabits/sec (Gbps) across 6 inches of printed circuit board (PCB) and 26 inches of coaxial cable, making it the industry's first programmable 4G Fibre Channel-based backplane transceiver in production. In June of this year, the Fibre Channel Industry Association (FCIA) voted in favor of extending 4Gbps Fibre Channel (4GFC) from an intra-cabinet storage device interconnect into switched Storage Area Network (SAN) fabrics. 4GFC serves as a bridge between the 10Gbps future and current 1-2Gbps systems. "Lattice's superior SERDES technology, systems knowledge and programmable technology expertise continue to provide effective solutions for high performance applications like storage arrays and next-generation storage networks," said Stan Kopec, vice president of corporate marketing at Lattice. "The ORT82G5 is productionproven, and we have been working with leading-edge vendors in the SAN market to verify the 4GFC capability of the device. All our tests confirm the superior speed, flexibility, and low power consumption of our solution. Our customers are getting a real jump on the 4GFC market with a proven device ready for design and production now," he added. Lattice's ORT82G5 can support up to 4 SERDES channels running at over 4.3Gbps, an embedded Fibre Channel Physical Coding Lattice's ORT82G5: the industry's fastest Sublayer (PCS) core with 8b/ device for high-speed serial backplane 10b encoding/decoding and data transmission link state machine, and over 10,000 programmable logic elements devices optimized for SONET/SDH, (equivalent 4-input lookup tables) in its Gigabit Ethernet, System Packet general-purpose FPGA section for the Interface (SPI) 4.2 and optical module easy integration of customer-specific interface applications. FPSCs offer intellectual property (IP). The device system designers the convenience also features 372 and time-to-market advantages of general-purpose propre-engineered, pre-characterized Selectable High-Speed Data Rates - 1.25 / 2.5 / 3.125 Gbits/sec grammable I/O pins standard interface functions combined supporting a variety with the flexibility of FPGA logic for the CML I/Os CML I/Os of advanced interface implementation of differentiated, apstandards including plication-specific features. Quad Serializer-DeSerializer Quad Serializer-DeSerializer HSTL, SSTL, GTL+ For additional information on the with 8B/10B Encoder/Decoder with 8B/10B Encoder/Decoder and others. A low 335 4GFC characteristics of the ORT82G5 milliwatts of power is SERDES technology, see techniconsumed per chancal note TN1045, ORT82G5 4.25 Quad Channel Quad Channel MUX/deMUX MUX/deMUX nel with the SERDES Gbit/s Fibre Channel Testing Results Microrunning in excess of available on the Lattice web site at processor Multi-Chan. Multi-Chan. 4.25Gbps. www.latticesemi.com. Interface Alignment Alignment and Lattice's FPSC deThe ORT82G5-3BM680C SERDES + FIFO + FIFO Registers vices are high-perfortransceiver is currently shipping. 2:1 Data 2:1 Data mance field programThe device is supported by Lattice's Selector Selector mable devices that ispLEVER version 3.1 design soft4k x 36 4k x 36 Dual-Port Dual-Port combine optimized ware, a dedicated design kit, HSPICE RAM RAM embedded core SERDES I/O buffer models to support Clock Parallel Data Parallel Data Clock System Bus functions together backplane simulation and popular with flexible, generalthird-party synthesis, simulation, and ORCA Series 4 FPGA Gates purpose FPGA logic. verification tools. Lattice currently has User-Configurable I/Os 10 FPSC devices available, including ORCA ORT82G5 block diagram December 2003/Page 8 Bringing the Best Together www.latticesemi.com Lattice Offers Lead-Free Product Options Due to increased worldwide environmental concerns, the need for lead-free solutions in electronic components and systems is receiving increasing attention within the semiconductor and electronics industries. Lattice has been actively tracking and is fully supportive of the various industry efforts throughout the world to phase out the use of lead and other undesirable elements from electronic equipment materials and manufacturing processes. Lattice is a leader in the development of lead-free and "green" (halogen-free) packaging solutions. Lattice currently offers an extensive list of standard products in lead-free packaging. Halogen-free "green" package options will become available later in 2004. Lattice is working to eliminate hazardous and toxic materials from its products, in compliance with the European Parliament Directive entitled "Restrictions on the use Of Hazardous Substances" (RoHS) as well as other international standards. Lattice has developed an extensive list of banned and restricted materials. Lattice's manufacturing supply partners are aware of these requirements and are aggressively working to eliminate these materials from all Lattice products. Lattice's Lead-Free Solutions Lattice has qualified a wide variety of package types in lead-free configurations. These qualified packages include the Thin Quad Flat Pack (TQFP), Plastic Ball Grid Array (PBGA), Fine Pitch BGA (fpBGA), Chip Scale BGA (csBGA) and Quad Flat-pack (QFN) packages. To better facilitate the industry transition to lead-free PLDs, Lattice offers the following broad assortment of standard, off-the-shelf, lead-free product families. manufacturing methodologies. This backward compatibility allows users to surface mount lead-free packages onto lead-based PCBs and/or use lead-free packaging with leaded solders. Users can now procure a single, lead-free component from Lattice and use it in either a leaded or lead-free manufacturing environment without any issues. This greatly simplifies inventory management challenges as users migrate to lead-free manufacturing. Lattice is currently evaluating BGA packaging for backward compatibility. For more information on Lattice's lead-free product offering, including device data sheets, visit the Lattice web site at www.latticesemi.com. Backward Compatible LeadFree Package Options All of Lattice's lead-free TQFP and QFN packages are "backward compatible" with conventional leaded Lead-Free Device Offerings from Lattice Product Family Device Family Device Family Description ispXPGA ispXPGA-B ispXPGA-C 3.3V/2.5V Non-volatile, Infinitely Reconfigurable FPGA 1.8V Non-volatile, Infinitely Reconfigurable FPGA ORCA 4 FPSC ORT42G5 ORT82G5 ORSO82G5 ORT8850H/L ORLI10G 1.5V ORCA 4 FPGA Plus Embedded High-Performance ASIC Core ispMACHTM 4000 ispMACH 4000V ispMACH 4000C 3.3V SuperFASTTM Low-Power CPLD 1.8V SuperFAST Low-Power CPLD ispMACH 4000Z 1.8V SuperFAST Zero-Power CPLD ispXPLD 5000MX ispXPLD 5000MV ispXPLD 5000MC 3.3V High Density CPLD + Memory 1.8V High Density CPLD + Memory ispGAL(R) ispGAL22V10AV 3.3V Industry's Fastest and Smallest CPLD ispPAC Power Manager ispPAC-POWR1208 Power Supply Sequencing and Monitoring ispPAC-POWR604 *3.3V ispMACH 4000V only. Backward Compatible Packaging Standard Packaging 256 fpBGA 516 fpBGA 680 fpSBGA 900 fpBGA 484 fpBGA 680 fpBGA 44 TQFP 48 TQFP 100 TQFP 128 TQFP 144 TQFP* 176 TQFP 256 fpBGA 48 TQFP 100TQFP 176TQFP 56 csBGA 132 csBGA 256 fpBGA 484 fpBGA 672 fpBGA 32 QFN 44 TQFP December 2003/Page 9 Lattice Listens What's new in ispLEVER v.3.1? ispLEVER v.3.1 has added support for the following new devices: * The low power ispMACH 4000Z in the 256-macrocell density * The flexible ispXPLD architecture in the 768-macrocell density In addition, the following software modules have been updated: Project Navigator: * Revision control support for CPLD devices * LPC (Lattice Parameter Configuration) source file support. This feature allows you to generate a component, such as a counter or a RAM block, as a parameterized module that can be imported directly into your source tree Preference/Constraint Editor: * Fully integrated Preference Editor for the ORCA FPGA design flow * The Nodal Constraint Editor allows you to open a constraint editor to set nodal level constraints on a node-by-node basis The ispLEVER Release Notes describes all of the new features included with this release in greater detail. How can Lattice's programmable technology help with some of the security issues I'm facing today? The most common FPGA technology in use today is SRAM-based, which is fast and re-configurable, but must be re-configured every time the FPGA is powered up. Typically, an external PROM is used to hold the configuration data for the FPGA. The link between the PROM and FPGA represents a significant security risk. Configuration data is exposed and vulnerable to piracy while the device powers up. Using a non-volatile FPGA eliminates this security risk. Traditionally, non-volatile FPGAs were based on Antifuse technology that is secure, but very expensive to use due to its one-time programmability and the associated increased manufacturing costs. Bringing the Best Together www.latticesemi.com Information Need Resource Technical Support Tel: 1-800-LATTICE or (408) 826-6002 e-mail: techsupport@latticesemi.com Software and Literature Download http://www.latticesemi.com European Literature Fulfillment Tel: +44 (0)117 934 1600 FAX: +44 (0)117 934 1601 e-mail: euro.lit@latticesemi.com Lattice offers a superior non-volatile FPGA solution with the ispXPGA family of FPGAs. The ispXPGA and ispXPLD families utilize Lattice's ispXP technology, which combines non-volatile cells and SRAM cells on the same chip. The non-volatile memory is used for storing the device configuration securely on the chip. The SRAM memory holds the working configuration after power-up. The technology used in the ispXPGA family of FPGAs allows for high security of the configuration pattern while delivering all the benefits of infinitely reconfigurable SRAM memory. Can I control negative power supplies with the ispPAC-POWR1208? Yes, although doing so requires a few external components to translate the ispPAC-POWR1208's positive-voltage control signal to negativevoltage signals. One of the simplest general-purpose ways to do this is to use a device called an optocoupler, as shown in the circuit below. In this circuit, when the ispPACPOWR1208's output goes low, it turns on the optocoupler's LED, which turns on the associated output transistor. The optocoupler's emitter output will then pull MOSFET Q1's gate positive towards ground. Because the MOSFET's source is sitting at -5V, this turns it on, and provides -5V to the load. When the ispPAC-POWR1208's output goes high, the optocoupler turns off, and R2 pulls the MOSFET's gate back down to -5V, shutting it off. Because the ispPAC-POWR1208's outputs are used in open-drain mode, this circuit will also work with the ispPAC-POWR604. This circuit works because there is no direct electrical connection between the optocoupler's inputs and outputs. This permits the output to be controlled by the input even when they are at widely differing voltages. Depending on the type of optocoupler used, it is possible to control loads that can be at hundreds or even thousands of volts in relation to the control signal. For this reason optocoupler interface circuits are also useful when controlling the +/-48V power supplies frequently used in telecommunications circuits. +5V U1 4N28 ispPAC-POWR1208 R1 1k R2 10k -5V Supply Q1 Switched -5V Supply LOAD An optocoupler can be used to convert the Power1208's positive voltage control signals to negative signals. December 2003/Page 10 Bringing the Best Together www.latticesemi.com Lattice Literature The following is a list of recently published documents, including descriptions and ordering numbers. On-line versions of these technical publications are available on the Lattice web site at www.latticesemi.com. Some of these documents are also available in print. To order print versions, call your local Lattice representative or Lattice's Literature Distribution Department at 1-888-477-7537 (outside the U.S. and Canada, call 503-268-8000) or order by FAX at 503-268-8556. In Europe, contact Lattice's European Literature Fulfillment Department by phone at +44 (0)117 934 1600, by FAX at +44 (0)117 934 1601 or by e-mail at euro.lit@latticesemi.com. General Information Title Description Web Print Order # ORSPI4 Product Brief Introduction to the ORSPI4 that includes two embedded SPI4.2 cores, 3.7Gbps SERDES, memory controller and FPGA. I0165 ORSPI4 White Paper Technical overview of Lattice's new ORSPI4 product. -- -- Consumer Solutions Brochure Describes Lattice's broad offering of PLDs that address the needs of consumer electronics designers. I0166 Lead-Free/Green Packaging Brochure Overview of Lattice's lead- and halogen-free package offerings. -- -- SONET White Paper Backplane solutions for next generation SONET line cards. -- -- ispXPGA Evaluation Board User's Guide Description of operation for the ispXPGA Evaluation Board. -- -- ispXPLD Evaluation Board User's Guide Description of operation for the ispXPLD Evaluation Board. -- -- Web Print Order # -- -- Data Sheets Title ORSPI4 Data Sheet Description Dual SPI4.2 interface and high-speed SERDES FPSC. Technical Notes/Application Notes Title Web Print Order # ORT82G5 4.25 Gbit/s Fibre Channel Testing Results ORT82G5 operation is demonstrated through a series of laboratory tests, eye diagrams, jitter performance and backplane performance. Description -- -- ORSPI4 PCB Design Guidelines for SPI4.2 and QDR Memory Controller Interfaces Guidelines for using the ORSPI4 FPSC, such as routing PCB signals, generating and supplying reference voltages and terminating signals. -- -- Controlling and Monitoring PowerOne Bricks and SIPs with the Lattice ispPAC-POWR1208 Details the interface between the ispPAC-POWR1208 and two different Power One DC-to-DC converters. -- -- Intellectual Property Web Print Order # PCI Data Sheet & User's Guide Title Both documents updated to include several new factory-tested configurations that are available now for free evaluation. Description -- -- UTOPIA Level 3 IP Cores Data Sheets & Users' Guides Updated to include factory-tested configurations available now for use with Lattice ispXPGA and ORCA Series 4 devices. -- -- Tri-Speed Ethernet Media Access Controller Data Sheet & User's Guide This core is available for use in either 10/100 or 1G modes in Lattice's ORCA Series 4 technology. -- -- ispLeverCORETM Evaluation Tutorials How to evaluate a Lattice ispLeverCORE product. This tutorial available in three versions: the "stand-alone quick-start" version, the detailed version and an interactive version. -- -- Copyright (c) 2003 Lattice Semiconductor Corporation. Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L (stylized), L (design), Lattice (design), E2CMOS, In-System Programmable, In-System Programmability, ISP, ispGAL, ispGDX2, ispLEVER, ispLeverCORE, ispMACH, ispPAC, ispUPDATE, ispXPGA, ispXPLD, LogiBuilder, MMI (logo), ORCA, PAC-Designer, Silicon Forest, SuperFAST, V Vantis (design), Vantis, (design) and XPIO are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United States and/or other countries. ISP is a service mark of Lattice Semiconductor Corporation. Synplicity and Synplify are registered trademarks of Synplicity, Inc. Mentor Graphics, LeonardoSpectrum and ModelSim are either registered trademarks or trademarks of Mentor Graphics Corporation. Other product names used in this publication are for identification purposes only and may be trademarks of their respective companies. LatticeNEWS is a publication of Lattice Semiconductor Corporation, 5555 N.E. Moore Ct., Hillsboro, OR 97124 USA Order #: NL0106