Lattice Semiconductor Corporation • December 2003 • Volume 9, Number 2
In This Issue
Lattice and Tyco
Electronics Demonstrate
10Gbps SERDES at the
CEATEC Exhibition
Cascaded ispPAC®
Power Manager ICs
Manage Distributed
Power Supplies
New Service Pack
Available for ispLEVER®
v.3.1
FPSC Demonstrates 4G
Fibre Channel Capability
Lattice Offers Lead-Free
Product Options
Lattice Listens
New Lattice Literature
Lattice Introduces Low-Power, Field
Programmable System-on-a-Chip for
SPI4.2 Solutions
New ORCA® ORSPI4 FPSC Offers Embedded SPI4.2 Core,
3.7Gbps SERDES, High-Speed Memory Controller + FPGA
(Please See Page 2)
Lattice has announced the availabil-
ity of the ORSPI4, a Field Program-
mable System-on-a-Chip (FPSC)
that efciently integrates ASIC and
FPGA technologies. By combining
the two approaches, Lattice has
developed a more highly integrated,
higher performance, lower cost and
lower power SPI4.2 solution when
compared to a full FPGA implemen-
tation. The pre-engineered ASIC
block on the ORSPI4 contains two
SPI4.2 interface blocks, a high-speed
Quad Data Rate (QDR II) SRAM
memory controller, 4 channels of
600 Mbps to 3.7 Gigabits per second
(Gbps) SERDES, 8b/10b encoding/
decoding and other supporting logic.
Connected to the ASIC block is a high
performance FPGA with over 16,000 FPGA
logic elements plus embedded block RAM.
The ORSPI4 FPSC is the world’s most highly
integrated eld programmable System-on-
a-Chip targeted at line card applications for
high-speed communications systems in the
Metro space.
The ORSPI4 FPSC is the tenth FPSC prod-
uct Lattice has introduced into the market, but
the rst targeted specically at a growing line
card segment. Analysts expect line card ship-
ments to rise from 1.9 million ports in 2002 to
4.8 million ports in 2006, a 27% compound
annual growth rate.1 Lattice will be there with
a highly-integrated device that will bridge
network processors, MACs and framers to
high-speed serial backplanes.
SPI4.2 (System-Packet Interface, Level 4,
Phase 2) is a recent system-level interface
standard that enables the development of
exible, scalable systems for a converged
data and telecommunications infrastructure.
Published in 2001 by the Optical Internetwork-
ing Forum (OIF), the SPI4.2 standard sup-
ports the transmission of multiple protocols
at variable, high-speed data rates, including:
Packet-over-SONET/SDH (POS), OC-192,
Ethernet, Fast Ethernet, Gigabit Ethernet,
10 Gigabit Ethernet, and 10 Gigabit Fibre-
Channel SAN. SPI4.2 eliminates proprietary
ASIC-based or specialized network processor
interfaces traditionally used to support a broad
range of data rates and services. The ben-
Lattice’s ORSPI4 FPSC is the lowest power
programmable SPI4.2 solution available today!
1. Semiconductors: Technology and Market Primer 1.0, CIBC World Markets Inc., May 30, 2003
December 2003/Page 2 Bringing the Best Together www.latticesemi.com
December 2003/Page 3 Bringing the Best Together www.latticesemi.com
(ORSPI4, Continued)
ets are a common standards-based
interface facilitating inter-connection
between diverse devices from multiple
manufacturers.
Designed for packet transfer be-
tween a MAC device and a network
processor or switch fabric, the SPI4.2
interface supports the aggregate band-
widths required of ATM and Packet-
over-SONET/SDH (POS) applications.
SPI4.2 provides a common interface
for 10 Gbps Wide Area Network
(WAN), Local Area Network (LAN),
Metro Area Network (MAN), and Stor-
age Area Network (SAN) technolo-
gies, and it is ideal for systems that
aggregate low-data rate channels into
a single 10 Gbps uplink for long haul
or backbone transmission. Lattice’s
ORSPI4 FPSC is unique in the pro-
grammable market as it embeds the
SPI4.2 core in pre-characterized ASIC
gates, unlike competitors who ship
soft SPI4.2 IP cores which must be
integrated into the overall design and
face the uncertainties of FPGA place
and route timing.
Advantages Over FPGA-Only
Approaches
Unlike other SPI4.2 implementa-
tions for FPGAs, the ORSPI4 FPSC
embeds all the high-speed functions in
an ASIC core of over 1 million gates,
allowing the FPGA gates to be used
for design-specic bridging functions.
Embedding these functions within
a hard core assures performance,
predictability and interoperability. This
implementation also provides a big
advantage in terms of total power con-
sumption. Typical programmable-only
FPGA IP cores consume upwards of
10W for one SPI4.2 interface imple-
mentation. In comparison, the ORSPI4
dissipates less than 2W per SPI4.2
implementation at 900 Mbps opera-
tion. This is a big advantage for power
hungry 10 Gbps line cards.
Line cards are getting “smarter”
all the time, with the incorporation of
NPUs and trafc management ca-
pabilities. This intelligence adds to
board complexity with the potential
for signal skew and strenuous layout
constraints. The SPI4.2 spec denes
a de-skew technique that relies on a
built-in training sequence with user-
selectable repetition rate and duration.
Referred to as dynamic alignment, this
timing mode eliminates phase errors
due to PCB traces of unequal lengths
by continuously monitoring the data
and adjusting the phase of the clock to
align with it. This can be a challenging
problem for programmable devices,
but Lattice’s FPSC technology affords
the opportunity to manage dynamic
alignment with predictable and reliable
ASIC technology.
SPI4.2 Core Features
The SPI4 interface blocks in the
ORSPI4 FPSC contains these indus-
try-best features:
Multiple SPI4.2 Interface Cores
• Two independent full-featured OIF-
compliant SPI4.2 interfaces for
>20 Gbps bandwidth.
• Supports quarter-rate mode for
2.5 Gbps operation
Data Alignment
• Supports both static and dynamic
alignment schemes
• Supports dynamic bit de-skew
over 16 phases of clock
• Supports receive clock aligned
or clock centered transmit data in
static mode.
Parity Generation and Checking
• DIP-2 and DIP-4 parity generation
and checking embedded in ASIC
Calendar Support
• Embedded 1K deep main and
shadow calendar built-in, supports
scheduling up to 256 ports and hit-
less bandwidth provisioning
User Design Interface
• User friendly FIFO interface from
ASIC to FPGA logic for clock do-
main transfer and ease of design
• Support of up to four user clock
domains and 32 FIFOs per Tx and
Rx
Signal Integrity
• Dedicated LVDS drivers and
receivers with center tap option in-
creases performance and reduces
jitter
Flow Control Flexibility
• An embedded set of write and
read port descriptor memories
supports a exible ow control
interface for each SPI4.2 port
Low Power
• Less than 2W of power for each
SPI4.2 interface at 900 Mbps
operation with dynamic alignment
• 1.5W for each SPI4.2 interface
at 700 Mbps operation with static
alignment
CML I/Os HSTL I/Os
Quad Channel
MUX/deMUX
System
Bus
LVDS I/Os
User-Configurable I/Os
Micro-
Processor
Interface
128-bit Data + Control Paths
Low-Speed Data
25-78 Mbits/s
Memory
Controller
Multi-Chan.
Alignment
+ FIFO
ORCA Series 4 FPGA Gates
Clock
4 x 2K
DPRAM
4 x 2K
DPRAM
Quad SERDES with
8B/10B Encoder/Decoder SPI4.2 Transmit
and
SPI4.2 Receive
Core
4 x 2K
DPRAM
4 x 2K
DPRAM
SPI4.2 Transmit
and
SPI4.2 Receive
Core
ORCA ORSPI4 block diagram (Please See Page 3)
December 2003/Page 2 Bringing the Best Together www.latticesemi.com
December 2003/Page 3 Bringing the Best Together www.latticesemi.com
Packet Buffering
• Embedded high-speed memory
controller for interface to external
QDR II SRAM for line-rate packet
buffering
The SPI4.2 cores on the OR-
SPI4 FPSC provide dual 10 Gbps
Physical-to-Link Layer interfaces in
conformance to the OIF-SPI4-02.0
specication. Each block provides a
bi-directional interface with an aggre-
gate bandwidth of 14.4 Gbps. This is
achieved by using 16 LVDS pairs each
for transmit and receive channel oper-
ating at a data rate of 900 Mbps with
a 450 MHz DDR clock. Both static and
dynamic alignment are supported at
the receive interface. DIP-4 and DIP-2
parity generation and checking are
also supported. 8K bytes of data buff-
ering is provided by embedded Dual-
Port RAM for both transmit and receive
in each SPI-4.2 core. Internal 1K deep
main and shadow calendars supports
scheduling of up to 256 ports. The
Transmit and Receive Status FIFOs
can also store ow control informa-
tion for up to 256 ports, the maximum
specied in the SPI-4.2 specication.
In order to provide wire-speed pack-
et processing, the ORSPI4 also con-
tains an independent Memory Control-
ler Block that provides data buffering
between the FPGA logic and external
memory and supports a throughput of
greater than 20 Gbps. Data is trans-
ferred to and from memory through
two sets of 36-bit unidirectional data
lines (one read, one write) operating
at up to 200 MHz DDR (400Mbps). A
set of 72 data signals is available to
transfer data across the core-FPGA
interface and allows the system to
utilize the bandwidth available with
second-generation QDR II SRAMs. Of
the 72 data signals, 8 signals can be
used either for parity or data. A second
memory controller can also be added
in the FPGA section to provide two in-
dependent line-rate buffers if needed.
High Speed SERDES I/O
The high-speed SERDES block sup-
ports four serial links, each operating
at up to 3.7 Gbps (2.96 Gbps data rate
with 8b/10b encoding and decoding),
to provide four full-duplex synchronous
interfaces with built-in receiver Clock
and Data Recovery (CDR) and trans-
mitter pre-emphasis. The SERDES
block is identical to that proven in
Lattice’s ORT82G5 and ORT42G5
FPSCs, supporting embedded 8b/
10b encoding/decoding as well as
link state machines for both 10 Gbps
Ethernet and Fibre Channel. The state
machines are IEEE P802.3ae/D4.01
XAUI compliant and also support FC
(ANSI X3.230: 1994) link synchroni-
zation. The SERDES in the ORSPI4
FPSC contains industry-best perfor-
mance with the following features:
Widest Range of Programmable
Data Rates
• 4 channels with industry-leading
performance from 0.6 Gbps to 3.7
Gbps
Multiple Standards Compliance
• Fibre Channel (1G, 2G), XAUI-
Ethernet (10G) and XAUI-FC
(10G)
(ORSPI4, Continued) Rx Jitter Tolerance
• 0.75UI p-p typical, 0.65 UI p-p
worst case, exceeds XAUI and
Fibre Channel specications
(@ 3.125 Gbps)
Tx Total Jitter
• 0.17UI p-p typical, 0.24 UI p-p
worst case, exceeds XAUI and
Fibre Channel specications
(@ 3.125 Gbps)
Low Power per SERDES Channel
• 225 mW worst case, including I/O
buffers @ 3.125 Gbps
Fast Locking Times
• Bit Realignment 300 nanoseconds
(938 bit times @ 3.125 Gbps)
nominal
Transmitter Output (CML)
• Full-amplitude mode: 0.8V p-p
Minimum
• Half-amplitude mode: 0.4V p-p
Minimum
Demonstrated Drive Length
• Over 40 inches (100cm) of FR-4
backplane
The ORSPI4 FPSC also contains a
dedicated microprocessor interface,
a 32-bit internal system bus (and 4
bits parity), and built-in system regis-
ters that act as the control and status
center for the SPI4.2, SERDES, and
memory controller blocks. The FPGA
portion of the device can also be con-
gured through this interface.
Availability
The ORSPI4 FPSC in the 1036
fpSBGA (1mm ball pitch, thermally
enhanced ne pitch ball grid array)
package is currently shipping. The
device will also be offered in an 1156
fpSBGA package without the SERDES
channels. The device is supported
by Lattice’s ispLEVER v.3.1 design
software, a dedicated design kit, and
popular third-party synthesis, simula-
tion, and verication tools.
Device
FPGA Usable
Gates PFUs LUTs
EBR RAM
Bits
Packaging/
User I/Os
I/O
Compatibility
SERDES
Channels
Max.
SERDES
Rates
SPI4.2
Cores
ORSPI4 471-899K 2,024 16,192 148K 1036 fpSBGA / 496 I/Os
1156 fpBGA / 352 I/Os
1.5/1.8/2.5/3.3 4 3.7Gbits/s 2
ORSPI4 Attributes
December 2003/Page 4 Bringing the Best Together www.latticesemi.com
December 2003/Page 5 Bringing the Best Together www.latticesemi.com
Lattice and Tyco Electronics joined
forces recently at the Combined
Exhibition of Advanced Technologies
(CEATEC) in Tokyo to demonstrate
the interoperability of Lattice’s XPIO™
110GXS physical layer electronic
transceiver with Tyco’s FR-4 backplane
and High-Speed long cables. The
demonstration utilized Lattice’s XPIO
110GXS 16-bit, 9.953 to 10.709 Gbps
transceivers and Tyco’s HM-Zd based
QuadRoute™ backplane and ZFP-I/O
high speed cables in conjunction with
passive equalizer and active equalizer
device.
“Using Tyco Electronics’ interconnect
solutions with our XPIO 110GXS to
actually demonstrate signals driving
over 16 inches (~406mm) and 30
inches (~762mm) of FR-4 backplane
and/or at least 7 meters of ZFP-I/O
cable assembly at speeds up to 10
Gbps NRZ is the best way to prove to
customers the quality and reliability
of our high-speed physical layer
solutions,” said Stan Kopec, Vice
President of Marketing for Lattice.
“This demonstration is a key step in
bringing cost-effective 10 Gbps cable
interconnect and electrical backplane
solutions to market,” added Kopec.
Tyco Electronics Circuit and Design
engineers have optimized the channel
losses of a backplane based on high-
speed Z-PACK™ HM-Zd connectors
with Lattice’s XPIO 110GXS as an
active interconnect using combined
passive and active equalization
technique. In addition, a high-speed
cable assembly based on the ZFP-I/O
connector was optimized to achieve
reliable transmission over a distance
of 7 meters using similar combined
passive and active equalization
technique.
Demo Conguration
A 9.953 Gbps serial NRZ-PRBS
211-1 bit stream was injected into the
Lattice XPIO SERDES using a Pulse
Pattern Generator. The XPIO then
hooked to one end of a 7 meter long
“ZFP-I/O” cable assembly through
Lattice and Tyco Electronics Demonstrate 10 Gbps SERDES Across
High Speed Cable Interconnect and FR-4 Backplane Solutions
interface boards. A second XPIO
SERDES was hooked to the other end
of the cable through combined passive
and active equalization. The XPIO
outputs were individually connected to
the DSO and BERT as single ended
signals.
“We demonstrated a reliable and
error free (BER better than 10-14)
system interconnect at 9.953 Gbps
that ran during the entire 5 days of the
show,” said Doron Lapidot, Director,
Circuit and Design, Tyco Electronics,
Asia/Pacic and EMEA.
“This is a breakthrough in 10G serial
link NRZ-coded system interconnect
since the solution also demonstrated
full interoperability,” added Lapidot.
“In today’s competitive market, this
cost effective and reliable solution
is an excellent example of how our
customers can utilize a exible solution
for system interconnect based on a
combined solution,” stated Minoru
Okamoto, Vice President,
Communications, Computer &
Consumer Electronics of Tyco.
Lattice ORCA FPGAs
Lattice has developed
the industry’s broadest and
fastest programmable device
family for high-speed serial
backplane data transmission.
The ORT82G5 integrates eight
backplane transceiver channels,
each operating over a range
from 600 Mbps to 3.7 Gbps
with a full duplex synchronous
interface with built-in Clock
and Data Recovery (CDR).
Also included are embedded
XAUI and Fibre-Channel state
machines, bypassable 8B/10B
encoding/decoding support
plus multi-channel alignment
capability without using any
FPGA gates. The device features
more than 400K FPGA gates
and up to 372 general-purpose
programmable I/O pins. The
new ORT42G5 contains four
backplane transceiver channels
providing similar performance and
FPGA density.
The ORSO82G5 includes eight
backplane transceiver channels,
each operating at up to 2.7 Gbps
data rate providing a full-duplex
synchronous interface with built-in
Clock/Data Recovery (CDR) and
more than 400K FPGA gates. The
ORSO82G5 contains an embedded
core for SONET data scrambling
and descrambling, streamlined
SONET framing, transport overhead
handling, cell insertion and extraction,
idle cell insertion/deletion plus the
programmable logic to terminate the
network into proprietary systems. All
SONET functionality is hidden from
the user and no prior networking
knowledge is required.
CEATEC, the largest electronics
and IT show in Asia Pacic, was held
October 7-11, 2003.
Lattice and Tyco Electronics
demonstrated 10Gbps SERDES at the
CEATEC Exhibition in Tokyo
December 2003/Page 4 Bringing the Best Together www.latticesemi.com
December 2003/Page 5 Bringing the Best Together www.latticesemi.com
Today’s circuit board power supply ar-
chitectures are moving away from the
traditional approach that uses isolated
power supplies to source all board
power supply voltages. Traditional
power supplies are bulky and costly
due to the magnetics used for isola-
tion. As a result, newer architectures
have resorted to two-stage power
conversion. The rst stage provides
isolation between the backplane and
a local circuit board supply bus. The
second stage, powered by the local
bus, generates the required power
supply voltages. Because the second
stage does not provide isolation, this
architecture is smaller for a given out-
put current. This method of distributing
the power supply functions is known
as the Distributed Power Architecture
(DPA).
Managing Power Supplies
in a Distributed Power
Architecture
While the use of DPA provides cost
effective solutions, the management
of these supplies (e.g., monitoring for
faults, controlling the sequence in a
coordinated manner) becomes more
complex since the designer must
not only control the power supply
sequence for a device, but must also
ensure that supplies of equal voltages
on the circuit board are turned on and
off at the same time.
Distributed Power Supply Se-
quence Synchronization: Designers
often use multiple, same voltage POLs
powering different ICs to minimize
coupling of power supply noise. At the
circuit board level, all these same-
voltage supplies need to be turned
on together while conforming to each
device’s power-up sequence speci-
cation. For example, the I/O voltage
of the CPU, an ASIC, etc., needs to
be turned on simultaneously while
not violating the CPU and the ASIC’s
sequence specication. This is further
complicated by the fact that some
devices require their lowest supply
to be turned on rst followed by the
higher voltage while another device
might require its highest voltage to be
turned on before the lower voltages.
Additionally, most devices require
the power supply be removed in the
reverse order of application. The actual
sequence of power supply turn-off can
depend on the event that initiated the
power supply turn-off sequence.
Power supply sequencing is further
complicated when the main card also
has a plug-in mezzanine card, which
is powered by the intermediate bus.
Mezzanine card sequencing should
be synchronized with the main card
and the power management function
on the main card should automatically
include monitoring voltages of the
mezzanine card.
Supervisory Signal Generation
Centralized Monitoring: All the sup-
plies on the circuit board should be
monitored continuously for low-voltage
or high-voltage conditions. If a supply
becomes faulty, the processor should
be interrupted to save critical data
and proceed to Phase 5 to turn off the
power supplies.
Centralized Reset Control: Often
the CPU reset signal is stretched (for
about 100 ms) after its supplies are
turned on to facilitate the execution
of built-in self-test. Also, in-order to
prevent the processor mis-execution
of instructions, the CPU reset signal
should also be generated when a fault
develops in any supply powering the
devices connected to its data bus. This
requires the reset signal be generated
from the supervisor chip that monitors
all the supplies. Additionally, during
Phase 4, the input reset signal activa-
tion or watchdog timer failure results in
resetting the processor.
Scaling: The power supply monitor-
ing function and supervisory signal
generation should not only cover the
supplies on the main circuit board, but
should also monitor the supplies on
the mezzanine cards. The operation in
Phases 3 and 4 should be extended to
include the mezzanine cards.
Power Management Using
ispPAC Power Manager
The gure at left shows an example
Intermediate Bus Architecture (IBA)
arrangement. Power management
is implemented using the ispPAC-
Cascaded ispPAC Power Manager ICs Manage Distributed Power Supplies
Pow
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Cascaded ispPAC Power Manager devices in an intermediate bus architecture(Please See Page 6)
December 2003/Page 6 Bringing the Best Together www.latticesemi.com
December 2003/Page 7 Bringing the Best Together www.latticesemi.com
POWR1208 (Power1208) and ispPAC-
POWR604 (Power604) devices from
Lattice in a master-slave conguration
with the Power1208 as master and the
Power604 as slave.
The isolated power supply, powered
by the backplane -48V, sources a
12V Intermediate Bus (IB). There are
two types of supplies: Point-Of-Load
supplies shown as POLs (3.3V, 2.5V,
1.2V, and 1.3V) located close to the
ASIC and the CPU and centralized
supplies (3.3V, 2.5V, and 1.5V). The
design uses separate POLs to power
2.5V and 3.3V to provide clean and
monotonic supplies, as required by the
CPU and ASIC devices. The Power604
is positioned close to the ASIC to
monitor 1.3V to improve precision in
monitoring.
This article, for convenience refers
to the supplies monitored by Power604
as POLs, and those monitored by
Power1208 as central supplies.
The master and slave Power Man-
ager devices operate from the 12V
supply. Card-level power management
functions are coordinated by means
of a Digital Control Bus between the
Power1208 (master) and Power604
(slave). This architecture can be
expanded to manage additional sup-
plies by adding more ispPAC Power
Manager devices on this Digital Con-
trol bus. For example, the mezzanine
card can use this bus to synchronize
its power supply management with the
main card. No modications are re-
quired for either the Digital Control Bus
or the master Power1208 device.
The Digital Control bus signals
consist of Clock, Reset, PWR0, and
PWR1 sourced by the master Pow-
er1208 and Response generated by
the slave Power604 device.
The master Power1208 synchro-
nizes power supply sequencing across
the circuit board, through the Digital
control bus, while monitoring all sup-
plies both during supply sequencing
and normal operation.
Centralized supervisory signal
generation is controlled by the master
Power1208 by logically combining the
Card_reset signal, watchdog timer
input and the status of all power sup-
plies on the circuit board.
The design can be expanded to
manage a larger number of power
supplies either by using another
Power1208 device as a slave or by
using additional slave devices (ei-
ther Power1208 or Power604), all
controlled by the digital control bus.
The algorithm on the master remains
the same irrespective of the number
of slave devices. However, the slave
device’s algorithm can be changed de-
pending on the power supply domain.
For example, with a slave Power1208,
full 5-phase power management can
be implemented for a mezzanine card
with its own CPU reset, brownout
interrupt, etc., while powering up/down
synchronously with the main card.
The entire design is implemented
using the PAC-Designer® software,
Lattice’s interactive, intuitive, PC-
based point-and-click software tool.
This tool is available for download from
www.latticesemi.com, free of charge.
(ispPAC Power Manager, Continued) Conclusion
The ispPAC Power Manager’s
unique architecture combines PLDs
and programmable analog circuits that
can be cascaded to provide reliable
power management solutions for a
distributed power architecture. The
resulting power management solution
is both exible and scalable.
This arrangement operates reliably
under noisy power supply conditions
and across various plug-in mezzanine
cards. This reliability is due to the
ruggedness of the Power1208 and
Power604 devices, their voltage moni-
toring precision, and reliable hand-
shake mechanisms through the digital
control bus.
The LogiBuilder section of the PAC-
Designer software further simplies
designs by providing a wide variety of
power management functions through
a simple and intuitive point-and-click
mechanism.
Feature Power604 Power1208
Programmable Sense Inputs 6 12
Sense Voltage Range 1V to 5.7V 1V to 5.7V
Supervisory Inputs 4 4
FET Drivers/Digital Inputs — 4
Reprogrammable Timers 2 4
CPLD Macrocells 8 16
Power Supply Voltage 2.25 to 5.5V 2.25 to 5.5V
Packaging 44 TQFP 44 TQFP
ispPAC Power Manager Attributes
Lattice provides regular service pack
updates to the ispLEVER design tool
to ensure users always have access
to the latest design tools and silicon
products. A new update for ispLEVER
v.3.1, called Service Pack 01, is now
available for download. The easiest
way to download and/or install Service
Pack 01 is to use the ispUPDATE™
utility, included with ispLEVER v.3.1.
Simply run ispUPDATE, and follow the
on-screen instructions. Alternatively,
you can download Service Pack 01
directly from the Lattice web site at
New Service Pack Available for ispLEVER v3.1
www.latticesemi.com/software. Select
the ispLEVER conguration you’re us-
ing, and choose “Downloads” from the
resource box.
Service Pack 01 updates device
libraries and databases for new
Lattice product families such as the
ispXPLD™ 5000MX, ispGDX2™,
ispXPGA® and ORCA FPSC design
kits. Service Pack 01 also includes a
number of updates and enhancements
to features and algorithms used in
many parts of the ispLEVER design
tool set.
December 2003/Page 6 Bringing the Best Together www.latticesemi.com
December 2003/Page 7 Bringing the Best Together www.latticesemi.com
Lattice has introduced its ORT82G5
Field Programmable System-on-
a-Chip (FPSC) that demonstrates
the ability to pass error-free data at
4.25Gigabits/sec (Gbps) across 6
inches of printed circuit board (PCB)
and 26 inches of coaxial cable, making
it the industry’s rst programmable
4G Fibre Channel-based backplane
transceiver in production. In June of
this year, the Fibre Channel Indus-
try Association (FCIA) voted in favor
of extending 4Gbps Fibre Channel
(4GFC) from an intra-cabinet stor-
age device interconnect into switched
Storage Area Network (SAN) fabrics.
4GFC serves as a bridge between the
10Gbps future and current 1-2Gbps
systems.
“Lattice’s superior SERDES technol-
ogy, systems knowledge and program-
mable technology expertise continue
to provide effective solutions for high
performance applications like storage
arrays and next-generation storage
networks,” said Stan Kopec, vice presi-
dent of corporate marketing at Lattice.
“The ORT82G5 is production-
proven, and we have been
working with leading-edge
vendors in the SAN market
to verify the 4GFC capabil-
ity of the device. All our tests
conrm the superior speed,
exibility, and low power con-
sumption of our solution. Our
customers are getting a real
jump on the 4GFC market
with a proven device ready for
design and production now,”
he added.
Lattice’s ORT82G5 can
support up to 4 SERDES
channels running at over
4.3Gbps, an embedded Fibre
Channel Physical Coding
Sublayer (PCS) core with 8b/
10b encoding/decoding and
link state machine, and over
10,000 programmable logic elements
(equivalent 4-input lookup tables) in its
general-purpose FPGA section for the
easy integration of customer-specic
intellectual property (IP). The device
also features 372
general-purpose pro-
grammable I/O pins
supporting a variety
of advanced interface
standards including
HSTL, SSTL, GTL+
and others. A low 335
milliwatts of power is
consumed per chan-
nel with the SERDES
running in excess of
4.25Gbps.
Lattice’s FPSC de-
vices are high-perfor-
mance eld program-
mable devices that
combine optimized
embedded core
functions together
with exible, general-
purpose FPGA logic.
Lattice currently has
10 FPSC devices
available, including
devices optimized for SONET/SDH,
Gigabit Ethernet, System Packet
Interface (SPI) 4.2 and optical module
interface applications. FPSCs offer
system designers the convenience
and time-to-market advantages of
pre-engineered, pre-characterized
standard interface functions combined
with the exibility of FPGA logic for the
implementation of differentiated, ap-
plication-specic features.
For additional information on the
4GFC characteristics of the ORT82G5
SERDES technology, see techni-
cal note TN1045, ORT82G5 4.25
Gbit/s Fibre Channel Testing Results
available on the Lattice web site at
www.latticesemi.com.
The ORT82G5-3BM680C SERDES
transceiver is currently shipping.
The device is supported by Lattice’s
ispLEVER version 3.1 design soft-
ware, a dedicated design kit, HSPICE
SERDES I/O buffer models to support
backplane simulation and popular
third-party synthesis, simulation, and
verication tools.
Lattice Field Programmable System-on-a-Chip Demonstrates 4G Fibre
Channel Capability
CML I/Os
Quad Channel
MUX/deMUX
Micro-
processor
Interface
and
Registers
CML I/Os
Quad Channel
MUX/deMUX
User-Configurable I/Os
4k x 36
Dual-Port
RAM
System Bus Parallel DataParallel Data
2:1 Data
Selector
Multi-Chan.
Alignment
+ FIFO
2:1 Data
Selector
Multi-Chan.
Alignment
+ FIFO
ORCA Series 4 FPGA Gates
Selectable High-Speed Data Rates – 1.25 / 2.5 / 3.125 Gbits/sec
Clock Clock
4k x 36
Dual-Port
RAM
Quad Serializer-DeSerializer
with 8B/10B Encoder/Decoder
Quad Serializer-DeSerializer
with 8B/10B Encoder/Decoder
Lattice’s ORT82G5: the industry’s fastest
device for high-speed serial backplane
data transmission
ORCA ORT82G5 block diagram
December 2003/Page 8 Bringing the Best Together www.latticesemi.com
December 2003/Page 9 Bringing the Best Together www.latticesemi.com
Due to increased worldwide envi-
ronmental concerns, the need for
lead-free solutions in electronic
components and systems is receiving
increasing attention within the semi-
conductor and electronics industries.
Lattice has been actively tracking
and is fully supportive of the various
industry efforts throughout the world
to phase out the use of lead and other
undesirable elements from electronic
equipment materials and manufactur-
ing processes.
Lattice is a leader in the develop-
ment of lead-free and “green” (halo-
gen-free) packaging solutions. Lattice
currently offers an extensive list of
standard products in lead-free pack-
aging. Halogen-free “green” package
options will become available later in
2004.
Lattice is working to eliminate
hazardous and toxic materials from
its products, in compliance with the
European Parliament Directive entitled
“Restrictions on the use Of Hazardous
Substances” (RoHS) as well as other
international standards. Lattice has
developed an extensive list of banned
and restricted materials. Lattice’s man-
ufacturing supply partners are aware
of these requirements and are ag-
gressively working to eliminate these
materials from all Lattice products.
Lattice’s Lead-Free Solutions
Lattice has qualied a wide variety
of package types in lead-free congu-
rations. These qualied packages in-
clude the Thin Quad Flat Pack (TQFP),
Plastic Ball Grid Array (PBGA), Fine
Pitch BGA (fpBGA), Chip Scale BGA
(csBGA) and Quad Flat-pack (QFN)
packages. To better facilitate the indus-
try transition to lead-free PLDs, Lattice
offers the following broad assortment
of standard, off-the-shelf, lead-free
product families.
Backward Compatible Lead-
Free Package Options
All of Lattice’s lead-free TQFP
and QFN packages are “backward
compatible” with conventional leaded
Lattice Offers Lead-Free Product Options
Product Family Device Family Device Family Description
Backward
Compatible
Packaging
Standard
Packaging
ispXPGA ispXPGA-B
ispXPGA-C
3.3V/2.5V Non-volatile, Innitely Recongurable FPGA
1.8V Non-volatile, Innitely Recongurable FPGA
256 fpBGA
516 fpBGA
680 fpSBGA
900 fpBGA
ORCA 4 FPSC ORT42G5
ORT82G5
ORSO82G5
ORT8850H/L
ORLI10G
1.5V ORCA 4 FPGA Plus Embedded High-Performance
ASIC Core
484 fpBGA
680 fpBGA
ispMACH™ 4000 ispMACH 4000V
ispMACH 4000C
3.3V SuperFAST™ Low-Power CPLD
1.8V SuperFAST Low-Power CPLD
44 TQFP
48 TQFP
100 TQFP
128 TQFP
144 TQFP*
176 TQFP
256 fpBGA
ispMACH 4000Z 1.8V SuperFAST Zero-Power CPLD 48 TQFP
100TQFP
176TQFP
56 csBGA
132 csBGA
ispXPLD 5000MX ispXPLD 5000MV
ispXPLD 5000MC
3.3V High Density CPLD + Memory
1.8V High Density CPLD + Memory
256 fpBGA
484 fpBGA
672 fpBGA
ispGAL®ispGAL22V10AV 3.3V Industry’s Fastest and Smallest CPLD 32 QFN
ispPAC Power Manager ispPAC-POWR1208
ispPAC-POWR604
Power Supply Sequencing and Monitoring 44 TQFP
*3.3V ispMACH 4000V only.
Lead-Free Device Offerings from Lattice
manufacturing methodologies. This
backward compatibility allows users
to surface mount lead-free packages
onto lead-based PCBs and/or use
lead-free packaging with leaded sol-
ders. Users can now procure a single,
lead-free component from Lattice and
use it in either a leaded or lead-free
manufacturing environment without
any issues. This greatly simplies
inventory management challenges as
users migrate to lead-free manufactur-
ing. Lattice is currently evaluating BGA
packaging for backward compatibility.
For more information on Lattice’s
lead-free product offering, including
device data sheets, visit the Lattice
web site at www.latticesemi.com.
December 2003/Page 8 Bringing the Best Together www.latticesemi.com
December 2003/Page 9 Bringing the Best Together www.latticesemi.com
What’s new in ispLEVER v.3.1?
ispLEVER v.3.1 has added sup-
port for the following new devices:
• The low power ispMACH 4000Z in
the 256-macrocell density
• The exible ispXPLD architecture
in the 768-macrocell density
In addition, the following software
modules have been updated:
Project Navigator:
• Revision control support for CPLD
devices
• LPC (Lattice Parameter Congu-
ration) source le support. This
feature allows you to generate a
component, such as a counter
or a RAM block, as a parameter-
ized module that can be imported
directly into your source tree
Preference/Constraint Editor:
• Fully integrated Preference Editor
for the ORCA FPGA design ow
• The Nodal Constraint Editor allows
you to open a constraint editor to
set nodal level constraints on a
node-by-node basis
The ispLEVER Release Notes de-
scribes all of the new features included
with this release in greater detail.
How can Lattice’s programmable
technology help with some of the
security issues I’m facing today?
The most common FPGA technol-
ogy in use today is SRAM-based,
which is fast and re-congurable, but
must be re-congured every time the
FPGA is powered up. Typically, an
external PROM is used to hold the
conguration data for the FPGA. The
link between the PROM and FPGA
represents a signicant security risk.
Conguration data is exposed and
vulnerable to piracy while the device
powers up. Using a non-volatile FPGA
eliminates this security risk. Tradition-
ally, non-volatile FPGAs were based
on Antifuse technology that is secure,
but very expensive to use due to its
one-time programmability and the
associated increased manufacturing
costs.
Lattice Listens Information Need Resource
Technical Support Tel: 1-800-LATTICE or (408) 826-6002
e-mail: techsupport@latticesemi.com
Software and Literature Download http://www.latticesemi.com
European Literature Fulllment Tel: +44 (0)117 934 1600
FAX: +44 (0)117 934 1601
e-mail: euro.lit@latticesemi.com
Lattice offers a superior non-vola-
tile FPGA solution with the ispXPGA
family of FPGAs. The ispXPGA and
ispXPLD families utilize Lattice’s ispXP
technology, which combines non-vola-
tile cells and SRAM cells on the same
chip. The non-volatile memory is used
for storing the device conguration se-
curely on the chip. The SRAM memory
holds the working conguration after
power-up. The technology used in
the ispXPGA family of FPGAs allows
for high security of the conguration
pattern while delivering all the ben-
ets of innitely recongurable SRAM
memory.
Can I control negative power sup-
plies with the ispPAC-POWR1208?
Yes, although doing so requires a
few external components to trans-
late the ispPAC-POWR1208’s posi-
tive-voltage control signal to negative-
voltage signals. One of the simplest
general-purpose ways to do this is to
use a device called an optocoupler, as
shown in the circuit below.
In this circuit, when the ispPAC-
POWR1208’s output goes low, it turns
on the optocoupler’s LED, which turns
on the associated output transistor.
The optocoupler’s emitter output
will then pull MOSFET Q1’s gate
positive towards ground. Because the
MOSFET’s source is sitting at -5V, this
turns it on, and provides -5V to the
load. When the ispPAC-POWR1208’s
output goes high, the optocoupler
turns off, and R2 pulls the MOSFET’s
gate back down to -5V, shutting it off.
Because the ispPAC-POWR1208’s
outputs are used in open-drain mode,
this circuit will also work with the
ispPAC-POWR604.
This circuit works because there
is no direct electrical connection
between the optocoupler’s inputs and
outputs. This permits the output to
be controlled by the input even when
they are at widely differing voltages.
Depending on the type of optocoupler
used, it is possible to control loads that
can be at hundreds or even thousands
of volts in relation to the control
signal. For this reason optocoupler
interface circuits are also useful when
controlling the +/-48V power supplies
frequently used in telecommunications
circuits.
L
O
A
D
is
p
PAC-POWR120
8
S
witche
d
-5V Suppl
y
-5V Supply
R2
10k
R
1
1k
U1
4N28
+5V
Q1
An optocoupler can be used to convert the Power1208’s
positive voltage control signals to negative signals.
December 2003/Page 10 Bringing the Best Together www.latticesemi.com
Title Description Web Print Order #
ORSPI4 Product Brief Introduction to the ORSPI4 that includes two embedded SPI4.2
cores, 3.7Gbps SERDES, memory controller and FPGA.
I0165
ORSPI4 White Paper Technical overview of Lattice’s new ORSPI4 product. — —
Consumer Solutions Brochure Describes Lattice’s broad offering of PLDs that address the
needs of consumer electronics designers.
I0166
Lead-Free/Green Packaging Brochure Overview of Lattice’s lead- and halogen-free package offerings. — —
SONET White Paper Backplane solutions for next generation SONET line cards. — —
ispXPGA Evaluation Board User’s Guide Description of operation for the ispXPGA Evaluation Board. — —
ispXPLD Evaluation Board User’s Guide Description of operation for the ispXPLD Evaluation Board. — —
Lattice Literature
The following is a list of recently published documents, including descriptions and ordering numbers. On-line versions
of these technical publications are available on the Lattice web site at www.latticesemi.com. Some of these documents
are also available in print. To order print versions, call your local Lattice representative or Lattice’s Literature Distribution
Department at 1-888-477-7537 (outside the U.S. and Canada, call 503-268-8000) or order by FAX at 503-268-8556. In
Europe, contact Lattice’s European Literature Fulllment Department by phone at +44 (0)117 934 1600, by FAX at
+44 (0)117 934 1601 or by e-mail at euro.lit@latticesemi.com.
General Information
Title Description Web Print Order #
ORSPI4 Data Sheet Dual SPI4.2 interface and high-speed SERDES FPSC. — —
Data Sheets
Title Description Web Print Order #
ORT82G5 4.25 Gbit/s Fibre Channel
Testing Results
ORT82G5 operation is demonstrated through a series of labo-
ratory tests, eye diagrams, jitter performance and backplane
performance.
— —
ORSPI4 PCB Design Guidelines for
SPI4.2 and QDR Memory Controller
Interfaces
Guidelines for using the ORSPI4 FPSC, such as routing PCB
signals, generating and supplying reference voltages and termi-
nating signals.
— —
Controlling and Monitoring Power-
One Bricks and SIPs with the Lattice
ispPAC-POWR1208
Details the interface between the ispPAC-POWR1208 and two
different Power One DC-to-DC converters.
— —
Technical Notes/Application Notes
Title Description Web Print Order #
PCI Data Sheet & User’s Guide Both documents updated to include several new factory-tested
congurations that are available now for free evaluation.
— —
UTOPIA Level 3 IP Cores Data Sheets &
Users’ Guides
Updated to include factory-tested congurations available now
for use with Lattice ispXPGA and ORCA Series 4 devices.
— —
Tri-Speed Ethernet Media Access
Controller Data Sheet & User’s Guide
This core is available for use in either 10/100 or 1G modes in
Lattice’s ORCA Series 4 technology.
— —
ispLeverCORE™ Evaluation Tutorials How to evaluate a Lattice ispLeverCORE product. This tutorial
available in three versions: the “stand-alone quick-start” version,
the detailed version and an interactive version.
— —
Intellectual Property
Copyright © 2003 Lattice Semiconductor Corporation.
Lattice Semiconductor Corporation, L Lattice Semiconductor Corporation (logo), L (stylized), L (design), Lattice (design), E2CMOS, In-System Programmable, In-System Program-
mability, ISP, ispGAL, ispGDX2, ispLEVER, ispLeverCORE, ispMACH, ispPAC, ispUPDATE, ispXPGA, ispXPLD, LogiBuilder, MMI (logo), ORCA, PAC-Designer, Silicon Forest,
SuperFAST, V Vantis (design), Vantis, (design) and XPIO are either registered trademarks or trademarks of Lattice Semiconductor Corporation or its subsidiaries in the United
States and/or other countries. ISP is a service mark of Lattice Semiconductor Corporation.
Synplicity and Synplify are registered trademarks of Synplicity, Inc. Mentor Graphics, LeonardoSpectrum and ModelSim are either registered trademarks or trademarks of Mentor
Graphics Corporation.
Other product names used in this publication are for identication purposes only and may be trademarks of their respective companies.
LatticeNEWS is a publication of Lattice Semiconductor Corporation, 5555 N.E. Moore Ct., Hillsboro, OR 97124 USA
Order #: NL0106
