FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
1.0 Features
• Complete programmable control via I2C™-bus
• Selectable CMOS or PECL compatible outputs
• External feedback loop capab ility allows genlocking
• Tunable VCXO loop for jitter attenuation
2.0 Description
The FS6131-01 is a monolithic CMOS clock generator/regenerator IC designed to minimize cost and component count in a variety of
electronic systems. Via the I2C-bus interface, the FS6131-01 can be adapted to many clock generation requirements.
The ability to tune the on-board voltage-controlled crystal oscillator (VCXO), the length of the reference and feed-back dividers, their
granularity, and the flexibility of the post divider make the FS6131-01 the most flexible stand-alone phase-locked loop (PLL) clock
generator available.
3.0 Applications
• Frequency synthesis
• Line-locked and gen lock applications
• Clock multiplication
• Telecom jitter attenuation
116
2
3
4
5
6
7
8
15
14
13
12
11
10
9
SCL
SDA
ADDR
VSS
XIN
XOUT
XTUNE
VDD LOCK/IPRG
EXTLF
VSS
REF
FBK
VDD
CLKP
CLKN
16-pin 0.150" SOIC
FS6131
Figure 1: Pin Configuration
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
FS6131
VCXO
Divider
(optional)
(optional)
CRYSTAL LOOP
MAIN LOOP
VCXO
XOUT
XIN
Control
ROM
XTUNE
Reference
Divider
(N
R
)
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
REF
FBK
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
Feedback
Divider
(N
F
)
Internal
Loop
Filter
EXTLF
I
2
C
Interface
SCL
SDA
ADDR
Registers
POST3[1:0]
POST2[1:0]
POST1[1:0]
REFDIV[11:0]
FBKDIV[13:0]
EXTLF
PDREF
PDFBK
VCOSPD,
OSCTYPE
LFTC
MLCP[1:0]
XLCP[1:0]
XLROM[2:0]
XLPDEN,
XLSWAP
REFDSRC
XCT[3:0],
XLVTEN
(f
REF
)
(f
VCO
)
LOCK/
IPRG
Post
Divider
(N
Px
)
Voltage
Controlled
Oscillator
Lock
Detect
CMOS
(optional)
STAT[1:0]
OUTMUX[1:0]
Clock
Gobbler
GBL
(optional)
FBKDSRC[1:0]
CMOS/PECL
Output
CLKN
(f
CLK
)
CLKP
R
LF
C
LF
C
LP
11
00
10
01
01
00
10
11
1
0
1
0
0
1
10
1
0
Figure 2: Block Diagram
Table 1: Pin Descriptions
Key: AI = Analog Input; AO = Analog Output; DI = Digital Input; DIU = Input with Internal Pull-Up; DID = Input with Internal Pull-Down;
DIO = Digital Input/Output; DI-3 = Three-Level Digital Input, DO = Digital Output; P = Power/Ground; # = Active Low pin
Pin Type Name Description
1 DI SCL Serial interface clock (requires an external pull-up)
2 DIO SDA Serial interface data input/output (requires an external pull-up)
3 DI ADDR
Address select bit (see Section 5.2.1)
4 P VSS Ground
5 AI XIN VCXO feedback
6 AO XOUT VCXO drive
7 AI XTUNE VCXO tune
8 P VDD Power supply (+5V)
9 DIO LOCK/IPRG Lock indicator / PECL current drive programming
10 AI EXTLF External loop filter
11 P VSS Ground
12 DI REF Reference frequency input
13 DI FBK Feedback input
14 P VDD Power supply (+5V)
15 DO CLKP Differential clock output (+)
16 DO CLKN Differential clock output (-)
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
4.0 Functional Block Description
4.1 Main Loop PLL
The main loop phase locked loop (ML-PLL) is a standard phase- and frequency- locked loop architecture. As shown in Figure 2, the
ML-PLL consists of a reference divider, a phase-frequency detector (PFD), a charge pump, an internal loop filter, a voltage-controlled
oscillator (VCO), a feedback divider, and a p ost divid er.
During operation, the reference frequency (f REF), generated by either the on-board crystal oscillator or an external frequency source, is
first reduced by the reference divider. T he integer value that the frequency is divide d by is called the mo dulus, and is denote d as NR for
the reference divider. The divi ded reference is then fed into the PFD.
The PFD controls the frequenc y of the VCO (fVCO) through the charge pump and lo op filter. The VCO provid es a high-speed, low noise ,
continuously variable frequency clock source for the ML-PLL. The output of the VCO is fed back to the PFD through the feedback
divider (the modulus is denoted by NF) to close the loop.
The PFD will drive the V CO up or do wn in frequ ency until t he divi ded ref erence freq uency and th e divid ed VCO freq uenc y appeari ng at
the inputs of the PFD are equal. The input/output relationship between the reference frequency and the VCO frequency is
R
REF
F
VCO N
f
N
f=
If the VCO frequency is used as the PLL output freque ncy (fCLK) then the basic PLL equation ca n be rewritten as
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
=
R
F
REFCLK N
N
ff
4.1.1 Reference Divider
The reference divid er is designed for l ow phase jitter. T he divider accepts either the output of either the cr ystal loop (the VCXO output)
or an external reference frequency, and provides a divided-down frequency to the PFD. The reference divider is a 12-bit divider, and
can be programmed for an y modulus from 1 to 4095. See both Table 3 and Table 8 for additional programming information.
4.1.2 Feedback Divider
The feedback divider is based on a dual-modulus pre-scaler technique. The technique allows the same granularity as a fully
programmable feedback divider, while still allowing the programmable portion to operate at low speed. A high-speed pre-divider (also
called a prescaler) is placed b etween the VCO and the programmable feedback divider b ecause of the high speeds at which the VCO
can operate. The dual-modulus technique insures reliable operation at any speed that the VCO can achieve and reduces the overall
power consumption of the divider.
For example, a fixed divide-by-eight could be used in the feedback divider. Unfortunately, a divide-by-eight would limit the effective
modulus of the feedback divider path to multiples of eight. The limitati on would restrict the ability of the PLL to achi eve a desired input-
frequency-to-output frequency ratio without making both the reference and feedback divider values comparatively large. Large divider
moduli are generally undesirable due to increased phase jitter.
Dual-
Modulus
Prescaler
A
Counter
M
Counter
f
vco
Figure 3: Feedback Divider
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
To understand the operation, refer to Figure 3. The M-counter (with a modulus of M) is cascaded with the dual-modulus pre-scaler. If
the prescaler modulus were fixed at N, the overall modulus of the feedback divider chain would be MXN. However, the A-counter
causes the pre-scaler modulus to be altered to N+1 for the first A outputs of the pre-scaler. The A-counter then causes the dual-
modulus prescaler to revert to a modulus of N until the M-counter reaches its terminal state and resets the entire divider. The overall
modulus can be expressed as )()1( AMNNA
−
+
+
where M ≥ A, which simplifies to ANM
+
×
4.1.3 Feedback Divider Progra m ming
The requirement that M ≥ A means that the feedb ack divider can only be programm ed for certain v alues bel ow a div ider modulus of 56.
The selection of divider values is listed in Table 2.
If the desired feedback divider is less than 56, find the divider value in the table. Follow the column up to find the A-counter program
value. Follow the row to the left to find the M-counter value.
Above a modulus of 56, the feedback divider can be programmed to any value up to 16383. See both Tabl e 3 and Table 8 for additional
programming information.
Table 2: Feedback Modulus Below 56 A-counter: FBKDIV[2:0]
M-Counter:
FBKDIV[13:3] 000 001 010 011 100 101 110 111
00000000001 8 9 - - - - - -
00000000010 16 17 18 - - - - -
00000000011 24 25 26 27 - - - -
00000000100 32 33 34 35 36 - - -
00000000101 40 41 42 43 44 45 - -
00000000110 48 49 50 51 52 53 54 -
00000000111 56 57 58 59 60 61 62 63
Feedback Divider Modulus
4.1.4 Post Divider
The post divider consists of three individually programmable divid ers, as sh own in Figure 4.
Post
Divider 1
(N
P1
)
Post
Divider 2
(N
P2
)
Post
Divider 3
(N
P3
)
POST3[1:0]POST2[1:0]POST1[1:0]
POST DIVIDER (N
Px
)
f
out
f
GBL
Figure 4: Post Divider
The moduli of the individu al dividers are denoted as NP1, NP2, and NP3, and together they make up the arra y modulus N Px.
321 PPPPx NNNN
×
×
=
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
The post divider performs se veral useful functions. First, it allows the VCO to be operat ed in a narrower range of speeds c ompared to
the variety of output clock speeds that the device is required to generate. Second, it changes the basic PLL equation to
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
=
PxR
F
REFCLK NN
N
ff 1
The extra integer in the denominator permits more flexibility in the programming of the loop for many applications where frequencies
must be achieved exactly.
Note that a nominal 50/50 duty factor is preserved for selections which have an odd modulus.
4.2 Phase Adjust and Sampling
In line-locked or genlock ed applications, it is necessar y to know the exact phase relation of the output clock rel ative to the input clock.
Since the VCO is included within the feedback loop in a simple PLL structure, the VCO output is exactly phase aligned with the input
clock. Every cycle of the input clock equals NR/NF cycles of the VCO clock.
Phase
Frequency
Detect
Feedback
Divider (N
F
)
VCO
f
IN
f
OUT
Reference
Divider (N
R
)
f
IN
f
OUT
Figure 5: Simple PLL
The addition of a post divider, while adding flexibility, makes the phase relation between the input and output clock unknown because
the post divider is outside the feedback l oop.
Phase
Frequency
Detect
Feedback
Divider (N
F
)
VCO
f
IN
f
OUT
Reference
Divi der (N
R
)
f
IN
f
VCO
Post
Divider (N
F
)
f
VCO
f
OUT
?
Figure 6: PLL with Post Divider
4.2.1 Clock Gobbler (Phase Adjust)
The clock gobbler circuit takes advanta ge of the unknown relationship between input and output clocks to permit the adjustment of the
CLKP/CLKN output clock phase rel ative to the REF input. T he clock gobbler circuit rem oves a V CO clock pulse before the pulse cl ocks
the post divider. In this way, the phase of the output clock can be slipped until the output phase is aligned with the input clock phase.
To adjust the phase relationship, s witch the feedback divider source to the post divider in put via the FBKDSRC bit, and toggle the GBL
register bit. The clock gobbler output clock is delayed by one VCO clock period for each transition of the GBL bit from zero to one.
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
4.2.2 Phase Alignment
To maintain a fixed phase relation between input and output clocks, the post divider must be placed inside the feedback loop. The
source for the feedback divider is obtained from the output of the post divider via the FBKDSRC switch. In addition, the feedback divider
must be dividing at a multiple of the post divider.
Phase
Frequency
Detect
Feedback
Divider (N
F
)
VCO
f
IN
f
OUT
Reference
Divider (N
R
)Post
Divider (N
F
)
f
IN
f
OUT
Figure 7: Aligned I/O Phase
4.2.3 Phase Sampling and Initial Align ment
However, the ability to adjust the phase is useless without knowing the initial relation between output and input phase. To aid in the
initial synchronizatio n of the output phase t o input phase, a phase al ign "flag" makes a transiti on (zero to one or one to zero ) when the
output clock phase becomes aligned with the feedback source phase. The feedback source clock is, by definition, locked to the input
clock phase.
First, the FS6131 is used to sample the output clock with the feedback source clock and set/clear the phase align flag when the two
clocks match to within a feedback source clock period. Then, the clock gobbler is used to delay the output phase relative to the input
phase one VCO clock at a time until a transition on the flag occurs. When a transition occurs, the output and input clocks are phase
aligned.
To enter this mode, set STAT[1] to one and clear STAT[0] to zero. If the CMOS bit is set to one, the LOCK/IPRG pin can display the
flag. The flag is always available under software control by reading back the STAT[1] bit, which will be overwritten by the flag in this
mode.
4.2.4 Feedback Divider Monitoring
The feedback divid er clock can be br ought out the LOCK/IPRG pin in dependent of the output cl ock to allow monitoring of the fe edback
divider clock. To enter this m ode, set both the STAT[1] and STAT[0] bits to one. The CMOS bit must also be set to one to enable the
LOCK/IPRG pin as an output.
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
4.3 Loop Gain Analysis
For applications where an external loop filter is required, the following analysis example can be used to determine loop gain and
stability.
The loop gain of a PLL is the product of all of the gains within the loop.
The transfer function of the phase detector and charge pu mp combination is (in A/rad):
π
2
chgpump
PD
I
K=
The transfer function of the loop filter is (in V/A):
⎟
⎟
⎟
⎟
⎠
⎞
⎜
⎜
⎜
⎜
⎝
⎛
⎟
⎠
⎞
⎜
⎝
⎛
+
+
=
1
21
1
1
)(
sC
R
sC
sK
LF
LF
The VCO transfer function (in rad/s, and accounting for the phase integration that occurs in the VCO) is:
s
AsK VCOVCO 1
2)(
π
=
The transfer function of the feedback divider is:
F
FN
K1
=
Finally, the sampling effect that occurs in the phase detector is accounted for by:
REF
f
s
SAMP f
s
e
sK REF
⎟
⎟
⎟
⎠
⎞
⎜
⎜
⎜
⎝
⎛−
=
⎟
⎠
⎞
⎜
⎝
⎛
−
1
)(
The loop gain of the PLL is: )()()()( sKKsKsKKsK SAMPFVCOLFPDLOOP
=
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
0.01
Frequency (f
i
)
0.1
0.1kHz 1kHz 10kHz 100kHz
1
10
100
Amplitude
Figure 8: Loop Gain vs. Frequency
The loop phase angle is:
[
]
)
2(arg iLOOPi fjK
π
=
Θ
-150°
Frequency (f
i
)
-100°
Phase
0.1kHz 1kHz 10kHz 100kHz
Figure 9: Loop Nyquist Plot
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
A Nyquist plot of gain vs. amplitude is shown belo w.
45°
0°
315°
270°
225°
180°
135°
90°
0.2
0.4
0.6
0.8
1.0
Phase
Amplitude
1.2
Gain Margin
Phase
Margin
Figure 10: Loop Nyquist Plot
4.4 Voltage-Controlled Crystal Oscillator
The VCXO provides a tunable, low-jitter frequency reference for the rest of the FS6131 system components. Loading capacitance for
the crystal is internal to the device. No external components (other than the resonator itself) are required for operation of t he VCXO.
The resonator loading capacitance is adjustable under register control. This feature permits factory coarse tuning of inexpensive
resonators to the necessar y precision for digital video applications. Continuous fine-tuni ng of the VCXO frequency is accomplis hed by
varying the voltage on the XTUNE pin. The total change (from one extreme to the other) in effective loading capacitance is 1.5pF
nominal, and the effect is shown in Figure 11. The oscillator operates the crystal resonator in the parallel-resonant mode. Crystal
warping, or the "pulling" of the crystal oscillation fre quency, is accomplish ed by altering the effective lo ad capacitance pres ented to the
crystal by the oscillator circui t. The actual amount that cha nging the load capacitance alt ers the oscillator frequency will be dependent
on the characteristics of the crystal as well as the oscillator circuit itself.
The motional capacitance of the crystal (usually referred to by crystal manufacturers as C1), the static capacitance of the crystal (C0)
and the load capacitanc e (CL) of the oscillator determine the warping capability of the crystal in the oscillator circuit. A simple formula t o
determine the total warping capability of a crystal is
(
)
()()
CCCC CCC
ppmf LL
LL
1020
6
121
210
)( +×+×
×−×
=∆
where CL1 and CL2 are the two extremes of the app lied load capacitance obtained from Table 11.
Example: A crystal with the following parameters is used with the FS6131. The total coarse tuning range is:
C1=0.02pF, C0=5.0pF, CL1=10.0pF, CL2=22.66pF
(
)
()()
ppm
.
..
f305
105662252 10106622020 6=
+×+×
×−×
=∆
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
4.4.1 VCXO Tuning
The VCXO may be coarse tuned by a pr ogrammable adjus tment of the cr ystal load capacitance via the XCT[3:0] control bits. See Table
11 for the control code and the associated l oading capacitance.
The actual amount of frequency warping caused by the tuning capacitance will depend on the crystal used. The VCXO tuning
capacitance includes an e xternal 6pF load capac itance (12pF from the XIN pin to gro und and 12pF from the XOUT pin to ground). The
fine tuning capability of the VCXO can be enabled by setting the XLVTEN bit to a one, or disabled by setting it to a zero.
Figure 11 shows the typical effect of the coarse and fine tuning mechanisms. The total coarse tune range is about 350ppm. The
difference in VCXO frequency in parts per million (ppm) is shown as the fine tuning voltage on the XTUNE pin varies from 0V to 5V.
Note that as the crystal loa d capacitanc e is increas ed the V CXO frequenc y is pu lled som e what less with each coars e step, an d the fi ne
tuning range decreases. The fine tuning range always overlaps a few coarse tuning ranges, eliminating the possibility of holes in the
VCXO response. The different cr ystal warping characteristic s may cha nge the scal ing on t he Y-ax is, but not the overall characteristic of
the curves.
VCXO Range (ppm) vs. XTUNE Voltage (V)
-200
-150
-100
-50
0
50
100
150
200
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Coarse Tune S et ting XCT[3:0]
VCXO Range (ppm)
XTUNE Voltage = 0.0V
XTUNE Voltage = 5.0V
Figure 11: VCXO Coarse and Fine Tuning
4.5 Crystal Loop
The crystal loop is designed to attenuate the jitter on a highly jittered, low-Q, low frequency reference. The crystal loop can also
maintain a constant frequenc y output into the main loop if the low frequency reference is intermittent.
The crystal loop consists of a voltage-controll able crystal os cillator (VCXO), a div ider, a PFD, and a charge pump that tunes the V CXO
to a frequency reference. The frequency reference is phase-locked to the divided frequency of an external, high-Q, jitter-free crystal,
thereby locking the VCXO to the reference frequency. The VCXO can continue to run off the crystal even if the frequency reference
becomes intermittent.
4.5.1 Locking to an External Frequency Source
When the cryst al loop is synchronized to an external frequenc y source, the FS6131 can monitor the crystal loop and detect if the loop
unlocks from the external source. The crystal loop tries to drive to zero frequency if the external source is dropped, and sets a lock
status error flag.
The crystal loop can also detect if the VCXO has dropped out of the fine tune range, requiring a change to the coarse tune. The lock
status also latches the direction the loop went out of range (high or l ow) when the loop became unlocked.
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
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4.5.1.1 Crystal Loop Lock Status Flag
To enable this mode, clear the STAT[1] and STAT[0] bits to zero. If the CMOS bit is set to one, the LOCK/IPRG pin will be low if the
crystal loop becomes unlocked. The flag is always available under software control by reading back the STAT[1] bit, which is
overwritten with the status flag (low = unlocked) in this mode (see Table 6).
4.5.1.2 Out-Of-Range High/Low
The direction the loop has gone out-of-range can be determined by clearing STAT[1] to zero and setting STAT[0] bit to one. If the
CMOS bit is set to one, the LOCK/IPRG pin will go high if t he crystal loop went o ut of range hig h. If the pin goes to a logic-l ow, the loop
went out of range low.
The out-of-range information is also available under software control by reading back the STAT[1] bit, which is overwritten by the flag
(high = outof-range high, lo w = out-of-range low) in this mod e. The bit is set or cleared only if the crystal loop los es lock (see Table 6).
4.5.1.3 Crystal Loop Disable
The crystal loop is disabled by setting the XLPDEN bit to a logic-high (1). The bit disable s the charge pump circuit in the loop.
Setting the XLPDEN bit low (0) permits the crystal loop to operate as a control loop.
4.6 Connecting the FS6131 to an External Reference Frequency
If a crystal oscillator is not used, tie XIN to ground and shut down the crystal oscillator by setting XLROM[2:0]=1.
The REF and F BK pins do not have pull-u p or pull-down current, but do have a small amount of hysteresis to reduce the possibility of
extra edges. Signals may be AC-coupled into these inputs with an external DC-bias circuit to generate a DC-bias of 2.5V. Any
reference or feedback signal shou ld be sq uare for best res u lt s, and the sig nals s hou ld be rail-to-ra il. Unu sed i nputs s hould be grounded
to avoid unwanted signal injection.
4.7 Differential Output Stage
The differential output stage supports both CMOS and pseudo-ECL (PECL) signals. The desired output interface is chosen via the
program registers (see T able 4).
If a PECL interface is used, the transmission line is usually terminated using a Thévenin termination. The output stage can only sink
current in the PECL mode, and the amount of sink current is set by a pro gramming resistor on the LOCK/IPRG pin. T he ratio of IPRG
current to output drive current is shown in Figure 12. Source current is provided by the pull-up resistor that is part of the Thévenin
termination.
0.0
5.0
10.0
15.0
20.0
25.0
0 20406080
CLKP/CLKN PECL Output C urren t (mA)
IPRG Input Current (mA)
Figure 12: IPRG to CLKP/CLKN Current
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
5.0 I2C-bus Control Interface
This device is a read/ write slave devic e meeting all Phili ps I2C-bus specifi cations except a "g eneral call." T he bus has to b e
controlled by a master device that generates the serial clock SCL, controls bus access and generates the START and
STOP conditions while the d evice works as a slave. B oth master a nd slave ca n oper ate as a tra nsmitter or receiver, but the
master device determines which mode is acti vated. A device that sends data onto the bu s is defined as the transmitter, and
a device receiving data as the receiver. I 2C-bus logic levels noted herein ar e based on a percentage of the power supply (V DD). A logic-
one corresponds to a nominal voltage of VDD, while a logic-zero correspon ds to ground (VSS).
5.1 Bus Conditions
Data transfer on the bus can only be initiate d when the bus is not busy. During the data transfer, the data line (SDA) must remain stable
whenever the clock li ne (SCL) is high. Chan ges in the d ata line while the cl ock line is high will be inter preted by the dev ice as a ST ART
or STOP condition. The following bus conditions are defined by the I2C-bus protocol.
5.1.1 Not Busy
Both the data (SDA) and clock (SCL) lines remain high to indicate the bus is not busy.
5.1.2 START Data Transfer
A high to low transition of the SDA line while the SCL in-put is high indicates a ST ART condition. All co mmands to the device must be
preceded by a START condition.
5.1.3 STOP Data Transfer
A low to high transition of the SDA line while SCL is held high indicates a STOP condition. All commands to the device must be
followed by a STOP condition.
5.1.4 Data Valid
The state of the SDA line repr esents va lid da ta if the SDA li ne is sta ble for the dur at io n of the high p eri od of the SCL lin e a fter a ST ART
condition occurs . The data on the SDA line must be change d only dur ing t he lo w period of the SCL sig nal. There is o ne clock pulse per
data bit.
Each data transfer is initiated by a START condition and terminated with a STOP condition. The number of data bytes transferred
between START and STOP conditions is determined by the master device, and can continue indefinitely. However, data that is
overwritten to the device after the first eight bytes will overflow into the first register, then the second, and so on, in a first-in, first-
overwritten fashion.
5.1.5 Acknowledge
When addressed, the receiving device is required to generate an acknowledge after each byte is received. The master device must
generate an extra clock pulse to coincide with the acknowledge bit. The acknowledging device must pull the SDA line low during the
high period of the master acknowledge cl ock pulse. Setup and hold times must be taken into account.
The master must signal an end of data to the slave by not generat ing an acknowledge bit on the last b yte that has been read (clocked)
out of the slave. In this case, the slave must leave the SDA line high to enable the master to generate a STOP condition.
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
5.2 I2C-bus Operation
All programmable registers can be accessed randomly or sequentially via this bi-directional two wire digital interface. The crystal
oscillator does not have to run for communication to occur.
The device accepts the following I2C-bus commands.
5.2.1 Slave Address
After generating a START condition, the bus master broadcasts a seven-bit slave address followed by a R/W bit. The address of the
device is:
A6 A5 A4 A3 A2 A1 A0
1 0 1 1 X 0 0
where X is controlled by the logic level at the ADDR pin. The variable ADDR bit allows two different FS6131 devices to exist on the
same bus. Note that every device on an I2C-bus must have a unique address to avoid bus conflicts. The default address sets A2 to 0
via the pull-down on the ADD R pin.
5.2.2 Random Register Write Procedure
Random write operations allow the master to directly write to any register. To initiate a write proced ure, the R/W bit that is transmitted
after the seven-bit device address is a logic- low. This indicates to the addressed slave device that a register address will follow after the
slave device acknowledges its device address. The register address is written into the slave's address pointer. Following an
acknowledge by the slave, the master is a llowed to write eight bits of data into the addr essed register. A final acknowledge is returned
by the device, and the master generates a STOP condition.
If either a STOP or a repeated START condi tion occurs during a register write, the data that has been transferred is ignored.
5.2.3 Random Register Read Proc edure
Random read operations allow the master to directly read from any register. To perform a read procedure, the R/W bit that is
transmitted after the seven-bit address is a logic-low, as in the register write procedure. This indicates to the addressed slave device
that a register address will follow after the sl ave device acknowledges its device address . The register address is then written into the
slave's address pointer.
Following an ackno wledge by the slave, the master generates a repeate d START condition. T he repeated START terminates the write
procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a
logic-high, indicating to the sl ave that data will be read. The slav e will ackno wledge the dev ice address , and then transmits t he eight-bit
word. The master does not acknowledge the transfer but does gen erate a STOP condition.
5.2.4 Sequential Register Write Procedure
Sequential write operations allow the master to write to each register in order. The register pointer is automatically incremented after
each write. This procedure is more efficient than the ra ndom register write if several registers must be written.
To initiate a write procedure, the R/W bit that is transmitted after the seven-bit device address is a logic-low. This indicates to the
addressed slave d evice that a regist er addre ss will follow af ter the slave device acknowledges its device ad dress. The register addres s
is written into the slave's address pointer. Following an acknowledge by the slave, the master is allowed to write up to eight bytes of
data into the addressed register before the register address pointer overflows back to the beginning address. An acknowledge by the
device between each byt e of data must occur before the n ext data byte is sent.
Registers are updated every time the device sends an acknowledge to the host. The register update does not wait for the STOP
condition to occur. Registers are therefor e updated at different times during a sequential register write.
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
5.2.5 Sequential Register Read Procedure
Sequential read operations allow the master to read from each register in order. The register pointer is automatically incremented by
one after each read. This procedure is more efficient than the random register read if several registers must be read.
To perform a read procedur e, the R/W bit that is transmitted after the seven-bit address is a logic-low, as in the register write procedure.
This indicates t o the addressed slave device that a register address will follow after the slave devic e acknowledges its devic e address.
The register address is then written into the slave's address pointer.
Following an ackno wledge by the slave, the master generates a repeate d START condition. T he repeated START terminates the write
procedure, but not until after the slave's address pointer is set. The slave address is then resent, with the R/W bit set this time to a
logic-high, indicating to the slave that data will be read. The slave will acknowledge the device address, and then transmits all eight
bytes of data starting with the initial ad dressed register. The register addr ess pointer will overflow if the initial register address is larger
than zero. After the last byte of data, the master does not acknowledge the transfer but does generate a STOP condition.
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
AA DATAW A
From bus host
to device
S REGISTER ADDRESS P
From device
to bus host
DEVICE ADDRESS
Register Address
Acknowledge STOP Condition
Data
Acknowledge
Acknowledge
START
Command WRITE Command
7-bit Receive
Device Address
Figure 13: Random Register Write Procedure
AR AAAWS REGISTER ADDRESS PS DEVICE ADDRESS
START
Command WRITE Command
Acknowledge
Register Address
Acknowledge READ Command
Acknowledge
Data
NO Acknowledge
STOP Condition
From bus host
to device From device
to bus host
7-bit Receive
Device Address
7-bit Receive
Device Address
DEVICE ADDRESS DATA
Repeat START
Figure 14: Random Register Read Procedure
AAAWS P
START
Command WRITE Command
Acknowledge
Register Address
Acknowledge
Data
Data
Acknowledge
Data
STOP Command
AcknowledgeAcknowledge
From bus host
to device From device
to bus host
7-bit Receive
Device Address
DEVICE ADDRESS AA REGISTER ADDRESS DATA DATA DATA
Figure 15: Sequential Register Write Procedure
AWS
START
Command WRITE Command
Acknowledge
Register Address
Acknowledge
Data
Acknowledge
Data
STOP Command
Acknowledge READ Command
NO Acknowledge
From bus host
to device From device
to bus host
7-bit Receive
Device Address 7-bit Receive
Device Address
DEVICE ADDRESS AA REGISTER ADDRESS AR A PS DEVICE ADDRESS DATA DATA
Repeat START
Figure 16: Sequential Register Read Procedure
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
6.0 Programming Information
All register bits are cleared to zero on power-up. All register bits may be read back as written except STAT[1] (Bit 63).
Table 3: Register Map
Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
STAT[1]
(Bit 63) STAT[0]
(Bit 62) XLVTEN
(Bit 61) CMOS
(Bit 60) XCT[3]
(Bit 59) XCT[2]
(Bit 58) XCT[1]
(Bit 57) XCT[0]
(Bit 56)
00 = Crystal Loop – Lock Status
01 = Crystal Loop – Out of Range 0 = Fine Tune
Inactive 0 = PECL
10 = Main Loop – Phase Status
Byte 7
11 = Feedback Divider Output 1 = Fine Tune
Active 1 = CMOS, Lock
Status
VCXO Coarse Tune
See Table 11
XLPDEN
(Bit 55) XLSWAP
(Bit 54) XLCP[1]
(Bit 53) XLCP[0]
(Bit 52) XLROM[2]
(Bit 51) XLROM[1]
(Bit 50) XLROM[0]
(Bit 49) GBL
(Bit 48)
00 = 1.5
µ
A
0 = Crystal Loop
Operates 0 = Use with
External VCXO 01 = 5
µ
A
0 = No Clock
Phase Adjust
10 = 8
µ
A
Byte 6
1 = Crystal Loop
Powered Dow n 1 = Use with
Internal VCXO 11 = 24
µ
A
Crystal Loop Control
See Table 10 1 = Clock Phase
Delay
OUTMUX[1]
(Bit 47) OUTMUX[0]
(Bit 46) OSCTYPE
(Bit 45) VCOSPD
(Bit 44) LFTC
(Bit 43) EXTLF
(Bit 42) MLCP[1]
(Bit 41) MLCP[0]
(Bit 40)
00 = VCO Output 00 = 1.5
µ
A
01 = Reference Divider Output 0 = Low Phase
Jitter Oscillator 0 = High Speed
Range 0 = Short Time
Constant 0 = Internal Loop
Filter 01 = 5
µ
A
10 = Phase Detector Input 10 = 8
µ
A
Byte 5
11 = VCXO Output 1 = FS6031
Oscillator 1 = Low Speed
Range 1 = Long Time
Constant 1 = External Loop
Filter 11 = 24
µ
A
FBKDSRC[1]
(Bit 39) FBKDSRC[0]
(Bit 38) FBKDIV[13]
(Bit 37) FBKDIV[12]
(Bit 36) FBKDIV[11]
(Bit 35) FBKDIV[10]
(Bit 34) FBKDIV[9]
(Bit 33) FBKDIV[8]
(Bit 32)
00 = Post Divider Output
01 = FBK Pin 8192 4096 2048 1024 512 256
10 = Post Divider Input
Byte 4
11 = FBK Pin M Counter
FBKDIV[7]
(Bit 31) FBKDIV[6]
(Bit 30) FBKDIV[5]
(Bit 29) FBKDIV[4]
(Bit 28) FBKDIV[3]
(Bit 27) FBKDIV[2]
(Bit 26) FBKDIV[1]
(Bit 25) FBKDIV[0]
(Bit 24)
128 64 32 16 8 4 2 1
Byte 3
M Counter A Counter – See Table 2
POST3[1]
(Bit 21) POST3[1]
(Bit 20) POST2[1]
(Bit 19) POST2[0]
(Bit 18) POST1[1]
(Bit 17) POST1[0]
(Bit 16)
00 = Divide by 1 00 = Divide by 1 00 = Divide by 1
01 = Divide by 3 01 = Divide by 3 01 = Divide by 2
10 = Divide by 5 10 = Divide by 5 10 = Divide by 4
Byte 2 Reserved (0) Reserved (0)
11 = Divide by 4 11 = Divide by 4 11 = Divide by 8
PDFBK
(Bit 15) PDREF
(Bit 14) SHUT
(Bit 13) REFDSRC
(Bit 12) REFDIV[11]
(Bit 11) REFDIV[10]
(Bit 10) REFDIV[9]
(Bit 9) REFDIV[8]
(Bit 8)
0 = Feedback
Divider 0 = Reference
Divider 0 = Main Loop
Operates 0 = VCXO
Byte 1
1 = FBK Pin 1 = REF Pin 1 = Main Loop
Powered Dow n 1 = Ref Pin 2048 1024 512 256
REFDIV[7]
(Bit 7) REFDIV[6]
(Bit 6) REFDIV[5]
(Bit 5) REFDIV[4]
(Bit 4) REFDIV[3]
(Bit 3) REFDIV[2]
(Bit 2) REFDIV[1]
(Bit 1) REFDIV[0]
(Bit 0)
Byte 0 128 64 32 16 8 4 2 1
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
Table 4: Device Configuration Bits
Name Description
REFerence Divider SouRCe
Bit = 0 Crystal Oscillator (VCXO)
REFDSRC
(Bit 12) Bit = 1 REF pin
main loop SHUT down select
Bit = 0 Disabled (main loop operates)
SHUT
(Bit 13) Bit = 1 Enabled (main loop shuts down)
Phase Detector REFerence source
Bit = 0 Reference Divider
PDREF
(Bit 14) Bit = 1 REF pin
Phase Detector FeedBacK source
Bit = 0 Feedback Divider
PDFBK
(Bit 15) Bit = 1 FBK pin
FeedBacK Divider SouRCe
Bit 39 = 0
Bit 38 = 0 Post Divider Output
Bit 39 = 0
Bit 38 = 1 FBK pin
Bit 39 = 1
Bit 38 = 0 VCO Output (Post Divider Input)
FBKDSRC[1:0]
(Bits 39-38)
Bit 39 = 1
Bit 38 = 1 FBK pin
EXTernal Loop Filter select
Bit = 0 Internal Loop Filter
EXTLF
(Bit 42) Bit = 1 EXTLF pin
OSCillator TYPe
Bit = 0 Low Phase Jitter Oscillator
OSCTYPE
(Bit 45) Bit = 1 FS6031 Compatible Oscillator
OUTput MUltipleXer select
Bit 47 = 0
Bit 46 = 0 Main Loop PLL (VCO Output)
Bit 47 = 0
Bit 46 = 1 Reference Divider Output
Bit 47 = 1
Bit 46 = 0 Phase Detector Input
OUTMUX[1:0]
(Bits 47-46)
Bit 47 = 1
Bit 46 = 1 VCXO Output
clock GobBLer control
Bit = 0 No Clock Phase Adjust
GBL
(Bit 48) Bit = 1 Clock Phase Delay
CLKP/CLKN output mode
Bit = 0 PECL Output
(positive-ECL output drive)
CMOS
(Bit 60) Bit = 1 CMOS Output /
Lock Status Indicator
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
Table 5: LOCK/IPRG Pin Configuration Bits
Name Description
Crystal Loop Lock STATus Mode /
Main Loop Phase Align STATus mode
(see also Table 6)
Bit 63 = 0
Bit 62 = 0 Crystal Loop Lock status:
Locked or Unlocked
Bit 63 = 0
Bit 62 = 1 Crystal Loop Lock status:
Out of Range High or Low
Bit 63 = 1
Bit 62 = 0 Main Loop Phase Align status
STAT[1:0]
(Bits 63-62)
Bit 63 = 1
Bit 62 = 1 Feedback Divider output
Table 6: Lock Status
CMOS STAT [1] STAT [0] LOCK /
IPRG PIN STAT[1]
Read Status
1 1 Locked
1 0 0 0 0 Unlocked
0 0 Out-of-Range: Low
1 0 1 1 1 Out-of-Range: High
Table 7: Main Loop Tuning Bits
Name Description
VCO SPeeD range select (see Table 16)
Bit = 0 High Speed Range
VCOSPD
(Bit 44) Bit = 1 Low Speed Range
Main Loop Charge Pump current
Bit 41 = 0
Bit 40 = 0 Current = 1.5µA
Bit 41 = 0
Bit 40 = 1 Current = 5µA
Bit 41 = 1
Bit 40 = 0 Current = 8µA
MLCP[1:0]
(Bits 41-40)
Bit 41 = 1
Bit 40 = 1 Current = 24µA
Loop Filter Time Constant (internal)
Bit = 0 Short Time Constant: 13.5µs
LFTC
(Bit 43) Bit = 1 Long Time Constant: 135µs
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
Table 8: Divider Control Bits
Name Description
REFDIV[11:0]
(Bits 11-0) REFerence DIVider (NR)
FeedBacK DIVider (NF)
FBKDIV[2:0] A-Counter Value
FBKDIV[13:0]
(Bits 37-24) FBKDIV[13:3] M-Counter Value
POST Divider #1 (NP1)
Bit 17 = 0
Bit 16 = 0 Divide by 1
Bit 17 = 0
Bit 16 = 1 Divide by 2
Bit 17 = 1
Bit 16 = 0 Divide by 4
POST1[1:0]
(Bits 17-16)
Bit 17 = 1
Bit 16 = 1 Divide by 8
POST Divider #2 (NP2)
Bit 19 = 0
Bit 18 = 0 Divide by 1
Bit 19 = 0
Bit 18 = 1 Divide by 3
Bit 19 = 1
Bit 18 = 0 Divide by 5
POST2[1:0]
(Bits 19-18)
Bit 19 = 1
Bit 18 = 1 Divide by 4
POST Divider #3 (NP3)
Bit 21 = 0
Bit 20 = 0 Divide by 1
Bit 21 = 0
Bit 20 = 1 Divide by 3
Bit 21 = 1
Bit 20 = 0 Divide by 5
POST3[1:0]
(Bits 21-20)
Bit 21 = 1
Bit 20 = 1 Divide by 4
Reserved (0)
(Bits 23-22) Set these reserved bits to 0
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
Table 9: Crystal Loop Tuning Bits
Name Description
Crystal Loop Charge Pump current
Bit 53 = 0
Bit 52 = 0 Current = 1.5µA
Bit 53 = 0
Bit 52 = 1 Current = 5µA
Bit 53 = 1
Bit 52 = 0 Current = 8µA
XLCP[1:0]
(Bits 53-52)
Bit 53 = 1
Bit 52 = 1 Current = 24µA
XLROM[2:0]
(Bits 51-49) Crystal Loop Divider R OM select and Crystal Oscillator Power-Down
(see Error! Reference source not found.)
Crystal Loop Voltage fine Tune ENable
Bit = 0 Disabled (fine tune is inactive)
XLVTEN
(Bit 61) Bit = 1 Enabled (fine tune is active)
Crystal Loop SW AP polarity
Bit = 0 Use with an external VCXO that increases in
frequency in response to an increasing voltage at
the XTUNE pin.
XLSWAP
(Bit 54)
Bit = 1
Use with a VCXO that increases in frequency in
response to a decreasing voltage at the XTUNE
pin.
Use this setting for Internal VCXO
Crystal Loop Power Down Enable
Bit = 0 Disabled (crystal loop operates)
XLPDEN
(Bit 55) Bit = 1 Enabled
(crystal loop is powered down)
XCT[3:0]
(Bits 59-56) Crystal Coarse Tune (see Table 11)
Table 10: Crystal Loop Control ROM
XLROM
[2] XLROM
[1] XLROM
[0] VCXO Divider Crystal Frequency (MHz)
0 0 0 1 -
0 0 1 3072 24.576
0 1 0 3156 25.248
0 1 1 2430 19.44
1 0 0 2500 20.00
1 0 1 4000 32.00
1 1 0 3375 27.00
1 1 1 Crystal oscillator power-down
6.1 VCXO Coarse Tune
The VCXO may be coarse tuned by a programmable adjustment of the crystal load capacitance via XCT[3:0]. The actual amount of
frequency warping caused by the tuning capacitance will depend on the crystal used. The VCXO tuning capacitance includes an
external 6pF load cap acitance (12pF from the XIN pin to ground an d 12pF from the XOUT pin to ground). The fine tuning cap ability of
the VCXO can be enabled by setting the XLVTEN bit to a logic-one, or disabled by setting the bit to a logic-zero.
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
Table 11: VCXO Coarse Running Capacitance
XCT[3] XCT[2] XCT[1] XCT[0] VCXO Tuning Capacitance (pf)
0 0 0 0 10.00
0 0 0 1 10.84
0 0 1 0 11.69
0 0 1 1 12.53
0 1 0 0 13.38
0 1 0 1 14.22
0 1 1 0 15.06
0 1 1 1 15.91
1 0 0 0 16.75
1 0 0 1 17.59
1 0 1 0 18.43
1 0 1 1 19.28
1 1 0 0 20.13
1 1 0 1 20.97
1 1 1 0 21.81
1 1 1 1 22.66
7.0 Electrical Specifications
Table 12: Absolute Maximum Ratings
Parameter Symbol Min. Max. Units
Supply Voltage, dc (VSS = ground) VDD VSS-0.5 7 V
Input Voltage, dc VIVSS-0.5 VDD+0.5 V
Output Voltage, dc VOVSS-0.5 VDD+0.5 V
Input Clamp Current, dc (VI < 0 or VI > VDD) IIK -50 50 mA
Output Clamp Current, dc (VI < 0 or VI > VDD) IOK -50 50 mA
Storage Temperature Range (non-condensing) TS-65 150 °C
Ambient Temperature Range, Under Bias TA-55 125 °C
Junction Temperature TJ 150 °C
Lead Temperature (soldering, 10s ) 260 °C
Input Static Discharge Voltage Protection (MIL-STD 883E, Method 3015.7) 2 kV
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These conditions represent a stress rating only, and functional
operation of the device at these or any other conditions above the operational limits noted in this specification is not implied. Exposure to maximum rating conditions for
extended conditions may affect device performance, functionality, and reliability.
CAUTION: ELECTROSTATIC SENSITIVE DEVICE
Permanent damage resulting in a loss of functionality or performance may occur if this device is subjected to a high-energy
electrostatic discharge.
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
Table 13: Operating Conditions
Parameter Symbol Conditions/Descriptions Min. Typ. Max. Units
Supply Voltage VDD 5V ± 10% 4.5 5 5.5 V
Ambient Operating Temperature Range TA 0 70 °C
Crystal Resonator Frequency fXIN 19.44 27 28 MHz
Crystal Resonator Load Capacitance CXL Parallel resonant, AT cut 18 pF
Crystal Resonator Motional Capacitance CXM Parallel resonant, AT cut 25 fF
Serial Data Transfer Rate Standard mode 10 100 400 kb/s
PECL Mode Programming Current
(LOCK/IPRG Pin High-Level Input Current) IIH PECL Mode 15 mA
Output Driver Load Capacitance CL 15 pF
Table 14: DC Electrical Specifications
Parameter Symbol Conditions/Description Min. Typ. Max. Units
Overall
Supply Current, Dynamic,
(with Loaded Outputs) IDD fCLK = 66MHz ; CMOS Mode, VDD = 5.5V 100 mA
Supply Current, Static IDDL SHUT = 1, XLROM[2:0] = 7, XLPDEN = 1
VDD = 5.5V 12 mA
Serial Communication I/O (SDA, SCL)
High-Level Input Voltage VIH Outputs off 3.5 VDD+0.3 V
Low-Level Input Voltage VIL Outputs off VSS-0.3 1.5 V
Hysteresis Voltage * Vhys Outputs off 2 V
Input Leakage Current II -1 1 µA
Low-Level Output Sink Current (SDA) IOL VOL = 0.4V 20 32 mA
Tristate Output Current IZ -10 10 µA
Address Select Input (ADDR)
High-Level Input Voltage VIH 2.4 VDD+0.3 V
Low-Level Input Voltage VIL VSS-0.3 0.8 V
High-Level Input Current (pull-down) IIH VIH = VDD = 5.5V 5 16 30 µA
Low-Level Input Current IIL -2 2 µA
Reference Frequency Input (REF, FBK)
High-Level Input Voltage VIH 3.5 VDD+0.3 V
Low-Level Input Voltage VIL VSS-0.3 1.5 V
Hysteresis Voltage Vhys 500 mV
Input Leakage Current II -1 1 µA
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
Table 14: DC Electrical Specifications (Continued)
Parameter Symbol Conditions/Description Min. Type. Max. Units
Loop Filter Input (EXTLF)
Input Leakage Current IIEXTLF = 0 -1 1 µA
VO = 0.8V; EXTLF =1, MLCP[1:0] = 0 -1.5
VO = 0.8V; EXTLF =1, MLCP[1:0] = 1 -5
VO = 0.8V; EXTLF =1, MLCP[1:0] = 2 -8
High-Level Output Source Current IOH
VO = 0.8V; EXTLF =1, MLCP[1:0] = 3 -24
µA
VO = 4.2V; EXTLF =1, MLCP[1:0] = 0 1.5
VO = 4.2V; EXTLF =1, MLCP[1:0] = 1 5
VO = 4.2V; EXTLF =1, MLCP[1:0] = 2 8
Low-Level Output Sink Current IOL
VO = 4.2V; EXTLF =1, MLCP[1:0] = 3 25
µA
Crystal Oscillator Input (XIN)
Threshold Bias Voltage VTH 1.5 2.2 3.5 V
High-Level Input Current IIH Outputs off; VIH = 5V 10 24 30 mA
Low-Level Input Current IIL Outputs off; VIL = 0V -10 -19 -30 mA
Crystal Loading Capacitance * CL(xtal) As seen by an external crystal connected
to XIN and XOUT; VCXO tuning disabled 10 pF
Input Loading Capacitance * CL(XIN) As seen by an external clock driver on
XOUT; XIN unconnected; VCXO disabled 20 pF
Crystal Oscillator Output (XOUT)
High-Level Output Source Current IOH VO = 0V, float XIN -20 -30 -50 mA
Low-Level Output Sink Current IOL VO = 5V, float XIN -20 -40 -50 mA
VCXO Tuning I/O (XTUNE)
High-Level Input Voltage VIH Lock Status: Out of Range HIGH 3.2 VDD+0.3 V
Low-Level Input Voltage VIL Lock Status: Out of Range LOW VSS-0.3 0.3 V
Hysteresis Voltage Vhys 1.0 V
Input Leakage Current IIXLPDEN = 0 -1 1 µA
VO = 0.8V; XLCP[1:0] = 0 -1.5
VO = 0.8V; XLCP[1:0] = 1 -5
VO = 0.8V; XLCP[1:0] = 2 -8
High-Level Output Source Current IOH
VO = 0.8V; XLCP[1:0] = 3 -24
µA
VO = 4.2V; XLCP[1:0] = 0 1.5
VO = 4.2V; XLCP[1:0] = 1 5
VO = 4.2V; XLCP[1:0] = 2 8
Low-Level Output Sink Current IOL
VO = 4.2V; XLCP[1:0] = 3 25
µA
Lock Indicator / PECL Current Program I/O (LOCK/IPRG)
Low-Level Input Current IIL PECL Mode -1 1 µA
High-Level Output Source Current IOH CMOS Mode; VO = 2.4V -25 -38 mA
Low-Level Output Sink Current IOL CMOS Mode; VO = 0.4V 5 9 mA
zOH VO = 0.5VDD; output driving high 66
Output Impedance * zOL VO = 0.5VDD; output driving low 76 Ω
Short Circuit Source Current * ISCH VO = 0V; shorted for 30s, max. -47 mA
Short Circuit Sink Current * ISCL VO = 5V; shorted for 30s, max. 47 mA
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
Table 14: DC Electrical Specifications (Continued)
Parameter Symbol Conditions/Description Min. Typ. Max. Units
Clock Outputs, CMOS Mode (CLKN, CLKP)
High-Level Output Source Current IOH VO = 2.4V -45 -68 mA
Low-Level Output Sink Current IOL VO = 0.4V 15 20 mA
zOH VO = 0.5VDD; output driving high 28
Output Impedance * zOL VO = 0.5VDD; output driving low 33 Ω
Short Circuit Source Current * ISCH VO = 0V; shorted for 30s, max. -100 mA
Short Circuit Sink Current * ISCL VO = 5V; shorted for 30s, max. 100 mA
Clock Outputs, PECL Mode (CLKN, CLKP)
IPRG Current to Output Current Ratio 1:4
Low-Level Output Sink Current IOL IPRG input current = 15mA 60 mA
Tristate Output Current IZ -10 10
µA
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent
nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical. Negative currents indicate current
flows out of the device.
Table 15: AC Timing Specifications
Parameter Symbol Conditions/Description Clock
(MHz) Min. Typ. Max. Units
Overall
CMOS Outputs 130
Output Frequency * fO(max) PECL Outputs 230 MHz
Low Phase Jitter Oscillator (OSCTYPE = 0)
VCOSPD = 0 40 160
VCOSPD = 1 40 100
FS6031 Compatible Oscillator (OSCTYPE = 1)
VCOSPD = 0 40 230
VCO Frequency * fVCO
VCOSPD = 1 40 140
MHz
Low Phase Jitter Oscillator (OSCTYPE = 0)
VCOSPD = 0 125
VCOSPD = 1 75
FS6031 Compatible Oscillator (OSCTYPE = 1)
VCOSPD = 0 130
VCO Gain * AVCO
VCOSPD = 1 78
MHz/V
LFTC = 0 13.5
Loop Filter Time Constant * LFTC = 1 135 µs
Rise Time * trCMOS Outputs, VO = 0.5V to 4.5V; CL = 15pF 1.1 ns
Fall Time * tfCMOS Outputs, VO = 4.5V to 0.5V; CL = 15pF 0.8 ns
Frequency Synthesis 200 µs
Lock Time (Main Loop) * Line Locked Modes (8kHz reference) 10 ms
Disable Time * From falling edge of SCL for the last data bit
(SHUT = 1 to 0) to output locked 10 µs
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
Table 15: AC Specifications (Continued)
Parameter Symbol Conditions/Description Clock
(MHz) Min. Typ. Max. Units
Divider Modulus
Feedback Divider NFFBKDIV[13:0] (See also Table 2) 8 16383
Reference Divider NRREFDIV[11:0] 1 4095
NP1 POST1[1:0] (See also Table 8) 1 8
NP2 POST2[1:0] (See also Table 8) 1 5
Post Divider
NP3 POST3[1:0] (See also Table 8) 1 5
Clock Output (CLKP, CLKN)
Duty Cycle * Ratio of pulse width (as measured from rising edge to next falling
edge at 2.5V) to one clock period 100 47 54 %
Rising edges 50ms apart at 2.5V, relative to an ideal clock,
CL=15pF, fREF=8kHz, NR=1, NF=193, NPx=64, CLF=0.054µF,
RLF=15.7kΩ, CLP=1800pF, OSCTYPE=0, MLCP=3, XLROM=7 1.544 270
Rising edges 50ms apart at 2.5V, relative to an ideal clock,
CL=15pF, fREF=15kHz, NR=1, NF=800, NPx=10, CLF=0.0246µF,
RLF=15.7kΩ, CLP=820pF, OSCTYPE=0, MLCP=3, XLROM=7 12.00 160
On rising edges 5ms apart at 2.5V relative to an ideal clock,
CL=15pF, fREF=31.5kHz, NR=1, NF=799, NPx=4, CLF=0.015µF,
RLF=15.7kΩ, CLP=470pF, OSCTYPE=0, MLCP=3, XLROM=7 25.175 100
On rising edges 500µs apart at 2.5V relative to an ideal clock,
CL=15pF, CMOS mode, fXIN=27MHz, NF=200, NR=27, NPx=2 100 30
Jitter, Long Term (σy(τ)) * tj(LT)
On rising edges 500µs apart at 2.5V relative to an ideal clock,
CL=15pF, PECL mode, fXIN=27MHz, NF=200, NR=27, NPx=1 200 30
ps
From rising edge to next rising edge at 2.5V, CL=15pF,
fREF=8kHz, NR=1, NF=193, NPx=64, CLF=0.054µF, RLF=15.7kΩ,
CLP=1800pF, OSCTYPE=0, MLCP=3, XLROM=7 1.544 140
From rising edge to next rising edge at 2.5V, CL=15pF,
fREF=15kHz, NR=1, NF=800, NPx=10, CLF=0.0246µF, RLF=15.7kΩ,
CLP=820pF, OSCTYPE=0, MLCP=3, XLROM=7 12.00 130
From rising edge to next rising edge at 2.5V, CL=15pF,
fREF=31.5kHz, NR=1, NF=799, NPx=4, CLF=0.015µF, RLF=15.7kΩ,
CLP=470pF, OSCTYPE=0, MLCP=3, XLROM=7 25.175 105
From rising edge to next rising edge at 2.5V, CL=15pF,
CMOS mode, fXIN=27MHz, NF=200, NR=27, NPx=2 100 340
Jitter, Period (peak-peak)
* tj(∆P)
From rising edge to next rising edge at 2.5V, CL=15pF,
PECL mode, fXIN=27MHz, NF=200, NR=27, NPx=1 200 270
ps
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent
nominal characterization data at TA = 27°C and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
Table 16: Serial Interface Timing Specifications
Parameter Symbol Conditions/Description Min. Max. Units
Clock frequency fSCL SCL 0 400 kHz
Bus free time between STOP and START tBUF 4.7 µs
Set up time, START (repeated) tsu:STA 4.7
µs
Hold time, START thd:STA 4.0 µs
Set up time, data input tsu:DAT SDA 250 ns
Hold time, data input thd:DAT SDA 0 µs
Output data valid from clock tAA Minimum delay to bridge undefined regio n of the falling
edge of SCL to avoid unintended START or STOP 3.5
µs
Rise time, data and clock tRSDA, SCL 1000 ns
Fall time, data and clock tFSDA, SCL 300 ns
High time, clock tHI SCL 4.0 µs
Low time, clock tLO SCL 4.7
µs
Set up time, STOP tsu:STO 4.0 µs
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent
nominal characterization data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical .
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
SCL
SDA
~
~~
~~
~
STOP
t
su:STO
t
hd:STA
START
t
su:STA
ADDRESS OR
DATA VALID DATA CAN
CHANGE
Figure 17: Bus Timing Data
SCL
SDA
IN
t
hd:DAT
~
~
t
hd:STA
t
su:STA
t
su:STO
t
LO
t
HI
SDA
OUT
t
su:DAT
~
~~
~
t
BUF
t
R
t
F
t
AA
t
AA
Figure 18: Data Transfer Sequence
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
Table 17: CLKP, CLKN Clock Outputs (CMOS Mode)
Low Drive Current (mA) High Drive Current (mA)
Voltage
(V) Min. Typ. Max. Voltage
(V) Min. Typ. Max.
0 0 0 0 0 -58 -98 -153
0.2 7 11 15 0.5 -56 -96 -150
0.5 18 27 37 1 -55 -94 -148
0.7 24 36 50 1.5 -53 -91 -142
1 32 49 69 2 -49 -85 -135
1.2 37 56 80 2.5 -43 -77 -124
1.5 43 66 95 2.7 -40 -73 -119
1.7 46 72 103 3 -35 -67 -111
2 51 79 115 3.2 -31 -62 -105
2.2 53 83 122 3.5 -25 -54 -95
2.5 55 88 130 3.7 -21 -48 -87
2.7 56 91 135 4 -14 -39 -75
3 57 93 140 4.2 -8 -32 -67
3.5 58 95 146 4.5 0 -21 -53
4 59 97 149 4.7 -13 -44
4.5 59 99 152 5 0 -28
5 100 155 5.2 -17
5.5 158 5.5 0
-200
-150
-100
-50
0
50
100
150
200
- 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Output Current (mA)
MIN
TYP
MAX
The data in this table represents nominal characterization data only.
Table 18: LOCK/IPRG Clock Output (CMOS Mode)
Low Drive Current (mA) High Drive Current (mA)
Voltage
(V) Min. Typ. Max. Voltage
(V) Min. Typ. Max.
0 0 0 0 0 -35 -46 -61
0.2 4 4 4 0.5 -34 -45 -60
0.5 9 10 11 1 -33 -43 -57
0.7 12 13 15 1.5 -31 -41 -54
1 16 18 21 2 -28 -37 -50
1.2 19 21 25 2.5 -24 -33 -45
1.5 23 26 30 2.7 -23 -31 -42
1.7 25 29 33 3 -20 -28 -39
2 28 32 38 3.2 -17 -26 -36
2.2 29 35 41 3.5 -14 -22 -32
2.5 32 38 45 3.7 -11 -19 -29
2.7 33 39 48 4 -7 -15 -25
3 34 42 51 4.2 -4 -12 -22
3.5 35 45 56 4.5 0 -8 -17
4 35 46 60 4.7 -5 -14
4.5 36 46 62 5 0 -9
5 47 63 5.2 -5
5.5 63 5.5 0
-80
-60
-40
-20
0
20
40
60
80
- 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Output Current (mA)
MIN
TYP
MAX
The data in this table represents nominal characterization data only.
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
8.0 Package Information for Both ‘Green’/’ROHS’ and ‘Non-Green’
Table 19: 16-pin SOIC (0.150") Package Dimensions
Dimension
Inches Millimeters
Min. Max. Min. Max.
A 0.061 0.068 1.55 1.73
A1 0.004 0.0098 0.102 0.249
A2 0.055 0.061 1.40 1.55
B 0.013 0.019 0.33 0.49
C 0.007
5 0.0098 0.191 0.249
D 0.386 0.393 9.80 9.98
E 0.150 0.157 3.81 3.99
e 0.050 BSC 1.27 BSC
H 0.230 0.244 5.84 6.20
h 0.010 0.016 0.25 0.41
L 0.016 0.035 0.41 0.89
Θ 0° 8° 0° 8°
Table 20: 16-pin SOIC (0.150") Package Characteristics
Parameter Symbol Conditions/Description Typ. Units
Thermal Impedance, Junction to Free-Air ΘJA Air flow = 0 ft./min. 108 °C/W
Corner lead 4.0
Lead Inductance, Self L11 Center lead 3.0 nH
Lead Inductance, Mutual L12 Any lead to any adjacent lead 0.4 nH
Lead Capacitance, Bulk C11 Any lead to VSS 0.5 pF
9.0 Ordering Information
Ordering Code Device # Package Type Operating Temp. Range Shipping Config.
11274-001-XTP (or –XTD) FS6131- 01 16-pin (0.150”) SOIC
(small outline package) 0°C to 70°C (Commercial) Tape-and-Reel (-XTP)
Tube/Tray (-XTD )
11274-502-XTP (or –XTD) FS6131-01g 16-pin (0.150”) SOIC
(green, ROHS or lead free packaging) 0°C to 70°C (Commercial) Tape-and-Reel (-XTP)
Tube/Tray (-XTD )
11274-901-XTP (or -XTD) FS6131-01i 16-pin (0.150”) SOIC
(small outline package) -40°C to 85°C (Industrial) Tape-and-Reel (-XTP)
Tube/Tray (-XTD )
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
10.0 Demonstration Software
MS Windows® based software is available from AMIS that illustrates the capabilities of the FS6131.
10.1 Software Requiremen ts
• PC running MS Windows 95, 98, 98SE, ME, NT4, 2000, XP Home or Professional Editions.
• 2.0MB available space on hard drive C:
10.2 Demo Program Operation
Run the fs6131.exe program. A warning message will appear stating that the hardware is not connected. Click “Ignore”.
The FS6131 demonstration h ardware is no longer supported by AMIS.
The opening screen is shown in Figure 19.
Figure 19: Opening Screen
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
10.2.1 Device Mode
The device mode block presets the demo program to program the FS6131 either as a frequency synthesizer (a stand alone clock
generator) or as a line-locked or genlock clock generator.
Frequency Synthesis: For use as a stand alone clock generator. Note that the reference source is the on-chip crystal oscillator, the
expected crystal frequency is 27MHz, and the voltage tune in the crystal oscillator (i.e. the VCXO) is disabled. The default output
frequency (CLK freq.) requested is 100MHz, with a maximum error of 10ppm, or about 100Hz. The output stage defaults to CMOS
mode.
Line-Locked/Genlock: For use in a line-lock or genlock application. Note that the reference source is the REF pin, and that the
expected reference frequency is 8kHz. The default output frequency requested is a 100x multiple of the referenc e frequency.
10.2.2 Example: Frequency Synthesizer Mode
By default the demo program assumes the FS6131 is configured as a stand alone clock generator. Note that the reference source
defaults to the on-chip crystal oscillator, the expected crystal freque ncy is 27MHz, and the voltage tune in the Crystal Oscillator block
(i.e. the VCXO) is disabled. T he default output frequency (CLK fr eq.) requested is 100MHz, with a maximum error of 10ppm, or about
100Hz. The Output Stage defaults to CMOS mode. The Loop Filter block is set to internal, and the Check Loop Stability switch is
on.
As an exercise, click on Calculate Solutions. The program takes into account all of the screen settings and calculates all possible
combinations of reference, fee dback and pos t divider values that will generate the output frequenc y (100MHz) from the inp ut frequency
(27MHz) within the desired tolerance (10ppm).
A box will momentarily appear: "Calculating Solutions: Press cancel to stop with the solutions calculated so far." A number in the box
will increment for every unique solution that is found. This example will create seven unique solutions, which are then displayed in a
window in the lower right portion of the program screen.
The best PLL performance is obtain ed by running the VCO at as high a speed as possible. The last three solutions sh ow a VCO speed
of 200MHz. Furthermore, good PLL performance is obtained with the smallest dividers possible, which means solution #4 should
provide the best results.
Figure 20: Frequency Synthesizer Screen
Clicking on Solution #4 highlights the row, and clicking on Disp/Save Register Values provides a window with the final values of key
settings. A click on OK then displays a second window containing register information per the register map. If the solutions are to be
saved to a file, two formats are available: a text format for viewing, and a data format for loading into the FS6131.
Note: As an update to this data sheet, the FS6131 hardware is no longer available from AMIS.
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
10.2.3 Example: Line-Locked Mod e
Selecting the line-locked/genlock option in the Device Mode block changes the program default settings. The Reference Source
changes to the REF pin i nput, and a bl ock appears to permit entr y of the REF input frequenc y in MHz. A Desi red Multiple block allows
entry of the reference frequenc y multiplying factor used to generate the output frequency.
Exercise: Change the ref pin frequency to 0.0315MHz, and alter the desired multiple to 800. Change the loop filter block to external,
but leave the values for C1 and R alone.
Click on Calculate Solutions. The program takes into account all of the current screen settings and calculates all possible
combinations of reference, feedback and post divider values t hat will generate an output frequency from the in put frequency (31.5kHz)
multiplied by the desired multiple of 800.
A box will appear: "No solutions were found! Do you want to retry calculations with the check loop stability option turned off?" Choose
Yes.
Another box may momentaril y appear: "Calculating Solutions: Press cancel to stop with the solutions calculated so far." A number in the
box will increm ent for ever y unique s olution that is fo und. This example will create eight unique solutions, which are then displayed in a
window in the lower right portion of the program screen.
For best results, try to keep the PostDiv value multiplied by the FbkDiv value from getting larger than 5000 while running the VCO as
much above 70MHz as possible. If a tradeoff must be made, it is better to run the VCO faster and allo w the divider values to get large.
Solution #3 provides a PostDiv value of 4 and a FbkDiv value of 800 for a combined value of 3200. The VCO is running at about
100MHz.
Click on Solution #3 to highlight the row, then click on Suggest in the Loop Filter box to have the program choose loop filter values.
Suggested values for an external loop filter are 4700pF and 47kW.
Now reselect the Check Loop Stability box to turn this feature on. Clicking on Calculate Solutions regenerates the same solutions
provided earlier, only this time the new loop filter values were used.
Figure 21: Line-Locked Screen
Clicking on Solution #3 highlights the row, and clicking on Disp/Save Register Values provides a window with the final values of key
settings. A click on OK then displays a second window containing register information per the register map. If the solutions are to be
saved to a file, two formats are available: a text format for viewing and a data format for loading into the FS6131.
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
Table 21: Sample Text Output
AMIS - FS6131 Solution Text File
Created: Today’s Date, Today’s Time
Line-Locked / Genlock Mode
Desired M ultiple = 800
Source = 0.0315MHz Reference Pin
External Loop Filter C1 = 4700pF R = 47kOhms
Crystal Oscillator Volta ge Tune Disabled
Output Stage = CMOS
Reference Divider = 1
Feedback Divider = 800
Post Divider = 4
Charge Pump (uA) = 10
EXTLF = 1
XLVTEN = 0
XCT = 7
CMOS = 1
Register 0 = 1H (1)
Register 1 = 40H (64)
Register 2 = 2H (2)
Register 3 = 20H (32)
Register 4 = 3H (3)
Register 5 = 26H (38)
Register 6 = 0H (0)
Re
g
ister 7 = 17H
(
23
)
11.0 Applications Information
A signal reflection will occur at any point on a PC-board trace where impedance mismatches exist. Reflections cause several
undesirable effects in high-speed applications, such as an increase in clock jitter and a rise in electromagnetic emissions from the
board. Using a properly designed series termination on each high-speed line can alleviate these problems by eliminating signal
reflections.
11.1 PECL Output Mode
If a PECL interface is desired, the transmission line must be terminated using a Thévenin, or dual, termination. The output stage can
only sink current in the PECL mode, and the amount of sink current is set by a programming resistor on the LOCK/IPRG pin. Source
current is provided by the pull -up resistor that is part of the Thévenin termination.
R
p1
IPRG
CLKN
CLKP
{
from
PLL
R
n1
R
p2
R
n2
R
i
LOADz
L
z
L
z
O
PECL Mode Output
V
CC
V
CC
Figure 22: Thévenin Termination (PECL)
Thévenin termination uses two resistors per transmission line. The parallel resistance of the termination resistors should be sized to
equal the transmission li ne impedance, taking into account the driver sink current, the desired rise a nd fall times, and the VIH and VI L
specifications of the load.
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
11.1.1 Example Calculation
In PECL mode, the output driver does not source curre nt, so the VIH value is determined by the ratios of the terminating resistors using
the equation
21
1
pp
p
CCNMH RR
R
VV +
×=
where Rp1 is the pull-up resistor, Rp2 is the pull - down resistor and VNMH is the desired noise margin, and
NMHCCIH VVV
−
=
The resistor ratio must also match the line impedance via the equation
21
21
pp
pp
LRR
RR
z+
=
where zL is the line impe dance.
Combining these equatio ns, and solving for Rp1 gives
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
−
+=
NMHCC
NMH
LLp VV V
zzR 1
If the load's VIH(min) = VCC - 0.6, choose a VNMH = 0.45V. If the line impe dance is 75W, then Rp1 is about 82W. Substituting int o the equation
for line impedance and solving for Rp2 gives a value of 880W (choose 910 W).
To solve for the load's VIL, an output sink curr ent must be programmed via the IPRG pin. If the desired VIH = VCC - 1.6, choose VCC - 2.0 for
some extra margin. A sink current of 25mA through the 82W resistor generates a 2.05V drop. The sink current is programmed via the
IPRG pin, where the ratio of IPRG current to output sink cu rrent is 1:4. An IPRG programming resistor of 750W at VDD = 5V generat es
6.6mA, or about 27mA output sink current.
11.2 CMOS Output Mode
If a CMOS interface is desired, a transmission line is typically terminated using a series termination. Series termination adds no dc
loading to the driver, and requires l ess power than other resistive termi nation methods. In addition, n o extra impedance e xists from the
signal line to a reference voltage, such as ground.
R
S
z
L
z
O
DRIVER RECEIVE
LINE
Figure 23: Series Termination (CMOS)
As shown in Figure 23, the sum of the driver's output impedance (zO) and the series termination resistance (RS) must equal the line
impedance (zL). That is,
OLS zzR
−
=
When the source impedance (zO+RS) is matched to the line impedance, then by voltage division the incident wave amplitude is one-half
of the full signal amplitude.
2)( )( V
zRz Rz
VV
LSO
SO
i=
++
+
=
33
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
However, the full sign al amplitude may take up to twice as long as the propagation dela y of the line to develop, reducing noise immunity
during the half-amplitude period. Note that the voltage at the receive end must add up to a signal amplitude that meets the receiver
switching thresholds. The slew rate of the signal may be reduced due to the additional RC delay of the load capacitance and the line
impedance. Also, note that the output driver impe dance will vary slightly with the output lo gic state (high or low).
11.3 Serial Communicatio ns
Connection of devices to a standard-mode implementation of the I2C-bus is similar to that shown in Figure 24. Selection of th e pull-up
resistors (RP) and the optio nal series resistor s (RS) on the SDA a nd SCL lines dep ends on the su pply voltage, the bus capacitanc e and
the number of connected devices with their associated in put currents.
Control of the clock and data lines is do ne through op en drai n/collector current-sink output s, and thus requires external pull- up resistor s
on both lines.
A guideline is
bus
r
PC
t
R×
<2
where tr is the maximum rise time (minus some margin) and C bus is the total bus capacita nce. Assuming an I2C co ntroll er and eight to ten
other devices on the bus, including this one, results in values in the 5kW to 7kW range. Use of a series resistor to provide protection
against high voltage spikes on the bus will alter the values for RP.
R
P
SDA
SCL
Data In
Data Out
Clock Out
Data In
Data Out
Clock In
R
P
R
S
(optional)
R
S
(optional)
R
S
(optional)
R
S
(optional)
RECEIVER
TRANSMITTER
Figure 24: Connections to the Serial Bus
11.3.1 For More Information
More information on the I2C -bus can be found in the document The I2C-bus And How To Use It (Including Specifications), available
from Philips Semiconductors at http://www-us2.semiconductors.philips.com.
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
12.0 Device Application: Stand-Alone Clock Generation
The length of the reference and feedback dividers, their granularity and the flexibility of the post divider make the FS6131 the most
flexible monolit hic stand-a lone PLL clock ge neratio n devic e avail able. The effective block diagram of the FS6131 when programme d for
stand-alone mode is shown in Figure 25.
The source of the feedback divider in the stand-alone mode is the output of the VCO. By dividing the input referenc e frequency down by
reference divider (NR), then multiplying it up i n the main loop through the feed back divider (NF), and final ly dividing the main loop output
frequency by the post divider (NPx), we have the defining relationship for this mode. The equation for the output clock frequency (fCLK)
can be written as
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
=
PxR
F
REFCLK NN
N
ff 1
where the reference source frequency (fREF) can be either supplied by the VCXO or applied to the REF pin.
Great flexibility is permitted in the programming of the FS6131 to achieve exact desired output frequencies since three integers are
involved in the computation.
12.1 Example Calculation
A Visual BASIC program is availa ble to completely program the FS6131 based on the given parameters.
Suppose that the reference source freque ncy is 14.318MHz and the d esired output frequency is 100MH z.
First, factor the 14.318MHz reference frequency (which is four times the NTSC television color sub-carrier) into prime numbers. The
exact expression is
11 753
2
81.14318181 172
5×××
==
REF
f
FS6131
VCXO
Divider
(optional)
(optional)
CRYSTAL LOOP
MAIN LOOP
VCXO
XOUT
XIN
Control
ROM
XTUNE
Reference
Divider
(N
R
)
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
REF
FBK
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
Internal
Loop
Filter
EXTLF
I
2
C
Interface
SCL
SDA
ADDR
Registers
POST3[1:0]
POST2[1:0]
POST1[1:0]
REFDIV[11:0]
EXTLF
PDREF
PDFBK
VCOSPD,
OSCTYPE
LFTC
MLCP[1:0]
XLCP[1:0]
XLROM[2:0]
XLPDEN,
XLSWAP
REFDSRC
XCT[3:0],
XLVTEN
(f
REF
)
(f
VCO
)
LOCK/
IPRG
Post
Divider
(N
Px
)
Voltage
Controlled
Oscillator
Lock
Detect
CMOS
(optional)
STAT[1:0]
OM[1:0]
Clock
Gobbler
GBL
(optional)
Feedback
Divider
(N
F
)
FBKDIV[14:0]
FBKDSRC[1:0]
CMOS/PECL
Output
CLKN
(f
CLK
)
CLKP
R
LF
C
LF
R
IPRG
C
LP
Figure 25: Block Diagram: Stand-Alone Clock Generation
35
AMI Semiconductor – Rev. 3.0, Jan. 08
www.amis.com Specifications subject to change without notice
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
Next, express the output and input frequencies as a ratio of fCLK to fREF, where fCLK has also been converted to a product of prime numbers.
(
)
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛×××
×
==
11 753
2
52
81.14318181
00.100000000
172
5
88
REF
CLK
f
f
Simplifying the above equation yields
(
)
()
73
1152
2
13
×
××
=
REF
CLK
f
f
Deciding how to apportion the denominator integers between the reference divider and the post divider is an iterative process. To
obtain the best performance, the VCO should be operated at the highest frequency possible without exceeding its upper limit of
230MHz. (see Table 15). The VCO frequency (fVCO) can be calculated by
R
F
REFVCO N
N
ff ×=
Recall that the reference divider can have a value between 1 and 4096, but the post divider is limited to values derived from
321 PPPPx NNNN
×
×
=
where the values NP1, NP2 and NP3 are found in Table 8.
In this example, the smallest integer that can be removed from the de nomi nator of E qn. 2 is three. Set the post div ider at NPx=3, and the
ratio of fCLK to fREF becomes (from Eqn. 1)
(
)
()
3
1
73 1152 13 ×
×
××
=
REF
CLK
f
f
Unfortunately, a post divider modulus of three requires a VCO frequency of 300MHz, which is greater than the allowable fVCO noted in
Table 15. For the best PLL p erformance, program the post divider mo dulus to allow the VCO to operate at a nominal frequency that is
at least 70MHz but l ess then 230MHz. T herefore, the reference divider cannot be reduc ed belo w the modulus of 32´7 (or 63) as shown
in Eqn. 2.
However, the VCO can still be operated at a frequency higher than fCLK. Multiplying both the numerator and the denominator by two
does not alter the output frequency, but it does increase the VCO frequency.
(
)
()
2
1
63
880
2
1
73
21152
1
2
13 ×=×
×
×××
=×=
PxR
F
REF
CLK NN
N
f
f
As Eqn. 3 shows, the VCO frequency can be doubled by multiplying the feedback divider by two. Set the post divider to two to return
the output frequency to the desired modu lus. These divider settings place the VCO frequency at 200MHz.
12.2 Example Programming
To generate 100.000MHz from 14.318MHz, program the following (refer to Figure 25):
• Set the reference divider input to select the VCXO via REFDSRC= 0
• Set the PFD input to select the reference divider and the feedback divider via PDREF=0 and PDFBK=0
• Set the reference divider (NR) to a modulus of 63 via REFDIV[11:0]
• Set the feedback divider input to select the VCO via FBKDSRC= 1
• Set the feedback divider (NF) to a modulus of 880 via FBKDIV[14:0]
• Set NP1=2, NP2=1 and NP3=1 for a combined post divider modulus of NPx=2 via POST1[1:0], POST2[1:0] and POST3[1:0].
• Select the internal loop filter via EXT LF=0
• Set XLVTEN=0 and XLPDEN=1 to disab le the VCXO fine tune and the crystal loop phase frequency detector
• Set VCOSPD=0 to select the VCO high speed range
36
AMI Semiconductor – Rev. 3.0, Jan. 08
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
13.0 Device Application: Line-Locked Clock Generation
Line-locked clock gener ation, as used here, refers to the process of s ynthesizing a clock frequency that is some integer multiple of the
horizontal line frequency in a graphics system. The F S6131 is easily configured to perform that function, as shown in Figure 26.
A line reference signal (fHSYNC) is applied to the REF input for direct application to the main loop PFD. The feedback divider (NF) is
programmed for the desired number of output clocks per line.
The source for the feedback divider is se lected to b e the output of th e post divider (NPx) so that the edges of the outp ut clock maintain a
consistent phase alignment with the line reference signal. The modulus of the post divider should be selected to maintain a VCO
frequency that is comfortably within the op erating range noted in Table 15.
13.1 Example Calculation
A Visual BASIC program is availa ble to completely program the FS6131 based on the given parameters.
Suppose that we wish to reconstruct the pixel clock from a VGA source. This is a typical requirement of an LCD projection panel
application.
First, establish the total number of pixel clocks desired between horizontal sync (HSYNC) puls es. The number of pixel clocks is kno wn
as the horizontal total, and the feedb ack divider is programmed to that value. In this example, choose the horizontal total to be 800.
Next, establish the frequency of the HSYNC pulses (fHSYNC) on the line reference signal for the video mode. In this case, let
fHSYNC=31.5kHz. The output clock frequency fCLK is calculated to be: MHz175.25800kHz5.31
=
×
=
×
=FHSYNCCLK Nff
Reference
HSYNC
FS6131
VCXO
Divider
(optional)
(optional)
CRYSTAL LOOP
MAIN LOOP
VCXO
XOUT
XIN
Control
ROM
XTUNE
Reference
Divider
(N
R
)
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
REF
FBK
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
Feedback
Divider
(N
F
)
Internal
Loop
Filter
EXTLF
I
2
C
Interface
SCL
SDA
ADDR
Registers
POST3[1:0],
POST2[1:0],
POST1[1:0]
REFDIV[11:0]
FBKDIV[14:0]
EXTLF
PDREF
PDFBK
VCOSPD,
OSCTYPE
LFTC
MLCP[1:0]
XLCP[1:0]
XLROM[2:0]
XLPDEN,
XLSWAP
REFDSRC
XCT[3:0],
XLVTEN
(f
REF
)
(f
VCO
)
LOCK/
IPRG
Post
Divider
(N
Px
)
Voltage
Controlled
Oscillator
Lock
Detect
CMOS
(optional)
STAT[1:0]
OM[1:0]
Clock
Gobbler
GBL
(optional)
FBKDSRC[1:0]
CMOS/PECL
Output
CLKN
(f
CLK
)
CLKP
R
LF
C
LF
R
IPRG
C
LP
Figure 26: Block Diagram: Line-Locked Clock Generation
37
AMI Semiconductor – Rev. 3.0, Jan. 08
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
However, the 31.5kHz line reference signal is too low in frequency for the internal loop filter to be used. A series combination of a
0.015mF capacitor and a 15k W resistor from power (VDD) to the EXT LF pin provides an external loop fi lter. A 100pF to 220 pF capacitor
in parallel with the combination may improve the filter performance.
For the best PLL performance, program the post divider modulus to allow the VCO to operate at a nominal frequency that is at least
70MHz but less than 230MHz. T he VCO frequency (fVCO) can be calculated b y
PxFHSYNCVCO NNff
×
×
=
Setting the post divider equal to four (NPx=4) is a reasonable solution, altho ugh there are a number of values that will work. Try to keep
5000
<
×
PxF NN
to avoid divider values from becoming too large. These settings place the VCO frequency at about 100MHz.
Calculate the ideal charge pump current (Ipump) as
VCOlflf
PxFHSYNC
pump ACR
NN
kHz
f
I2
2
15 ×=
where Rlf is th e e xternal lo op fi lter ser ies resis tor, Clf is the external loop filte r series ca pac itor and A VCO is the VCO gain. T he VCO gain is
either: AVCO=125MHz/V if the high range is selected , or
AVCO=75MHz/V if the low range is selected.
See Table 15 for more information on the V CO range. With fhsync=31.5kHz, Clf=0.015mF, Rlf=15kW, NF=800, NPx=4, and AVCO=125MHz/V,
the charge pump current is 39.3mA. A 220pF cap across the entire loop filter is also helpful.
13.2 Example Programming
To generate 800 pixel clocks b et ween HSYNC puls es occur ring o n the li ne reference si gn al ever y 31.5kHz, program th e follo wing ( refer
to Figure 26):
• Clear the OSCTYPE bit to 0
• Turn off the crystal oscillator via XLROM=7
• Set the PFD inputs to select the REF pin and the feedback divid er via PDREF=1 and PDFBK=0
• Set the feedback divider input to select the post divider via FBKDSRC=0
• Set the feedback divider (NF) to a modulus of 800 (the d esired number of pixel clocks per line) via FBKDIV[14:0]
• Set NP1=4, NP2=1 and NP3=1 for a combined post divider modulus of NPx=4 via POST1[1:0], POST2[1:0] and POST3[1:0].
• Select the external loop filter via EXTLF=1
• Set XLVTEN=0 and XLPDEN=1 to disab le the VCXO fine tune and the crystal loop phase frequency detector
• Set VCOSPD=1 to select the VCO low speed range
• Set MLCP[1:0] to 3 to select the 32mA range
The output clock frequency fCLK is 25.175MHz, with an internal VCO frequency of 100.8MHz. Note that the crystal loop was unused in
this application.
38
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
14.0 Device Application: Genlocking
Genlocking refers to the process of synchronizing the horizontal sync pulses (HSY NC) of a target graphics system to the HSYNC of a
source graphics system. In a genlocked mode, the FS6131 increases (or decreases) the frequency of the VCO until the FBK input is
frequency matched and phase-aligned to the frequency applied to the REF input. Since the feedback divider is within the graphics
system and the graphics system is the sour ce of the signal applied to the FBK input of the FS6131, the graphics system is effectively
synchronized to the REF input as shown in Figure 27.
To configure the FS6131 for g enlockin g, the REF input (p in 12) and the F B K input (pin 13) are switched directly onto the feedba ck input
of the PFD. The reference and feedback dividers are not used.
The output clock frequency is: totalhorizontalff HSYNCCLK
×
=
The only remaining task is to select a post di vider modulus (NPx) that allows the VCO frequency to be within its nominal range.
14.1 Example Calculation
A Visual BASIC program is availa ble to completely program the FS6131 based on the given parameters.
The FS6131 is being used to genlock an LCD projection panel system to a VGA card-generated HSYNC. The total number of pixel
clocks generated by the VGA card, kno wn as the horizontal total, are 800. Therefore, the LCD panel graphics system that is clocked by
the FS6131 is set to divide the output clock frequency (fCLK) by 800. The input HSYNC reference frequency (fHSYNC) is 15kHz.
Video Graphics System
System HSYNC Clock In
Reference
HSYNC
FS6131
VCXO
Divider
(optional)
(optional)
CRYSTAL LOOP
MAIN LOOP
VCXO
XOUT
XIN
Control
ROM
XTUNE
Reference
Divider
(N
R
)
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
REF
FBK
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
Feedback
Divider
(N
F
)
Internal
Loop
Filter
R
LF
C
LF
EXTLF
I
2
C
Interface
SCL
SDA
ADDR
Registers
POST3[1:0],
POST2[1:0],
POST1[1:0]
REFDIV[11:0]
FBKDIV[14:0]
FBKDSRC[1:0]
EXTLF
PDREF
PDFBK
VCOSPD,
OSCTYPE
LFTC
MLCP[1:0]
XLCP[1:0]
XLROM[2:0]
XLPDEN,
XLSWAP
REFDSRC
XCT[3:0],
XLVTEN
(f
CLK
)
(f
CLK
)
(f
VCO
)
R
IPRG
LOCK/
IPRG
Post
Divider
(N
Px
)
Voltage
Controlled
Oscillator
Lock
Detect
CMOS
(optional)
STAT[1:0]
OM[1:0]
Clock
Gobbler
GBL
(optional)
CMOS/PECL
Output
CLKN
(f
CLK
)
CLKP
C
LP
Figure 27: Block Diagram: Genlocking
39
AMI Semiconductor – Rev. 3.0, Jan. 08
www.amis.com Specifications subject to change without notice
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
The output clock frequency is calculated as MHz0.12800kHz15
=
×
=
CLK
f
For best performance, program the post divider (NPx) modulus to allow the VCO to operate at a nominal frequency that is at least
70MHz but less than 230MHz. T he VCO frequency (fVCO) can be calculated b y
PxCLKVCO Nff
=
Selecting the post divider modulus of NPx=6 is a reasonable solution, although there are a number of values that will work. T ry to keep
5000
<
×
PxF NN
to avoid divider values from becoming too large. The settings place the V CO frequency at about 72MHz.
Calculate the ideal charge pump current (Ipump) as
VCOlflf
PxFHSYNC
pump ACR
NN
kHz
f
I2
2
15 ×=
where Rlf is th e e xternal lo op fi lter ser ies resis tor, Clf is the external loop filte r series ca pac itor and A VCO is the VCO gain. T he VCO gain is
either AVCO=125MHz/V if the high range is selected, or
AVCO=75MHz/V if the low range is selected.
See Table 15 for more information on the VCO range. With fhsync=15kHz, Clf=0.015mF, Rlf=15kW, NF=800, NPx=6, and AVCO=125MHz/V,
the charge pump current is 24mA. A 220pF cap across the entire loop filter is also helpful.
14.2 Example Programming
To generate 800 pixel clocks bet ween HSYNC puls es occurring on the line referenc e signal every 15kHz, program th e following (refer
to Figure 27):
• Clear the OSCTYPE bit to 0
• Turn off the crystal oscillator via XLROM=7
• Set the PFD inputs to select the REF and FBK pins via PDREF=1 and PD FBK=1
• Set NP1=2, NP2=3 and NP3=1 for a combined post divider modulus of NPx=6 via POST1[1:0], POST2[1:0] and POST3[1:0].
• Select the external loop filter via EXTLF=1
• Set XLVTEN=0 and XLPDEN=1 to disab le the VCXO fine tune and the crystal loop phase frequency detector
• Set VCOSPD=1 to select the VCO low speed range
• Set MLCP[1:0] to 3 to select the 32mA range
The output clock frequency fCLK is 12MHz, with an internal VCO frequency of 72MHz. Note that the crystal loop was unused in this
application.
40
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
15.0 Device Application: Telecom Clock Regenerator
The FS6131 can be used as a clock regenerator as shown in Figure 28. This mode uses the VCXO in its own phase-locked loop,
referred to as the crystal loop. The VCXO provides a "de-jittered" multiple of the reference frequency at the REF pin (usually 8kHz in
telecom applications) for use b y the main loop. In essence, the crystal loop "cleans up" the reference signal for the main loop.
The control ROM for the VCXO divider is preloaded with the most common ratios to permit locking of most standard
telecommunications crystals to an 8kHz signal applied to the REF pin. The de-jittered multiple of the reference frequency from the
VCXO is then supplied to the reference divider in the main loop. The reference divider, along with the feedback divider, can be
programmed to achieve the desired output clock frequency.
15.1 Example Calculation
A Visual BASIC program is availa ble to completely program the FS6131 based on the given parameters.
In this example, an 8kHz reference freq uency is supplied to the FS6131 and an o utput clock frequency of 51.84MHz is desired.
First, select the frequency at which the VCXO will operate from Table 10. The table shows the external crystal frequency options
available to choose from, since the VCXO runs at the crystal frequency. While the main loop can be programmed to work with any of
the frequencies in the table, the best performance will be achieved with the highest frequency at the main loop PFD.
The frequency at the main loop PFD (fMLpfd) is the VCXO frequency (fVCXO) divided by the main loop refere nce divider (NR).
R
VCXO
MLpfd N
f
f=
8kHz IN
(typical)
FS6131
VCXO
Divider
(optional)
(optional)
CRYSTAL LOOP
MAIN LOOP
VCXO
XOUT
XIN
Control
ROM
XTUNE
Reference
Divider
(N
R
)
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
REF
FBK
Phase-
Frequency
Detector
Charge
Pump
UP
DOWN
Feedback
Divider
(N
F
)
Internal
Loop
Filter
EXTLF
I
2
C
Interface
SCL
SDA
ADDR
Registers
POST3[1:0],
POST2[1:0],
POST1[1:0]
REFDIV[11:0]
FBKDIV[14:0]
EXTLF
PDREF
PDFBK
VCOSPD,
OSCTYPE
LFTC
MLCP[1:0]
XLCP[1:0]
XLROM[2:0]
XLPDEN,
XLSWAP
REFDSRC
XCT[3:0],
XLVTEN
(f
REF
)
(f
VCO
)
LOCK/
IPRG
Post
Divider
(N
Px
)
Voltage
Controlled
Oscillator
Lock
Detect
CMOS
(optional)
STAT[1:0]
OM[1:0]
Clock
Gobbler
GBL
(optional)
CMOS/PECL
Output
CLKN
(f
CLK
)
CLKP
FBKDSRC[1:0]
R
LF
C
LF
R
IPRG
C
LP
Figure 28: Block Diagram: Telecom Clock Generator
41
AMI Semiconductor – Rev. 3.0, Jan. 08
www.amis.com Specifications subject to change without notice
FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
The goal is to choose the highest crystal frequency from Table 10 that generates the smallest value of NR.
The equation establishing the output frequency (fCLK) as a function of the input VCXO frequency is
R
F
VCXO
CLK N
N
ff=
where NF is the feedback divi der modulus.
Choose a few different crystal frequencies from Table 10 and factor both the input VCXO and output clock frequencies into prime
numbers. Look for the factors that will give the smallest modulus for NR with the largest FVCXO. The output and VCXO freq uenc ies and th e
reduced factors from Eqn. 1 are in Table 22.
Table 22: Clock Regenerator Example
A 19.44MHz crystal provides the smallest modulus for NR (NR=3) with the highest crystal frequency.
Finally, choose a post divider (NPx) modulus that keeps the VCO frequency in its most comfortable rang e. The VCO frequency (fVCO) can
be calculated by
PxCLKVCO Nff
=
Selecting an overall modulus of NPx=3 sets the VCO frequency at 155.52MHz when the loop is locked.
15.2 Example Programming
To generate a de-jittered o utput frequency of 51.84MHz from an 8kHz reference, program the following (refer to Figure 28):
• Program the VCXO control ROM to 3 via XLROM[2:0] to select an external 19.4 4MHz crystal
• Enable the VCXO fine tune via XLVTEN=1
• Enable the crystal loop PFD via XLPDEN=0 and XLSWAP =0
• Set the reference divider input to select the VCXO via REFDSRC
• Set the PFD input to select the reference divider and the feedback divider via PDREF and PDFBK
• Set the reference divider (NR) to a modulus of 3 via REFDIV[11:0]
• Set the feedback divider input to select the VCO via FBKDSRC
• Set the feedback divider (NF) to a modulus of 8 via FBKDIV[14:0]
• Set NP1=1, NP2=3 and NP3=1 for a combined post divider modulus of NPx=3 via POST1[1:0], POST2[1:0] and POST3[1:0].
• Select the internal loop filter via EXT LF
• Set VCOSPD=0 to select the VCO high speed range
These settings provide the highest frequency at the main loop phase frequency detector of 6.48MHz. The use of a 19.44MHz crystal
requires that XLROM[2:0] be set to three as shown in Table 10.
42
AMI Semiconductor – Rev. 3.0, Jan. 08
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FS6131-01/FS6131-01g Programmable Line Lock Clock Generator IC Data Sheet
16.0 Company or Product Inquiries
For more information about AMI Semiconductor, our technology and our product, visit our Web site at: http://www.amis.com
.
North America
Tel: +1.208.233.4690
Fax: +1.208.234.6795
Europe
Tel: +32 (0) 55.33.22.11
Fax: +32 (0) 55.31.81.12
Devices sold by AMIS are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMIS makes no warranty, express, statutory,
implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMIS makes no warranty of
merchantability or fitness for any purposes. AMIS reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI
Semiconductor's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high
reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMIS for such
applications. Copyright ©2008 AMI Semiconductor, Inc.
43
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