SG5841J -- Highly Integrated Green-Mode PWM Controller Features Description The highly integrated SG5841/J series of PWM controllers provides several features to enhance the performance of flyback converters. Green-Mode PWM Controller Low Startup Current : 14A Low Operating Current: 4mA Programmable PWM Frequency with Hopping Peak-Current-Mode Control Cycle-by-Cycle Current Limiting Synchronized Slope Compensation Leading-Edge Blanking (LEB) Constant Output Power Limit Totem Pole Output with Soft Driving VDD Over-Voltage Clamping Programmable Over-Temperature Protection (OTP) Internal Open-Loop Protection VDD Under-Voltage Lockout (UVLO) GATE Output Maximum Voltage Clamp:18V Applications General-purpose, switch-mode, power supplies and flyback power converters, including: To minimize standby power consumption, a proprietary green-mode function provides off-time modulation to continuously decrease the switching frequency at lightload conditions. This green-mode function enables the power supply to meet international power conservation requirements. To further reduce power consumption, SG5841/J is manufactured using the BiCMOS process. This allows a low startup current, around 14A, and an operating current of only 4mA. As a result, a large startup resistance can be used. The built-in synchronized slope compensation achieves stable peak-current-mode control. The proprietary internal sawtooth power-limiter ensures a constant output power limit over a wide range of AC input voltages, from 90VAC to 264VAC. SG5841/J provides many protections. In addition to cycle-by-cycle current limiting, the internal open-loop protection circuit ensures safety should an open-loop or output-short-circuit failure occur. PWM output is disabled until VDD drops below the UVLO lower limit, then the controller restarts. An external NTC thermistor can be applied for over-temperature protection. SG5841/J is available in an 8-pin DIP or SOP package. Power Adapters Open-Frame SMPS Ordering Information Part Number Ambient Operating Frequency Temperature Range Hopping Eco Status Package SG5841JSZ -20 to +85C Yes RoHS 8-Pin Small Outline Package (SOP) SG5841JSY -20 to +85C Yes Green 8-Pin Small Outline Package (SOP) SG5841JDZ -20 to +85C Yes RoHS 8-Pin Dual Inline Package (DIP) SG5841SZ -20 to +85C No RoHS 8-Pin Small Outline Package (SOP) SG5841SY -20 to +85C No Green 8-Pin Small Outline Package (SOP) SG5841DZ -20 to +85C No RoHS 8-Pin Dual Inline Package (DIP) For Fairchild's definition of "green" Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. (c) 2006 Fairchild Semiconductor Corporation SG5841J * Rev. 1.3.4 www.fairchildsemi.com SG5841J -- Highly Integrated Green-Mode PWM Controller October 2008 Figure 1. Application Diagram Block Diagram SG5841J -- Highly Integrated Green-Mode PWM Controller Typical Application Figure 2. Block Diagram (c) 2006 Fairchild Semiconductor Corporation SG5841J * Rev. 1.3.4 www.fairchildsemi.com 2 SG5841HTP XXXX XXXXYWW marking for SG5841JSZ (pb-free) marking for SG5841JDZ (pb-free) marking for SG5841SZ (pb-free) marking for SG5841DZ (pb-free) ZXYTT 5841/J TPM marking for SG5841JSY (green-compound) marking for SG5841SY (green-compound) H: J = with Frequency Hopping Null = without Frequency Hopping T: D = DIP, S = SOP P: Z = Lead Free Null = regular package XX XXXXXX : Wafer Lot Y: Year; WW : Week V: Assembly Location F: Fairchild Logo Z:Plant Code X:1 Digit Year Code Y:1 Digit Week Code TT:2 Digit Die Run Code T: Package Type (D:DIP, S:SOP) P:Y = Green Package M:Manufacturing Flow Code SG5841J -- Highly Integrated Green-Mode PWM Controller Marking Information Figure 3. Top Mark (c) 2006 Fairchild Semiconductor Corporation SG5841J * Rev. 1.3.4 www.fairchildsemi.com 3 GND GATE FB VDD VIN SENSE RI RT Figure 4. Pin Configuration Pin Definitions Pin # Name Function 1 GND Ground Feedback Description Ground. The signal from the external compensation circuit is fed into this pin. The PWM duty cycle is determined in response to the signal from this pin and the currentsense signal from pin 6. If FB voltage exceeds the threshold, the internal protection circuit disables PWM output after a predetermined delay time. 2 FB 3 VIN 4 RI 5 RT 6 SENSE Current Sense Current sense. The sensed voltage is used for peak-current-mode control and cycle-by-cycle current limiting. 7 VDD Power Supply Power supply. If VDD exceeds a threshold, the internal protection circuit disables PWM output. 8 GATE Driver Output The totem-pole output driver for the power MOSFET, which is internally clamped below 18V. SG5841J -- Highly Integrated Green-Mode PWM Controller Pin Configuration For startup, this pin is pulled HIGH to the rectified line input via a resistor. Since Startup Input the startup current requirement is very small, a large startup resistance is used to minimize power loss. Reference Setting A resistor connected from the RI to GND provides a constant current source. This determines the center PWM frequency. Increasing the resistance reduces PWM frequency. Using a 26K resistor results in a 65KHz center PWM frequency. For over-temperature protection. An external NTC thermistor is connected from Temperature this pin to the GND pin. The impedance of the NTC decreases at high temperatures. Once the voltage of the RT pin drops below a fixed limit, PWM Detection output is disabled. (c) 2006 Fairchild Semiconductor Corporation SG5841J * Rev. 1.3.4 www.fairchildsemi.com 4 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. All voltage values, except differential voltages, are given with respect to GND pin. Symbol Parameter Min. Max. Unit VDD Supply Voltage 30 V VIN Input Terminal 30 V VFB Input Voltage to FB Pin -0.3 7.0 V VSENSE Input Voltage to SENSE Pin -0.3 7.0 V VRT Input Voltage to RT Pin -0.3 7.0 V VRI Input Voltage to RI Pin -0.3 7.0 V PD Power Dissipation (TA < 50C ) JA Thermal Resistance (Junction-to-Air) JC Thermal Resistance (Junction-to-Case) TJ TSTG TL ESD DIP 800 SOP 400 DIP 82.5 SOP 141 DIP 59.7 SOP 80.8 mW C/W C/W Operating Junction Temperature -40 +125 C Storage Temperature Range -55 +150 C 260 C 3 kV 250 V Lead Temperature (Wave Soldering or Infrared, 10 Seconds) Human Body Model, JESD22-A114 Charged Device Model, JESD22-C101 SG5841J -- Highly Integrated Green-Mode PWM Controller Absolute Maximum Ratings Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol TA Parameter Operating Ambient Temperatures (c) 2006 Fairchild Semiconductor Corporation SG5841J * Rev. 1.3.4 Min. Max. Unit -20 +85 C www.fairchildsemi.com 5 VDD = 15V, TA = 25C, unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Units 24.7 V VDD Section VDD-OP Continuously Operating Voltage VDD-ON Start Threshold Voltage 15 16 17 V VDD-OFF Minimum Operating Voltage 9 10 11 V IDD-ST IDD-OP Startup Current VDD=VDD-ON-0.16V 14 30 A Operating Supply Current VDD=15V, RI=26K, GATE=OPEN 4 5 mA VDD-CLAMP VDD Over-Voltage-Clamping Level tD-VDDCLAMP VDD Over-Voltage-Clamping Debounce Time RI=26K 28 29 50 100 V 200 s 36.0 K RI Section RINOR RI Operating Range 15.5 RIMAX Maximum RI Value for Protection 230 K RIMIN Minimum RI Value for Protection 10 K Oscillator Section Center Frequency RI=26K 62 65 68 Hopping Range RI=26K (SG5841J only) 3.7 4.2 4.7 Hopping Period RI=26K (SG5841J only) 3.9 4.4 4.9 ms Green-Mode Frequency RI=26K 18 22 25 KHz fDV Frequency Variation vs. VDD Deviation VDD=11.5V to 24.7V 5 % fDT Frequency Variation vs. Temperature Deviation TA=-20 to +85C 5 % 1/2.75 V/V 7 K fOSC Normal PWM Frequency tHOP fOSC-G KHz SG5841J -- Highly Integrated Green-Mode PWM Controller Electrical Characteristics Feedback Input Section AV FB Input to Current Comparator Attenuation ZFB Input Impedance 1/3.75 1/3.20 4 VFB-OPEN FB Output High Voltage VFB-OLP FB Open-Loop Trigger Level FB pin open 5 6 4.2 4.5 4.8 V RI=26K 26 29 32 ms 1.9 2.1 2.3 tD-OLP Delay Time of FB Pin Open-Loop Protection VFB-N Green-Mode Entry FB Voltage RI=26K VFB-G Green-Mode Ending FB Voltage RI=26K VFB-N-0.5 V V V fOSC fOSC -GREEN Figure 5. PWM Frequency (c) 2006 Fairchild Semiconductor Corporation SG5841J * Rev. 1.3.4 www.fairchildsemi.com 6 VDD = 15V, TA = 25C, unless otherwise noted. Symbol Parameter Conditions Min. Typ. Max. Unit Current-Sense Section ZSENSE Input Impedance VSTHFL Current Limit Flatten Threshold Voltage 12 VSTHVA Current Limit Valley Threshold Voltage VSTHFL-VSTHVA 0.22 tPD Propagation Delay to GATE Output RI=26K 150 200 ns tLEB Leading-Edge Blanking Time RI=26K 200 270 350 ns 60 65 70 % 0.85 0.90 K 0.95 V V GATE Section DCYMAX Maximum Duty Cycle VGATE-L Output Voltage Low VDD=15V, IO=50mA VGATE-H Output Voltage High VDD=12.5V, IO=50mA 7.5 Rising Time VDD=15V, CL=1nF 150 250 350 tf Falling Time VDD=15V, CL=1nF 30 50 90 IO Peak Output Current VDD=15V, GATE=6V 230 Gate Output Clamping Voltage VDD=24.7V tr VGATECLAMP 1.5 V V ns ns mA 18 19 V 92 100 108 A 0.585 0.620 0.655 V SG5841J -- Highly Integrated Green-Mode PWM Controller Electrical Characteristics (Continued) RT Section IRT Output Current of RT Pin VRTTH Trigger Voltage for OverTemperature Protection VRT-RLS tD-OTP RI=26K OTP Release Voltage Over-Temperature Debounce (c) 2006 Fairchild Semiconductor Corporation SG5841J * Rev. 1.3.4 VRTTH +0.03 RI=26K 60 100 V 140 s www.fairchildsemi.com 7 SG5841J -- Highly Integrated Green-Mode PWM Controller Typical Performance Characteristics 5. 0 26 4. 5 IDD-OP (mA) 30 IDD-ST (A) 22 18 4. 0 3. 5 3. 0 14 2. 5 10 -40 - 25 -10 5 20 35 50 65 80 95 110 - 40 125 -25 -10 5 Figure 6. Startup Current (IDD-ST) vs. Temperature 50 65 80 95 110 125 17. 0 12 16. 5 9 VDD-ON (V) IDD-OP (mA) 35 Figure 7. Operating Supply Current (IDD-OP) vs. Temperature 15 6 3 16. 0 15. 5 15. 0 0 11 13 15 17 19 21 23 25 27 - 40 29 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (C) VDD Voltage (V) Figure 8. Operating Current (IDD-OP) vs. VDD Voltage Figure 9. Start Threshold Voltage (VDD-ON) vs. Temperature 11. 0 68 67 10. 5 66 fOSC (KHz) VDD-OFF (V) 20 Temperature (C) Temperature (C) 10. 0 9. 5 65 64 63 9. 0 62 - 40 -25 -10 5 20 35 50 65 80 95 110 125 -40 -25 -10 5 Temperature (C) Figure 10. Minimum Operating Voltage (VDD-ON) vs. Temperature (c) 2006 Fairchild Semiconductor Corporation SG5841J * Rev. 1.3.4 20 35 50 65 80 95 110 125 Temperature (C) Figure 11. PWM Frequency (fOSC) vs. Temperature www.fairchildsemi.com 8 70 DCY MAX (%) 68 66 64 62 60 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (C) Figure 12. Maximum Duty Cycle (DCYMAX) vs. Temperature 0.66 0.65 0.64 V (RTTH) (V) 0.63 0.62 SG5841J -- Highly Integrated Green-Mode PWM Controller Typical Performance Characteristics (Continued) 0.61 0.60 0.59 0.58 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature (C) Figure 13. Trigger Voltage for Over-Temperature Protection VRTTH vs. Temperature 108 IRT (A) 104 100 96 92 -40 - 25 -10 5 20 35 50 65 80 95 110 125 Temperature (C) Figure 14. Output Current of RT Pin (IRT) vs. Temperature (c) 2006 Fairchild Semiconductor Corporation SG5841J * Rev. 1.3.4 www.fairchildsemi.com 9 Startup Current Leading-Edge Blanking (LEB) Typical startup current is only 14A, which allows a high-resistance and low-wattage startup resistor to minimize power loss. For an AC/DC adapter with universal input range, a 1.5M, 0.25W startup resistor and a 10F/25V VDD hold-up capacitor are enough for this application. Each time the power MOSFET is switched on, a turn-on spike occurs at the sense-resistor. To avoid premature termination of the switching pulse, a leading-edge blanking time is built in. During this blanking period, the current-limit comparator is disabled and cannot switch off the gate drive. Operating Current Under-Voltage Lockout (UVLO) Operating current is around 4mA. The low operating current enables better efficiency and reduces the requirement of VDD hold-up capacitance. The turn-on and turn-off thresholds are fixed internally at 16V and 10V. During startup, the hold-up capacitor must be charged to 16V through the startup resistor to enable the IC. The hold-up capacitor continues to supply VDD before the energy can be delivered from auxiliary winding of the main transformer. VDD must not drop below 10V during this startup process. This UVLO hysteresis window ensures that hold-up capacitor is adequate to supply VDD during startup. Green-Mode Operation The proprietary green-mode function provides off-time modulation to continuously decrease the PWM frequency under light-load conditions. To avoid acoustic noise problems, the minimum PWM frequency is set above 22KHz. Green mode dramatically reduces power consumption under light-load and zero-load conditions. Power supplies using a SG5841/J controller can meet restrictive international regulations regarding standby power consumption. Gate Output / Soft Driving The SG5841/J BiCMOS output stage is a fast totempole gate driver. Cross conduction has been avoided to minimize heat dissipation, increase efficiency, and enhance reliability. The output driver is clamped by an internal 18V Zener diode to protect power MOSFET transistors against undesirable gate over-voltage. A soft driving waveform is implemented to minimize EMI. Oscillator Operation A resistor connected from the RI pin to the GND pin generates a constant current source for the SG5841/J controller. This current is used to determine the center PWM frequency. Increasing the resistance reduces PWM frequency. Using a 26K resistor, RI, results in a corresponding 65KHz PWM frequency. The relationship between RI and the switching frequency is: fPWM = 1690 (KHz) RI (K) Built-in Slope Compensation The sensed voltage across the current-sense resistor is used for peak-current-mode control and pulse-by-pulse current limiting. Built-in slope compensation improves stability or prevents sub-harmonic oscillation. SG5841/J inserts a synchronized, positive-going ramp at every switching cycle. (1) Constant Output Power Limit The range of the PWM oscillation frequency is designed as 47KHz ~ 109KHz. When the SENSE voltage across the sense resistor, RS, reaches the threshold voltage, around 0.85V, the output GATE drive is turned off after delay, tPD. This delay introduces additional current, proportional to tPD * VIN / LP. The delay is nearly constant, regardless of the input voltage VIN. Higher input voltage results in larger additional current and the output power limit is higher than under low-input line voltage. To compensate this variation for a wide AC input range, a sawtooth powerlimiter (saw limiter) is designed to solve the unequal power-limit problem. The saw limiter is designed as a positive ramp signal (Vlimit_ramp) and fed to the inverting input of the OCP comparator. This results in a lower current limit at high-line inputs than at low-line inputs. SG5841J also integrates a frequency hopping function internally. The frequency variation ranges from around 62KHz to 68KHz for a center frequency of 65KHz. The frequency-hopping function helps reduce EMI emission of a power supply with minimum line filters. Current Sensing / PWM Current Limiting Peak-current-mode control is utilized in to regulate output voltage and provide pulse-by-pulse current limiting. The switch current is detected by a sense resistor into the SENSE pin. The PWM duty cycle is determined by this current-sense signal and the feedback voltage. When the voltage on the SENSE pin reaches around VCOMP = (VFB-1.0)/3.2, a switch cycle is terminated immediately. VCOMP is internally clamped to a variable voltage around 0.85V for output power limit. (c) 2006 Fairchild Semiconductor Corporation SG5841J * Rev. 1.3.4 SG5841J -- Highly Integrated Green-Mode PWM Controller Functional Description VDD Over-Voltage Clamping VDD over-voltage clamping prevents damage due to abnormal conditions. If VDD voltage is over the VDD overvoltage clamping voltage (VDD-CLAMP) and lasts for tDVDDCLAMP, the PWM pulses are disabled until the VDD drops below the VDD over-voltage clamping voltage. www.fairchildsemi.com 10 When VDD goes below the turn-off threshold (e.g. 10V) the controller totally shuts down. VDD is charged up to the turn-on threshold voltage of 16V through the startup resistor until PWM output is restarted. This protection remains activated as long as the overloading condition persists. This prevents the power supply from overheating due to overloading conditions. An NTC thermistor RNTC in series with a resistor RA can be connected from the RT pin to ground. A constant current IRT is output from pin RT. The voltage on the RT pin can be expressed as VRT = IRT x (RNTC + RA), in which IRT = 2 x (1.3V / RI). At high ambient temperature, RNTC is smaller, such that VRT decreases. When VRT is less than 0.62V, the PWM is completely turned off. Noise Immunity Limited Power Control Noise on the current-sense or control signal may cause significant pulse-width jitter, particularly in the continuous-conduction mode. Slope compensation helps alleviate this problem. Good placement and layout practices should be followed. Avoiding long PCB traces and component leads, locating compensation and filter components near SG5841/J, and increasing power MOS gate resistance improve performance. The FB voltage increases every time the output of the power supply is shorted or overloaded. If the FB voltage remains higher than a built-in threshold for longer than tD-OLP, PWM output is turned off. As PWM output is turned off, the supply voltage VDD begins decreasing. t D - OLP (ms) = 1 . 115 x RI(K ) (c) 2006 Fairchild Semiconductor Corporation SG5841J * Rev. 1.3.4 (2) SG5841J -- Highly Integrated Green-Mode PWM Controller Thermal Protection www.fairchildsemi.com 11 2 F1 CN1 Q1 BD1 R1 4 C2 4 L3 1 2 Vo+ 2 + D1 R3 C6 3 1 3 C7 R4 + D3 + C8 D2 2 2 R7 1 1 C5 1 1 3 1 C4 R5 C3 2 2 3 R2 TR1 2 T1 1 1 L2 C1 VZ1 2 L1 2 4 2 1 1 2 3 2 D4 R9 VIN R12 R16 6 SENSE RI 3 7 VDD 5 RT R11 R10 SG5841/J C11 C9 R8 4 THER2 + 1 4 FB 1 2 3 8 GATE 1 2 GND 1 Q2 U1 1 U2 C12 K 2 3 R13 C10 R14 R U3 VO+ A R15 Figure 15. Reference Circuit BOM Reference Component Reference Component BD1 BD 4A/600V Q2 MOS 7A/600V C1 XC 0.68F/300V R1, R2 R 1M 1/4W C2 XC 0.1F/300V R3 R 100KW 1/2W C3 CC 0.01F/500V R4 R 47 1/4W C4 EC 120/400V R5, R7 R 750K 1/4W C5 YC 222p/250V R6 R 2K 1/8W C6 CC 1000pF/100V R8 R 0.3 2W C7 EC 1000F/25V R9 R 33K 1/8W C8 EC 470F/25V R10 R 4.7K 1/8W 1% C9 EC 10F/50V R11 R 470 1/8W C10 CC 222pF/50V R12 R 0 1/8W C11 CC 470pF/50V R13 R 4.7K 1/8W C12 CC 102pF/50V (Option) R14 R 154K 1/8W D1 LED R15 R 39K 1/8W D2 Diode BYV95C R16 R 100 1/8W D3 TVS P6KE16A THER2 Thermistor TTC104 D4 Diode FR103 T1 Transformer (600H-PQ2620) F1 FUSE 4A/250V U1 IC SG5841/J L1 Choke (900H) U2 IC PC817 L2 Choke (10mH) U3 IC TL431 L3 Inductor (2H) VZ1 VZ 9G Q1 Diode 20A/100V (c) 2006 Fairchild Semiconductor Corporation SG5841J * Rev. 1.3.4 R6 SG5841J -- Highly Integrated Green-Mode PWM Controller Reference Circuit www.fairchildsemi.com 12 5.00 4.80 A 0.65 3.81 8 5 B 6.20 5.80 PIN ONE INDICATOR 1.75 4.00 3.80 1 5.60 4 1.27 (0.33) 0.25 M 1.27 C B A LAND PATTERN RECOMMENDATION 0.25 0.10 SEE DETAIL A 1.75 MAX R0.10 0.10 0.51 0.33 0.50 x 45 0.25 C OPTION A - BEVEL EDGE GAGE PLANE R0.10 8 0 0.90 0.406 0.25 0.19 C SG5841J -- Highly Integrated Green-Mode PWM Controller Physical Dimensions OPTION B - NO BEVEL EDGE 0.36 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13 SEATING PLANE (1.04) DETAIL A SCALE: 2:1 Figure 16. 8-Pin Small Outline Package (SOP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. (c) 2006 Fairchild Semiconductor Corporation SG5841J * Rev. 1.3.4 www.fairchildsemi.com 13 SG5841J -- Highly Integrated Green-Mode PWM Controller Physical Dimensions (Continued) 9.83 9.00 6.67 6.096 8.255 7.61 3.683 3.20 5.08 MAX 7.62 0.33 MIN 3.60 3.00 (0.56) 2.54 0.56 0.355 0.356 0.20 9.957 7.87 1.65 1.27 7.62 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5M-1994 E) DRAWING FILENAME AND REVSION: MKT-N08FREV2. Figure 17. 8-Pin Dual Inline Package (DIP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. (c) 2006 Fairchild Semiconductor Corporation SG5841J * Rev. 1.3.4 www.fairchildsemi.com 14 SG5841J -- Highly Integrated Green-Mode PWM Controller (c) 2006 Fairchild Semiconductor Corporation SG5841J * Rev. 1.3.4 www.fairchildsemi.com 15