(INTERSIL FEATURES AD7520/ AD7530: 10 Bit Resolution; 8, 9 and 10 Bit Linearity AD7521/AD7531: 12 Bit Resolution; 8, 9 and 10 Bit Linearity Low Power Dissipation: 20 mW (Max) Low Nonlinearity Tempco: 2 PPM of FSR/C (Max) Current Settling Time: 500 ns to 0.05% of FSR Supply Voltage Range: +5V to +15V DTL/TTL/CMOS Compatible Full Input Static Protection 883B Processed Versions Available AD7520/7530 AD7521/7531 10 & 12 Bit Monolithic Multiplying D/A Converters GENERAL DESCRIPTION The AD7520/AD7530 and AD7521/AD7531 are monolithic, high accuracy, low cost 10-bit and 12-bit resolution, multiplying digital-to-analog converters (DAC). INTERSIL thin-film on CMOS processing gives up to 10- bit accuracy with DTL/TTL/CMOS compatible operation. Digital inputs are fully protected against static discharge by diodes to ground and positive supply. Typical applications include digital/analog interfacing, muitiplication and division, programmable power supplies, CRT character generation, digitally controlled gain circuits, integrators and attenuators, etc. The AD7530 and AD7531 are identical to the AD7520 and AD7521, respectively, with the exception of output leakage current and feedthrough specifications. FUNCTIONAL DIAGRAM TOKiy 10Kir 10KiY 20K, four tout! 10K: RFeeoeack (Switches shown for Digital inputs High? (Resistor values are nominal) CHIP TOPOGRAPHY Foutz lout RFB Vecr V* t ano MsB m pitse 0.086 in 2.235 mm BIT Bit2 Bits 1 * Pr BIT4 BITS BITS BIT? BITS 0.098 in 2.489 mm BITIO la errs | PACKAGE IDENTIFICATION AD7520 JON Suftix D: Cerdip package Suffix N: Plastic DIP package e ty General Type ORDERING INFORMATION Temperature Range Nonlinearity OCS to F7OCS -25C to +85C] -85C to +125C AD7520JN AD7520ND AD7520SD 0.2% (8-Bit) AD7530JN AD7530J/D AD7521JN AD7521JD AD7521SD AD7531J0N AD7531ND AD7520KN AD7520KD AD7520TD 0.1% (9-Bit) AD7530KN AD7530KD AD7521KN AD7521KD AD7521TD AD7531KN A07531KD AD7520LN AD7520LD AD7520UD 0.05% (10-Bit) AD7530LN AD7530LD AD7521LN AD7521L0 AD7521UD AD7531LN AD7531LD PIN CONFIGURATION (Outline dwgs DE, PE) TOP VIEW &D7520 (AD7530} fouty [i6] AFEEDBACK toutz [3] 1 iS] Ver . ono ig vt BIT 1 (mSB)i4] 13) BIT a1 {LSB) BIT 2 (5) aT3 ar 3] (ii) BIT 6 eit 4 110) SIT 7 elt siay SI BITs BIT 10 4-68AD7520/7530/7521/7531 INIERSIL ABSOLUTE MAXIMUM RATINGS (Ta = 25 C unless otherwise noted) Vit cc cece eee ener ete e eee eneeeeeee tee eeeee +17V Operating Temperatures VREF 1.005. eee e een e nent eee e nee eeeaeee +25V JN,KN,LN Versions ...... veneer ee eee ... OPC to+70C Digital Input Voltage Range .............. v* to GND JD, KD,LD Versions ......... cee reece e ee 25C to 86C Output Voltage Compliance ........... -100mV to V* SD, TD, UD Versions ..............665 ~55C to +126C Power Dissipation (package) Storage Temperature ...........ce seer 65C to + 150C (0) ok Co iat do ea nS 450 mW derate above +75C @ .........6-.ee eee CAUTION: 1) The digital contro! inputs are zener protected; however, permanent damage may occur on unconnected units under high energy electrostatic fields. Keep unused units in conductive foam at all times. 2) Do not apply voltages higher than Vpp or less than GND potential on any terminal except VReF and Fp. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specitications is not implied. Exposure to ab- solute maximum rating conditions for extended periods may affect device reliability. SPECIFICATIONS (v+ = +15V, Vrer = +10V, TA=25C unless otherwise specified) AD7520 AD7521 : PARAMETER (AD7530) (AD7531) UNITS LIMIT TEST CONDITIONS FIG. DC ACCURACY (Note 1) Resolution 10 12 Bits Nontinearity J 0.2 (8-Bit) . % of FSR Max S, T, U: over -55C to =125C 1 S K 0.1 (9-Bit) % of FSR Max 1 T L 0.05 (10-Bit) % of FSR Max -10V <Vrers =10V 1 U Nonlinearity Tempco 2 PPM of FSR/C Max Gain Error (Note 2) 03 % of FSA Typ 10V <Vner = +10V Gain Error Tempco (Note 2) 10 PPM of FSR/C Max Output Leakage Current 200 nA Max Over the specified temperature (either output) {300) range Power Supply Rejection +0.005 % of FSR/% Typ 2 AC ACCURACY Output Current Settling 500 ns Typ To 0.05% of FSR (All digital 6 Time inputs low to high and high to low) Feedthrough Error 10 mV pp Max Vrer = 20V pp, 100kHz 5 (50kHz) All digital inputs low REFERENCE INPUT 5k Min Input Resistance (Note 3) 10k 2 Typ All digital inputs high. 20k Max Jout1 at ground. ANALOG OUTPUT Voltage Compliance See absolute max. ratings {both outputs) Output Capacitance lout1 120 pF - Typ All digital inputs high 4 lout2 37 pF Typ lout: 37 pF Typ All digital inputs low 4 lout2 120 pF Typ Output Noise Equivalent to 10k Typ 3 (both outputs) Johnson noise DIGITAL INPUTS Low State Threshold 0.8 v Max Over the specified temp range High State Threshold 2.4 Vv Min Input Current 1 uA Typ (tow to high state) Input Coding Binary/Offset Binary See Tables 1 & 2 on pages 4 and 5 : POWER REQUIREMENTS Power Supply Voltage Range +5 to +15 Vv 1+ 5 nA Typ All digital inputs at GND 2 mA Max Ail digital inputs high or low Total Power Dissipation 20 mw Typ (Including the ladder) NOTES: _ 2. Using internal feedback resistor, RFEEDBACK. 3. Ladder and feedback resistor Tempco is approximately -150ppm/C. 1. Full scale range (FSR) is 10V for unipolar and +10V for bipolar modes. 4-69AD7520/7530/7521/7531 TEST CIRCUITS INTERSIL NOTE: The following test circuits apply for the AD7520. Similar circuits can be used for the AD7530, AD7521 and AD7531. VReF +15 V BIT1 10 BIT BINARY COUNTER AD7520 40K 01% 1MEG ERROR 10K 01% xX 100 Figure 1. Nontinearity +11V (ADJUST FOR Vout = 0V) +15V 1k | f = kHz BW = 1Hz 14 : ~ lloure toon 10k Quan WAVE ANALYZER Figure 3. Noise +154 Vrer = 20 V p-p 130 kHz SINE WAVE Vout Figure 5. Feedthrough Error LINEARITY H5V UNGROUNDED SINE WAVE GENERATOR 500K 40Hz 2V p-p HOV Vere WN ~ 5K 0.01% [HAz6 . ve Biri (msByt "5 4 Tceepsack 5K 0.01% y x10 16 rP outs \ 1 ' AD7521 air ft 13 97520 afioee pene (t$8) 3 _[exo Figure 2. Power Supply Rejection +15V nc +15, 100 mVp-p BIT 10 (LSB) ON ) mz Figure 4. Output Capacitance +15V sto v VEE St 1% SETTLING (1 mV) EXTRAPOLATE &t: 0.03% SETTLING , t=rlse time arriqmsey| * iv n mn OSCILLOSCOPE w a1 "D782 +100 mv TLL o____4 1 ob: DIGITAL INPUT hour2 U Fi BIT 10 (LSB) 3 3 @ 1000 GND L Figure 6. Output Current Settling Time DEFINITION OF TERMS NONLINEARITY: Error contributed by deviation of the DAC transfer function from a best straight line function. Normally expressed as a percentage of full scale range. For a multiplying DAC, this should hold true over the entire Vrer range. RESOLUTION: Value of the LSB. For example, a unipolar converter with n bits has a resolution of (27) (Vper). A bipolar converter of n bits has a resolution of (2-(-1)] (Vrer ]. Resolution in no way implies linearity. SETTLING TIME: Time required for the output function of the DAC to settle to within 1/2 LSB for agiven digital input stimulus, i.e.,.0 to Full Scale. . 4-70 GAIN: Ratio of the DACs operational amplifier output voltage to the nominal input voltage value. FEEDTHROUGH ERROR: Error:caused by capacitive coupling from Vref to output with all switches OFF. OUTPUT CAPACITANCE: Capacity from lout1 and lout2 terminals to ground. OUTPUT LEAKAGE CURRENT: Current which appears on lout: terminal with all digital inputs LOW or on lout2 terminal when all inputs are HIGH.AD7520/7530/7521/7531 GENERAL CIRCUIT INFORMATION The AD7520 (AD7530) and AD7521 (AD7531) are monolithic, multiplying D/A converters. Highly stable thin film R-2A resistor ladder network and NMOS SPDT switches form the basis of the converter circuit, CMOS level shifters permit low power DTL/TTL/CMOS compatible operation. An external voltage or current reference and an operational amplifier are all that is required for most voitage output applications. A simplified equivalent circuit of the DAC is shown in Figure 7. The NMOS SPOT switches steer the ladder leg currents between lout1 and lout2 busses which must be held either at ground or virtual ground potential. This configuration maintains a constant current in each ladder leg independent of the input code. 10K 1OKO 10KQ. 10KQ, Vac (18/17) 20K0 20KQ. SPDT lourz (2) fours (1) NMOS SWITCHES MSB BIT2 BIT3 (16/18) (4) (5) 16) (Switches shown for Digital Inputs High) Figure 7. 7520/7521 Functional Diagram 1 4 10KQ 4 oe RrEEDBACK (NWERSIL Converter errors are further reduced by using separate metal interconnections between the major bits and the outputs. Use of high threshold switches reduces the offset (leakage) errors toa negligible level. The level shifter circuits are comprised of three inverters with a positive feedback from the output of the second to the first, (Figure 8). This configuration results in DTL/ TTL/CMOS compatible operation over the full military temperature range. With the ladder SPOT switches driven by the level shifter, each switch is binarily weighted for an ON resistance proportional to the respective ladder leg current. This assures a constant voltage drop across each switch, creating equipotential terminations for the 2R ladder resistors and highly accurate leg currents. TO LADDER DTL/TTL/CMOS INPUT fourz Foutt Figure 8. CMOS Switch APPLICATIONS UNIPOLAR BINARY OPERATION The circuit configuration for operating the AD7520 (AD7530) and AD7521 (AD7531) in unipolar mode is shown in Figure 9. With positive and negative Vrer values the circuit is capable of 2-Quadrant multiplication. The Digital Input Code/Analog Output Value table for _ unipolar mode is given in Table 1. +15V Vrer BIT 1 (msB) 1 15 DIGITAL | INPUT | AD7520 3 Vout BIT 10 GND Figure 9. Unipolar Binary Operation (2-Quadrant Multiplication) Zero Offset Adjustment 1. Connect all digital inputs to GND. 4-71 2. Adjust the offset zero adjust trimpot of the output operational amplifier for OV 1 mV at Vour. Gain Adjustment 1..Connect all AD7520 (AD7530) or AD7521 (AD7531) digital inputs to Vt. 2. Monitor Vout for a Vrer (1-2~ "reading. (n =10 for AD7520 (AD7530) and n =12 for AD7521 (AD7531)). 3. To decrease Vout, connect a series resistor (0 to 500 ohms) between the reference voltage and the Vreer ter- minal. 4. To increase Vout, connect a series resistor (0 to 500) ohms) in the loyr, amplifier feedback loop. TABLE 1 CODE TABLE UNIPOLAR BINARY OPERATION DIGITAL INPUT ANALOG OUTPUT 1444999914 Vrer (1 - 2-9) 4000000001 -Vreer (1/2 + 2-7) 1000000000 Vaer / 2 o1tii44444 ~Vrer (1/2 - 2-7) 0000000001 Vrer (2-9) 0000000000 0 NOTE: 1,.LSB=2 Vrer 2. n= 10 for 7520, 7521 n= 12 for 7530, 7531AD7520/7530/7521/7531 (APPLICATIONS, Cont'd.) BIPOLAR (OFFSET BINARY) OPERATION The circuit configuration for operating the AD7520 (AD7530) or AD7521 (AD7531) in the bipolar mode is given in Figure 10. Using offset binary digital input codes and positive and negative reference voltage values 4- Quadrant multiplication can be realized. The Digital Input Code/Analog Output Value table for bipolar mode is given in Table 2. +15 R3 Vrer 10 MEGOHM BIT 1 (MSB) DIGITAL (INPUT , AD7520 toute BIT 10 (LS8) Figure 10. Bipolar Operation (4-Quadant Multiplication) A Logic 1 input at any digital input forces the cdrresponding ladder switch to steer the bit current to lout bus. A Logic 0 input forces the bit current to lout2 bus. For any code the lout: and lout2 bus currents are complements of one another. The current amplifier at lout2 changes the polarity of lout2 current and the transconductance amplifier at lout: output sums the two currents. This configuration doubles the output range but halves the resolution of the DAC. The difference current resulting at zero offset binary code, (MSB = Logic 1, All other bits = Logic 0), is corrected by using an external resistor, (10 Megohm), from Vrer to loutz2. IINWERSIL Offset Adjustment T, Adjust Vrer to approximately +10V. 2. Connect all digital inputs to Logic 1. 3. Adjust lout2 amplifier offset zero adjust trimpot for OV +1mV at lout2 amplifier output. 4. Connect MSB (Bit 1) to Logic 1 and all other bits to Logic 0. : 5. Adjust lout1 amplifier offset zero adjust trimpot for OV +1 mV at Vout. Gain Adjustment T. Connect all digital inputs to V*. 2. Monitor Vout for a VrerF (1-2-(9-1)) volts reading. (n= 10 for AD7520 and AD7530, and n = 12 for AD7521 and AD7531). 3. To increase VouT, connect a series resistor of up to 50029 between Vout and Rib. 4. To decrease Vout, connect a series resistor of up to 5000 between the reference voltage and the Vrer terminal. TABLE 2 CODE TABLE BIPOLAR (OFFSET BINARY) OPERATION DIGITAL INPUT ANALOG OUTPUT 4411111911 Vrer (1 2-(9-1)) 1000000001 ~Vrer (27(9-1) 1000000000 0 0111914111 Var (27(9-1)) 0000000001 Vrer (1 - 274-10) 0000000000 VREF 2. n = 10 for 7520 and 7521 n = 12 for 7530 and 7531 NOTE: 1.LSB =2-") Vac POWER DAC DESIGN USING AD7520 30KO 1 16 2 15 |- Vrer (+10) fF 3 ta[ +18 INTERSIL = 14 apzsz0 13 ts8 45 12; BIT nt ~BIT SWITCHES 7 10;- ls8 of SWITCHES 100pt 0.680) 10K ib INTERSIL 1CH8S510 TSK Figure 11. The Basic Power DAC A typical power DAC designed for 8 bit accuracy and 10 bit resolution is shown in Figure 11. An INTERSIL IH8510 power amplifier (1 Amp continuous output at up to +25 V) is driven by the AD7520. Asumming amplifier between the AD7520 and the IH8510 is used to separate the gain block containing the AD7520 on-chip resistors from the power amplifier gain stage whose gain is set only by the external resistors. This approach minimizes drift since the resistor pairs will track properly. Otherwise the AD7520 can be directly connected to the IH8510, by using a 25 V reference for the DAC. 4-72 An important note on the AD7520/101A interface concerns the connection of pin 1 of the DAC and pin 2 of the 101A. Since this point is the summing junction of an amplifier with an AC gain of 50,000 or better, stray capacitance should be minimized; otherwise instabilities and poor noise performance will result. Note that the output of the 101A is fed into an inverting amplifier with a gain of -3, which can be easily changed to anon-inverting configuration. (For more information see, INTERSIL Application Bulletin A021-Power D/A Converters Usinc The IH8510 by Dick Wilenken.)AD7520/7530/7521/7531 INTERSIL (APPLICATIONS, Cont'd.) ANALOG/DIGITAL DIVISION This is division of an analog variable (Vin) by.a digital word. With the AD7520 connected in its normal multiplying Fen ats ne ities 1S eID ON, configuration as shown in figure 15, the transfer function division by zero isn't defined. With the LSB (Bit-10) ON, is the gain is 1023. With all bits ON, the gain is 1 (+1 LSB). Ai Az , As An Vo =~VIN (3 toe tot s) where the coefficients Ax assume a value of 1 for an ON bit and 0 for an OFF bit. By connecting the DAC in the feedback of an operational BIT-1 amplifier, as shown in Figure 12, the transfer function OINPUT Vout becomes amare -VIN = = Vo= | Ar, Az As | An : 21 22 23 an Figure 12. Analog/Digital Divider 4-73